Processor context storage and recovery method based on shadow register

Abstract

The invention discloses a processor context storage and recovery method based on a shadow register. The main purpose of the invention is to realize more bottom-layer flexible processor context switching under complex processor scenes such as a multi-privilege mode based on a shadow register structure. By introducing a shadow register structure, when the context of the processor is saved and recovered, logic registers at different positions in a saving and loading instruction are mapped into different physical register files, so that the damage of a context saving program to an original site is avoided. Compared with a classic context storage and recovery method, the method can flexibly support the context switching of the processor in different modes, simplifies the context storage of a switching program, and improves the switching efficiency while guaranteeing the context integrity of the processor.

Description

Technical field:

[0001] The invention discloses a processor context saving and recovery method based on a shadow register, relates to a recovery and saving technology in processor context switching, and belongs to the field of computer technology. Background technology:

[0002] With the continuous expansion of application scenarios such as the Internet of Things, general-purpose processors need to flexibly operate in different privileged modes to improve system interactivity and execution performance. In this context, achieving efficient context switching between multiple programs in different privileged mode combinations has become a difficult problem in processor design.

[0003] The existing context switching mechanism mainly relies on the process or thread management function provided by the operating system. The processor shares execution resources among multiple processes through time slice rotation, and the operating system schedules and completes the saving and restoration of execution contexts such as program counters, general registers, and floating-point registers during switching. However, for terminal processors that do not run a complete operating system, multiple programs may still need to be executed in parallel, so they still need to rely on a dedicated context saving and recovery mechanism to support effective switching between programs. In addition, in scenarios such as the Trusted Execution Environment (TEE), the processor needs to switch between multiple operating systems, which also requires a more low-level and reliable context switching mechanism to ensure the security and functional integrity of the system.

[0004] The above context switching mechanism usually uses a specific program to save the current processor state to memory or other storage structures through a series of load and store instructions. However, this process requires using certain registers in the general registers as base registers for addressing in memory. This process will destroy the current state of the general registers and affect the integrity and correctness of the context.

[0005] To address these challenges, existing methods typically use register 0 as the base register for context saving and restoration, or reserve some registers specifically for secure context management. However, the former is difficult to adapt to diverse application requirements due to the limited addressable space of register 0, and lacks flexibility. While the latter can expand addressing capabilities, it relies on more complex software control logic, increasing implementation difficulty and system burden. In addition, during the context switch process, not only does the execution state of the target program need to be saved and restored, but the processor state of the context switching program itself also needs to be written to on-chip storage resources, further increasing storage pressure and introducing additional performance overhead.

[0006] In summary, existing processors generally face problems such as insufficient flexibility, complex software control, register state corruption, and large additional storage and performance overhead when performing context switching in multi-privileged modes. These problems make it difficult to meet the urgent needs of scenarios such as IoT terminals and trusted execution environments for efficient, secure, and low-overhead context switching mechanisms. Summary of the invention:

[0007] This invention discloses a shadow register-based processor context save and restore method. By introducing a shadow register structure, different register mapping methods are used in different processor states. This method achieves flexible and efficient context save and restore without destroying the original general register state. The main contents of this method are as follows.

[0008] This invention incorporates a customized design during the processor's register renaming phase. In addition to the existing physical register file, a new physical register file with the same number of physical registers is added. Different mapping strategies are employed for mapping logical registers to physical registers in different processor states. Hereinafter, the existing physical register file is referred to as the normal register file, and the newly introduced physical register file is referred to as the shadow register file. The specific mapping strategies are as follows.

[0009] 1) When the processor is executing a normal program, the source operands in the instruction are mapped into the normal register file and the processor executes normally.

[0010] 2) When the processor executes other programs in the context switch program except the context save and restore program, the source operand in the instruction is mapped to the shadow register file, and the processor performs program scheduling and other tasks.

[0011] 3) When the processor executes context save and restore procedures, different locations in the load and save instructions use different mapping strategies. Logical registers that serve as base registers are mapped to the shadow register file, while source operands that need to be saved and restored are mapped to the normal register file. The processor performs context save and restore operations.

[0012] In the mapping strategy adopted by the present invention, the base register and the source operand register are mapped to different physical register stacks, thereby avoiding the destruction of the original general register stack state during the preservation and restoration of the processor execution context. In order to achieve efficient management of physical registers, the present invention designs two independent circular queue structures for the ordinary register stack and the shadow register stack, respectively, to record the currently available physical registers. When the pipeline needs to allocate a new physical register for the destination register, the system takes out a physical register from the head of the corresponding queue for allocation. In addition, the present invention sets two mapping tables of logical registers to physical registers, selects to access the corresponding mapping tables in different processor states, and realizes dynamic switching and isolation of physical register mapping relationships, thereby supporting context-independent mapping and safe switching in a multi-state environment.

[0013] The present invention introduces two custom privileged registers to identify the current state of the processor being executed and read them in the pipeline register renaming stage to achieve cross-mapping of register stacks in different ways. In the present invention, the combination of the two registers is recorded as CPUState[1:0]. When its value is 00, it represents the switching program execution context save and restore. When the value is 01, it represents that the processor executes the normal program. When the value is 10, it represents the processor execution context save and restore process.

[0014] After the above register remapping mechanism is introduced, the context switching process of the processor execution unit is as follows: First, when the timer interrupt arrives, the processor saves the current program counter (PC) value and enters the execution phase of the switching program. The switching program first sets CPUState[0] to 0 and empties the pipeline through instructions to indicate that it is currently in the switching program execution state. Next, the switching program configures the register mapping control CPUState[1] to map the register operands involved in the store instruction to a specific physical register stack. Subsequently, the switching program performs a context save operation to save the processor state including general registers and CSR registers to the DTCM. After completing the save operation, the CPUState[1] is reset and the switching program enters the scheduling phase, executes the scheduling and boot logic, and determines the next execution program to be scheduled. After completing the scheduling, the switching program empties the pipeline again and reconfigures CPUState[1] to restore the register mapping in the current processor instruction to the physical register set corresponding to the target isolation domain, and then restores the processor context state of the isolation domain from the on-chip storage. Finally, the processor jumps the PC to the location where the isolation domain last paused execution and continues the execution of the program.

[0015] Advantages of the present invention include:

[0016] The processor context saving and restoring method based on shadow registers proposed in the present invention has the following advantages compared with the prior art:

[0017] When existing processors perform context switching in multiple privileged modes, they generally face problems such as insufficient flexibility, complex software control, register state destruction, and large additional storage and performance overhead. This makes it difficult to meet the urgent needs of scenarios such as IoT terminals and trusted execution environments for efficient, secure, and low-overhead context switching mechanisms. In response to the above problems, the present invention proposes a processor context saving and recovery method based on shadow registers. Different register renaming mechanisms are adopted in different execution states of the processor. When the context is saved and restored, different logical registers in the instruction are mapped to different physical register stacks. In the scenario of multi-privileged mode program switching, the integrity and correctness of the processor context are guaranteed. At the same time, by introducing shadow registers, the processor does not need to save the general register stack of the switching program itself when switching context, which reduces the performance overhead during context switching. Description of the drawings:

[0018] Figure 1 Schematic diagram of non-context save and restore instruction execution in context switch program based on shadow register.

[0019] Figure 2 Schematic diagram of context save and restore instruction execution in context switching program based on shadow register.

[0020] Figure 3 It is a functional configuration diagram of the present invention. Specific implementation method:

[0021] The present invention will be further described in detail below with reference to the accompanying drawings.

[0022] like Figure 1 As shown in FIG, this is a schematic diagram of the execution of non-context save and restore instructions of the context switch program based on the shadow register proposed by the present invention. At this time, before the context is saved and restored, the base address register for addressing must be configured by an I-type instruction. At this time, the value of CPUState[1:0] should be 00. Figure 1 Taking Li$s1,0x4000 in as an example, the logical register numbered x9, $s1, is used as the base register. When this instruction reaches the register renaming stage, the register remapping controller selects 64 shadow physical registers dedicated to the switching program in the physical register queue according to the value of CPUState[1:0]. At this time, the first element of the queue is register 102. The processor assigns this physical register to the instruction and writes the mapping relationship from x9 to 102 into the physical register mapping table. After that, in the pipeline, execution continues using register 102 as the physical register.

[0023] like Figure 2 As shown in the figure, when the program is switched to save and restore the context, register renaming uses another mapping method. At this time, CPUState[1:0] should be 10. Figure 2 Take the sw$t0,8($s1) instruction in the example, when the instruction reaches the register renaming stage, the two different logical registers in the instruction use different mapping methods. Among them, t0 (register number x5) is the destination register. When the physical registers are allocated, it is allocated to the first register P2 in the 0-63 register queue, and the mapping from x5 to P2 is added to the original register mapping table. The s1 register (register number x9) as the base register does not need to be allocated through the physical register queue, but is directly searched in the register mapping table of the shadow register, and hits the physical register P102 that has been configured by the immediate instruction. Different operands from the same instruction are mapped to different register stacks, avoiding the destruction of the original register state when switching program execution.

[0024] Figure 3 This is a schematic diagram of the functional configuration of the present invention. Figure 3 The present invention discloses a processor context saving and restoring method based on shadow registers. The main purpose of the present invention is to realize more low-level and flexible processor context switching in complex processor scenarios such as multi-privilege modes based on the shadow register structure. The present invention introduces a shadow register structure, and when performing processor context saving and restoring, the logical registers at different positions in the save and load instructions are mapped to different physical register stacks, thereby avoiding the destruction of the original scene by the context saving program. Compared with the classic context saving and restoring method, the present invention can flexibly support processor context switching in different modes, and simplifies the context saving of the switching program itself, thereby improving the efficiency of switching while ensuring the integrity of the processor context.

[0025] Finally, it should be noted that the present invention may also have many other application scenarios. Without departing from the spirit and essence of the present invention, technical personnel familiar with the field can make various corresponding changes and deformations based on the present invention, but these corresponding changes and deformations should all fall within the scope of protection of the present invention.

Claims

1. A processor context saving and restoring method based on shadow registers, characterized in that: By introducing a shadow register structure in the processor pipeline register renaming stage, different logical register to physical device mapping strategies are adopted in different processor states to achieve flexible and secure processor context switching. Based on the introduction of shadow registers, the operands in an instruction are mapped to different register files during the processor context save and restore process, thus preventing the underlying processor context switch program from damaging the original processor state and achieving more flexible and efficient processor context save and restore. The execution states of the processor context save and restore method based on shadow registers in different processor states are as follows: (1) when the processor is executing a normal program, the source operand in the instruction is mapped to the ordinary register stack, and the processor executes normally; (2) when the processor executes other programs in the context switch program except the context save and restore program, the source operand in the instruction is mapped to the shadow register stack, and the processor performs program scheduling; (3) when the processor executes the context save and restore program, different mapping strategies are adopted for different positions in the load and save instructions, wherein the logical register serving as the base register is mapped to the shadow register stack, and the source operand to be saved and restored is mapped to the ordinary register stack; the processor performs context save and restore work.

2. The method according to claim 1, wherein: It includes designing two independent circular queue structures for the normal register stack and the shadow register stack, respectively, to record the currently available physical registers; when the pipeline needs to allocate a new physical register for the destination register, the system takes a physical register from the head of the corresponding queue for allocation.

3. The method according to claim 1, wherein: This includes setting up two mapping tables from logical registers to physical registers, selecting access to the corresponding mapping tables in different processor states, and realizing dynamic switching and isolation of physical register mapping relationships, thereby supporting context-independent mapping and secure switching in multi-state environments.

4. The method according to claim 1, wherein: It includes introducing two custom privileged registers to identify the current state of the processor execution and reading them in the pipeline register renaming stage to achieve cross-mapping of register stacks in different ways; the combination of the two registers is recorded as CPUState[1:0], when its value is 00, it represents the switching program execution context save and restore, when the value is 01, it represents the processor executing normal programs, and when the value is 10, it represents the processor execution context save and restore process.

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