A bus exception prediction and handling method, device, medium and product

Abstract

The application discloses a bus exception prediction and processing method and device, medium and product, relates to the technical field of computers, and comprises a feature extraction module, which calculates and obtains time domain features and frequency domain features of a digital level signal, and an intelligent prediction module, which obtains a fault prediction result of a bus according to the time domain features and the frequency domain features, thereby solving the technical problem that bus exceptions depend on manual troubleshooting or fixed threshold detection, achieving the technical effect of predicting bus exceptions in advance; a self-healing control module generates a target control instruction according to the fault prediction probability, and transmits the target control instruction to a data acquisition module to perform corresponding operations, thereby solving the technical problem that fault recovery depends on restarting or hardware replacement, and achieving the technical effect of automatically repairing bus exceptions.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a bus exception prediction and processing method, device, medium and product. BACKGROUND

[0002] Low-speed buses are widely used in communication between devices due to low cost and simplicity, but low-speed bus communication is susceptible to physical environment and logical errors, leading to communication exception or even system paralysis. The current bus exception detection method has the following problems: ① passive fault handling: bus exception relies on manual troubleshooting or fixed threshold detection, and cannot predict potential faults in advance; ② poor protocol compatibility: designed for a single bus protocol, difficult to adapt to multi-bus mixed scenarios; ③ low repair efficiency: fault recovery relies on restart or hardware replacement, lacking an automated self-healing mechanism. SUMMARY

[0003] The present application provides a bus exception prediction and processing method, device, medium and product to at least solve the problems of inability to predict potential faults in advance and lack of an automated self-healing mechanism in the related art.

[0004] The present application provides a bus exception prediction and processing method, applied to a bus exception prediction and processing system, the bus exception prediction and processing system at least comprising a data acquisition module, a feature extraction module, an intelligent prediction module and a self-healing control module, and the bus exception prediction and processing method comprising:

[0005] acquiring a digital level signal of the bus through the data acquisition module, and transmitting the digital level signal to the feature extraction module;

[0006] calculating time domain features and frequency domain features of the digital level signal through the feature extraction module, and transmitting the time domain features and the frequency domain features to the intelligent prediction module;

[0007] obtaining a fault prediction result of the bus according to the time domain features and the frequency domain features through the intelligent prediction module, and transmitting the fault prediction result to the self-healing control module, wherein the fault prediction result at least comprises a fault prediction probability;

[0008] generating a target control instruction according to the fault prediction probability through the self-healing control module, and transmitting the target control instruction to the data acquisition module to perform corresponding operations.

[0009] The present application also provides an electronic device comprising a memory for storing a computer program, and a processor for executing the computer program to implement at least a bus exception prediction and processing method comprising the following steps:

[0010] acquiring a digital level signal of the bus through the data acquisition module, and transmitting the digital level signal to the feature extraction module;

[0011] The time domain features and the frequency domain features of the digital level signal are calculated by the feature extraction module, and the time domain features and the frequency domain features are transmitted to the intelligent prediction module;

[0012] The fault prediction result of the bus is obtained by the intelligent prediction module according to the time domain features and the frequency domain features, and the fault prediction result is transmitted to the self-recovery control module, wherein the fault prediction result at least includes a fault prediction probability;

[0013] The target control instruction is generated by the self-recovery control module according to the fault prediction probability, and the target control instruction is transmitted to the data acquisition module to perform corresponding operations.

[0014] The application also provides a computer readable storage medium, and the computer readable storage medium stores a computer program, wherein the computer program is executed by a processor to implement at least a bus anomaly prediction and processing method including the following steps:

[0015] The digital level signal of the bus is acquired by the data acquisition module, and the digital level signal is transmitted to the feature extraction module;

[0016] The time domain features and the frequency domain features of the digital level signal are calculated by the feature extraction module, and the time domain features and the frequency domain features are transmitted to the intelligent prediction module;

[0017] The fault prediction result of the bus is obtained by the intelligent prediction module according to the time domain features and the frequency domain features, and the fault prediction result is transmitted to the self-recovery control module, wherein the fault prediction result at least includes a fault prediction probability;

[0018] The target control instruction is generated by the self-recovery control module according to the fault prediction probability, and the target control instruction is transmitted to the data acquisition module to perform corresponding operations.

[0019] The application also provides a computer program product, including a computer program, and the computer program is executed by a processor to implement at least a bus anomaly prediction and processing method including the following steps:

[0020] The digital level signal of the bus is acquired by the data acquisition module, and the digital level signal is transmitted to the feature extraction module;

[0021] The time domain features and the frequency domain features of the digital level signal are calculated by the feature extraction module, and the time domain features and the frequency domain features are transmitted to the intelligent prediction module;

[0022] The fault prediction result of the bus is obtained by the intelligent prediction module according to the time domain features and the frequency domain features, and the fault prediction result is transmitted to the self-recovery control module, wherein the fault prediction result at least includes a fault prediction probability;

[0023] The self-recovery control module generates a target control instruction according to the fault prediction probability, and transmits the target control instruction to the data acquisition module to perform corresponding operations.

[0024] According to the application, the feature extraction module calculates time domain features and frequency domain features of the digital level signal, and the intelligent prediction module obtains a fault prediction result of the bus according to the time domain features and the frequency domain features, thereby solving the technical problem of bus anomaly relying on manual troubleshooting or fixed threshold detection, and achieving the technical effect of predicting bus anomaly in advance; the self-recovery control module generates a target control instruction according to the fault prediction probability, and transmits the target control instruction to the data acquisition module to perform corresponding operations, thereby solving the technical problem of fault recovery relying on restart or hardware replacement, and achieving the technical effect of automatic bus anomaly repair. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0026] Figure 1 A flowchart of a bus anomaly prediction and processing method in an embodiment;

[0027] Figure 2 An architecture diagram of a bus anomaly prediction and processing system in an embodiment;

[0028] Figure 3 A flowchart of long short-term memory network training in an embodiment;

[0029] Figure 4 A schematic diagram of a redundant link controller in an embodiment;

[0030] Figure 5 An internal structure diagram of an electronic device in an embodiment. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0032] It should be noted that in the description of the present application, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles or devices that include a series of elements not only include those elements, but also include other elements not explicitly listed, or inherent to such processes, methods, articles or devices. The terms "first", "second", etc. in the present application are used to distinguish similar objects, not to describe a specific order or sequence.

[0033] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below in conjunction with the drawings and specific embodiments.

[0034] In one embodiment, as shown in Figure 1 A bus exception prediction and processing method is provided, applied to a bus exception prediction and processing system, the bus exception prediction and processing system at least includes a data acquisition module, a feature extraction module, an intelligent prediction module and a self-healing control module, the bus exception prediction and processing method includes:

[0035] The digital level signal of the bus is acquired by the data acquisition module, and the digital level signal is transmitted to the feature extraction module;

[0036] The time domain feature and the frequency domain feature of the digital level signal are calculated by the feature extraction module, and the time domain feature and the frequency domain feature are transmitted to the intelligent prediction module;

[0037] The fault prediction result of the bus is obtained by the intelligent prediction module according to the time domain feature and the frequency domain feature, and the fault prediction result is transmitted to the self-healing control module, wherein the fault prediction result at least includes a fault prediction probability;

[0038] The target control instruction is generated by the self-healing control module according to the fault prediction probability, and the target control instruction is transmitted to the data acquisition module to perform corresponding operation.

[0039] Specifically, the feature extraction module calculates the time domain feature and the frequency domain feature of the digital level signal, and the intelligent prediction module obtains the fault prediction result of the bus according to the time domain feature and the frequency domain feature, which solves the technical problem of bus exception relying on manual investigation or fixed threshold detection, and achieves the technical effect of predicting bus exception in advance; The self-healing control module generates a target control instruction according to the fault prediction probability, and transmits the target control instruction to the data acquisition module to perform corresponding operation, which solves the technical problem of fault recovery relying on restart or hardware replacement, and achieves the technical effect of automatic bus exception repair.

[0040] In specific implementation, as Figure 2As shown, the bus exception prediction and processing system comprises a data acquisition module, a feature extraction module, an intelligent prediction module, a self-healing control module and a protocol adaptation module, the data acquisition module comprises a level sensor, an analog-to-digital converter and a first controller, the intelligent prediction module comprises a long short-term memory network and a random forest classifier, the self-healing control module comprises a dynamic strategy engine and a redundant link controller; the level sensor is connected with the bus, and the output end of the level sensor is connected with the input end of the analog-to-digital converter; the output end of the analog-to-digital converter is connected with the first input end of the first controller; the output end of the first controller is connected with the input end of the feature extraction module; the output end of the feature extraction module is connected with the input end of the long short-term memory network; the output end of the long short-term memory network is connected with the input end of the random forest classifier; the output end of the random forest classifier is connected with the input end of the dynamic strategy engine; the first output end of the dynamic strategy engine is connected with the second input end of the first controller, the second output end of the dynamic strategy engine is connected with the input end of the protocol adaptation module, and the third output end of the dynamic strategy engine is connected with the input end of the redundant link controller; the output end of the redundant link controller is connected with the third input end of the first controller; the output end of the protocol adaptation module is connected with the fourth input end of the first controller.

[0041] Further, the data acquisition module at least comprises a level sensor, an analog-to-digital converter and a first controller, the digital level signal of the bus is acquired through the data acquisition module, and the digital level signal is transmitted to the feature extraction module, comprising:

[0042] The analog level signal of the bus is acquired through the level sensor, and the analog level signal is transmitted to the analog-to-digital converter;

[0043] The analog level signal is converted into a corresponding digital level signal through the analog-to-digital converter, and the digital level signal is transmitted to the first controller;

[0044] The digital level signal is transmitted to the feature extraction module through the first controller.

[0045] Specifically, through the level sensor, the analog-to-digital converter and the first controller, the analog level signal of the bus can be acquired and converted into a corresponding digital level signal for fault prediction.

[0046] In a specific implementation, the first controller of the embodiment is a complex programmable logic device. The data acquisition module is located in the hardware layer and is composed of a complex programmable logic device, an analog-to-digital converter, and a level sensor, which acquires the level signal and timing data of the bus in real time. The complex programmable logic device is directly connected to the physical signal line of the bus through the general-purpose input-output pin as the core controller. The analog-to-digital converter receives the analog signal from the level sensor, converts it into a digital signal, and then transmits it to the complex programmable logic device through the serial peripheral interface. The level sensor is deployed on each signal line of the bus to monitor the level state in real time and is connected to the analog-to-digital converter through the analog signal line.

[0047] Further, the feature extraction module calculates the time domain features and frequency domain features of the digital level signal and transmits them to the intelligent prediction module, including:

[0048] The time domain features and frequency domain features of the digital level signal are calculated by a sliding window.

[0049] The original feature matrix is generated according to the time domain features and frequency domain features, and the original feature matrix is transmitted to the intelligent prediction module.

[0050] Specifically, the original feature matrix of the digital level signal is obtained by the feature extraction module, wherein the original feature matrix includes time domain features and frequency domain features, and fault prediction is performed according to the original feature matrix.

[0051] In a specific implementation, the feature extraction module receives the digital level signal and calculates the time domain features including mean μ, variance σ 2 , and the frequency domain features including noise spectrum energy E f by fast Fourier transform through a sliding window. The input of the feature extraction module receives the digital level signal sent by the complex programmable logic device through the internal bus, and the output of the feature extraction module transmits the extracted time domain features and frequency domain features to the intelligent prediction module through the data bus. The window length T can be set to 100 ms.

[0052] Further, the intelligent prediction module at least includes a long short-term memory network and a random forest classifier, and the fault prediction result of the bus is obtained according to the time domain features and frequency domain features by the intelligent prediction module, and the fault prediction result is transmitted to the self-healing control module, including:

[0053] The time sequence feature matrix is generated from the original feature matrix by the long short-term memory network, and the time sequence feature matrix is transmitted to the random forest classifier;

[0054] The fault prediction result is generated from the time sequence feature matrix by the random forest classifier;

[0055] The interrupt signal is generated by the random forest classifier, and the fault prediction result is transmitted to the self-healing control module through the interrupt signal.

[0056] Specifically, the original feature matrix X = [μ, σ 2 , E f , the number of missing confirmation characters] is a time step statistical quantity, which cannot directly reflect the time sequence dynamics, such as the burstiness of missing confirmation characters and the gradual trend of the signal. The time sequence feature matrix H ∈ R N×64 is generated by the long short-term memory network, so that the 64-dimensional features of each time step contain historical / future context information. Different features have different physical meanings and dimensions, such as μ and the number of missing confirmation characters. The time sequence feature matrix H ∈ R N×64 converts all features into dimensionless hidden vectors, which facilitates the processing of the random forest classifier.

[0057] In specific implementation, N represents the number of time steps or sequence length, for example, if a signal lasting 100 seconds is analyzed, sampling once per second, then N = 100; D represents the feature dimension of each time step, for example, the original feature matrix X = [μ, σ 2 , E f , the number of missing confirmation characters], each feature is a scalar, and there are 4 dimensions, i.e. D = 4. Each row X[i] represents a 4-dimensional feature vector of the i-th time step, and each row H[i] represents a 64-dimensional feature vector of the i-th time step.

[0058] Intelligent prediction module: a hybrid model composed of a long short-term memory network and a random forest classifier, which inputs the original feature matrix X = [μ, σ 2 , E f , the number of missing confirmation characters], and outputs the fault prediction probability P fault and the fault prediction type of “physical layer short circuit” or “logical conflict”. The input of the long short-term memory network: receives the original feature matrix X ∈ R N×D ; the output of the long short-term memory network: transmits the time sequence feature matrix H ∈ R N×64 to the random forest classifier. The input of the random forest classifier: receives the time sequence feature matrix H ∈ R N×64 ; the output of the random forest classifier: the fault prediction type and the fault prediction probability P faul t are transmitted to the self-healing control module through the interrupt signal.

[0059] In specific implementation, the long short-term memory network contains three gates and one memory unit, wherein the three gates are input gate, forget gate and output gate, which control the flow of information: forget gate: decides which historical information to discard; input gate: decides which new information to add; output gate: decides the output at the current time. Set the current time as t, the input as x tthe hidden state of the previous time is h t-1 the cell state of the previous time is C t-1 the calculation process of the long short-term memory network is as follows:

[0060] Step 1: calculate the forget gate f t =σ(W f ·[h t-1 , x t ]+b f ), wherein W f is a forget gate weight matrix, b f is a forget gate bias term, and σ is a Sigmoid activation function, and the output value is in [0, 1], indicating the retention ratio;

[0061] Step 2: calculate the input gate i t =σ(W i ·[h t-1 , x t ]+b i ), the candidate cell state C ~ t =tanh(W c ·[h t-1 , x t ]+b c ), wherein W i is an input gate weight matrix, b i is an input gate bias term, W c is a candidate cell weight matrix, and b c is a candidate cell bias term;

[0062] Step 3: calculate the cell state C t at the current time f t ⊙C t-1 +i t ⊙C ~ t , wherein ⊙ represents element-wise multiplication;

[0063] Step 4: calculate the output gate o t =σ(W o ⋅[h t-1 , x t ]+b o ), the current hidden state h t =o t ⊙tanhC t , wherein W o is an output gate weight matrix, b o is an output gate bias term, and h t is transmitted to the next time and serves as the output of the current time.

[0064] In a specific implementation, the device runs a process accompanied by model data updating, according to the received original feature matrix, the long short-term memory network continuously updates the model data to improve the accuracy of fault prediction, and the training process is as shown in Figure 3 The specific process is as follows:

[0065] Step 1: The feature extraction module continuously sends the original feature matrix to the long short-term memory network;

[0066] Step 2: The full connection layer outputs the abnormal probability P fault , and passes it to the long short-term memory layer to complete the weight matrix information update;

[0067] Step 3: After the information is updated, it is first synchronized to the second controller through the intelligent platform management interface. The second controller of the embodiment is a baseboard management controller, which directly completes the information burning of the storage device of the complex programmable logic device. The storage device of the embodiment is a flash memory;

[0068] Step 4: After the information is burned, the baseboard management controller notifies the complex programmable logic device to reload the flash memory, so that the data update takes effect.

[0069] Further, the self-healing control module at least includes a dynamic strategy engine, which generates a target control instruction according to the fault prediction probability through the self-healing control module, and transmits the target control instruction to the data acquisition module to perform corresponding operations, including:

[0070] If the fault prediction probability is greater than or equal to the first threshold value and less than the second threshold value, a bus frequency reduction instruction is generated through the dynamic strategy engine, and the bus frequency reduction instruction is transmitted to the first controller to perform a bus frequency reduction operation, wherein the first threshold value is less than the second threshold value;

[0071] If the fault prediction probability is greater than or equal to the second threshold value, a link switching instruction is generated through the dynamic strategy engine, and the link switching instruction is transmitted to the first controller to perform a link switching operation.

[0072] Specifically, according to the size relationship between the fault prediction probability and the first threshold value and the second threshold value, the bus frequency reduction instruction or the link switching instruction is generated through the dynamic strategy engine, so as to realize full automation from fault prediction to fault repair.

[0073] In a specific implementation, the self-healing control module: according to the fault prediction result, triggers a dynamic strategy, for example, adjusts the bus frequency or controls the analog switch to switch the redundant link. The input of the dynamic strategy engine: receives the P faultand fault prediction type; the output of the dynamic strategy engine: generating control instructions, which are sent to the bus hardware through the input / output pins of the complex programmable logic device, wherein the control instructions include frequency reduction commands and switching instructions. The hierarchical response mechanism of the dynamic strategy engine: first-level response: when P fault ≥ 70% and P fault < 90%, generate bus frequency reduction instruction f new = f orig × (1 - αP fault ), wherein f new is the target frequency of the bus, f orig is the current frequency of the bus, and α is the attenuation coefficient, which has a default value of 0.3; second-level response: when P fault ≥ 90%, generate link switching instruction to switch the current link to the redundant link, and after the switching is completed, report the fault channel number through the baseboard management controller to prompt the user to replace the hardware in time.

[0074] Further, the self-healing control module further comprises a redundant link controller, generates a link switching instruction through the dynamic strategy engine, and transmits the link switching instruction to the first controller to perform a link switching operation, comprising:

[0075] generating a link switching instruction through the dynamic strategy engine and transmitting the link switching instruction to the redundant link controller;

[0076] analyzing the link switching instruction through the redundant link controller, obtaining target link information, and transmitting the target link information to the first controller;

[0077] switching the current link of the bus to the target link corresponding to the target link information through the first controller according to the target link information.

[0078] Specifically, if the fault prediction probability is greater than or equal to the second threshold value, the system stability and maintainability are improved by switching to the redundant link.

[0079] Further, the bus anomaly prediction and processing system further comprises a protocol adaptation module, generates a bus frequency reduction instruction through the dynamic strategy engine, and transmits the bus frequency reduction instruction to the first controller to perform a bus frequency reduction operation, comprising:

[0080] generating a bus frequency reduction instruction through the dynamic strategy engine and transmitting the bus frequency reduction instruction to the first controller and the protocol adaptation module respectively;

[0081] analyzing the bus frequency reduction instruction through the protocol adaptation module, obtaining the target configuration parameters of the bus, and transmitting the target configuration parameters to the first controller;

[0082] In response to the bus frequency reduction instruction, the current configuration parameter of the bus is updated to the target configuration parameter by the first controller.

[0083] Specifically, the target configuration parameter is written into an internal register of the complex programmable logic device to dynamically adjust the bus protocol parameter, implement the I 2 The unified management of C (Inter-Integrated Circuit, Inter-Integrated Circuit), SPI (Serial Peripheral Interface, Serial Peripheral Interface), and LPC (Low Pin Count, Low Pin Count) is improved, and the system versatility is improved, wherein the dynamic adjustment of the bus protocol parameter includes the clock polarity and the clock phase of the SPI bus.

[0084] Further, the bus anomaly prediction and processing system further comprises a second controller, and the bus anomaly prediction and processing method further comprises:

[0085] If the failure prediction probability is greater than or equal to the first threshold value, the current link information of the bus is obtained by the self-healing control module, and a target control instruction is generated;

[0086] The target control instruction and the current link information are transmitted to the first controller by the self-healing control module to perform corresponding bus frequency reduction operation or link switching operation;

[0087] If the bus frequency reduction operation is completed or the link switching operation is completed, the bus failure prompt is generated by the first controller according to the current link information, and the bus failure prompt is transmitted to the second controller.

[0088] Specifically, after completing the link switching or the bus frequency reduction, the complex programmable logic device generates a bus failure prompt according to the link information before the frequency reduction / switching, and sends the bus failure prompt to the baseboard management controller to remind the user to replace the bus hardware in time, thereby ensuring the stability of the system and the continuity of the bus data transmission.

[0089] Further, the bus frequency reduction instruction is generated by the dynamic strategy engine, and the bus frequency reduction instruction is transmitted to the first controller to perform the bus frequency reduction operation, and the bus frequency reduction instruction further comprises:

[0090] The current frequency of the bus is obtained by the dynamic strategy engine, and the target frequency of the bus is calculated according to the current frequency and the attenuation coefficient;

[0091] The bus frequency reduction instruction is generated by the dynamic strategy engine according to the current frequency and the target frequency, and the bus frequency reduction instruction is transmitted to the first controller and the protocol adaptation module, respectively;

[0092] The target frequency is obtained by analyzing the bus frequency reduction instruction by the protocol adaptation module, and the target frequency is transmitted to the first controller.

[0093] In response to the bus frequency reduction instruction, the value of the frequency parameter of the bus is updated from the current frequency to the target frequency by the first controller.

[0094] Further, the target frequency of the bus is calculated according to the current frequency and the attenuation coefficient, comprising:

[0095] According to the fault prediction probability and the attenuation coefficient, the frequency attenuation ratio is calculated, and according to the frequency attenuation ratio, the frequency retention ratio is calculated;

[0096] According to the frequency retention ratio and the current frequency, the target frequency is calculated.

[0097] Further, the bus anomaly prediction and processing method further comprises:

[0098] The bus is detected for faults, and the fault duration of the bus is recorded;

[0099] If the fault duration is less than the third threshold, the bus is continuously detected for faults;

[0100] If the fault duration is greater than or equal to the third threshold, and the fault prediction probability is greater than or equal to the second threshold, a link switching instruction is generated by the dynamic strategy engine, and the link switching instruction is transmitted to the first controller to perform a link switching operation.

[0101] Specifically, since only the fault prediction probability is relied on, false alarm may occur; only relying on the fault duration, a short-term disturbance including electromagnetic pulse may trigger a false switching, resulting in frequent oscillation. Therefore, on the basis of the fault prediction probability, the bus is judged in combination with the fault duration, which can significantly reduce the false switching rate and improve the system availability.

[0102] In specific implementation, the third threshold of the embodiment is 5ms, which can also be adjusted according to actual conditions.

[0103] Further, in response to the bus frequency reduction instruction, the current configuration parameter of the bus is updated to the target configuration parameter by the first controller, comprising:

[0104] The bus frequency reduction instruction is parsed by the protocol adaptation module to obtain the bus type;

[0105] The corresponding target register is searched by the protocol adaptation module according to the bus type, and the configuration parameter field of the bus is read from the target register to obtain the current configuration parameter;

[0106] In response to the bus frequency reduction instruction, the value of the configuration parameter field is updated from the current configuration parameter to the target configuration parameter by the first controller.

[0107] Specifically, a hardware abstraction layer and a flexible register interface are designed, configuration parameters of different buses are normalized into programmable register fields, configuration is modified in real time by writing registers, a unified interface across buses is provided by combining hardware multiplexing, and software development is simplified.

[0108] In specific implementation, the protocol adaptation module: abstracts configuration parameters of different bus protocols, realizes dynamic switching through register mapping, and specifically includes I 2 C slave address configuration, SPI clock polarity and clock phase mode selection. The input of the protocol adaptation module: parameter adjustment instructions received from the self-healing control module, such as I 2 C bus frequency reduction instructions; the output of the protocol adaptation module: dynamically adjusts bus protocol parameters through internal register write operations of the complex programmable logic device.

[0109] As shown in Figure 4 , a first controller, a host, a slave, a buffer, an analog switch, and a transistor are arranged on the bus, the transistor at least includes a first transistor and a second transistor, a first output end of the host is connected with a first input end of the first transistor, a second output end of the host is connected with an input end of the buffer, an output end of the first transistor is connected with a first input end of the analog switch, an output end of the buffer is connected with a first input end of the second transistor, a first output end of the first controller is connected with a second input end of the first transistor, a second output end of the first controller is connected with a second input end of the second transistor, a third output end of the first controller is connected with a second input end of the analog switch, an output end of the second transistor is connected with a third input end of the analog switch, an output end of the slave is connected with a fourth input end of the analog switch, and an input end of the slave is connected with an output end of the analog switch, the first controller is used for switching the current link of the bus to a target link corresponding to target link information according to the target link information, and the method comprises the steps of:

[0110] If the connection between the first transistor and the analog switch is in a conductive state, and the target link information is the link information between the second transistor and the analog switch, the first controller is used for controlling the analog switch to conduct the connection between the second transistor and the analog switch, and the first controller is used for pulling down the gate voltage of the first transistor at the same time.

[0111] If the connection between the second transistor and the analog switch is in a conductive state, and the target link information is the link information between the first transistor and the analog switch, the first controller is used for controlling the analog switch to conduct the connection between the first transistor and the analog switch, and the first controller is used for pulling down the gate voltage of the second transistor at the same time.

[0112] Specifically, the switching of the link is realized by conducting the connection between the second transistor and the analog switch, and the fault link is physically isolated by pulling down the gate voltage of the first transistor.

[0113] In a specific implementation, the input of the redundant link controller: receives a link switching instruction, such as SWITCH_TO_CH1; the output of the redundant link controller: controls the SEL0 / SEL1 pin of the analog switch through the general input and output pin of the complex programmable logic device, and switches the link. The principle of the redundant link controller: the signal sent by the host is copied by the buffer and used as the input of the analog switches CH0 and CH1, respectively. After the complex programmable logic device receives the link switching instruction, the analog switch is controlled to complete the switching of CH0 / CH1, and the gate voltage of the transistor on the faulty link is pulled down, so as to physically isolate the faulty link. The transistor in the embodiment is a metal oxide semiconductor field effect transistor.

[0114] It should be understood that, although Figure 1 、 Figure 3 the steps in the flowcharts are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, Figure 1 、 Figure 3 at least part of the steps in the flowcharts can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or sub-steps or stages of other steps.

[0115] In one embodiment, an electronic device is provided, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program:

[0116] acquire the digital level signal of the bus through the data acquisition module, and transmit the digital level signal to the feature extraction module;

[0117] calculate the time domain feature and the frequency domain feature of the digital level signal through the feature extraction module, and transmit the time domain feature and the frequency domain feature to the intelligent prediction module;

[0118] obtain the fault prediction result of the bus according to the time domain feature and the frequency domain feature through the intelligent prediction module, and transmit the fault prediction result to the self-healing control module, wherein the fault prediction result at least includes a fault prediction probability;

[0119] generate a target control instruction according to the fault prediction probability through the self-healing control module, and transmit the target control instruction to the data acquisition module to perform corresponding operations.

[0120] The program instructions, when read and executed by one or more processors, can also perform operations corresponding to the various steps of the method embodiments described above. Reference can be made to the above description, which will not be repeated here. Reference Figure 5 An exemplary architecture of an electronic device is shown, which can specifically include a processor 510, a video display adapter 511, a disk drive 512, an input / output interface 513, a network interface 514, and a memory 520. The processor 510, the video display adapter 511, the disk drive 512, the input / output interface 513, the network interface 514, and the memory 520 can be communicatively connected through a communication bus 530.

[0121] The processor 510 can be implemented in the form of a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits, etc., for executing related programs to implement the technical solutions provided in the present application.

[0122] The memory 520 can be implemented in the form of a read only memory (ROM), a random access memory (RAM), a static storage device, a dynamic storage device, etc. The memory 520 can store an operating system 521 for controlling the operation of the electronic device 500, a basic input / output system (BIOS) 522 for controlling the low-level operation of the electronic device 500. In addition, a web browser 523, a data storage management 524, and an icon font processing system 525, etc. can also be stored. The icon font processing system 525 can be an application program that specifically implements the operations of the above steps in the embodiments of the present application. In general, when the technical solutions provided in the present application are implemented by software or firmware, the related program codes are stored in the memory 520 and executed by the processor 510.

[0123] The input / output interface 513 is used to connect input / output modules to realize information input and output. The input / output modules can be configured as components in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. The input devices can include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output devices can include a display, a speaker, a vibrator, an indicator light, etc.

[0124] The network interface 514 is configured to connect a communication module (not shown in the figure) to realize the communication interaction between the device and other devices. The communication module can realize communication through wired mode (such as USB, network cable, etc.), or realize communication through wireless mode (such as mobile network, WIFI, Bluetooth, etc.).

[0125] The bus 530 includes a path for transmitting information between various components (such as the processor 510, the video display adapter 511, the disk drive 512, the input / output interface 513, the network interface 514, and the memory 520) of the device.

[0126] In addition, the electronic device 500 can also obtain the information of the specific collection condition from the virtual resource object collection condition information database (not shown in the figure) to be used for condition judgment.

[0127] It should be noted that although the above electronic device 500 only shows the processor 510, the video display adapter 511, the disk drive 512, the input / output interface 513, the network interface 514, the memory 520, the bus 530, etc., in the specific implementation process, the electronic device can also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above device can also only contain the components necessary to implement the scheme of the present application, and does not have to contain all the components shown in the figure.

[0128] From the above description of the embodiments, those skilled in the art can clearly understand that the present application can be realized by means of software and the necessary general hardware platform. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes a plurality of instructions for causing an electronic device (which can be a personal computer, a cloud server, or a network device, etc.) to execute the method of each embodiment or some part of the embodiment of the present application.

[0129] In one embodiment, a computer readable storage medium is provided, which stores a computer program. The computer program is executed by a processor to implement the following steps:

[0130] The data acquisition module acquires the digital level signal of the bus and transmits the digital level signal to the feature extraction module;

[0131] The feature extraction module calculates the time domain feature and the frequency domain feature of the digital level signal, and transmits the time domain feature and the frequency domain feature to the intelligent prediction module;

[0132] The intelligent prediction module obtains a bus fault prediction result according to the time domain feature and the frequency domain feature, and transmits the fault prediction result to the self-recovery control module, wherein the fault prediction result at least includes a fault prediction probability;

[0133] The self-recovery control module generates a target control instruction according to the fault prediction probability, and transmits the target control instruction to the data acquisition module to perform corresponding operations.

[0134] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, the computer program can include the processes of the above-mentioned embodiments. Any reference to memory, storage, database or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct RAM bus dynamic RAM (DRDRAM) and memory bus dynamic RAM (RDRAM) and the like.

[0135] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0136] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled persons in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are within the scope of the present application.

[0137] In one embodiment, a computer program product is provided, and a computer program is stored on the computer program product. The computer program is executed by a processor to implement the following steps:

[0138] The data acquisition module obtains the digital level signal of the bus and transmits the digital level signal to the feature extraction module;

[0139] The feature extraction module calculates the time domain feature and the frequency domain feature of the digital level signal and transmits the time domain feature and the frequency domain feature to the intelligent prediction module;

[0140] The intelligent prediction module obtains the fault prediction result of the bus according to the time domain feature and the frequency domain feature and transmits the fault prediction result to the self-recovery control module, wherein the fault prediction result at least includes a fault prediction probability;

[0141] The self-recovery control module generates a target control instruction according to the fault prediction probability and transmits the target control instruction to the data acquisition module to perform corresponding operations.

[0142] In one embodiment, a computer program product is provided, comprising a non-volatile computer-readable storage medium storing a computer program, the computer program being executed by a processor to implement the following steps:

[0143] The data acquisition module obtains the digital level signal of the bus and transmits the digital level signal to the feature extraction module;

[0144] The feature extraction module calculates the time domain feature and the frequency domain feature of the digital level signal and transmits the time domain feature and the frequency domain feature to the intelligent prediction module;

[0145] The intelligent prediction module obtains the fault prediction result of the bus according to the time domain feature and the frequency domain feature and transmits the fault prediction result to the self-recovery control module, wherein the fault prediction result at least includes a fault prediction probability;

[0146] The self-recovery control module generates a target control instruction according to the fault prediction probability and transmits the target control instruction to the data acquisition module to perform corresponding operations.

[0147] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware, and the computer program can be stored in a computer program product, and when the computer program is executed, the computer program can include the processes of the above-mentioned embodiments.

[0148] The technical features of the above embodiments can be combined in any manner, and to make the description concise, not all possible combinations of the technical features in the above embodiments are described, however, as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present disclosure.

[0149] The above embodiments only express several implementation ways of the present application, and the description is specific and detailed, but it should not be understood as a limitation to the scope of the patent. It should be pointed out that, for ordinary skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are all within the scope of protection of the present application.

Claims

1. A method for bus anomaly prediction and processing, applied to a bus anomaly prediction and processing system, the bus anomaly prediction and processing system comprising at least a data acquisition module, a feature extraction module, an intelligent prediction module and a self-recovery control module, characterized in that, The method comprises: acquiring, by the data acquisition module, a digital level signal of the bus, and transmitting the digital level signal to the feature extraction module; calculating, by the feature extraction module, time domain features and frequency domain features of the digital level signal, and transmitting the time domain features and the frequency domain features to the intelligent prediction module; obtaining, by the intelligent prediction module, a fault prediction result of the bus according to the time domain features and the frequency domain features, and transmitting the fault prediction result to the self-healing control module, wherein the fault prediction result at least includes a fault prediction probability; generating, by the self-healing control module, a target control instruction according to the fault prediction probability, and transmitting the target control instruction to the data acquisition module to perform corresponding operations; wherein the intelligent prediction module at least includes a long short-term memory network and a random forest classifier, and is characterized in that the obtaining, by the intelligent prediction module, of the fault prediction result of the bus according to the time domain features and the frequency domain features comprises: generating, by the long short-term memory network, a time sequence feature matrix according to an original feature matrix, and transmitting the time sequence feature matrix to the random forest classifier, wherein the original feature matrix is generated by the time domain features and the frequency domain features; generating, by the random forest classifier, the fault prediction result according to the time sequence feature matrix; the data acquisition module at least includes a first controller, and the self-healing control module at least includes a dynamic strategy engine, and is characterized in that the generating, by the self-healing control module, of the target control instruction according to the fault prediction probability, and the transmitting of the target control instruction to the data acquisition module to perform corresponding operations comprises: if the fault prediction probability is greater than or equal to a first threshold value and less than a second threshold value, generating, by the dynamic strategy engine, a bus frequency reduction instruction, and transmitting the bus frequency reduction instruction to the first controller to perform a bus frequency reduction operation, wherein the first threshold value is less than the second threshold value; if the fault prediction probability is greater than or equal to the second threshold value, generating, by the dynamic strategy engine, a link switching instruction, and transmitting the link switching instruction to the first controller to perform a link switching operation.

2. The method of claim 1, wherein said data acquisition module further comprises at least a level sensor and an analog-to-digital converter. The acquiring, by the data acquisition module, of the digital level signal of the bus, and the transmitting of the digital level signal to the feature extraction module comprises: acquiring, by the level sensor, an analog level signal of the bus, and transmitting the analog level signal to the analog-to-digital converter; converting, by the analog-to-digital converter, the analog level signal into a corresponding digital level signal, and transmitting the digital level signal to the first controller; transmitting, by the first controller, the digital level signal to the feature extraction module.

3. The method of claim 1, wherein, The calculating, by the feature extraction module, of the time domain features and the frequency domain features of the digital level signal, and the transmitting of the time domain features and the frequency domain features to the intelligent prediction module comprises: calculating the time domain features and the frequency domain features of the digital level signal by a sliding window; Generate an original feature matrix according to the time domain feature and the frequency domain feature, and transmit the original feature matrix to the intelligent prediction module.

4. The method of claim 1, wherein, The transmitting the fault prediction result to the self-healing control module comprises: Generate an interrupt signal through the random forest classifier, and transmit the fault prediction result to the self-healing control module through the interrupt signal.

5. The method of claim 1, wherein the self-healing control module further comprises at least a redundant link controller. The generating the link switching instruction through the dynamic strategy engine and transmitting the link switching instruction to the first controller to perform a link switching operation comprises: Generate a link switching instruction through the dynamic strategy engine, and transmit the link switching instruction to the redundant link controller; Obtain target link information through the redundant link controller by analyzing the link switching instruction, and transmit the target link information to the first controller; Switch the current link of the bus to the target link corresponding to the target link information according to the target link information through the first controller.

6. The method of claim 1, wherein the bus exception prediction and handling system further comprises at least a protocol adaptation module, and wherein: The generating the bus frequency reduction instruction through the dynamic strategy engine and transmitting the bus frequency reduction instruction to the first controller to perform a bus frequency reduction operation comprises: Generate the bus frequency reduction instruction through the dynamic strategy engine, and transmit the bus frequency reduction instruction to the first controller and the protocol adaptation module respectively; Obtain the target configuration parameter of the bus by analyzing the bus frequency reduction instruction through the protocol adaptation module, and transmit the target configuration parameter to the first controller; Update the current configuration parameter of the bus to the target configuration parameter through the first controller in response to the bus frequency reduction instruction.

7. The method of claim 1, wherein said bus exception prediction and handling system further comprises at least a second controller, and wherein The method further comprises: If the fault prediction probability is greater than or equal to the first threshold, obtain the current link information of the bus through the self-healing control module, and generate the target control instruction at the same time; Transmit the target control instruction and the current link information to the first controller through the self-healing control module to perform a corresponding bus frequency reduction operation or link switching operation; If the bus frequency reduction operation is completed or the link switching operation is completed, generate a bus fault prompt according to the current link information through the first controller, and transmit the bus fault prompt to the second controller.

8. The method of claim 6, wherein, The generating the bus frequency reduction instruction through the dynamic strategy engine and transmitting the bus frequency reduction instruction to the first controller to perform a bus frequency reduction operation further comprises: Obtain the current frequency of the bus through the dynamic strategy engine, and calculate the target frequency of the bus according to the current frequency and a decay coefficient; Generate the bus frequency reduction instruction according to the current frequency and the target frequency through the dynamic strategy engine, and transmit the bus frequency reduction instruction to the first controller and the protocol adaptation module respectively; Obtain the target frequency through the protocol adaptation module by analyzing the bus frequency reduction instruction, and transmit the target frequency to the first controller; In response to the bus frequency reduction instruction, the first controller updates a value of a frequency parameter of the bus from the current frequency to the target frequency.

9. The method of claim 8, wherein, The target frequency of the bus is calculated according to the current frequency and a decay coefficient, and the method comprises: According to the fault prediction probability and the decay coefficient, a frequency decay ratio is calculated, and a frequency retention ratio is calculated according to the frequency decay ratio. The target frequency is calculated according to the frequency retention ratio and the current frequency.

10. The method of claim 1, wherein, The method further comprises: detecting a fault of the bus and recording a fault duration of the bus; if the fault duration is less than a third threshold, continue to detect the fault of the bus; if the fault duration is greater than or equal to the third threshold and the fault prediction probability is greater than or equal to a second threshold, a link switching instruction is generated by the dynamic strategy engine and transmitted to the first controller to perform a link switching operation.

11. The method of claim 6, wherein, The target configuration parameter of the bus is updated by the first controller in response to the bus frequency reduction instruction, and the method comprises: The bus frequency reduction instruction is parsed by the protocol adaptation module to obtain a bus type; The corresponding target register is searched by the protocol adaptation module according to the bus type, and the configuration parameter field of the bus is read from the target register to obtain the current configuration parameter; In response to the bus frequency reduction instruction, the first controller updates a value of a frequency parameter of the bus from the current frequency to the target frequency.

12. An electronic device, comprising: comprises: a memory for storing a computer program; a processor for executing the computer program to implement the steps of the bus anomaly prediction and processing method according to any one of claims 1 to 11.

13. A computer-readable storage medium, characterized in that, The computer program is stored in the computer readable storage medium, and when the computer program is executed by the processor, the steps of the bus anomaly prediction and processing method according to any one of claims 1 to 11 are implemented.

14. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the bus anomaly prediction and processing method according to any one of claims 1 to 11.

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