Scheduling method of double data rate (DDR) command

Abstract

The embodiment of the invention provides a double data rate (DDR) command scheduling method, which comprises the following steps of: scheduling a DDR read command and a DDR write command through multi-stage arbitration on the basis of a double data rate (DDR) command time sequence constraint condition and adjoint information of the DDR read command and the DDR write command, and determining a priority ranking result of the DDR read command and the DDR write command; and outputting a DDR read command and a DDR write command in sequence according to a priority ranking result. Through the embodiment of the invention, the problem that read-write access may be delayed due to the fact that the DDR read command and the DDR write command are not reasonably scheduled in related technologies is solved, and the effect of reasonably and efficiently outputting the DDR read command and the DDR write command in unit time is achieved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of communications, and in particular to a method for scheduling double data rate (DDR) commands. Background Art

[0002] Double Data Rate Synchronous Dynamic Random-Access Memory (DDR SDRAM) refers to SDRAM storage technology that can transmit data on both the rising and falling edges of the clock signal, achieving a double data transfer rate. The development of SDRAM has gone through the stages of synchronous dynamic random access memory (SDR) and double data rate (DDR). Traditional SDR SDRAM only uses the rising edge of the clock for data transmission. For high-speed system-on-chip (SoC) chips, SDR SDRAM can no longer meet the system's data rate requirements for external storage. DDR SDRAM, on the other hand, uses both edges of the clock for data transmission, resulting in a bandwidth twice that of SDR SDRAM of the same specification, significantly supporting the system's bandwidth requirements. With its many excellent features, such as low latency, high speed, low power consumption, and low cost, DDR SRAM has become the preferred choice for high-speed peripheral storage systems in SoC systems.

[0003] The latest DDR SDRAM standard is JESD79-5B, released by the JEDEC Solid State Technology Association. DDR5 SDRAM boasts a data transmission speed of 6400Mbps. However, due to the physical structure and electrical characteristics of SDRAM, the JESD79-5B standard imposes numerous operational constraints on DDR systems regarding data read / write, data retention, and data integrity. These include, but are not limited to, requirements for the time interval between SDRAM access commands, periodic data maintenance requirements for SDRAM storage, and periodic calibration and training requirements for the data and command buses.

[0004] The JESD standard imposes strict usage constraints on DDR SDRAM, and given the complexity and uncertainty of SoC chip business scenarios, SoC design requirements for DDR controllers have been significantly increased. Achieving the maximum data rates specified in the JESD79-5B standard or maintaining high-bandwidth DDR data throughput for extended periods has become extremely difficult. Inadequate DDR controller performance can lead to data rate mismatches between external SDRAM storage and the CPU. Failure to receive timely SDRAM data responses forces the CPU into prolonged wait mode, limiting the full performance of the entire SoC. Summary of the Invention

[0005] An embodiment of the present application provides a method for scheduling double data rate (DDR) commands, to at least solve the problem in the related art of possible delays in read and write accesses due to a lack of reasonable scheduling of DDR read commands and DDR write commands.

[0006] According to one embodiment of the present application, a method for scheduling double data rate (DDR) commands is provided, comprising: scheduling the DDR read commands and DDR write commands through multi-level arbitration based on double data rate (DDR) command timing constraints and accompanying information of the DDR read commands and DDR write commands, determining priority ranking results for the DDR commands and DDR write commands; and outputting the DDR read commands and DDR write commands in sequence according to the priority ranking results.

[0007] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is configured to execute the steps in the above embodiment when running.

[0008] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to perform the steps in the above embodiment.

[0009] According to another embodiment of the present application, a computer program product is provided, including a computer program, which implements the steps in the above embodiment when executed by a processor.

[0010] Through the above-described embodiments of the present application, based on the double data rate (DDR) command timing constraints and the accompanying information of the DDR read and write commands, DDR read and write commands are rationally scheduled through multi-level arbitration, the priority ranking results of the DDR commands and DDR write commands are determined, and the DDR read and write commands are output in sequence according to the priority ranking results. Therefore, the problem of possible read and write access delays caused by the lack of rational scheduling of DDR read and DDR write commands in the related art can be solved, thereby achieving the effect of more rational and efficient output of DDR read and DDR write commands within a unit time. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 1 is a hardware structure block diagram of a computer terminal according to a method for scheduling double data rate DDR commands according to an embodiment of the present application;

[0012] Figure 2 1 is a schematic diagram of an implementation architecture of a method for scheduling double data rate DDR commands according to an embodiment of the present application;

[0013] Figure 3 is a flowchart of a method for scheduling double data rate DDR commands according to an embodiment of the present application;

[0014] Figure 4 1 is a structural block diagram of a scheduling device for double data rate DDR commands according to an embodiment of the present application;

[0015] Figure 5 is a block diagram of a DDR command unit according to an embodiment of the present application;

[0016] Figure 6 FIG. 4 is a flowchart of a method for scheduling double data rate (DDR) commands according to another embodiment of the present application. DETAILED DESCRIPTION

[0017] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0018] It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0019] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a computer terminal as an example, Figure 1 This is a hardware block diagram of the computer terminal running the method embodiment of this application. Figure 1 As shown, the computer terminal may include one or more ( Figure 1 Only one is shown) a processor 102 (the processor 102 may include but is not limited to a microprocessor MCU or a programmable logic device FPGA and other processing devices) and a memory 104 for storing data. The computer terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It will be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. For example, the computer terminal may also include Figure 1 More or fewer components than shown, or with Figure 1 Different configurations shown.

[0020] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the scheduling method of the double data rate DDR command in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implementing the above-mentioned method. The memory 104 may include a high-speed random access memory and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories can be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0021] The transmission device 106 is used to receive or transmit data via a network. A specific example of the aforementioned network may include a wireless network provided by a communications provider of a computer terminal. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0022] Figure 2 This is a schematic diagram of the architecture for implementing a double data rate (DDR) command scheduling method according to an embodiment of the present application. The method primarily includes modules such as an input interface, a task parameter delivery unit, a command optimization and scheduling unit, a command storage unit, a timing constraint unit, and an output interface. The command optimization and scheduling unit is the primary execution component of this embodiment, while the other units are required components to support the implementation of this method.

[0023] Input interface: mainly completes the reception of AXI read and write transactions, and stores the data to be calculated into the storage resource pool according to the task parameters for use by subsequent computing units.

[0024] Task parameter processing unit: This unit is responsible for configuring and issuing the parameters required by the address hash calculation unit and the command optimization scheduling unit to ensure the flexibility of the method.

[0025] Command Optimization Scheduling Unit: The command optimization scheduling unit is mainly based on the command timing constraints and bank status feedback from the timing constraint unit. Through a three-level arbitration process, it preferentially schedules activation, precharge, read, and write commands. This ensures that the commands meet the DDR command time interval requirements while maximizing the read and write utilization of the dedicated full-speed interface (DFI) bus, improving data throughput and reducing read and write access latency.

[0026] Command storage unit: This unit maps Advanced eXtensible Interface (AXI) read and write transaction addresses to SDRAM physical addresses, converts AXI read and write transactions into DDR read and write commands, stores DDR read and write commands pointing to different SDRAM physical addresses, and outputs them to the command dispatch unit.

[0027] Command timing constraint unit: The command timing constraint unit mainly receives the DDR command currently scheduled to the DFI port, calculates the time when the next valid command can be executed based on the execution time of the current command, and calculates the activation and deactivation status of each bank at the same time, and feeds back the command timing constraint and bank status information to the command optimization scheduling unit.

[0028] Output interface: The output interface mainly sends the DDR commands scheduled by the command scheduling optimization unit to the DFI interface and timing constraint unit to send the DDR commands to the post-processing stage and calculate the timing constraints related to the DDR commands.

[0029] In this embodiment, a method for scheduling double data rate DDR commands running on the above-mentioned computer terminal or architecture is provided. Figure 3 FIG. 1 is a flow chart of a method for scheduling a double data rate DDR command according to an embodiment of the present application. Figure 3 As shown, the process includes the following steps:

[0030] Step S302, scheduling the DDR read command and the DDR write command through multi-level arbitration based on the double data rate DDR command timing constraint and the command information of the DDR read command and the DDR write command, and determining the priority ranking result of the DDR read command and the DDR write command;

[0031] It's important to note that a DDR read command is a request from a computer system to read data from DDR memory, while a DDR write command is an instruction from a computer system to write data to DDR memory. DDR read and write commands are fundamental components of memory operations and are crucial for ensuring that data is transferred correctly and efficiently between the processor and memory.

[0032] In an exemplary embodiment of the present application, the command information includes at least one of the following: row hit information, row miss information, address conflict information, and timeout information.

[0033] In an exemplary embodiment of the present application, DDR read commands and DDR write-related commands are scheduled through multi-level arbitration, including: performing first-level arbitration on the DDR read commands and DDR write commands to determine whether the DDR read commands and DDR write commands meet the timing requirements of the DDR synchronous dynamic random access memory; performing second-level arbitration on the DDR read commands and DDR write commands that meet the timing requirements of the DDR synchronous dynamic random access memory, and performing first priority sorting according to command information of the DDR read commands and DDR write commands; performing third-level arbitration on the DDR read commands and DDR write commands that are sorted by the first priority, and performing second priority sorting according to the command information of the DDR read commands and DDR write commands, and outputting the sorted DDR read commands and DDR write commands to the data transmission interface.

[0034] In an exemplary embodiment of the present application, a first-level arbitration is performed on a DDR read command and a DDR write command to determine whether the DDR read command and the DDR write command meet the timing requirements of the DDR synchronous dynamic random access memory, including: determining a DDR read command that meets the timing requirements of the DDR synchronous dynamic random access memory, an activate command and a precharge command sent for a row miss read transaction as DDR read-related commands; and determining a DDR write command that meets the timing requirements of the DDR synchronous dynamic random access memory, and an activate and precharge commands sent for a row miss write transaction as DDR write-related commands.

[0035] In an exemplary embodiment of the present application, a second-level arbitration is performed on DDR read commands and DDR write commands that meet the timing requirements of DDR synchronous dynamic random access memory, and a first priority sorting is performed according to the command information of the DDR read commands and DDR write commands, including: determining whether there is an address conflicting command, and if the determination result is yes, outputting the address conflicting command for a third-level arbitration; if the determination result is no, determining whether there is a timed-out command, and if the determination result is yes, outputting the timed-out command for a third-level arbitration; if the determination result is no, determining whether there is a row hit command, and if the determination result is yes, outputting the row hit command for a third-level arbitration; if the determination result is no, outputting a row miss command for a third-level arbitration; if there are multiple row miss commands, outputting an activate command, otherwise outputting a precharge command for a third-level arbitration.

[0036] In an exemplary embodiment of the present application, a third-level arbitration is performed on the DDR read commands and DDR write commands that are sorted with the first priority, and a second priority sorting is performed based on the command information of the DDR read commands and the DDR write commands, and the sorted DDR read commands and the DDR write commands are output to the data transmission interface, including: judging whether there is an address conflict command, and giving priority to inputting the address conflict command if the address conflict command judgment result is yes, and giving priority to scheduling the command that enters the command storage unit earliest if both the read and write commands are address conflict commands; judging whether there is a timed-out command if the address conflict command judgment result is no, and outputting the timed-out command if the judgment result is yes, and giving priority to scheduling the timed-out read command if both the read and write commands have timed out; judging whether there is a row hit read or write command if the judgment result is no, and outputting the row hit command if the judgment result is yes, and scheduling according to the attributes of the last executed command if both the read and write commands are row hits; and judging whether there is a row hit command if the row hit judgment result is no, and giving priority to outputting the activation command issued due to the row miss, followed by the precharge command if both the read and write commands are row miss commands.

[0037] In an exemplary embodiment of the present application, based on the double data rate DDR command timing constraints and the command information of the DDR read command and the DDR write command, before scheduling the DDR read command and the DDR write command through multi-level arbitration, it also includes: receiving advanced extensible interface AXI read and write transactions, and converting the AXI read and write transactions to generate DDR read commands and DDR write commands, and obtaining the command information of the DDR read command and the DDR write command.

[0038] Step S304: outputting DDR read commands and DDR write commands in sequence according to the priority sorting result.

[0039] In an exemplary embodiment of the present application, after outputting the DDR read command and the DDR write command in sequence according to the priority sorting result, the method further includes: calculating the timing constraints of the DDR read command and the DDR write command.

[0040] Through the embodiments of the present application, multi-level arbitration scheduling of DDR read and write commands improves DDR data throughput and reduces read and write access latency. At the same time, the embodiments of the present application are highly configurable and versatile to adapt to different application scenarios and the continuous evolution of protocols.

[0041] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0042] This embodiment also provides a double data rate (DDR) command scheduling device, which is used to implement the above-mentioned embodiments and preferred embodiments. Details already described will not be repeated here. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0043] Figure 4 FIG. 1 is a block diagram of a scheduling device for a double data rate DDR command according to an embodiment of the present application. Figure 4 As shown, the device includes a determination module 10 and an output module 20:

[0044] a determination module 10 for scheduling the DDR read commands and the DDR write commands through multi-level arbitration based on the double data rate (DDR) command timing constraint conditions and accompanying information of the DDR read commands and the DDR write commands, and determining a priority ranking result of the DDR read commands and the DDR write commands;

[0045] The output module 20 is configured to output DDR read commands and DDR write commands in sequence according to the priority sorting result.

[0046] It should be noted that the above modules can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0047] In order to facilitate the understanding of the technical solutions provided by the application embodiments, the embodiments are described below in conjunction with specific scenarios.

[0048] With the rapid development of mobile electronics, consumers are increasingly concerned about the performance of SoC chips. DDR is currently the most widely used, highest-performance, and lowest-cost high-speed, large-capacity dynamic data storage technology. However, processors in SoC systems are placing increasingly stringent demands on the data transfer rate and latency of high-speed memory. This can lead to overall performance degradation in SoC systems as processors wait for DDR data.

[0049] To meet these requirements, the present invention proposes a DDR read and write command optimization method. By more rationally scheduling read and write command storage within the DDR controller, the DFI bus can be fully utilized, reducing unnecessary command read and write interval overhead. Therefore, for business scenarios with high requirements for data bandwidth and data latency, such as high-definition video analysis, large-scale gaming, real-time communications, advanced environmental awareness computing, and intelligent driving, the proposed method can significantly improve the bandwidth utilization of the DDR system, increase data throughput, reduce access latency, and thus support SoC systems in processing large amounts of data and improve system performance.

[0050] Figure 5 DDR command unit block diagram according to an embodiment of the present application, such as Figure 5 As shown, the command scheduling unit includes first-level arbitration, second-level arbitration, and third-level arbitration. The first-level arbitration includes read / write timing arbitration and activation / precharge timing arbitration; the second-level arbitration includes read command priority arbitration, write command priority arbitration, and activation / precharge priority arbitration; and the third-level arbitration includes priority arbitration between read and write commands. Read / write commands, accompanying read / write command information, command scheduling configuration parameters, and command timing constraints are input into the command scheduling unit, which then outputs read / write commands and activate / precharge commands.

[0051] Figure 6 FIG. 1 is a flow chart of a method for scheduling double data rate DDR commands according to another embodiment of the present application. Figure 6 As shown, the process includes the following steps:

[0052] In step S601, after the DDR controller is powered on and reset, the high-level software writes the initialization configuration required for the DDR controller to work into the corresponding register through the external interface. After the register is written, it is reset and released.

[0053] Step S602, determine whether there is an AXI read / write transaction currently. If so, proceed to step S603; otherwise, wait for the arrival of the AXI transaction.

[0054] In step S603, the AXI read / write transaction enters the command parsing unit, which parses it into a DDR read / write command. This command includes the SDRAM physical address information (rank, bank, row, and column addresses), as well as accompanying transaction information (row hit, row miss, address conflict, priority, and timeout information). The DDR read command and command information enter the DDR read transaction storage unit, while the DDR write command and command information enter the DDR write transaction storage unit. The process then proceeds to step S604.

[0055] In step S604, for read or write commands that hit a row, the transaction storage unit sends them to the command dispatch unit as directly executable DDR read or write commands. For read or write commands that miss a row, if the current bank does not have an activated row, an activate command is sent to that bank. If another row in the current bank has been activated, a precharge command is sent to that bank. The process then proceeds to step S605.

[0056] In step S605, the precharge command, activation command, read command, and write command output by the read transaction storage unit and the write transaction storage unit for executing different SDRAM physical addresses are sent to the command optimization scheduling unit for first-level arbitration. Commands that do not meet the DDR SDRAM timing requirements will remain in the first-level arbitration stage until they meet the timing requirements and enter the second-level arbitration. Read commands that meet the DDR SDRAM timing requirements, as well as activation and precharge commands sent for row-miss read transactions, are called read-related commands. Write commands that meet the DDR SDRAM timing requirements, as well as activation and precharge commands sent for row-miss transactions, are called write-related commands. The read-related commands and write-related commands are sent to the command optimization scheduling unit for step S606.

[0057] In step S606, all read and write commands that meet the DDR SDRAM timing requirements are prioritized based on their command information and then subjected to second-level arbitration. First, a determination is made as to whether any commands have an address conflict. If so, the address conflicting command is prioritized. Second, a determination is made as to whether any commands have timed out, meaning that the waiting time in the memory cell for scheduling has exceeded a set threshold. If so, the timed-out command is prioritized. Third, a determination is made as to whether any commands have a row hit. If so, the row hit command is prioritized; otherwise, a row miss command is prioritized. Finally, if multiple row miss commands exist, an activate command is prioritized, meaning that no row in the bank targeted by the command exists. Otherwise, a precharge command is prioritized, meaning that other rows in the bank targeted by the command exist. The output read and write commands are sent to the third-level arbitration, and the process proceeds to step S607.

[0058] Step S607: The read and write commands output after the second-level arbitration are prioritized again based on their command information, and then a third-level arbitration is performed. First, a determination is made as to whether there are address-conflicting commands. If so, the address-conflicting command is prioritized. If both the read and write commands are address-conflicting commands, the command that entered the command storage unit earliest is prioritized. Second, a determination is made as to whether there are timed-out commands, i.e., the time a read or write command has waited in the storage unit for scheduling exceeds a set threshold. If so, the timed-out command is prioritized. If both the read and write commands have timed out, the timed-out read command is prioritized. Third, a determination is made as to whether there are row-hit read and write commands. If so, the row-hit command is prioritized. If both the read and write commands are row-hit, scheduling is performed based on the attributes of the last executed command. If the last executed command was a read command, the read command is prioritized; otherwise, the write command is prioritized. Finally, if both the read and write commands are row-miss commands, the activate command issued due to the row-miss is prioritized, followed by the precharge command. If all read and write related commands that do not hit the row are activation commands or precharge commands, they are scheduled according to the attributes of the last executed command. If the last executed command is a read command, the read command is scheduled; otherwise, the write command is scheduled, and the process goes to step S608.

[0059] Step S608: Output the DDR read and write related commands to the DFI interface, wait for the response from the subsequent module, and complete the optimized scheduling of the read and write commands.

[0060] Finally, it should be noted that the above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art may still modify the technical solutions described in the aforementioned embodiments or substitute equivalents for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

[0061] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above method embodiments when run.

[0062] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0063] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0064] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0065] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0066] The JESD79-5B standard specifies the timing constraints that DDR command execution must follow, including sending an activation command to activate the corresponding row before executing a read or write command. If there is an activated row in the bank, a precharge command must be sent first to close the activated bank before sending the activation command. For read and write commands pointing to the same or different bank groups or banks, there are also different time interval requirements between the previous and subsequent commands. In addition, the standard also specifies additional command time interval requirements for the continuous sending of read commands and write commands. Therefore, the embodiment of the present application proposes a DDR read and write command optimization scheduling method. Through a three-level arbitration method, while meeting the DDR command timing constraints, as many read and write commands as possible are sent to the DFI bus per unit time, reducing the idleness of the DFI data bus caused by the precharge command and the activation command, avoiding the frequent read and write command conversion that causes the command interval to become larger, fully improving the utilization rate of the DFI command bus and the data bus, and increasing the data access bandwidth of the DDR.

[0067] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0068] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A method for scheduling double data rate (DDR) commands, characterized in that: include: Based on a double data rate (DDR) command timing constraint condition and command information of a DDR read command and a DDR write command, scheduling the DDR read command and the DDR write command through multi-level arbitration to determine a priority ranking result of the DDR read command and the DDR write command; The DDR read command and the DDR write command are output in sequence according to the priority sorting result.

2. The method according to claim 1, characterized in that The command information includes at least one of the following: row hit information, row miss information, address conflict information and timeout information.

3. The method according to claim 2, characterized in that The scheduling of the DDR read command and the DDR write-related command through multi-level arbitration includes: Performing a first-level arbitration on the DDR read command and the DDR write command to determine whether the DDR read command and the DDR write command meet the timing requirements of the DDR synchronous dynamic random access memory; performing a second-level arbitration on the DDR read command and the DDR write command that meet the timing requirement of the DDR synchronous dynamic random access memory, and performing a first priority sorting according to the command information of the DDR read command and the DDR write command; A third-level arbitration is performed on the DDR read command and the DDR write command that are sorted with the first priority, a second-priority sorting is performed according to the command information of the DDR read command and the DDR write command, and the sorted DDR read command and the DDR write command are output to the data transmission interface.

4. The method according to claim 3, characterized in that Performing a first-level arbitration on the DDR read command and the DDR write command to determine whether the DDR read command and the DDR write command meet the timing requirements of the DDR synchronous dynamic random access memory, including: Determining the DDR read command that meets the timing requirement of the DDR synchronous dynamic random access memory, the activate command and the precharge command sent for the row miss read transaction as DDR read-related commands; The DDR write command that meets the timing requirement of the DDR synchronous dynamic random access memory and the activate and precharge commands sent for the row miss write transaction are determined as DDR write-related commands.

5. The method according to claim 4, characterized in that The method further comprises: performing a second-level arbitration on the DDR read command and the DDR write command that meet the timing requirement of the DDR synchronous dynamic random access memory, and performing a first priority sorting according to command information of the DDR read command and the DDR write command, including: a command to determine whether there is an address conflict, and if the determination result is yes, outputting a command indicating that there is an address conflict to perform a third-level arbitration; If the judgment result is no, determining whether there is a timed-out command, and if the judgment result is yes, outputting the timed-out command to perform a third-level arbitration; If the judgment result is negative, determining whether there is a row-hit command, and if the judgment result is positive, outputting the row-hit command for third-level arbitration; If the judgment result is negative, a row miss command is output to perform third-level arbitration; In the case that there are multiple row miss commands, the activate command is output; otherwise, the precharge command is output to perform the third-level arbitration.

6. The method according to claim 4, characterized in that The method further comprises: performing a third-level arbitration on the DDR read command and the DDR write command that have been sorted with the first priority, performing a second-priority sorting according to command information of the DDR read command and the DDR write command, and outputting the sorted DDR read command and the DDR write command to a data transmission interface, including: Determine whether there is an address conflict command. If the address conflict command judgment result is yes, give priority to inputting the command with address conflict. If both read and write commands are address conflict commands, give priority to scheduling the command that enters the command storage unit earliest. If the address conflict command is judged as no, determine whether there is a timed-out command. If so, output the timed-out command. If both the read and write commands are timed out, prioritize the timed-out read command. If the timeout command is judged as negative, determine whether there is a read or write command that is hit in the row. If the judgment result is yes, output the command that is hit in the row. If both the read and write commands are hit in the row, schedule according to the attributes of the last executed command. When the row hit judgment result is negative, and both the read command and the write command are row miss commands, the activate command issued due to the row miss is output first, followed by the precharge command.

7. The method according to claim 1, characterized in that Before scheduling the DDR read command and the DDR write command through multi-level arbitration based on the double data rate DDR command timing constraint condition and the command information of the DDR read command and the DDR write command, the method further includes: An advanced extensible interface (AXI) read / write transaction is received, and the AXI read / write transaction is converted into a DDR read command and a DDR write command, and the command information of the DDR read command and the DDR write command is obtained.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 7 are implemented.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

Images