Data transmission system and implementation method for communicating with FPGA (Field Programmable Gate Array) by using USB (Universal Serial Bus) interface module

Abstract

The invention relates to the technical field of FPGA digital design, in particular to a data transmission system and an implementation method for using a USB interface module to communicate with an FPGA, the system comprises an upper computer, the FPGA, the USB interface module and N SPI host interfaces, and the upper computer uses the USB interface module to establish a bidirectional communication link with the FPGA so as to use the USB interface module to read a register of the FPGA to control the working state of the FPGA. According to the data transmission system provided by the invention, the two-way communication link between the upper computer and the FPGA is established by using the USB interface module, and compared with the scheme of integrating an SOC in the prior art, the communication link can be effectively simplified, the power consumption of equipment can be reduced, and the communication link can be conveniently and quickly constructed so as to facilitate the expansion of FPGA functions and use scenes.

Description

Technical Field

[0001] The present invention relates to the field of FPGA digital design technology, and in particular to a data transmission system and a method for implementing communication between a USB interface module and an FPGA. Background Art

[0002] In existing technologies, hybrid architectures of SoC (system-on-chip) and FPGA, such as Xilinx ZYNQ, can directly control FPGA devices through high-level languages ​​​​such as C / C++ or Python programming, achieving efficient processing of software and hardware collaboration. However, although this solution excels in performance and flexibility, its high implementation cost limits its popular application in certain scenarios. On the other hand, for some application scenarios, users only need to enable the host computer (such as PC) to communicate with the FPGA quickly and efficiently through a USB interface or other high-speed interfaces. In this case, the solution of using SoC+FPGA appears too complex and bloated, and the addition of an SoC unit will also bring additional power consumption burden.

[0003] In addition, there are many bus and USB conversion methods and devices in the prior art. For example, by converting the bus commands of the chip system into USB format, the external model can receive these commands through USB and perform reverse conversion when returning the status word, or further converting the USB interface generated by the FPGA into a target interface, and using a microcontroller chip with an integrated USB3.0 interface to realize data transmission between the FPGA and the host computer.

[0004] However, the above methods mainly focus on ultra-high-speed transmission of large amounts of data, and their implementation methods are relatively simple, and the cost and power consumption are relatively high. Summary of the Invention

[0005] In view of this, an object of the present invention is to provide a data transmission system and an implementation method for communicating with an FPGA using a USB interface module.

[0006] In a first aspect, an embodiment of the present invention provides a data transmission system, comprising: a host computer, an FPGA, a USB interface module, and an N-channel SPI host interface. The host computer uses the USB interface module to establish a bidirectional communication link with the FPGA, and uses the USB interface module to read / write FPGA registers to control the working state of the FPGA. The N-channel SPI host interface is integrated into the FPGA, and each SPI host interface is connected to the SPI slave interface of the fingerprint chip via an independent SPI bus, thereby realizing the configuration control of the multi-channel fingerprint chip by the FPGA.

[0007] Wherein, N is an integer greater than 1.

[0008] In combination with the first aspect, the FPGA obtains the fingerprint image data collected by the fingerprint chip through the SPI host interface and caches it in the FPGA internal buffer;

[0009] When the amount of cached data reaches a preset threshold, the FPGA uses the USB interface module to send data packets to the host computer in batch transfer mode.

[0010] Combined with the first aspect, the host computer uses the USB interface module to send the FPGA firmware to the FPGA and the external SPIFlash to achieve OTA online upgrade.

[0011] In combination with the first aspect, the FPGA is also connected to the SPI Flash through the SPI Flash interface. The host computer reads the status register of the FPGA. When the status register indicates that the remaining space of the FPGA temporary memory of the SPI Flash does not meet the write conditions, data writing is suspended until the remaining space of the FPGA temporary memory of the SPI Flash meets the write conditions and then continues to write data.

[0012] In conjunction with the first aspect, the SPI Flash further includes a background image storage area for storing background image data associated with the fingerprint chip;

[0013] The host computer writes image data to the background image storage area through the USB interface module and FPGA;

[0014] When the background image read instruction is triggered, data is extracted from the background image storage area and returned using the USB interface module.

[0015] In a second aspect, the present application provides a method for implementing communication with an FPGA via a USB interface, characterized in that, when applied to the system as described above, the method comprises:

[0016] The host computer uses the USB interface module to send register read and write instruction packets to the FPGA;

[0017] FPGA parses the read and write instruction packets and obtains the instruction type of the read and write instruction packets;

[0018] If it is a write register instruction, the target register value is updated to control the communication parameters of the specified SPI host interface;

[0019] If it is a register read instruction, read the target register value and encapsulate it into a return data packet;

[0020] Use the USB interface module to send return data packets to the host computer in real time.

[0021] In conjunction with the second aspect, the method further includes:

[0022] FPGA receives image data collected by fingerprint chip through SPI host interface;

[0023] Cache the image data into the FPGA internal buffer and count the accumulated data volume;

[0024] When the accumulated data volume reaches the preset threshold, the USB interface module batch transmission mechanism is triggered to send the data packets to the host computer.

[0025] In conjunction with the second aspect, the method further includes:

[0026] The host computer uses the USB interface module to send firmware data packets to the FPGA;

[0027] FPGA temporarily stores the firmware data in the firmware data packet and then writes it to SPI Flash;

[0028] The FPGA detects the remaining space of the SPI Flash temporary storage in real time and updates the status register;

[0029] The host computer reads the status register value:

[0030] If the remaining space is less than the threshold, data sending is suspended.

[0031] In conjunction with the second aspect, the method further includes:

[0032] The host computer sends an SPI configuration instruction packet to the FPGA, specifying the target channel number and configuration parameters;

[0033] The FPGA writes the configuration parameters to the control register of the target SPI host interface corresponding to the target channel number;

[0034] The target SPI host interface establishes communication with the fingerprint chip according to the configuration parameters.

[0035] In conjunction with the second aspect, the method further includes:

[0036] The host computer uses the USB interface module to send SPI Flash access instructions to the FPGA;

[0037] If the SPIFlash access instruction is a background image read instruction, data is read from the SPIFlash and returned to the host computer using the USB interface module.

[0038] The embodiments of the present invention bring the following beneficial effects: The present application provides a data transmission system and an implementation method for communicating with an FPGA using a USB interface module. The system includes: a host computer, an FPGA, a USB interface module, and an N-channel SPI host interface. The host computer uses the USB interface module to establish a bidirectional communication link with the FPGA, so as to use the USB interface module to read the registers of the FPGA to control the working state of the FPGA; the N-channel SPI host interface is integrated into the FPGA, and each SPI host interface is connected to the SPI slave interface of the fingerprint chip via an independent SPI bus, thereby realizing the configuration control of the multi-channel fingerprint chip by the FPGA; wherein N is an integer greater than 1.

[0039] The data transmission system provided in this application uses a USB interface module to establish a two-way communication link between the host computer and the FPGA. Compared with the solution of integrating SOC in the existing technology, it can effectively simplify the communication link, reduce the power consumption of the equipment, and conveniently and quickly build the communication link to facilitate the expansion of FPGA functions and usage scenarios.

[0040] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purposes and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0041] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0043] Figure 1 A schematic diagram of the structure of a data transmission system provided by an embodiment of the present invention;

[0044] Figure 2 A flowchart of a method for implementing communication between a USB interface module and an FPGA provided in an embodiment of the present invention;

[0045] Figure 3 A schematic diagram showing a host computer using a USB interface module to write register values ​​to an FPGA according to an embodiment of the present invention;

[0046] Figure 4A schematic diagram of a host computer using a USB interface module to read register values ​​from an FPGA according to an embodiment of the present invention;

[0047] Figure 5 The host computer provided in the embodiment of the present invention uses the USB interface module to configure the fingerprint chip connected to the FPGA for debugging and recording printing information;

[0048] Figure 6 The host computer provided in the embodiment of the present invention uses the USB interface module to configure the fingerprint chip connected to the FPGA for debugging and recording printing information;

[0049] Figure 7 A schematic diagram of specific data corresponding to the editor of the fingerprint image provided by an embodiment of the present invention;

[0050] Figure 8 A diagram showing the speed of testing the USB interface module for reading image data. DETAILED DESCRIPTION

[0051] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work shall fall within the scope of protection of the present invention.

[0052] To facilitate understanding of this embodiment, the following is a brief introduction to the technical terms used in this application.

[0053] An FPGA (Field-Programmable Gate Array) is a logic device that can be programmed on-site. It is essentially an integrated circuit chip consisting of a large number of programmable logic cells, input / output modules, and programmable interconnect resources.

[0054] SPI Flash is a flash memory storage device that operates through a serial peripheral interface (SPI). It uses the SPI communication protocol to exchange data with a host controller and is widely used in embedded systems.

[0055] After introducing the technical terms involved in this application, the application scenarios and design concepts of the embodiments of this application are briefly introduced.

[0056] Existing methods and devices for converting between various buses and USB mainly focus on large-scale data transmission. Their implementation methods are relatively simple, and their costs and power consumption are relatively high.

[0057] Based on this, an embodiment of the present application provides a data transmission system and an implementation method for communicating with an FPGA using a USB interface module.

[0058] Example 1

[0059] This application provides a data transmission system, combined with Figure 1 As shown, the system includes: a host computer, FPGA, USB interface module and N-channel SPI host interface.

[0060] The host computer uses the USB interface module to establish a bidirectional communication link with the FPGA to read the registers of the FPGA using the USB interface module to control the working status of the FPGA.

[0061] N SPI host interfaces are integrated into the FPGA. Each SPI host interface is connected to the SPI slave interface of the fingerprint chip through an independent SPI bus, realizing the configuration control of the multi-channel fingerprint chip by the FPGA; where N is an integer greater than 1.

[0062] In this embodiment, the host computer uses a USB interface module to achieve fast communication with the FPGA. Leveraging the USB interface module's rapid and convenient communication, the FPGA can be conveniently and effectively utilized, significantly expanding its use cases and capabilities. Compared to existing approaches that integrate SOCs, this approach simplifies the communication link, reduces power consumption, and facilitates rapid and cost-effective communication link establishment.

[0063] In this embodiment, the USB interface module can be divided into USB1.1, USB2.0, and USB3.x based on its different data transmission speeds. The fastest communication speed can reach USB3.0's 5Gbps, which is close to 500M bytes / second. As an example, Nanjing Qinheng's USB2.0 conversion chip ch346 can be used, with the fastest communication speed reaching 30M bytes / second. Among them, the host computer software programming can use C / C++ and is controlled and implemented through the SDK API interface provided by the manufacturer. The present invention uses the Python scripting language and a DLL library written in C / C++ to achieve control and data transmission of the FPGA device via USB.

[0064] A simple protocol is used between the host computer and the FPGA, and data is transmitted through the USB interface module, enabling the host computer to read / write register control on the FPGA side, thereby realizing the control of multiple channels of fingerprint chips. In this embodiment, the fingerprint chip has C channels. The configuration of the fingerprint chip with these C channels is controlled by connecting to the SPI interface provided by the fingerprint chip. The FPGA side implements a 13-channel SPI fingerprint chip interface (here, the SPI Master host interface, the FPGA side is the master, and the fingerprint chip side SPI Slave is the slave). The control of the SPI host logic on the FPGA side is achieved by using the USB interface module to read / write the registers of each SPI host interface implemented on the FPGA, thereby communicating with the N-channel SPI host interface. Wherein, N ≥ C, for example, in this embodiment, N = 13, C = 12.

[0065] In combination with the first aspect, the FPGA obtains the fingerprint image data collected by the fingerprint chip through the SPI host interface and caches it in the FPGA internal buffer;

[0066] When the amount of cached data reaches a preset threshold, the FPGA uses the USB interface module to send data packets to the host computer in batch transfer mode.

[0067] The image data generated by the fingerprint chip does not need to go through the custom protocol, but is directly sent to the host computer using the USB interface module. The specific data is sent in batches, which can improve the utilization of USB bandwidth and thus increase the transmission speed of large amounts of image data.

[0068] The specific implementation method is as follows: when the FPGA is sending image data, it waits until the data reaches a certain number (for example, 512 bytes) before initiating the USB interface module's transmission. Conversely, when sending data to read register values, the USB interface module immediately initiates the transmission process to send the data. The data volume (image data is typically large) and the fingerprint chip's status after collecting fingerprint information can be used to determine whether the current transmission is image data (when the fingerprint chip completes collection, its status register may set certain flags to indicate that the current transmission is image data).

[0069] Combined with the first aspect, the host computer uses the USB interface module to send the FPGA firmware to the SPIFlash external to the FPGA to achieve OTA online upgrade.

[0070] In the prior art, upgrading via the JTAG interface usually requires a dedicated FPGA programming tool, which is generally not user-friendly and convenient, and does not support OTA online upgrades. In this application, a USB interface module is used to send the FPGA firmware file to the FPGA's temporary storage space, thereby achieving remote firmware updates without the need for a physical connection to the programmer.

[0071] The data here is also large, and the FPGA generally receives 512 bytes of data at a time, which makes the transmission speed very fast. Generally, the write speed of SPIFlash is much slower than the transmission speed of the USB interface module. This ensures that on a device like an FPGA with a small storage space (usually SRAM), the upgrade firmware data, which exceeds its storage space by many times, can be written efficiently and completely to the SPI Flash connected to the FPGA itself.

[0072] In combination with the first aspect, the FPGA is also connected to the SPI Flash through the SPI Flash interface. The host computer reads the status register of the FPGA. When the status register indicates that the remaining space of the FPGA temporary memory of the SPI Flash does not meet the write conditions, data writing is suspended until the remaining space of the FPGA temporary memory of the SPI Flash meets the write conditions and then continues to write data.

[0073] When the FPGA write space is full, the host computer obtains this information by reading the register on the FPGA. The host computer then stops writing data and waits until it reads that there is enough FPGA write space, such as one Flash page (a Flash page is generally 256 bytes), before continuing to start writing.

[0074] In combination with the first aspect, the SPI Flash includes a background image storage area for storing background image data associated with the fingerprint chip; the host computer writes image data to the background image storage area through the USB interface module and FPGA; when the background image read instruction is triggered, data is extracted from the background image storage area and returned using the USB interface module.

[0075] In this embodiment, the SPI Flash memory chip also stores background image data related to the fingerprint chip, making full use of the SPI Flash storage space. The background image data can be saved to the SPI Flash or read back from the SPI Flash using a USB interface module. Reading using the USB interface module is similar to writing during an OTA upgrade, also utilizing the small amount of storage space on the FPGA. The only difference is that the data flow is reversed, with the SPI Flash being read. A pause and wait operation similar to that used for sending fingerprint image data is also employed. When sending background image data stored in the SPI Flash, the USB interface module is activated only after the data reaches a certain size (e.g., 512 bytes). This improves the data transmission speed of the USB interface module.

[0076] It is understandable that in actual application, the USB interface module does not specifically use a certain device from a certain manufacturer, and it is also possible to use a solution that implements the USB2.0 interface protocol inside the FPGA. For example, although the ch346 solution of Nanjing Qinheng is used here, it has also been tested to directly use Gaoyun's FPGA, use its FPGA embedded LVDS to USB solution, and then implement the USB2.0 interface protocol inside the FPGA, which can also communicate. In addition, this embodiment only considers small-package FPGAs, small-package ch346s, and a small number of fingerprint chips (for example, 4 fingerprint chips). Then, the circuit board and the device can be made to be approximately 25mm×25mm in size to meet the small size requirements of the device.

[0077] Furthermore, any FPGA model can be used, using an external USB phy like the FPGA + ulpi phy, or implementing the USB 2.0 interface protocol internally within the FPGA. For example, a solution using the Unigroup Tongchuang PGL22G + Microchip's USB3300 ulpi phy can be used. It's worth noting that these USB module implementations are relatively affordable. For example, the Qinheng ch346 offers low volume pricing and speeds of approximately 30M bytes / second.

[0078] Next, a function is implemented here to debug a specific SPI bus interface by reading and writing registers. If all 13 SPI interfaces are to be debugged simultaneously in the FPGA, virtually every FPGA manufacturer provides online debugging capabilities. This is generally not possible because online debugging requires SRAM memory, and 13 SPI interfaces would take up a significant amount of space. Therefore, a register can be written to set a specific SPI interface as debugged. This debug information is then added to the FPGA's online debugging function, allowing for convenient debugging of each SPI interface. Simply write the SPI interface to be debugged into the register.

[0079] In a second aspect, the present application provides a method for communicating with an FPGA via a USB interface, which is applied to the system described above. Figure 2 As shown, the method includes:

[0080] S110: The host computer uses the USB interface module to send a register read and write instruction packet to the FPGA.

[0081] S120, FPGA parses the read / write instruction packet and obtains the instruction type of the read / write instruction packet.

[0082] S130: If it is a write register instruction, update the target register value to control the communication parameters of the specified SPI host interface.

[0083] S140, if it is a register read instruction, read the target register value and encapsulate it into a return data packet;

[0084] S150: Use the USB interface module to send a return data packet to the host computer in real time.

[0085] Combine Figure 3As shown, here wire_cs_n, wire_addr, usb_data, data_oe, wire_rdne_n, wire_wrnf_n, wire_wr_n, and wire_rd_n are dedicated signals of the Qinheng ch346 passive parallel port bus, where wire_cs_n indicates that the input chip select signal is valid at a low level and is used to control whether the peripheral participates in the communication; wire_addr indicates the input register address, which is used to specify the target register for reading and writing; usb_data indicates a bidirectional USB data channel for transmitting commands or status data; data_oe indicates the output data bus direction control, which is used to control whether usb_data is input or output; wire_rdne_n indicates the input receiving FPGA FIFO unit non-empty flag, which is used to determine whether there is data to read; wire_wrnf_n indicates the input sending FPGA FIFO unit non-full flag, which is used to determine whether new data can be written; wire_wr_n indicates the input write enable signal, which is used to start a write operation; wire_rd_n indicates the input read enable signal, which is used to start a read operation.

[0086] This indicates that USB data is being operated according to their preset protocol requirements, and that the USB interface module and FPGA can now communicate.

[0087] The following rx_vld is the receive data valid signal. Each pulse represents the receipt of a byte of data. rx_data represents the data received via USB in byte units. For example, this represents the receipt of 6 consecutive bytes of data: 0xaa 0x55 0x00x22 0x16 0xdd . The following wr is the write register signal. Each pulse writes a register. addr is the register address being written, and wr_data is the value being written to the register.

[0088] It's worth noting that the register value and address are both 16 bits wide. The timing diagram here shows a complete register write operation, ultimately writing data with a value of 0x16dd to the FPGA register at address 0x22.

[0089] Similarly, combined Figure 4The following diagram shows the timing diagram for reading FPGA registers through the USBA interface. cmd_txen indicates the data write valid signal to the USB interface module. Each pulse writes one piece of data. Four consecutive valid pulses indicate that four pieces of data are written in one burst. tx_data is the data being written, in 8-bit byte units. rd indicates the read valid signal. rd_data is the data being read. Since the register is being read, it is also 16-bit wide. addr indicates the register address being read, also 16-bit wide. You can see that the value read from register address 0x27 is 0xc000, which is returned to the host computer via the USB interface module.

[0090] In conjunction with the second aspect, the method further includes:

[0091] S210, FPGA receives image data collected by the fingerprint chip through the SPI host interface.

[0092] S220, cache the image data into the internal buffer of the FPGA and count the accumulated data volume.

[0093] S230, when the accumulated data volume reaches a preset threshold, the USB interface module batch transmission mechanism is triggered to send the data packet to the host computer.

[0094] As you can understand, the FPGA's internal buffer is the FIFO unit mentioned above. Image data collected by the fingerprint chip is cached in the FIFO unit, using a first-in-first-out method to mitigate the difference in the rate of receiving and reading fingerprint data. By sending data in batches, the USB interface module's bandwidth utilization is improved, thereby improving the transmission efficiency of large amounts of image data. The preset threshold is 512 bytes.

[0095] In conjunction with the second aspect, the method further includes:

[0096] S310: The host computer sends a firmware data packet to the FPGA using the USB interface module.

[0097] S320, the FPGA writes the firmware data in the firmware data packet into the temporary storage space and then writes it into the SPI Flash.

[0098] S330: The FPGA detects the remaining temporary storage space of the SPI Flash in real time and updates the status register.

[0099] S340, the host computer reads the status register value.

[0100] S350: If the remaining space is less than the threshold, suspend data transmission.

[0101] S360: If the remaining space is greater than or equal to the threshold, continue sending data.

[0102] The FPGA receives firmware data packets from the host via the USB interface and stores them in an internal buffer for subsequent processing. Typically, before writing data to the SPI Flash, the FPGA performs a check (such as a CRC check) to ensure data integrity and correctness.

[0103] The FPGA then initializes the SPI interface, configuring parameters such as the clock frequency and data format. Before writing new data, the target address area must be erased (due to the characteristics of Flash memory, which requires erasing before writing). The FPGA then sends data to the SPI Flash via the MOSI line and monitors the remaining space in the SPI Flash's FPGA temporary memory. If the remaining space is low, the process pauses. If sufficient, data transfer continues. The threshold is 256 bytes.

[0104] In conjunction with the second aspect, the method further includes:

[0105] S410, the host computer sends an SPI configuration instruction packet to the FPGA, specifying the target channel number and configuration parameters.

[0106] S420, the FPGA writes the configuration parameters into the control register of the target SPI host interface corresponding to the target channel number.

[0107] S430, the target SPI host interface establishes communication with the fingerprint chip according to the configuration parameters.

[0108] In this embodiment, the Python program for communicating with the FPGA using the USB interface module is as follows:

[0109] 1. ex_usb_sfrread, ex_usb_sfrwrite, ex_usb_sramwrite, ex_usb_sramread;

[0110] 2. ex_usbff_open,ex_usbff_close;

[0111] 3. ex_usbser_write, ex_usbser_read;

[0112] 4. ex_usb_setdbgno, ex_usbser_resetdevice;

[0113] Among them, Program 1 is a packaged API interface function that uses the USB interface module to read / write fingerprint chip register operations. Here, the SPI interface is finally used through the FPGA to communicate with up to 13 fingerprint chips with SPI interfaces.

[0114] Program 2 is to open / close the interface of ch346 or other USB interface modules.

[0115] Program 3 directly uses the read and write communication operation interface functions between the USB interface module and the FPGA, that is, it directly uses the USB interface module to read / write raw data without going through a custom protocol.

[0116] The first step in Program 4 sets the Nth SPI serial number for the current debugger. As before, in this example, N = 0 to 12, for a total of 13 SPI bus interfaces, corresponding to the debug module inside the FPGA. The second interface is the API function for resetting the ch346USB module.

[0117] Combine Figure 5 As shown in the figure, after the Python program is executed, the debug log of the parameters of the first SPI (RX1) is printed. It can be seen that the register address and value are all 16-bit wide as before, and the value range is from 0 to 65535. And it can be seen that these are basically operations to write registers to the FPGA, because the parameters to configure the fingerprint chip are basically written to the registers of the fingerprint chip through the SPI bus operation. After the parameters are sent to the 13 SPI buses in sequence, the corresponding image data can be read back from the fingerprint chip. Figure 5 Simulates a 13-channel SPI bus fingerprint chip.

[0118] Combine Figure 6 As shown, the analog image data read back is a series of light and dark stripe data. Figure 7 The data values ​​shown are the same as the preset ones, which means that the design has achieved the goal and is as expected.

[0119] In addition, combined Figure 8 The figure shows the speed of the USB interface module reading fingerprint images, tested by a Python program. The speed is only about 8MB / s. This is because image uploading is a process, and the speed at which the fingerprint chip generates image data does not reach the maximum transmission speed of the USB interface module, which is much slower. The USB interface module only reaches 8MB / s when reading, and the actual speed may be even slower. This is just to illustrate that the speed of the USB interface module ch346 is greater than 8MB / s, and it has been proven that the module speed can reach above 8MB / s.

[0120] In conjunction with the second aspect, the method further includes:

[0121] S510: The host computer sends an SPI Flash access instruction to the FPGA using the USB interface module.

[0122] S520: If the SPI Flash access instruction is a background image data read instruction, read the data from the SPI Flash and return it to the host computer using the USB interface module.

[0123] It can be understood that the SPIFlash also stores background image data associated with the fingerprint chip. When the host computer uses the USB interface module to send instructions to the FPGA to read the background image data, the USB interface module is used to batch feed back the background images to be read to the host computer.

[0124] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems and devices can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0125] In addition, in the description of the embodiments of the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0126] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0127] Finally, it should be noted that the above embodiments are only specific implementation methods of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A data transmission system, characterized in that: include: A host computer, an FPGA, a USB interface module, and an N-channel SPI host interface. The host computer uses the USB interface module to establish a bidirectional communication link with the FPGA to read the FPGA's registers through the USB interface module to control the FPGA's operating state. The N-channel SPI host interface is integrated into the FPGA. Each SPI host interface is connected to the SPI slave interface of the fingerprint chip via an independent SPI bus, enabling the FPGA to control the configuration of the multi-channel fingerprint chip. Wherein, N is an integer greater than 1.

2. The system according to claim 1, wherein: The FPGA obtains the fingerprint image data collected by the fingerprint chip through the SPI host interface and caches it in the FPGA internal buffer; When the amount of cached data reaches a preset threshold, the FPGA sends the data packets to the host computer in batch transmission mode through the USB interface module.

3. The system according to claim 1, wherein: The host computer sends the FPGA firmware to the SPI Flash external to the FPGA through the USB interface module to achieve OTA online upgrade.

4. The system according to claim 1, wherein: The FPGA is also connected to the SPIFlash through an SPI Flash interface. The host computer reads the status register of the FPGA, and suspends writing data when the status register indicates that the remaining temporary storage space of the SPIFlash does not meet the write condition, and resumes writing data until the remaining temporary storage space of the SPI Flash meets the write condition.

5. The system according to claim 4, characterized in that The SPI Flash also includes a background image storage area for storing background image data associated with the fingerprint chip; The host computer writes picture data into the background picture storage area through the USB interface module and the FPGA; When the background image reading instruction is triggered, data is extracted from the background image storage area and returned through the USB interface module.

6. A method for communicating with FPGA via a USB interface, characterized in that: Applied to the system according to any one of claims 1 to 5, the method comprises: The host computer uses the USB interface module to send register read and write instruction packets to the FPGA; The FPGA parses the read / write instruction packet and obtains an instruction type of the read / write instruction packet; If it is a write register instruction, the target register value is updated to control the communication parameters of the specified SPI host interface; If it is a register read instruction, read the target register value and encapsulate it into a return data packet; The USB interface module is used to send the returned data packet to the host computer in real time.

7. The method according to claim 6, characterized in that The method further comprises: The FPGA receives the image data collected by the fingerprint chip through the SPI host interface; Cache the image data into the internal buffer of FPGA and count the accumulated data volume; When the accumulated data volume reaches a preset threshold, the USB interface module batch transmission mechanism is triggered to send the data packets to the host computer.

8. The method according to claim 6, characterized in that The method further comprises: The host computer sends a firmware data packet to the FPGA through the USB interface module; The FPGA temporarily stores the firmware data in the firmware data packet and then writes it into the SPI Flash; the FPGA detects the FPGA temporary remaining space of the SPIFlash in real time and updates the status register; The host computer reads the status register value: If the remaining space is less than the threshold, data sending is suspended.

9. The method according to claim 6, characterized in that The method further comprises: The host computer sends an SPI configuration instruction packet to the FPGA, specifying the target channel number and configuration parameters; The FPGA writes the configuration parameters into a control register of a target SPI host interface corresponding to the target channel number; The target SPI host interface establishes communication with the fingerprint chip according to the configuration parameters.

10. The method according to claim 6, characterized in that The method further comprises: The host computer sends an SPI Flash access instruction to the FPGA through the USB interface module; If the SPI Flash access instruction is a background image reading instruction, data is read from the SPI Flash and returned to the host computer through the USB interface module.

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