A method for using the uplink to provide a reference clock in an A-PHY system

Abstract

This invention discloses a reference clock provision structure for the uplink in an A-PHY system, belonging to the field of signal transmission. This invention uses a ROU structure, where an external crystal oscillator is placed at the deserializer end. The serializer end achieves synchronization with the external crystal oscillator, the clock source of the A-PHY system, by recovering the clock from the data in the uplink. This invention significantly reduces the use of crystal oscillators and other oscillators. Crystal oscillators are more susceptible to external interference, while the ROU structure extracts the clock from the reverse channel, making it less affected by interference. The serializer end is often small in size; using the ROU structure eliminates the need for an additional crystal oscillator on the board, saving space. It also offers strong compatibility with the A-PHY protocol, requiring only simple modifications to the silent state defined in the A-PHY protocol for compatibility.

Description

Technical Field

[0001] This invention relates to the field of signal transmission technology, and in particular to a reference clock provision structure for the uplink in an A-PHY system. Background Technology

[0002] In the MIPI A-PHY system, the existing serializer and deserializer each require a crystal oscillator to provide a reference clock for their respective chips. Finally, the deserializer recovers the clock from the downlink to synchronize with the system clock source XTAL at the serializer end.

[0003] Since the number of serializers in practical application systems is often much greater than the number of deserializers, taking a traditional surround-view system as an example, there are 4 serializers and 1 deserializer, requiring a total of 5 external crystal oscillators, which greatly increases the complexity and area of ​​the board-level circuitry at the serializer end. Summary of the Invention

[0004] The purpose of this invention is to provide a reference clock provision structure for the uplink in an A-PHY system to solve the problems in the prior art.

[0005] To address the aforementioned technical problems, this invention provides a reference clock provision structure for the uplink in an A-PHY system, which is a ROU structure (reference over uplink, obtaining the reference clock through the uplink).

[0006] An external crystal oscillator is placed at the deserializer end, and the serializer end achieves synchronization with the external crystal oscillator, the clock source of the A-PHY system, by recovering the clock from the data in the uplink.

[0007] In one embodiment, the serializer includes: a training sequence transmission unit, a phase-locked loop, a clock recovery unit, and an uplink data processing unit;

[0008] The training sequence sending unit is used to send training sequences in a specific format, allowing the deserializer to enter or exit ROU mode.

[0009] The uplink data transmission unit has the ability to transmit training sequences to set the ROU mode at the serializer end;

[0010] The clock recovery unit is responsible for extracting the clock from the uplink data in ROU mode and sending this clock to the phase-locked loop.

[0011] The phase-locked loop selects either a locally recovered clock or an external crystal oscillator clock as the reference clock, depending on whether it is currently in ROU mode.

[0012] In one embodiment, the deserializer includes: a training sequence monitoring unit, a pattern judgment unit, and an uplink data transmission unit;

[0013] The training sequence monitoring unit detects low-speed signals at a fixed frequency before the A-PHY system establishes a link; after the A-PHY system establishes a link, it detects the A-PHY control sequence to provide decision-making basis for the mode judgment unit.

[0014] The mode determination unit receives the remote control signal decoded from the training sequence monitoring unit and, based on external settings, comprehensively determines whether it should currently operate in ROU mode.

[0015] The uplink data transmission unit determines the data to be transmitted based on whether it is currently in ROU mode:

[0016] (1) When the deserializer is in a silent state;

[0017] If in ROU mode, the uplink data transmission unit sends data, which helps the serializer recover the clock and detect the silent state.

[0018] If not in ROU mode, the uplink data transmission unit does not transmit data, which is the silent state specified in A-PHY;

[0019] (2) When the deserializer is not in a silent state, the uplink data transmission unit will transmit uplink data normally regardless of whether it is in ROU mode. If it is in ROU mode, the serializer will restore the clock from the normal uplink data.

[0020] In one implementation, the data transmitted by the uplink data transmission unit provides enough transitions to facilitate the clock recovery unit in extracting the clock; the transitions are regular to facilitate the uplink data processing unit in detecting the silent state at the deserializer end.

[0021] In one implementation, before the A-PHY system establishes a link, the training sequence is a low-speed signal with a fixed frequency; after the A-PHY system establishes a link, it transmits a custom control sequence conforming to the A-PHY system specification via the downlink.

[0022] In one embodiment, a control unit is also included for controlling the serializer end and the deserializer end.

[0023] In one implementation, the uplink data processing unit parses the uplink data and is responsible for two functions within the ROU architecture:

[0024] (1) In ROU mode, the current peer is in a silent state by verifying the data format;

[0025] (2) Parse the training sequence sent from the other end and set the local ROU mode.

[0026] The present invention provides a reference clock provision structure for the uplink in an A-PHY system, which has the following advantages:

[0027] (1) Reduced system cost: The use of crystal oscillators and oscillators is greatly reduced (the number of serializers in the system is often greater than the number of deserializers; in a typical look-through system, the ratio of serializers to deserializers is 4:1).

[0028] (2) Improved reliability: Crystal oscillators are more susceptible to external interference, while the ROU structure extracts the clock from the reverse channel and is less affected by interference;

[0029] (3) Reduce board area: The serializer is often small in size. The ROU structure eliminates the need to place an additional crystal oscillator on the board, saving space.

[0030] (4) Simplified board layout: There is no need to worry about the impact of crystal oscillator layout on other components at the serializer end;

[0031] (5) It has strong compatibility with the A-PHY protocol. It can be compatible by simply modifying the silent state defined by the A-PHY protocol. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the ROU structure of the present invention.

[0033] Figure 2 This is a schematic diagram of the structure for providing an uplink reference clock in an A-PHY system, as provided by the present invention. Detailed Implementation

[0034] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a more detailed explanation of the uplink reference clock provision structure proposed in this invention for an A-PHY system. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise scales, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0035] like Figure 1 As shown, the technical solution of the present invention is a ROU structure (reference over uplink, obtaining the reference clock through the uplink). Unlike the traditional MIPI-A-PHY architecture, the ROU structure places the XTAL (external crystal oscillator) on the deserializer side, while the serializer side achieves synchronization with the system clock source XTAL by recovering the clock from the data in the uplink.

[0036] like Figure 2 The diagram shows the implementation structure of the present invention.

[0037] The serializer includes a training sequence transmission unit, a phase-locked loop (PLL), a clock recovery unit, and an uplink data processing unit. The main function of the training sequence transmission unit is to send a training sequence in a specific format, allowing the deserializer to enter or exit ROU mode. Before the A-PHY system establishes a link, the training sequence is a low-speed signal at a fixed frequency; after the A-PHY system establishes a link, a custom control sequence conforming to the A-PHY system specification can be transmitted via the downlink.

[0038] The deserializer includes a training sequence monitoring unit, a mode judgment unit, and an uplink data transmission unit. The main function of the training sequence monitoring unit is to detect low-speed signals at a fixed frequency before the A-PHY system establishes a link, and to detect the A-PHY control sequence after the A-PHY system establishes a link, providing decision-making basis for the mode judgment unit.

[0039] The mode determination unit is used to receive remote control signals decoded from the training sequence monitoring unit and, based on external settings such as CPU access and EEPROM settings, comprehensively determine whether it should be working in ROU mode.

[0040] The uplink data transmission unit determines the data to send based on whether it is currently in ROU mode. If in ROU mode, the A-PHY system in silent mode cannot remain silent like in non-ROU mode; it must send data. The downlink from the serializer to the deserializer can remain silent in silent mode, maintaining the same behavior as the A-PHY protocol, because the deserializer does not need to recover its clock from the downlink. Only the uplink from the deserializer to the serializer needs to send data in silent mode when ROU mode is enabled, to maintain the accurate clock on the serializer.

[0041] The data sent should have the following characteristics:

[0042] 1. Sufficient transitions should be provided to enable the clock recovery unit at the serializer end to extract the clock;

[0043] 2. These transitions should be regular so that the uplink data processing unit at the serializer end can detect the silent state at the deserializer end.

[0044] Data used to indicate a silent state includes, but is not limited to, PRBS, simple clock transitions of 0 and 1, etc. The uplink data transmission unit also has the capability to transmit training sequences and can configure the ROU mode at the serializer end.

[0045] The uplink data processing unit on the serializer side parses the uplink data and is mainly responsible for two functions in the ROU architecture: 1. In ROU mode, it checks the data format to determine whether the peer is in a silent state; 2. It parses the training sequence sent from the peer and sets the local ROU mode.

[0046] The clock recovery unit on the serializer side is responsible for extracting the clock from the uplink data in ROU mode and sending this clock to the phase-locked loop.

[0047] The phase-locked loop (PLL) at the serializer end can select either a locally recovered clock or an external crystal oscillator clock as the reference clock, depending on whether it is currently in ROU mode. The A-PHY system can easily switch between ROU mode and non-ROU mode.

[0048] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A reference clock provision structure for the uplink in an A-PHY system, characterized in that, In order to obtain the reference clock structure via the uplink, An external crystal oscillator is located at the deserializer end, and the serializer end achieves synchronization with the external crystal oscillator, the clock source of the A-PHY system, by recovering the clock from the data in the uplink. The serializer includes: a training sequence transmission unit, a phase-locked loop, a clock recovery unit, and an uplink data processing unit; The training sequence sending unit is used to send training sequences in a specific format, allowing the deserializer to enter or exit the uplink reference clock acquisition mode. The uplink data transmission unit has the ability to transmit training sequences in order to set the reference clock mode obtained through the uplink at the serializer end; The clock recovery unit is responsible for extracting the clock from the uplink data when obtaining the reference clock mode through the uplink and sending this clock to the phase-locked loop. The phase-locked loop selects either a locally recovered clock or an external crystal clock as the reference clock, depending on whether it is currently in the mode of obtaining the reference clock via the uplink.

2. The reference clock provision structure for the uplink in an A-PHY system as described in claim 1, characterized in that, The deserializer includes: a training sequence monitoring unit, a pattern judgment unit, and an uplink data transmission unit; The training sequence monitoring unit detects low-speed signals at a fixed frequency before the A-PHY system establishes a link; after the A-PHY system establishes a link, it detects the A-PHY control sequence to provide decision-making basis for the mode judgment unit. The mode determination unit receives the remote control signal decoded by the training sequence monitoring unit and, based on external settings, comprehensively determines whether it should currently operate in the mode of obtaining the reference clock via the uplink. The uplink data transmission unit determines the data to be transmitted based on whether it is currently in the mode of obtaining a reference clock via the uplink: (1) When the deserializer is in a silent state; If the reference clock is obtained via the uplink, the uplink data transmission unit transmits data, which helps the serializer recover the clock and detect the silent state. If the uplink data transmission unit is not in the mode of obtaining the reference clock via the uplink, it does not transmit data, which is the silent state specified in A-PHY; (2) When the deserializer is not in a silent state, the uplink data transmission unit transmits uplink data normally regardless of whether it is in the uplink reference clock acquisition mode. If it is in the uplink reference clock acquisition mode, the serializer recovers the clock from the normal uplink data.

3. The reference clock provision structure for the uplink in an A-PHY system as described in claim 2, characterized in that, The data transmitted by the uplink data transmission unit provides enough transitions to facilitate the clock recovery unit in extracting the clock; the transitions are regular so that the uplink data processing unit can detect the silent state at the deserializer end.

4. The reference clock provision structure for the uplink in an A-PHY system as described in claim 1, characterized in that, Before the A-PHY system establishes a link, the training sequence is a low-speed signal with a fixed frequency; after the A-PHY system establishes a link, it transmits a custom control sequence that conforms to the A-PHY system specification through the downlink.

5. The reference clock provision structure for the uplink in an A-PHY system as described in claim 1, characterized in that, The uplink data processing unit parses the uplink data and is responsible for two functions in the architecture for obtaining the reference clock via the uplink: (1) When obtaining the reference clock mode through the uplink, the current peer is in a silent state by verifying the data format; (2) Parse the training sequence sent from the other end and set the local reference clock mode obtained through the uplink.

6. The reference clock provision structure for the uplink in an A-PHY system as described in claim 1, characterized in that, It also includes a control unit for controlling the serializer and deserializer ends.

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