Chip fault prediction method based on long short-term memory network

Abstract

The invention discloses a chip fault prediction method based on a long short-term memory network. The method comprises the following steps: S1, collecting chip operation data; s2, performing denoising, filling, normalization and standardization processing on the data; s3, constructing a time sequence diagram convolution network model containing diagram convolution and an LSTM structure; s4, performing global optimization on the shared feature layer parameters by using a Bayesian optimization algorithm; s5, performing fine tuning training on the LSTM layer based on an optimization result to improve prediction precision; s6, inputting real-time data into the optimization model to generate a fault prediction result; s7, generating a report containing risk levels and suggestions according to a prediction result; and S8, deploying the model and dynamically updating prediction, and supporting continuous monitoring and intelligent early warning of the running state of the chip. According to the invention, accurate prediction and real-time early warning of chip faults are realized, and the stability and maintenance efficiency of system operation are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip fault prediction, and in particular to a chip fault prediction method based on a long short-term memory network. Background Art

[0002] With the continuous improvement of chip integration and their widespread application in critical systems, chip operational stability and reliability have become core factors affecting device performance and safety. Traditional chip fault detection methods are mostly based on static testing, regular maintenance, or threshold monitoring strategies. They often rely on manually set monitoring indicators and regularly sample and compare operating status parameters such as temperature, voltage, and power consumption to determine whether there are any anomalies. Although such methods are effective in simple scenarios, their detection capabilities are limited by the high-dimensional, strongly coupled, and time-varying operating characteristics of modern chip systems, making it difficult to predict potential faults in a timely and accurate manner.

[0003] Existing research methods have attempted to incorporate statistical or machine learning approaches to model and analyze chip operating states, such as using support vector machines (SVMs), decision trees, or multilayer perceptrons (MLPs) for fault classification. However, these methods mostly rely on static features or data from a single point in time for modeling. They lack in-depth utilization of the time series information in chip operating data and struggle to capture potential long-term evolutionary trends, thus limiting the timeliness and accuracy of fault prediction. Traditional machine learning models are particularly prone to misjudgments or missed detections in scenarios where fault characteristics are subtle and the evolution process is complex.

[0004] In recent years, with the increasing success of deep learning in time series modeling, long short-term memory (LSTM) networks have been gradually introduced into industrial forecasting tasks due to their excellent ability to model long-term dependencies in time series data. However, existing LSTM-based chip fault prediction methods often rely solely on time series features, ignoring the potential structural correlations between chip operating data, such as the coupling relationship between multiple state parameters and the spatial distribution information between different sampling nodes. This limits the model's ability to model global correlations. Furthermore, most current models have fixed structures and lack effective structural parameter optimization mechanisms, resulting in weak model generalization and difficulty adapting to different chip architectures or operating conditions.

[0005] Furthermore, traditional training methods such as stochastic gradient descent are prone to falling into local optima in high-dimensional parameter spaces. This can lead to slow convergence and poor stability during training, especially when the model structure is complex and the number of parameters is high. The lack of efficient and intelligent strategies for parameter optimization further hinders improvements in predictive performance.

[0006] In summary, the existing chip fault prediction technology still has shortcomings in terms of timing modeling depth, structural information fusion capabilities and optimization strategies. There is an urgent need for a new method that integrates graph structure and timing modeling, has parameter adaptive optimization capabilities and can achieve high-precision prediction, so as to improve the accuracy, real-time and robustness of chip fault prediction.

[0007] Therefore, how to provide a chip fault prediction method based on long short-term memory network is a problem that technicians in this field urgently need to solve. Summary of the Invention

[0008] One purpose of the present invention is to propose a chip fault prediction method based on long short-term memory network. The present invention fully combines the temporal graph convolution structure and the LSTM modeling mechanism, constructs a prediction model that integrates the multi-dimensional operation data of the chip, and introduces the Bayesian optimization algorithm to adaptively adjust the parameters of the shared feature layer. It describes in detail the temporal feature extraction, model construction, parameter optimization and prediction output process of chip faults, and has the advantages of high prediction accuracy, strong adaptability and good real-time performance.

[0009] A chip fault prediction method based on a long short-term memory network according to an embodiment of the present invention includes the following steps:

[0010] S1. Obtain chip operation data;

[0011] S2. Preprocessing the acquired chip operation data to generate a processed data set;

[0012] S3. Based on the processed dataset, a temporal graph convolutional network model is constructed, including a graph convolution layer, a temporal modeling layer, and an adaptive graph convolution module.

[0013] S4. Use historical data to train the time series graph convolutional network model, learn the time series features and graph structure features in the chip operation data, and generate a preliminary fault prediction model;

[0014] S5. Optimize the parameters in the fault prediction model and use the natural gradient descent algorithm to update the fault prediction model parameters to improve the convergence and training efficiency of the model;

[0015] S6. Apply the optimized fault prediction model to real-time chip operation data to perform fault risk prediction and output specific fault prediction results;

[0016] S7. Generate a report based on the fault prediction results, providing fault diagnosis and early warning information for reference by chip maintenance personnel;

[0017] S8. Based on fault prediction and diagnosis results, maintenance measures are automatically triggered to optimize the chip's operating status and improve system stability.

[0018] Optionally, the operating data of the S1 chip includes: operating temperature data, voltage data, power consumption data, frequency data, load conditions, number of clock cycles, fault log data and real-time status data collected by relevant sensors.

[0019] Optionally, the S2 preprocessing includes: preprocessing, including denoising, missing value filling, normalization, outlier detection and standardization, using median filtering to remove high-frequency noise, using linear interpolation to fill missing data, normalizing the data to the [0,1] interval, eliminating dimensional differences between features, identifying and removing abnormal data points by calculating the Z-score, and standardizing each feature.

[0020] Optionally, the S3 specifically includes:

[0021] S31. The input data is the preprocessed chip operation data set, which is input into the LSTM model. The LSTM network consists of several LSTM layers to capture the temporal dependency of the chip operation data. The input of each layer is the output of the previous layer, and each LSTM unit contains an input gate, a forget gate, and an output gate.

[0022] The output of the S32 LSTM model includes the prediction results for each time step. The prediction results are the probability of chip failure or the type of failure. By training the LSTM model, the future failure status is predicted based on historical data.

[0023] S33. During the training process, a gradient descent optimization algorithm is used to minimize the loss function, wherein the loss function is the mean square error or the cross entropy loss, and the weights in the LSTM network are updated by the back propagation algorithm to gradually optimize the predictive ability of the model;

[0024] S34. Train the LSTM model for multiple iterations until the loss function converges.

[0025] S35. After the training is completed, an optimized LSTM model is generated.

[0026] Optionally, the S4 specifically includes:

[0027] S41. Using a Bayesian optimization algorithm to globally optimize the parameters of the shared feature layer, the parameters of the shared feature layer include the weights and bias terms of the graph convolutional layer. Bayesian optimization constructs a probabilistic model of the objective function, uses a Gaussian process to estimate the value of the objective function, and updates the posterior probability based on historical evaluation results to select the parameter set that is most likely to optimize the objective function. This method can effectively reduce the exploration range of the parameter space and improve optimization efficiency.

[0028] S42. Bayesian optimization updates the posterior probability based on historical evaluation results, adopts strategies such as expected improvement or probability optimization, gradually explores the parameter space, and optimizes the weights and bias terms of the shared feature layer to improve the accuracy of the fault prediction model;

[0029] S43. Update the parameters of the shared feature layer through multiple iterations, gradually converging to the optimal parameter set. After each update, Bayesian optimization evaluates model performance based on the new parameter set and updates the posterior distribution, thereby improving the model's ability to predict chip failures and ensuring optimal feature transfer between the graph convolution layer and the LSTM time series modeling layer.

[0030] S44. During the optimization process, use cross-validation to evaluate the performance of the optimized model on different datasets to avoid overfitting and improve the generalization ability of the model.

[0031] S45. Apply the optimized shared feature layer parameters to the trained temporal graph convolutional network model to ensure that the model can effectively predict chip faults and generate the final optimized fault prediction model.

[0032] Optionally, the S41 specifically includes:

[0033] S411. Define the optimization objective function as the prediction error of the shared feature layer on the training data set, where the prediction error is obtained by calculating the mean square error of the model on the training set;

[0034] S412. Construct a Gaussian process as a probability model of the objective function, wherein the Gaussian process is used to estimate the value of the objective function in the parameter space, and update the posterior probability according to the historical optimization results;

[0035] S413. Select the parameter set that is most likely to improve the objective function through Bayesian optimization, and update the weights and bias terms of the graph convolution layer of the shared feature layer to minimize the prediction error.

[0036] S414. Explore new parameters through sampling strategies, use historical optimization information to guide the search process, and gradually optimize the parameters of the shared feature layer, so that the prediction accuracy of the model is gradually improved;

[0037] S415. Update the optimization parameters through multiple iterations until the model performance converges to the best, and finally obtain the optimal parameter set of the shared feature layer.

[0038] Optionally, the S5 specifically includes:

[0039] S51. Based on the optimized shared feature layer parameters, fine-tune the temporal graph convolutional network model using the training dataset and adjust the weights of the LSTM temporal modeling layer.

[0040] S52, adopt an adaptive learning rate strategy to dynamically adjust the learning rate according to the change of the loss function after each training, maintain the stability of the training process, and avoid gradient disappearance or explosion;

[0041] S53. Use the validation set to evaluate model performance after each round of fine-tuning. Calculate the mean squared error to evaluate the model's prediction error and ensure the model's generalization ability on unseen data.

[0042] S54. Perform multiple rounds of fine-tuning training to gradually optimize the parameters of the LSTM timing modeling layer, enabling the model to more accurately capture the timing characteristics of chip operation data and improve the accuracy of fault prediction.

[0043] S55. When the fine-tuning training converges, save the final trained temporal graph convolutional network model.

[0044] Optionally, the S6 specifically includes:

[0045] S61, inputting the pre-processed chip operation data into the optimized timing graph convolutional network model to complete normalization and standardization processing;

[0046] S62, using the LSTM time series modeling layer to capture the temporal dependencies in the chip operation data and generate a predicted value for each time step, indicating the chip's failure risk or failure type;

[0047] S63. Based on the output of the LSTM time series modeling layer and the features of the graph convolution layer, the time series features and the graph structure features are integrated to generate a comprehensive fault prediction result.

[0048] S64. Based on the generated prediction results, determine whether the fault risk exceeds the set threshold. If so, trigger a fault warning and output the fault type, occurrence time and likelihood.

[0049] S65. Generate a real-time fault report based on the prediction results, and provide fault diagnosis and handling suggestions to chip maintenance personnel;

[0050] S66. Compare the real-time prediction results with historical data and dynamically adjust the model.

[0051] Optionally, the S7 generates a report based on the fault prediction results, specifically including the predicted type of chip fault, predicted time, probability of fault occurrence and risk level, and provides a list of areas or modules with high to low probability of fault occurrence. The report contains a description of the fault risk level, divided into low, medium and high risk levels, and comes with recommended maintenance measures to help maintenance personnel take corresponding prevention or repair plans for different fault types. The report can also include a fault trend graph, a probability distribution graph and a spatial distribution graph. The final generated report is automatically transmitted to the maintenance personnel's work platform.

[0052] The beneficial effects of the present invention are:

[0053] (1) The present invention constructs a timing modeling structure based on a long short-term memory network, which can effectively capture the long-term dependencies in chip operation data. Combined with the graph convolution mechanism, it introduces spatial correlation modeling between multi-dimensional features, which significantly enhances the model's ability to recognize complex fault modes and effectively avoids misjudgments and missed judgments caused by traditional methods that ignore timing or structural characteristics.

[0054] (2) The present invention introduces the Bayesian optimization algorithm to globally optimize the key parameters of the graph convolution layer and the shared feature layer, and can dynamically adjust the model structure and parameter combination according to the feedback information during the training process, overcoming the problems of weak generalization and poor migration ability of existing fixed structure models, and improving the applicability of the model in multi-chip architectures and various operating environments.

[0055] (3) The present invention constructs a complete automated process from data acquisition, preprocessing, modeling, optimization, prediction to report generation, integrating adaptive learning rate control, outlier elimination and multi-round iterative training mechanism, ensuring the stability of the system during long-term operation and the continuous reliability of the prediction results, and providing efficient support for chip failure warning and maintenance decision-making. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0057] Figure 1 This is an overall flow chart of a chip fault prediction method based on long short-term memory network proposed by the present invention;

[0058] Figure 2 This is a structural diagram of a time-series graph convolutional network model for a chip fault prediction method based on a long short-term memory network proposed in the present invention;

[0059] Figure 3 This is a diagram of the Bayesian optimization parameter update process of a chip fault prediction method based on long short-term memory network proposed in the present invention. DETAILED DESCRIPTION

[0060] The present invention will now be described in further detail with reference to the accompanying drawings, which are simplified schematic diagrams that illustrate the basic structure of the present invention in a schematic manner.

[0061] refer to Figure 1-3 , a chip fault prediction method based on long short-term memory network, comprising the following steps:

[0062] S1. Obtain chip operation data;

[0063] S2. Preprocess the acquired chip operation data to generate a processed data set;

[0064] S3. Based on the processed dataset, a temporal graph convolutional network model is constructed, including a graph convolution layer, a temporal modeling layer, and an adaptive graph convolution module.

[0065] S4. Use historical data to train the time series graph convolutional network model, learn the time series features and graph structure features in the chip operation data, and generate a preliminary fault prediction model;

[0066] S5. Optimize the parameters in the fault prediction model and use the natural gradient descent algorithm to update the fault prediction model parameters to improve the convergence and training efficiency of the model;

[0067] S6. Apply the optimized fault prediction model to real-time chip operation data to perform fault risk prediction and output specific fault prediction results;

[0068] S7. Generate a report based on the fault prediction results, providing fault diagnosis and early warning information for reference by chip maintenance personnel;

[0069] S8. Based on fault prediction and diagnosis results, maintenance measures are automatically triggered to optimize the chip's operating status and improve system stability.

[0070] This paper proposes a complete chip fault prediction process, encompassing eight stages: data acquisition, preprocessing, modeling, optimization, prediction, and report output, forming an end-to-end intelligent prediction system. Compared to traditional solutions that rely solely on static thresholds or single models, this paper integrates a clearly structured multi-stage process with deep modeling, improving the systematicity and deployability of fault prediction, effectively meeting the real-time and accuracy requirements in complex operating scenarios.

[0071] In this embodiment, the operating data of the S1 chip includes: operating temperature data, voltage data, power consumption data, frequency data, load conditions, number of clock cycles, fault log data and real-time status data collected by relevant sensors.

[0072] In this embodiment, the S2 preprocessing includes: preprocessing, including denoising, missing value filling, normalization, outlier detection and standardization, using median filtering to remove high-frequency noise, using linear interpolation to fill missing data, normalizing the data to the [0,1] interval, eliminating the dimensional differences between features, identifying and removing abnormal data points by calculating the Z-score, and standardizing each feature.

[0073] In this embodiment, S3 specifically includes:

[0074] S31. The input data is the preprocessed chip operation data set, which is input into the LSTM model. The LSTM network consists of several LSTM layers to capture the temporal dependency of the chip operation data. The input of each layer is the output of the previous layer, and each LSTM unit contains an input gate, a forget gate, and an output gate.

[0075] The output of the S32 LSTM model includes the prediction results for each time step. The prediction results are the probability of chip failure or the type of failure. By training the LSTM model, the future failure status is predicted based on historical data.

[0076] S33. During the training process, a gradient descent optimization algorithm is used to minimize the loss function, wherein the loss function is the mean square error or the cross entropy loss, and the weights in the LSTM network are updated by the back propagation algorithm to gradually optimize the predictive ability of the model;

[0077] S34. Train the LSTM model for multiple iterations until the loss function converges.

[0078] S35. After the training is completed, an optimized LSTM model is generated.

[0079] This paper adopts the LSTM network as the core of timing modeling, and combines the adjacency relationship in the graph structure to realize the joint extraction of the spatial-temporal features of the chip operation status. Compared with the solution that only uses static graphs or simple RNNs, it significantly enhances the model's ability to model complex timing changes and improves the accuracy of capturing the evolution trend of fault occurrence.

[0080] In this embodiment, the S4 specifically includes:

[0081] S41. Using a Bayesian optimization algorithm to globally optimize the parameters of the shared feature layer, the parameters of the shared feature layer include the weights and bias terms of the graph convolutional layer. Bayesian optimization constructs a probabilistic model of the objective function, uses a Gaussian process to estimate the value of the objective function, and updates the posterior probability based on historical evaluation results to select the parameter set that is most likely to optimize the objective function. This method can effectively reduce the exploration range of the parameter space and improve optimization efficiency.

[0082] S42. Bayesian optimization updates the posterior probability based on historical evaluation results, adopts strategies such as expected improvement or probability optimization, gradually explores the parameter space, and optimizes the weights and bias terms of the shared feature layer to improve the accuracy of the fault prediction model;

[0083] S43. Update the parameters of the shared feature layer through multiple iterations, gradually converging to the optimal parameter set. After each update, Bayesian optimization evaluates model performance based on the new parameter set and updates the posterior distribution, thereby improving the model's ability to predict chip failures and ensuring optimal feature transfer between the graph convolution layer and the LSTM time series modeling layer.

[0084] S44. During the optimization process, use cross-validation to evaluate the performance of the optimized model on different datasets to avoid overfitting and improve the generalization ability of the model.

[0085] S45. Apply the optimized shared feature layer parameters to the trained temporal graph convolutional network model to ensure that the model can effectively predict chip faults and generate the final optimized fault prediction model.

[0086] This paper introduces a Bayesian optimization algorithm to adaptively adjust key parameters of the shared feature layer globally, addressing the problem of relying on manual experience when selecting structural parameters in deep model training. Compared with traditional fixed-structure models, this method can automatically search for the optimal parameter combination, improving model prediction performance while enhancing adaptability and generalization across chip architectures.

[0087] In this embodiment, the S41 specifically includes:

[0088] S411. Define the optimization objective function as the prediction error of the shared feature layer on the training data set, where the prediction error is obtained by calculating the mean square error of the model on the training set;

[0089] S412. Construct a Gaussian process as a probability model of the objective function, wherein the Gaussian process is used to estimate the value of the objective function in the parameter space, and update the posterior probability according to the historical optimization results;

[0090] S413. Select the parameter set that is most likely to improve the objective function through Bayesian optimization, and update the weights and bias terms of the graph convolution layer of the shared feature layer to minimize the prediction error.

[0091] S414. Explore new parameters through sampling strategies, use historical optimization information to guide the search process, and gradually optimize the parameters of the shared feature layer, so that the prediction accuracy of the model is gradually improved;

[0092] S415. Update the optimization parameters through multiple iterations until the model performance converges to the best, and finally obtain the optimal parameter set of the shared feature layer.

[0093] During fine-tuning, this method employs a structural freezing strategy based on optimization results, performing refinement training only on the LSTM layer and dynamically adjusting the parameter update cadence using an adaptive learning rate mechanism. Compared to a full-training strategy, this approach significantly reduces the risk of overfitting while maintaining improved accuracy, enhancing the model's stability and reliability across diverse application environments.

[0094] In this embodiment, the S5 specifically includes:

[0095] S51. Based on the optimized shared feature layer parameters, fine-tune the temporal graph convolutional network model using the training dataset and adjust the weights of the LSTM temporal modeling layer.

[0096] S52, adopt an adaptive learning rate strategy to dynamically adjust the learning rate according to the change of the loss function after each training, maintain the stability of the training process, and avoid gradient disappearance or explosion;

[0097] S53. Use the validation set to evaluate model performance after each round of fine-tuning. Calculate the mean squared error to evaluate the model's prediction error and ensure the model's generalization ability on unseen data.

[0098] S54. Perform multiple rounds of fine-tuning training to gradually optimize the parameters of the LSTM timing modeling layer, enabling the model to more accurately capture the timing characteristics of chip operation data and improve the accuracy of fault prediction.

[0099] S55. When the fine-tuning training converges, save the final trained temporal graph convolutional network model.

[0100] This method applies the optimized model to real-time chip data, enabling continuous, online fault status prediction and triggering fault alerts based on set thresholds. This method supports dynamic chip status monitoring and trend warnings. Compared to traditional offline analysis methods, it can identify potential risks in advance and reduce system downtime losses.

[0101] In this embodiment, S6 specifically includes:

[0102] S61, inputting the pre-processed chip operation data into the optimized timing graph convolutional network model to complete normalization and standardization processing;

[0103] S62, using the LSTM time series modeling layer to capture the temporal dependencies in the chip operation data and generate a predicted value for each time step, indicating the chip's failure risk or failure type;

[0104] S63. Based on the output of the LSTM time series modeling layer and the features of the graph convolution layer, the time series features and the graph structure features are integrated to generate a comprehensive fault prediction result.

[0105] S64. Based on the generated prediction results, determine whether the fault risk exceeds the set threshold. If so, trigger a fault warning and output the fault type, occurrence time and likelihood.

[0106] S65. Generate a real-time fault report based on the prediction results, and provide fault diagnosis and handling suggestions to chip maintenance personnel;

[0107] S66. Compare the real-time prediction results with historical data and dynamically adjust the model.

[0108] The prediction report constructed by this invention covers fault type, probability, time, impact range, and recommended maintenance suggestions, and provides a multi-dimensional visual display, improving maintenance decision-making efficiency. Compared with existing methods that suffer from a single output format and difficulty in interpretation, this invention presents prediction results in a more practical and instructive manner, facilitating actual project deployment and management.

[0109] In this embodiment, the S7 generates a report based on the fault prediction results, specifically including the predicted type of chip fault, predicted time, probability of fault occurrence and risk level, and provides a list of areas or modules with high to low probability of fault occurrence. The report contains a description of the fault risk level, which is divided into low, medium and high risk levels, and comes with recommended maintenance measures to help maintenance personnel take corresponding prevention or repair plans for different fault types. The report can also include a fault trend graph, a probability distribution graph and a spatial distribution graph. The final generated report is automatically transmitted to the maintenance personnel's work platform.

[0110] Example 1:

[0111] In order to verify the feasibility of the present invention in implementation, the present invention was applied to the quality control system of a large-scale smart terminal chip manufacturer, which is used to monitor the operating status and predict fault risks of chips in mass production. In actual applications, the company has long faced a key problem: some chips have functional abnormalities shortly after delivery and use, and conventional static detection methods are unable to detect such latent faults before leaving the factory, resulting in an increase in the return rate and customer complaints. In order to improve the forward detection capability, the chip fault prediction method based on the long short-term memory network proposed in the present invention was introduced into the company's production and testing process and embedded into the existing data acquisition and analysis platform.

[0112] During the application process, 8,000 chips are first randomly selected from the production line, and an operation monitoring module is installed to collect the original operation data such as temperature, voltage, current, frequency, energy consumption fluctuations, etc. during the operation process, and the corresponding fault label data is recorded. The collected data undergoes the preprocessing process described in the present invention, including median filtering denoising, missing value linear interpolation, extreme value removal, normalization and standardization conversion to construct a data input set in a unified format. In the model construction stage, a graph structure is used to represent the state correlation relationship between multiple channels within the chip, and LSTM is used to extract the operation dynamics of each time series. At the same time, the Bayesian optimization algorithm is used to automatically adjust the connection parameters between the graph convolution layer and the time series layer during the training stage to achieve the optimal expression of the shared feature layer.

[0113] After the system was deployed, the actual operation of 2,000 chips was continuously monitored in a real-world test environment, performing online predictions and dynamic evaluations. During the test period, the system flagged 78 chips with high-risk failures. Subsequent functional verification confirmed that 68 of these chips indeed experienced stability anomalies after more than 500 hours of simulated operation, with an early warning accuracy rate of 87.18%. Compared to the old system before the deployment of the present invention's solution, the average fault prediction accuracy increased by 23%, and the early identification cycle was shortened from 10 hours to less than 2 hours, significantly improving operation and maintenance efficiency and risk prevention and control capabilities.

[0114] Furthermore, in edge deployment environments, prediction model loading time is controlled within 150ms, and inference time after a single data input averages no more than 40ms, meeting real-time requirements. Maintenance personnel can directly view fault probability trends, risk levels, fluctuation indicators, and recommended solutions through the fault prediction report interface. Combined with the system's graphical distribution map, they can quickly locate and intervene in potential anomalies, significantly reducing the probability of uncontrollable risks after the chip leaves the factory.

[0115] The following table summarizes the data collected and verified during the implementation process, which is used to illustrate the accuracy and practicality of the present invention in actual scenarios:

[0116] Table 1: Summary of chip failure prediction experimental data and performance indicators

[0117]

[0118] From Table 1 "Chip Fault Prediction Experimental Data and Performance Index Summary Table", it can be seen that the chip fault prediction method based on long short-term memory network proposed in the present invention has shown significant advantages in multiple key performance dimensions. Taking chips such as C101, C205, C610 and C723 as representatives, the predicted failure probabilities reached 92.4%, 88.6%, 84.5% and 93.1% respectively, and all successfully hit the actual failure events during actual operation. The corresponding prediction result was "yes", verifying the effectiveness of the model in identifying high-risk samples. Further observation showed that the time points of failure occurrence were all concentrated around 500 hours, indicating that the model can not only accurately identify high-risk chips, but also has the ability to make early judgments on the trend of medium-term stability degradation.

[0119] Furthermore, for chips like C318, C567, and C837, we can see that when the predicted failure probability was low (below 12%), no failure actually occurred. The model maintained excellent low false positive performance, avoiding unnecessary maintenance intervention. A comparison of average power consumption fluctuation and peak temperature also shows that high-risk samples are often accompanied by increased power consumption fluctuation (e.g., 14.8% for C723) and abnormally high temperatures (e.g., 85.3°C for C101). The proposed model effectively combines the correlations between these multi-dimensional parameters in both temporal and spatial structures, generating more discriminatory predictions.

[0120] Furthermore, the risk level output is largely consistent with the actual fault status: all high-risk chips are classified as high-risk, and no low-risk chips are misclassified. This further demonstrates the rational design of the reporting mechanism and threshold strategy, and their practical deployment value. Overall, this table demonstrates the superior performance of the proposed method in terms of prediction accuracy, response timeliness, fault identification sensitivity, and false alarm control, validating its effectiveness and practicality in chip-level fault monitoring and maintenance decision-making.

[0121] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. A chip fault prediction method based on long short-term memory network, characterized in that: The steps include: S1. Obtain chip operation data; S2. Preprocess the acquired chip operation data to generate a processed data set; S3. Based on the processed dataset, a temporal graph convolutional network model is constructed, including a graph convolution layer, a temporal modeling layer, and an adaptive graph convolution module. S4. Use historical data to train the time series graph convolutional network model, learn the time series features and graph structure features in the chip operation data, and generate a preliminary fault prediction model; S5. Optimize the parameters in the fault prediction model and use the natural gradient descent algorithm to update the fault prediction model parameters to improve the convergence and training efficiency of the model; S6. Apply the optimized fault prediction model to real-time chip operation data to perform fault risk prediction and output specific fault prediction results; S7. Generate a report based on the fault prediction results, providing fault diagnosis and early warning information for reference by chip maintenance personnel; S8. Based on fault prediction and diagnosis results, maintenance measures are automatically triggered to optimize the chip's operating status and improve system stability.

2. The chip fault prediction method based on long short-term memory network according to claim 1 is characterized in that: The operating data of the S1 chip includes: operating temperature data, voltage data, power consumption data, frequency data, load conditions, number of clock cycles, fault log data and real-time status data collected by related sensors.

3. The chip fault prediction method based on long short-term memory network according to claim 1 is characterized in that: The S2 preprocessing includes: preprocessing, including denoising, missing value filling, normalization, outlier detection and standardization, using median filtering to remove high-frequency noise, using linear interpolation to fill missing data, normalizing the data to the [0,1] interval to eliminate dimensional differences between features, identifying and removing abnormal data points by calculating the Z-score, and standardizing each feature.

4. The chip fault prediction method based on long short-term memory network according to claim 1 is characterized in that: The S3 specifically includes: S31. The input data is the preprocessed chip operation data set, which is input into the LSTM model. The LSTM network consists of several LSTM layers to capture the temporal dependency of the chip operation data. The input of each layer is the output of the previous layer, and each LSTM unit contains an input gate, a forget gate, and an output gate. The output of the S32 LSTM model includes the prediction results for each time step. The prediction results are the probability of chip failure or the type of failure. By training the LSTM model, the future failure status is predicted based on historical data. S33. During the training process, a gradient descent optimization algorithm is used to minimize the loss function, wherein the loss function is the mean square error or the cross entropy loss, and the weights in the LSTM network are updated by the back propagation algorithm to gradually optimize the predictive ability of the model; S34. Train the LSTM model for multiple iterations until the loss function converges. S35. After the training is completed, an optimized LSTM model is generated.

5. The chip fault prediction method based on long short-term memory network according to claim 1 is characterized in that: The S4 specifically includes: S41. Using a Bayesian optimization algorithm to globally optimize the parameters of the shared feature layer, the parameters of the shared feature layer include the weights and bias terms of the graph convolutional layer. Bayesian optimization constructs a probabilistic model of the objective function, uses a Gaussian process to estimate the value of the objective function, and updates the posterior probability based on historical evaluation results to select the parameter set that is most likely to optimize the objective function. This method can effectively reduce the exploration range of the parameter space and improve optimization efficiency. S42. Bayesian optimization updates the posterior probability based on historical evaluation results, adopts strategies such as expected improvement or probability optimization, gradually explores the parameter space, and optimizes the weights and bias terms of the shared feature layer to improve the accuracy of the fault prediction model; S43. Update the parameters of the shared feature layer through multiple iterations, gradually converging to the optimal parameter set. After each update, Bayesian optimization evaluates model performance based on the new parameter set and updates the posterior distribution, thereby improving the model's ability to predict chip failures and ensuring optimal feature transfer between the graph convolution layer and the LSTM time series modeling layer. S44. During the optimization process, use cross-validation to evaluate the performance of the optimized model on different datasets to avoid overfitting and improve the generalization ability of the model. S45. Apply the optimized shared feature layer parameters to the trained temporal graph convolutional network model to ensure that the model can effectively predict chip faults and generate the final optimized fault prediction model.

6. The chip fault prediction method based on long short-term memory network according to claim 5 is characterized in that: The S41 specifically includes: S411. Define the optimization objective function as the prediction error of the shared feature layer on the training data set, where the prediction error is obtained by calculating the mean square error of the model on the training set; S412. Construct a Gaussian process as a probability model of the objective function, wherein the Gaussian process is used to estimate the value of the objective function in the parameter space, and update the posterior probability according to the historical optimization results; S413. Select the parameter set that is most likely to improve the objective function through Bayesian optimization, and update the weights and bias terms of the graph convolution layer of the shared feature layer to minimize the prediction error. S414. Explore new parameters through sampling strategies, use historical optimization information to guide the search process, and gradually optimize the parameters of the shared feature layer, so that the prediction accuracy of the model is gradually improved; S415. Update the optimization parameters through multiple iterations until the model performance converges to the best, and finally obtain the optimal parameter set of the shared feature layer.

7. The chip fault prediction method based on long short-term memory network according to claim 1 is characterized in that: The S5 specifically includes: S51. Based on the optimized shared feature layer parameters, fine-tune the temporal graph convolutional network model using the training dataset and adjust the weights of the LSTM temporal modeling layer. S52, adopt an adaptive learning rate strategy to dynamically adjust the learning rate according to the change of the loss function after each training, maintain the stability of the training process, and avoid gradient disappearance or explosion; S53. Use the validation set to evaluate model performance after each round of fine-tuning. Calculate the mean squared error to evaluate the model's prediction error and ensure the model's generalization ability on unseen data. S54. Perform multiple rounds of fine-tuning training to gradually optimize the parameters of the LSTM timing modeling layer, enabling the model to more accurately capture the timing characteristics of chip operation data and improve the accuracy of fault prediction. S55. When the fine-tuning training converges, save the final trained temporal graph convolutional network model.

8. The chip fault prediction method based on long short-term memory network according to claim 1 is characterized in that: The S6 specifically includes: S61, inputting the pre-processed chip operation data into the optimized timing graph convolutional network model to complete normalization and standardization processing; S62, using the LSTM time series modeling layer to capture the temporal dependencies in the chip operation data and generate a predicted value for each time step, indicating the chip's failure risk or failure type; S63. Based on the output of the LSTM time series modeling layer and the features of the graph convolution layer, the time series features and the graph structure features are integrated to generate a comprehensive fault prediction result. S64. Based on the generated prediction results, determine whether the fault risk exceeds the set threshold. If so, trigger a fault warning and output the fault type, occurrence time and likelihood. S65. Generate a real-time fault report based on the prediction results, and provide fault diagnosis and handling suggestions to chip maintenance personnel; S66. Compare the real-time prediction results with historical data and dynamically adjust the model.

9. The chip fault prediction method based on long short-term memory network according to claim 1, characterized in that: The S7 generates a report based on the fault prediction results, specifically including the predicted type of chip fault, predicted time, probability of fault occurrence and risk level, and provides a list of areas or modules with high to low probability of fault occurrence. The report contains a description of the fault risk level, divided into low, medium and high risk levels, and comes with recommended maintenance measures to help maintenance personnel take corresponding prevention or repair plans for different fault types. The report can also include a fault trend graph, probability distribution graph and spatial distribution graph. The final generated report is automatically transmitted to the maintenance personnel's work platform.

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