Error correction code circuit, memory system including same, and method of error correction

Abstract

An error correction code circuit, a memory system including the same, and a method of error correction are disclosed. The error correction code circuit includes: a first sub error correction code circuit for correcting a first error including a first error bit; a second sub error correction code circuit for correcting a second error including a second error bit; an output multiplexer circuit for outputting a plurality of bits, in which a first plurality of bits among the plurality of bits are output to the first sub-error correction code circuit, and in which a second plurality of bits among the plurality of bits are output to the second sub-error correction code circuit; and a control logic circuit configured to control the output multiplexer circuit, and wherein the control logic circuit is further configured to: determine, based on the number of the first error bits exceeding the first number and the number of the second error bits being less than the first number, the first error bits; and controlling the output multiplexer circuit to output at least one of the first error bits to the second sub error correction code circuit.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2024-0038085 filed on March 19, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of the present disclosure described herein relate to an error correction code circuit, a memory system including the error correction code circuit, and a method of error correction. Background Art

[0003] Nonvolatile memory is a type of computer memory that retains stored information even when power is interrupted. Flash memory is an example of nonvolatile memory. Resistive memory devices, such as PRAM (phase change RAM), NFGM (nano floating gate memory), PoRAM (polymer RAM), MRAM (magnetic RAM), FeRAM (ferroelectric RAM), and RRAM (resistive RAM), along with flash memory, are also referred to as nonvolatile memory devices.

[0004] A nonvolatile memory system typically includes a memory controller and a nonvolatile memory (NVM) device.

[0005] Non-volatile memory systems may include error correction code (ECC) circuitry that corrects data to be written to or read from the NVM devices.

[0006] Specifically, in the case of MRAM, which stores or reads data based on the magnetization direction and the resistance value formed by the current applied to the variable resistance element, bit errors may occur during the data storage and reading process due to the characteristics of using quantum mechanical effects. Therefore, in the case of memory systems that utilize quantum mechanical effects, such as MRAM, an ECC circuit is generally provided.

[0007] However, in order to increase the number of error bits that can be corrected by the ECC circuit, the circuit configuration for implementing the memory system may increase exponentially. Summary of the Invention

[0008] Embodiments of the present disclosure provide an ECC circuit that increases the operating speed of a memory system and the number of bits that can be error corrected.

[0009] According to an embodiment of the present disclosure, an ECC circuit includes: a first sub-ECC circuit configured to correct a first error including a first error bit; a second sub-ECC circuit configured to correct a second error including a second error bit; an output multiplexer circuit configured to output a plurality of bits, wherein a first plurality of bits among the plurality of bits are output to the first sub-ECC circuit, and wherein a second plurality of bits among the plurality of bits are output to the second sub-ECC circuit; and a control logic circuit configured to control the output multiplexer circuit, and wherein the control logic circuit is further configured to: based on the number of the first error bits exceeding the first number and the number of the second error bits being less than the first number, control the output multiplexer circuit to output at least one of the first error bits to the second sub-ECC circuit.

[0010] According to an embodiment of the present disclosure, a method for performing error correction on multiple bits read from a memory device includes: storing multiple input bits in the memory device; reading multiple bits stored at addresses corresponding to address values ​​of the multiple input bits from the memory device; determining the number of first error bits occurring in a first plurality of bits among the multiple bits that a first sub-ECC circuit can correct errors in and the number of second error bits occurring in a second plurality of bits among the multiple bits that a second sub-ECC circuit can correct errors in; and controlling an output multiplexer circuit to output at least one of the first error bits to a second sub-ECC circuit based on the number of first error bits exceeding a first number and the number of second error bits being less than the first number.

[0011] According to an embodiment of the present disclosure, a memory system includes: a memory device that reads multiple bits; and a memory controller that controls the operation of the memory device, and the memory controller includes an ECC circuit, the ECC circuit including: a first sub-ECC circuit configured to correct a first error including a first error bit, and a second sub-ECC circuit configured to correct a second error including a second error bit, and wherein the memory device includes: an output multiplexer circuit configured to output multiple bits, wherein a first plurality of bits among the multiple bits are output to the first sub-ECC circuit, and wherein a second plurality of bits among the multiple bits are output to the second sub-ECC circuit, and a control logic circuit configured to control the output multiplexer circuit, and wherein the control logic circuit is further configured to: based on the number of the first error bits exceeding the first number and the number of the second error bits being less than the first number, control the output multiplexer circuit to output at least a portion of the first error bits to the second sub-ECC circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0013] Figure 1A is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0014] Figure 1B is a diagram illustrating a memory system in which an ECC circuit receives a plurality of bits read from a memory device according to an embodiment of the present disclosure.

[0015] Figure 2 is a block diagram illustrating an output multiplexer circuit including a plurality of multiplexers outputting a plurality of bits to a sub-ECC circuit according to an embodiment.

[0016] Figure 3 is a block diagram illustrating control logic for controlling an output multiplexer circuit according to an embodiment.

[0017] Figure 4A is a block diagram illustrating control logic for controlling an output multiplexer circuit according to an embodiment.

[0018] Figure 4B is a block diagram illustrating control logic for controlling an output multiplexer circuit according to an embodiment.

[0019] Figure 5 is a block diagram illustrating control logic for controlling an output multiplexer circuit according to an embodiment.

[0020] Figure 6 is a block diagram illustrating control logic for controlling an output multiplexer circuit according to an embodiment.

[0021] Figure 7 is a flowchart illustrating an error correction process of a memory device according to an embodiment.

[0022] Figure 8 is a flowchart illustrating a process of controlling a multiplexer included in an output multiplexer circuit according to an embodiment.

[0023] Figure 9 is a flowchart illustrating a process of storing selection information and address information according to values ​​of a plurality of bits according to an embodiment.

[0024] Figure 10 is a flow chart illustrating a process of controlling an output multiplexer circuit based on stored address information and stored select information according to an embodiment.

[0025] Figure 11 is a block diagram illustrating a memory system according to an embodiment.

[0026] Figure 12 is a block diagram illustrating a memory system in which a control logic circuit controls an input multiplexer and an output multiplexer according to an embodiment.

[0027] Figure 13is a block diagram illustrating a memory system including a memory controller and a memory device according to an embodiment.

[0028] Figure 14 It shows Figure 13 Block diagram of a memory device in FIG. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present disclosure will be described clearly and in detail so that those skilled in the art can easily realize the technical concept of the present disclosure.

[0030] Expressions such as “first,” “second,” etc. used in the present disclosure may modify various elements regardless of order and / or importance, and are only used to distinguish one element from another without limiting the order or importance of the elements.

[0031] As is conventional in the disclosed art, embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will appreciate that these blocks, units, and / or modules are physically implemented using electronic (or optical) circuits (such as logic circuits, separate components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc.) that can be produced using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein and can optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) that performs other functions.

[0032] Figure 1A is a block diagram illustrating a memory system according to an embodiment of the present disclosure. Figure 1B Shown in Figure 1A The ECC circuit receives a configuration of a plurality of bits read from the memory device.

[0033] like Figure 1A and Figure 1B As shown together, a memory system 100 according to an embodiment may include an error correction code (ECC) circuit 110 and a memory device 120 .

[0034] The memory system 100 may include a memory device 120 that stores input data.

[0035] In more detail, the memory device 120 may store data input from the outside. In addition, the memory device 120 may output the stored data in response to a read request received from the outside.

[0036] In this case, the memory device 120 may be a non-volatile memory (such as a flash memory, magnetic RAM (MRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), and resistive RAM (ReRAM). However, the embodiments of the present disclosure are not limited thereto, and as an example, the memory device 120 may include a dynamic random access memory (DRAM) (such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics DDR (GDDR), etc.).

[0037] However, hereinafter, for convenience of description, it is assumed that the memory device 120 is an MRAM.

[0038] Furthermore, the memory system 100 may include an ECC circuit 110 connected to the memory device 120 .

[0039] According to an embodiment, the ECC circuit 110 may receive the plurality of bits BT output from the memory device 120. In addition, the ECC circuit 110 may transmit the plurality of bits BT to the memory device 120.

[0040] According to an embodiment, the ECC circuit 110 may correct a bit that is an error (hereinafter referred to as an “error bit”) among a plurality of bits BT to be output from the memory device 120 .

[0041] In more detail, the ECC circuit 110 may correct an error bit having a different value from a bit input to the memory device 120 among a plurality of bits BT to be output from the memory device 120 .

[0042] According to an embodiment, the ECC circuit 110 may include a first sub-ECC circuit 111, a second sub-ECC circuit 112, an output multiplexer circuit 113 (in Figure 1A referred to as “multiplexer circuit 113”) and control logic circuit 114.

[0043] The ECC circuit 110 may include a first sub-ECC circuit 111 and a second sub-ECC circuit 112, each of which corrects errors including error bits whose number is less than a first number. As an example, the first sub-ECC circuit 111 may correct a first error bit, and the second sub-ECC circuit 112 may correct a second error bit. The number of the first error bits and the number of the second error bits may be less than or equal to the first number.

[0044] In more detail, the ECC circuit 110 may include a first sub-ECC circuit 111 that corrects errors of error bits whose number is less than or equal to a first number among the plurality of first bits BT1 .

[0045] like Figure 1B As shown in , the plurality of first bits BT1 (also referred to as “first plurality of bits”) may include a plurality of first data bits DQ1[1] to DQ1

[32] and a plurality of first parity bits PB1[1] to PB1[6].

[0046] Therefore, for example, the first sub-ECC circuit 111 can correct errors among the plurality of first data bits DQ1[1] to DQ1

[32] including first error bits whose number is less than or equal to the first number by using at least a portion of the plurality of first parity bits PB1[1] to PB1[6].

[0047] For another example, the first sub-ECC circuit 111 may correct errors among the plurality of first parity bits PB1[1] to PB1[6], including error bits whose number is less than or equal to the first number, by using at least a portion of the plurality of first parity bits PB1[1] to PB1[6].

[0048] Furthermore, for example, the first sub-ECC circuit 111 may correct errors including first error bits whose number is two or less among the 32 first data bits DQ1 [ 1 ] to DQ1 [ 32 ] output from the output multiplexer circuit 113 .

[0049] Furthermore, the ECC circuit 110 may include a second sub-ECC circuit 112 that corrects errors including erroneous bits whose number is less than or equal to the first number among the plurality of second bits BT2 .

[0050] like Figure 1B As shown in , the plurality of second bits BT2 (also referred to as “second plurality of bits”) may include a plurality of second data bits DQ2[1] to DQ2

[32] and a plurality of second parity bits PB2[1] to PB2[6].

[0051] Thus, for example, the second sub-ECC circuit 112 can correct errors among the plurality of second data bits DQ2[1] to DQ2

[32] including second error bits whose number is less than or equal to the first number by using at least a portion of the plurality of second parity bits PB2[1] to PB2[6].

[0052] For another example, the second sub-ECC circuit 112 may correct errors among the plurality of second parity bits PB2[1] to PB2[6], including error bits whose number is less than or equal to the first number, by using at least a portion of the plurality of second parity bits PB2[1] to PB2[6].

[0053] Furthermore, for example, the second sub-ECC circuit 112 may correct errors including second error bits whose number is two or less among the 32 second data bits DQ2 [ 1 ] to DQ2 [ 32 ] output from the output multiplexer circuit 113 .

[0054] In detail, the ECC circuit 110 may correct errors including erroneous bits whose number is less than or equal to a second number (eg, “4”) which is twice the first number (eg, “2”) among the plurality of bits BT.

[0055] However, the number and configuration of the plurality of bits BT, the plurality of first bits BT1, and the plurality of second bits BT2 are not limited to the above examples. In one example, the first plurality of bits BT1 (or referred to as the plurality of first bits) and the second plurality of bits (or referred to as the plurality of second bits) BT2 may each include the same number of bits.

[0056] like Figure 1A As shown in , the ECC circuit 110 may include an output multiplexer circuit 113 that outputs a plurality of first bits BT1 among a plurality of bits BT output from the memory device 120 to the first sub-ECC circuit 111 and outputs a plurality of second bits BT2 to the second sub-ECC circuit 112.

[0057] For example, Figure 1B As shown in , the output multiplexer circuit 113 may output 32 first data bits DQ1[1] to DQ1

[32] and / or 6 first parity bits PB1[1] to PB1[6] among the plurality of bits BT to the first sub-ECC circuit 111 .

[0058] In addition, for example, the output multiplexer circuit 113 may output 32 second data bits DQ2[1] to DQ2

[32] and / or 6 second parity bits PB2[1] to PB2[6] among the plurality of bits BT to the second sub-ECC circuit 112 .

[0059] Furthermore, the ECC circuit 110 may include a control logic circuit 114 . The control logic circuit 114 controls the output multiplexer circuit 113 .

[0060] For example, the control logic circuit 114 may execute software (or a program) to control at least one other component of the ECC circuit 110 (e.g., the output multiplexer circuit 113) and may perform various data processing or calculations. The control logic circuit 114 may include a central processing unit or a microprocessor and may control the overall operation of the ECC circuit 110. Therefore, the operations performed by the ECC circuit 110 can be understood as being performed under the control of the control logic circuit 114.

[0061] According to an embodiment, the control logic circuit 114 may include an algorithm for controlling the output multiplexer circuit 113. For example, the algorithm may be a software code programmed into the control logic circuit 114. As another example, the algorithm may be a hard code obtained by hard coding into the control logic circuit 114, but is not limited thereto.

[0062] In more detail, the control logic circuit 114 may control the output multiplexer circuit 113 by outputting a plurality of selection signals SEL according to an algorithm.

[0063] According to an embodiment, the control logic circuit 114 may control the output multiplexer circuit 113 to output at least a portion of the plurality of first bits BT1 to the first sub-ECC circuit 111 .

[0064] Furthermore, the control logic circuit 114 may control the output multiplexer circuit 113 to output at least a portion of the plurality of second bits BT2 to the second sub-ECC circuit 112 .

[0065] Furthermore, the control logic circuit 114 may determine the number of error bits occurring in each of the plurality of first bits BT1 and the plurality of second bits BT2 .

[0066] For example, the control logic circuit 114 may determine the number of first error bits among the plurality of first bits BT1 , and the control logic circuit 114 may determine the number of second error bits among the plurality of second bits BT2 .

[0067] Furthermore, when the number of first error bits exceeds a first number, the control logic circuit 114 may control the output multiplexer circuit 113 to output at least a portion of the first error bits to the second sub-ECC circuit 112 .

[0068] For example, when more than a first number of first error bits occur among the multiple first bits BT1 and when less than the first number of second error bits occur among the multiple second bits BT2, the control logic circuit 114 may control the output multiplexer circuit 113 to output at least a portion of the first error bits to the second sub-ECC circuit 112.

[0069] According to another embodiment, when the number of second erroneous bits exceeds the first number, the control logic circuit 114 may control the output multiplexer circuit 113 to output at least a portion of the plurality of second bits BT2 to the first sub-ECC circuit 111 .

[0070] For example, when more than a first number of second error bits occur among the multiple second bits BT2 and when a first error bit occurs among the multiple first bits BT1 whose number is less than the first number, the control logic circuit 114 may control the output multiplexer circuit 113 to output at least a portion of the second error bits to the first sub-ECC circuit 111.

[0071] When there are error bits whose number is less than or equal to the second number, the control logic circuit 114 may control the output multiplexer circuit 113 so that each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 receives error bits whose number is less than or equal to the first number to correct the errors.

[0072] According to an embodiment in the present disclosure, the ECC circuit 110 according to the embodiment can correct errors in a second number (twice the first number) of error bits using two sub-ECC circuits 111 and 112 (each correcting an error bit number less than or equal to the first number).

[0073] In detail, the ECC circuit 110 may correct errors including error bits exceeding a specific number by utilizing a plurality of sub-ECC circuits 111 and 112 , each of which corrects error bits whose number is less than or equal to the specific number.

[0074] The ECC circuit 110 may correct a relatively large number of erroneous bits with a relatively small circuit configuration and a relatively small logic depth.

[0075] Therefore, the ECC circuit 110 according to an embodiment of the present disclosure may improve the operating speed of the memory system 100 by using a relatively small circuit configuration and a relatively small logic depth.

[0076] Furthermore, the ECC circuit 110 may include a plurality of sub-ECC circuits 111 and 112 that correct erroneous bits whose number is less than or equal to a specific number among different bits, thereby increasing the number of bits capable of error correction in the memory system 100 .

[0077] Therefore, the ECC circuit 110 according to an embodiment of the present disclosure may improve the operating speed of the memory device 120 (or the memory system 100 ) by having a relatively small circuit configuration.

[0078] Furthermore, the ECC circuit 110 may improve the yield of the memory device 120 (or the memory system 100 ) by increasing the number of bits that can be error corrected.

[0079] Figure 2A configuration is shown in which an output multiplexer circuit including a plurality of multiplexers outputs a plurality of bits to a first sub-ECC circuit and / or a second sub-ECC circuit according to an embodiment.

[0080] like Figure 2 As shown in , the output multiplexer circuit 113 according to an embodiment may include a plurality of output multiplexers MUX1 to MUX12.

[0081] In more detail, the output multiplexer circuit 113 may include a plurality of output multiplexers MUX1 to MUX12 connected to one bit of the plurality of first bits BT1 and one bit of the plurality of second bits BT2 , respectively.

[0082] The number of multiplexers included in the output multiplexer circuit 113 according to the present disclosure is not limited to the above description, and may be understood as having a number corresponding to the number of the plurality of bits BT.

[0083] However, in the drawings and the following description, for convenience of description, the output multiplexer circuit 113 will be indicated and described as including the first to twelfth output multiplexers MUX1 to MUX12 .

[0084] Furthermore, the control logic circuit 114 may control at least a portion of the plurality of output multiplexers MUX1 to MUX12 to provide each of the plurality of bits BT to the first sub-ECC circuit 111 and / or the second sub-ECC circuit 112 .

[0085] For example, the output multiplexer circuit 113 may include a first output multiplexer MUX1 connected to a 1-1 bit DQ1[1] (ie, one bit of the plurality of first bits BT1) and a 2-1 bit DQ2[1] (ie, one bit of the plurality of second bits BT2).

[0086] In this case, the first output multiplexer MUX1 may selectively output one of the 1-1 bit DQ1 [ 1 ] and the 2-1 bit DQ2 [ 1 ] to the first sub-ECC circuit 111 based on the first selection signal SEL[ 0 ].

[0087] For example, the output multiplexer circuit 113 may include a second output multiplexer MUX2 connected to the 1-1 bit DQ1 [ 1 ] and the 2-1 bit DQ2 [ 1 ].

[0088] In this case, the second output multiplexer MUX2 may selectively output one of the 1-1 bit DQ1 [ 1 ] and the 2-1 bit DQ2 [ 1 ] to the second sub-ECC circuit 112 based on the first selection signal SEL[ 0 ].

[0089] In detail, the first and second output multiplexers MUX1 and MUX2 may output different bits of 1-1 bit DQ1[1] and 2-1 bit DQ2[1] to the first and second sub-ECC circuits 111 and 112, respectively, based on the first selection signal SEL[0].

[0090] In this case, for example, the first output multiplexer MUX1 and the second output multiplexer MUX2 may be understood as forming a pair.

[0091] In addition, for example, the output multiplexer circuit 113 may include a third output multiplexer MUX3 connected to the 1-2 bit DQ1[2] (i.e., another bit in the plurality of first bits BT1) and the 2-2 bit DQ2[2] (i.e., another bit in the plurality of second bits BT2).

[0092] In this case, the third output multiplexer MUX3 may selectively output one of the 1-2 bit DQ1 [ 2 ] and the 2-2 bit DQ2 [ 2 ] to the first sub-ECC circuit 111 based on the second selection signal SEL[ 1 ].

[0093] Furthermore, for example, the output multiplexer circuit 113 may include a fourth output multiplexer MUX4 connected to the 1-2 bit DQ1 [ 2 ] and the 2-2 bit DQ2 [ 2 ].

[0094] In this case, the fourth output multiplexer MUX4 may selectively output one of the 1-2 bit DQ1 [ 2 ] and the 2-2 bit DQ2 [ 2 ] to the second sub-ECC circuit 112 based on the second selection signal SEL[ 1 ].

[0095] In detail, the third output multiplexer MUX3 and the fourth output multiplexer MUX4 may output different bits of 1-2 bit DQ1[2] and 2-2 bit DQ2[2] to the first sub-ECC circuit 111 and the second sub-ECC circuit 112, respectively, based on the second selection signal SEL[1].

[0096] Therefore, the third output multiplexer MUX3 and the fourth output multiplexer MUX4 may be understood to form a pair.

[0097] Therefore, the output multiplexer circuit 113 may include a plurality of output multiplexers MUX1 to MUX12 operating in pairs.

[0098] Furthermore, the control logic circuit 114 may control at least a portion of the plurality of output multiplexers MUX1 to MUX12 included in the output multiplexer circuit 113 so that each of the first and second sub-ECC circuits 111 and 112 receives and corrects less than or equal to the first number of error bits.

[0099] According to an embodiment of the present disclosure, the ECC circuit 110 according to the embodiment may control at least a portion of the plurality of output multiplexers MUX1 to MUX12 to correct a relatively large number of error bits using a relatively small circuit configuration.

[0100] Therefore, the ECC circuit 110 according to an embodiment of the present disclosure may improve the operating speed of the memory system 100 by using a relatively small circuit configuration.

[0101] In addition, the ECC circuit 110 may include a plurality of sub-ECC circuits 111 and 112 that correct erroneous bits whose number is less than or equal to a specific number among distinct bits (or, different bits), thereby increasing the number of bits that can be error-corrected in the memory system 100.

[0102] By doing so, the ECC circuit 110 may improve the performance (eg, read speed) and yield of the memory device 120 (or the memory system 100 ).

[0103] Figure 3 A configuration according to an embodiment is shown in which the control logic circuit controls the output multiplexer circuit when each of the number of first error bits and the number of second error bits is smaller than the first number.

[0104] like Figure 3 As shown in , the control logic circuit 114 according to an embodiment may control the output multiplexer circuit 113 to output each of the plurality of bits BT to the first sub-ECC circuit 111 and / or the second sub-ECC circuit 112 .

[0105] In more detail, when an error bit number less than or equal to a first number occurs in each of the multiple first bits BT1 and the multiple second bits BT2, the control logic circuit 114 may control the output multiplexer circuit 113 to output each of the multiple first bits BT1 and the multiple second bits BT2 to the first sub-ECC circuit 111 and / or the second sub-ECC circuit 112.

[0106] For example, when error bits whose number is less than or equal to the first number occur in each of the plurality of first bits BT1 and the plurality of second bits BT2, the control logic circuit 114 may input a selection signal having a value of '0' to each of the plurality of output multiplexers MUX1 to MUX12.

[0107] Through this, the control logic circuit 114 can control the output multiplexer circuit 113 to output the plurality of first bits BT1 and the plurality of second bits BT2 to the first sub-ECC circuit 111 and the second sub-ECC circuit 112 , respectively.

[0108] In this case, it is assumed that each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 can correct errors including erroneous bits whose number is less than or equal to a first number (eg, “2”).

[0109] When first error bits whose number among the plurality of first bits BT1 is less than or equal to the first number occur, the control logic circuit 114 may control the output multiplexer circuit 113 to output the plurality of first bits BT1 to the first sub-ECC circuit 111 .

[0110] For example, when an error occurs in two bits DQ1[1] and DQ1[2] among multiple first bits BT1, the control logic circuit 114 can control the output multiplexer circuit 113 to output multiple first bits BT1 including 1-1 bit DQ1[1] and 1-2 bit DQ1[2] to the first sub-ECC circuit 111.

[0111] When second error bits whose number among the plurality of second bits BT2 is less than or equal to the first number occur, the control logic circuit 114 may control the output multiplexer circuit 113 to output the plurality of second bits BT2 to the second sub-ECC circuit 112 .

[0112] For example, when an error occurs in two bits DQ2[1] and DQ2[6] among the multiple second bits BT2, the control logic circuit 114 can control the output multiplexer circuit 113 to output the multiple second bits BT2 including 2-1 bit DQ2[1] and 2-6 bit DQ2[6] to the second sub-ECC circuit 112.

[0113] Furthermore, each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 may correct errors including erroneous bits of inputs whose number is less than or equal to the first number.

[0114] In more detail, the first sub-ECC circuit 111 may correct 1-1 bit DQ1[1] and 1-2 bit DQ1[2] in which errors occur among the plurality of input first bits BT1.

[0115] In addition, the second sub-ECC circuit 112 can correct 2-1 bits DQ2[1] and 2-6 bits DQ2[6] in which errors occur among the plurality of second bits BT2 input.

[0116] According to an embodiment of the present disclosure, when error bits whose number is less than or equal to the second number occur among the plurality of bits BT, the control logic circuit 114 may control the output multiplexer circuit 113 so that each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 receives and corrects the error bits whose number is less than or equal to the first number.

[0117] In detail, the ECC circuit 110 can correct a relatively large number of error bits through a relatively small circuit configuration.

[0118] By doing so, the ECC circuit 110 may improve the performance (eg, read speed) and yield of the memory device 120 (or the memory system 100 ).

[0119] Figure 4A A configuration according to an embodiment is shown in which the control logic circuit controls the output multiplexer circuit when the number of first error bits exceeds a first number and the number of second error bits is less than the first number. Figure 4B A configuration according to an embodiment is shown in which the control logic circuit controls the output multiplexer circuit when the number of first error bits is less than a first number and the number of second error bits exceeds the first number.

[0120] like Figure 4A As shown in , when more than a first number of first error bits occur in the plurality of first bits BT1 , the control logic circuit 114 according to an embodiment may control the output multiplexer circuit 113 to output at least one of the first error bits to the second sub-ECC circuit 112 .

[0121] In more detail, when more than a first number of first error bits occur in multiple first bits BT1, and a number of second error bits less than the first number occurs in multiple second bits BT2, the control logic circuit 114 can control the output multiplexer circuit 113 to output at least a portion of the first error bits to the second sub-ECC circuit 112.

[0122] In this case, it is assumed that each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 can correct errors including erroneous bits whose number is less than or equal to a first number (eg, “2”).

[0123] According to an embodiment, when three first error bits (e.g., DQ1[1], DQ1[2], and DQ1[3]) occur in a plurality of first bits BT1, and one second error bit (e.g., DQ2[1]) occurs in a plurality of second bits BT2, the control logic circuit 114 may control the output multiplexer circuit 113 to output 1-3 bits DQ1[3] to the second sub-ECC circuit 112.

[0124] For example, when three first error bits (e.g., DQ1[1], DQ1[2], and DQ1[3]) occur in the plurality of first bits BT1, and one second error bit (e.g., DQ2[1]) occurs in the plurality of second bits BT2, the control logic circuit 114 may input the third selection signal SEL[2] having a value of “1” to the fifth output multiplexer MUX5 and the sixth output multiplexer MUX6.

[0125] By this, the control logic circuit 114 can control the fifth output multiplexer MUX5 to output the 2-3 bits DQ2[3] to the first sub-ECC circuit 111. In addition, the control logic circuit 114 can control the sixth output multiplexer MUX6 to output the 1-3 bits DQ1[3] in which an error occurs to the second sub-ECC circuit 112.

[0126] In addition, the control logic circuit 114 may input a selection signal having a value of “0” (excluding the third selection signal SEL[ 2 ]) to the plurality of output multiplexers MUX1 , MUX2 , MUX3 , MUX4 , and MUX7 to MUX12 .

[0127] Thus, the control logic circuit 114 can control the input of a plurality of first bits BT1 excluding the 1-3 bits DQ1[3] to the first sub-ECC circuit 111. In addition, the control logic circuit 114 can control the input of a plurality of second bits BT2 excluding the 2-3 bits DQ2[3] to the second sub-ECC circuit 112.

[0128] Furthermore, each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 may correct errors including erroneous bits of inputs whose number is less than or equal to the first number.

[0129] For example, the first sub-ECC circuit 111 may correct 1-1 bit DQ1[1] and 1-2 bit DQ1[2] in which errors occur among input bits.

[0130] In addition, the second sub-ECC circuit 112 can correct 2-1 bits DQ2[1] and 1-3 bits DQ1[3] in which errors occur among the input bits.

[0131] According to another embodiment Figure 4B As shown in , when more than a first number of second error bits occur in the plurality of second bits BT2 , the control logic circuit 114 may control the output multiplexer circuit 113 to output at least a portion of the second error bits to the first sub-ECC circuit 111 .

[0132] In more detail, when second error bits exceeding the first number occur in multiple second bits BT2, and first error bits whose number is less than the first number occur in multiple first bits BT1, the control logic circuit 114 can control the output multiplexer circuit 113 to output at least a portion of the second error bits to the first sub-ECC circuit 111.

[0133] In this case, it is assumed that each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 can correct errors including erroneous bits whose number is less than or equal to a first number (eg, “2”).

[0134] According to an embodiment, when one first error bit (e.g., DQ1[1]) occurs among a plurality of first bits BT1 and three second error bits (e.g., DQ2[1], DQ2[2], and DQ2[3]) occur among a plurality of second bits BT2, the control logic circuit 114 may control the output multiplexer circuit 113 to output the 2-3 bits DQ2[3] to the first sub-ECC circuit 111.

[0135] For example, when one first error bit (e.g., DQ1[1]) occurs among multiple first bits BT1 and three second error bits (e.g., DQ2[1], DQ2[2], DQ2[3]) occur among multiple second bits BT2, the control logic circuit 114 may input the third selection signal SEL[2] having a value of "1" to the fifth output multiplexer MUX5 and the sixth output multiplexer MUX6.

[0136] By this, the control logic circuit 114 can control the fifth output multiplexer MUX5 to output the 2-3 bits DQ2[3] in which the error occurs to the first sub-ECC circuit 111. In addition, the control logic circuit 114 can control the sixth output multiplexer MUX6 to output the 1-3 bits DQ1[3] to the second sub-ECC circuit 112.

[0137] In addition, the control logic circuit 114 may input a selection signal having a value of “0” (excluding the third selection signal SEL[ 2 ]) to the plurality of output multiplexers MUX1 , MUX2 , MUX3 , MUX4 , and MUX7 to MUX12 .

[0138] Thus, the control logic circuit 114 can control the input of a plurality of first bits BT1 excluding the 1-3 bits DQ1[3] to the first sub-ECC circuit 111. In addition, the control logic circuit 114 can control the input of a plurality of second bits BT2 excluding the 2-3 bits DQ2[3] to the second sub-ECC circuit 112.

[0139] Furthermore, each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 may correct errors including erroneous bits of inputs whose number is less than or equal to the first number.

[0140] For example, the first sub-ECC circuit 111 may correct 1-1 bit DQ1[1] and 2-3 bit DQ2[3] in which errors occur among input bits.

[0141] In addition, the second sub-ECC circuit 112 can correct 2-1 bit DQ2[1] and 2-2 bit DQ2[2] in which errors occur among the input bits.

[0142] According to an embodiment of the present disclosure, when error bits whose number is less than or equal to the second number (e.g., “4”) occur among the plurality of bits BT, the control logic circuit 114 may control the output multiplexer circuit 113 so that each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 receives error bits whose number is less than or equal to the first number (e.g., “2”) to correct the errors.

[0143] Through this, the ECC circuit 110 can correct a relatively large number of error bits with a relatively small circuit configuration and a relatively small logic depth.

[0144] Therefore, the ECC circuit 110 according to an embodiment of the present disclosure may improve the performance (eg, read speed) and yield of the memory device 120 (or the memory system 100 ).

[0145] Figure 5 A configuration is shown in which a control logic circuit controls an output multiplexer circuit when the number of first error bits exceeds a first number according to an embodiment.

[0146] like Figure 5 As shown in , when more than a first number of first error bits occur in the plurality of first bits BT1 , the control logic circuit 114 according to an embodiment may control the output multiplexer circuit 113 to output at least a portion of the first error bits to the second sub-ECC circuit 112 .

[0147] In this case, it is assumed that each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 can correct errors including erroneous bits whose number is less than or equal to a first number (eg, “2”).

[0148] According to an embodiment, when three first error bits (e.g., DQ1[1], DQ1[2], and DQ1[3]) occur in a plurality of first bits BT1, and no second error bit occurs in a plurality of second bits BT2, the control logic circuit 114 may control the output multiplexer circuit 113 to output 1-3 bits DQ1[3] to the second sub-ECC circuit 112.

[0149] For example, when three first error bits (e.g., DQ1[1], DQ1[2], and DQ1[3]) occur in the plurality of first bits BT1, and no second error bit occurs in the plurality of second bits BT2, the control logic circuit 114 may input a third selection signal SEL[2] having a value of "1" to the fifth output multiplexer MUX5 and the sixth output multiplexer MUX6.

[0150] By this, the control logic circuit 114 can control the fifth output multiplexer MUX5 to output the 2-3 bits DQ2[3] to the first sub-ECC circuit 111. In addition, the control logic circuit 114 can control the sixth output multiplexer MUX6 to output the 1-3 bits DQ1[3] in which an error occurs to the second sub-ECC circuit 112.

[0151] In addition, the control logic circuit 114 may input a selection signal having a value of “0” (excluding the third selection signal SEL[ 2 ]) to the plurality of output multiplexers MUX1 , MUX2 , MUX3 , MUX4 , and MUX7 to MUX12 .

[0152] Thus, the control logic circuit 114 can control the input of a plurality of first bits BT1 excluding the 1-3 bits DQ1[3] to the first sub-ECC circuit 111. In addition, the control logic circuit 114 can control the input of a plurality of second bits BT2 excluding the 2-3 bits DQ2[3] to the second sub-ECC circuit 112.

[0153] Furthermore, each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 may correct errors including erroneous bits of inputs whose number is less than or equal to the first number.

[0154] For example, the first sub-ECC circuit 111 may correct 1-1 bit DQ1[1] and 1-2 bit DQ1[2] in which errors occur among input bits.

[0155] In addition, the second sub-ECC circuit 112 can correct 1-3 bits DQ1[3] in which errors occur among the input bits.

[0156] According to an embodiment of the present disclosure, when error bits whose number is less than or equal to the second number (e.g., “4”) occur among the plurality of bits BT, the control logic circuit 114 may control the output multiplexer circuit 113 so that each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 receives and corrects the error bits whose number is less than or equal to the first number (e.g., “2”).

[0157] Through this, the ECC circuit 110 can correct a relatively large number of error bits with a relatively small circuit configuration and a relatively small logic depth.

[0158] Therefore, the ECC circuit 110 according to an embodiment of the present disclosure may improve the performance (eg, read speed) and yield of the memory device 120 (or the memory system 100 ).

[0159] Figure 6 A configuration according to another embodiment is shown in which the control logic circuit controls the output multiplexer circuit when the number of first error bits exceeds a first number and the number of second error bits is less than the first number.

[0160] like Figure 6 As shown in , when more than a first number of first error bits occur in the plurality of first bits BT1 , the control logic circuit 114 according to an embodiment may control the output multiplexer circuit 113 to output at least a portion of the first error bits to the second sub-ECC circuit 112 .

[0161] In this case, it is assumed that each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 can correct errors including erroneous bits whose number is less than or equal to a first number (eg, “2”).

[0162] According to an embodiment, when four first error bits (e.g., DQ1[1], DQ1[2], DQ1[3], and DQ1[4]) occur in a plurality of first bits BT1, and no second error bit occurs in a plurality of second bits BT2, the control logic circuit 114 may control the output multiplexer circuit 113 to output 1-1 bit DQ1[1] and 1-2 bit DQ1[2] to the second sub-ECC circuit 112.

[0163] For example, when four first error bits (e.g., DQ1[1], DQ1[2], DQ1[3], and DQ1[4]) occur in the plurality of first bits BT1 and no second error bit occurs in the plurality of second bits BT2, the control logic circuit 114 may input a first selection signal SEL[0] having a value of “1” to the first output multiplexer MUX1 and the second output multiplexer MUX2. In addition, the control logic circuit 114 may input a second selection signal SEL[1] having a value of “1” to the third output multiplexer MUX3 and the fourth output multiplexer MUX4.

[0164] By this, the control logic circuit 114 can control the first output multiplexer MUX1 to output 2-1 bit DQ2[1] to the first sub-ECC circuit 111. In addition, the control logic circuit 114 can control the second output multiplexer MUX2 to output 1-1 bit DQ1[1] in which an error occurs to the second sub-ECC circuit 112.

[0165] By this, the control logic circuit 114 can control the third output multiplexer MUX3 to output 2-2 bit DQ2[2] to the first sub-ECC circuit 111. In addition, the control logic circuit 114 can control the fourth output multiplexer MUX4 to output 1-2 bit DQ1[2] in which an error occurs to the second sub-ECC circuit 112.

[0166] Furthermore, the control logic circuit 114 may input a selection signal having a value of “0” (excluding the first selection signal SEL[ 0 ] and the second selection signal SEL[ 1 ]) to the plurality of output multiplexers MUX5 to MUX12 .

[0167] Through this, the control logic circuit 114 can input a plurality of first bits BT1 excluding 1-1 bit DQ1[1] and 1-2 bit DQ1[2] to the first sub-ECC circuit 111. In addition, the control logic circuit 114 can input a plurality of second bits BT2 excluding 2-1 bit DQ2[1] and 2-2 bit DQ2[2] to the second sub-ECC circuit 112.

[0168] Furthermore, each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 may correct errors including erroneous bits of inputs whose number is less than or equal to the first number.

[0169] For example, the second sub-ECC circuit 112 may correct 1-1 bit DQ1[1] and 1-2 bit DQ1[2] in which errors occur among the input bits.

[0170] In addition, the first sub-ECC circuit 111 can correct 1-3 bits DQ1[3] and 1-4 bits DQ1[4] in which errors occur among the input bits.

[0171] According to an embodiment of the present disclosure, when error bits whose number is less than or equal to the second number (e.g., “4”) occur among the plurality of bits BT, the control logic circuit 114 may control the output multiplexer circuit 113 so that each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 receives and corrects the error bits whose number is less than or equal to the first number (e.g., “2”).

[0172] Through this, the ECC circuit 110 can correct a relatively large number of error bits with a relatively small circuit configuration and a relatively small logic depth.

[0173] Therefore, the ECC circuit 110 according to an embodiment of the present disclosure may improve the performance (eg, read speed) and yield of the memory device 120 (or the memory system 100 ).

[0174] Figure 7 is a flowchart illustrating an error correction method of a memory device according to an embodiment. Figure 8 is a flowchart illustrating a method of controlling a multiplexer included in an output multiplexer circuit according to an embodiment.

[0175] like Figure 7 and Figure 8 As shown together in FIG, the ECC circuit 110 (or the control logic circuit 114) according to an embodiment may control the output multiplexer circuit 113 so that each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 receives and corrects error bits whose number is less than or equal to a first number (e.g., “2”).

[0176] like Figure 7As shown in , when more than a first number of first error bits occur in the plurality of first bits BT1 , the ECC circuit 110 according to an embodiment may control the output multiplexer circuit 113 to output at least a portion of the first error bits to the second sub-ECC circuit 112 .

[0177] In operation S10 , the ECC circuit 110 according to an embodiment may store (write) a plurality of input bits in the memory device 120 .

[0178] For example, the ECC circuit 110 may input a plurality of input bits into the memory device 120 through at least one ECC encoder.

[0179] In this case, the ECC circuit 110 may transmit a write request including a plurality of input bits and input address information corresponding to each of the plurality of input bits to the memory device 120 .

[0180] According to an embodiment, two adjacent bits among the plurality of input bits may be stored in the memory device 120 with the same value.

[0181] For example, the 1-1 input bit and the 1-2 input bit may be stored with the same value in the memory device 120. Furthermore, the 1-3 input bit and the 1-4 input bit may be stored with the same value in the memory device 120.

[0182] In operation S20 , the ECC circuit 110 according to an embodiment may read a plurality of bits BT stored at addresses corresponding to addresses of a plurality of input bits.

[0183] In more detail, the ECC circuit 110 may read a plurality of bits BT stored in advance from the memory device 120. In this case, the plurality of bits BT may include a plurality of data bits and a plurality of parity bits.

[0184] In operation S30 , the ECC circuit 110 according to an embodiment may determine the number of first error bits and the number of second error bits.

[0185] In more detail, the ECC circuit 110 may determine the number of first error bits in which errors occur among the plurality of first bits BT1 .

[0186] The ECC circuit 110 according to an embodiment may determine that a bit having a value different from a value of a bit input to a corresponding address among a plurality of input bits is a first error bit among a plurality of first bits BT1 .

[0187] For example, when a 1-1 input bit having an address value corresponding to the 1-1 bit DQ1[1] is input to the memory device 120 as a value of “0”, but the 1-1 bit DQ1[1] is output from the memory device 120 as a value of “1”, the ECC circuit 110 may determine the 1-1 bit DQ1[1] as a first error bit.

[0188] For another example, when a 1-1 input bit having an address value corresponding to the 1-1 bit DQ1[1] is input to the memory device 120 with a value of “0” and the 1-1 bit DQ1[1] is output from the memory device 120 with a value of “0”, the ECC circuit 110 may determine that there is no error in the 1-1 bit DQ1[1].

[0189] In addition, the ECC circuit 110 may determine the number of second error bits in which errors occur among the plurality of second bits BT2 .

[0190] The ECC circuit 110 according to an embodiment may determine, among the plurality of second bits BT2 , that a bit having a value different from a value of a bit input to a corresponding address among the plurality of input bits is a second error bit.

[0191] For example, when the 2-3 input bit having an address value corresponding to the 2-3 bit DQ2[3] is input to the memory device 120 with a value of “1”, but the 2-3 bit DQ2[3] is output from the memory device 120 with a value of “0”, the ECC circuit 110 may determine that the 2-3 bit DQ2[3] is the second error bit.

[0192] The ECC circuit 110 according to an embodiment may determine whether an error occurs in each of a plurality of first bits BT1 and a plurality of second bits BT2 , thereby determining the number of first error bits and second error bits, respectively.

[0193] For example, the ECC circuit 110 may determine that errors occur in three bits of the plurality of first bits BT1. In detail, the ECC circuit 110 may determine that three first error bits occur among the plurality of first bits BT1.

[0194] In addition, the ECC circuit 110 may determine that an error occurs in one bit among the plurality of second bits BT2. In detail, the ECC circuit 110 may determine that one second error bit occurs among the plurality of second bits BT2.

[0195] In operation S40 , the ECC circuit 110 according to an embodiment may control the output multiplexer circuit 113 to output at least one of the first error bits to the second sub-ECC circuit 112 .

[0196] In more detail, when first error bits exceeding a first number occur in multiple first bits BT1, and second error bits whose number is less than the first number occur in multiple second bits BT2, the ECC circuit 110 can control the output multiplexer circuit 113 to output at least one of the first error bits to the second sub-ECC circuit 112.

[0197] In this case, it is assumed that each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 can correct errors including erroneous bits whose number is less than or equal to a first number (eg, “2”).

[0198] like Figure 8 As shown in , when three first error bits (e.g., DQ1[1], DQ1[2], and DQ1[3]) occur in a plurality of first bits BT1, and one second error bit (e.g., DQ2[6]) occurs in a plurality of second bits BT2, the ECC circuit 110 may control the output multiplexer circuit 113 to output the 1-1 bit DQ1[1] to the second sub-ECC circuit 112.

[0199] In operation S41 , the ECC circuit 110 may output the 1-1 bit DQ1 [ 1 ] to the second sub-ECC circuit 112 through the first output multiplexer MUX1 .

[0200] For example, the ECC circuit 110 may input the first selection signal SEL[0] having a value of “1” to the first output multiplexer MUX1. By doing so, the ECC circuit 110 may control the first output multiplexer MUX1 to output the 1-1 bit DQ1[1] in which an error occurs to the second sub-ECC circuit 112.

[0201] In operation S42 , the ECC circuit 110 may output the 2-1 bit DQ2 [ 1 ] to the first sub-ECC circuit 111 through the second output multiplexer MUX2 .

[0202] For example, the ECC circuit 110 may input the first selection signal SEL[0] having a value of “1” to the second output multiplexer MUX2 . In this case, the second output multiplexer MUX2 may output the 2-1 bit DQ2[1] to the first sub-ECC circuit 111 .

[0203] In addition, the ECC circuit 110 may input a selection signal having a value of “0” (excluding the first selection signal SEL[ 0 ]) to the plurality of output multiplexers MUX3 to MUX12 .

[0204] Thus, the control logic circuit 114 can control the input of the plurality of first bits BT1 excluding the 1-1 bit DQ1[1] to the first sub-ECC circuit 111. In addition, the control logic circuit 114 can control the input of the plurality of second bits BT2 excluding the 2-1 bit DQ2[1] to the second sub-ECC circuit 112.

[0205] Furthermore, each of the first and second sub-ECC circuits 111 and 112 according to an embodiment may correct errors including erroneous bits of inputs whose number is less than or equal to the first number.

[0206] For example, the first sub-ECC circuit 111 may correct 1-2 bits DQ1[2] and 1-3 bits DQ1[3] in which errors occur among the input bits.

[0207] In addition, the second sub-ECC circuit 112 can correct 2-6 bits DQ2[6] and 1-1 bits DQ1[1] in which errors occur among the input bits.

[0208] According to an embodiment of the present disclosure, when error bits whose number is less than or equal to the second number (e.g., “4”) occur among the plurality of bits BT, the control logic circuit 114 may control the output multiplexer circuit 113 so that each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 receives and corrects the error bits whose number is less than or equal to the first number (e.g., “2”).

[0209] Through this, the ECC circuit 110 can correct a relatively large number of error bits with a relatively small circuit configuration and a relatively small logic depth.

[0210] Therefore, the ECC circuit 110 according to an embodiment of the present disclosure may improve the performance (eg, read speed) and yield of the memory device 120 (or the memory system 100 ).

[0211] Figure 9 is a flowchart illustrating a method of storing selection information and address information according to values ​​of a plurality of bits according to an embodiment. Figure 10 is a flow chart illustrating a method of controlling an output multiplexer circuit based on stored address information and stored selection information according to an embodiment.

[0212] like Figure 9 and Figure 10 As shown in , the ECC circuit 110 according to an embodiment may store address information and selection information based on whether an error occurs in a plurality of bits BT. In addition, the ECC circuit 110 may control the output multiplexer circuit 113 based on the selection information stored in response to the address information.

[0213] In operation S43 , the ECC circuit 110 according to an embodiment may output one bit among the first error bits to the second sub-ECC circuit 112 .

[0214] In more detail, when the number of first error bits exceeds a first number and the number of second error bits is less than the first number, the ECC circuit 110 may control the output multiplexer circuit 113 to output one of the first error bits to the second sub-ECC circuit 112 .

[0215] Furthermore, in operation S44 , the ECC circuit 110 according to the embodiment may output one bit among the plurality of second bits BT2 to the first sub-ECC circuit 111 .

[0216] In more detail, the ECC circuit 110 may control the output multiplexer circuit 113 to output a bit identical to one of the first error bits input to the multiplexer among the plurality of second bits BT2 to the first sub-ECC circuit 111 .

[0217] For example, the ECC circuit 110 may control the output multiplexer circuit 113 to output the 1-1 bit DQ1 [ 1 ] in which an error occurs to the second sub-ECC circuit 112 .

[0218] In addition, the ECC circuit 110 may control the output multiplexer circuit 113 to output 2-1-bit DQ2 [ 1 ], which is the same as the 1-1-bit DQ1 [ 1 ] input to the multiplexer (eg, MUX1 or MUX2 ), to the first sub-ECC circuit 111 .

[0219] In this case, it is assumed that there is no error in the 2-1 bit DQ2[1].

[0220] Furthermore, in operation S50 , the ECC circuit 110 according to an embodiment may determine whether there is an error bit among the bits output from the first and second sub-ECC circuits 111 and 112 .

[0221] In more detail, the ECC circuit 110 may determine whether there is a bit output with a value different from a value of a bit input to a corresponding address among a plurality of input bits among the bits output from the first and second sub-ECC circuits 111 and 112 .

[0222] In detail, the ECC circuit 110 may determine whether there is an error bit output with a value different from a value of a bit input to a corresponding address among bits output from the first and second sub-ECC circuits 111 and 112 .

[0223] In this case, when an error bit exists among the bits output from the first and second sub-ECC circuits 111 and 112 , the ECC circuit 110 may output one of the first error bits to the second sub-ECC circuit 112 .

[0224] For example, when the value reduced by 1 from the number of first error bits exceeds the first number and the value increased by 1 from the number of second error bits is less than the first number, the ECC circuit 110 can output the 1-2 bit DQ1[2] in which the error occurs to the second sub-ECC circuit 112 through the fourth output multiplexer MUX4.

[0225] In addition, the ECC circuit 110 may output one of the plurality of second bits BT2 in which no error occurs to the first sub-ECC circuit 111. For example, the ECC circuit 110 may output the 2-2 bit DQ2[2] in which no error occurs to the first sub-ECC circuit 111 through the third output multiplexer MUX3.

[0226] In operation S60 , according to an embodiment, when there is no error bit among the bits output from the first and second sub-ECC circuits 111 and 112 , the ECC circuit 110 may store selection information.

[0227] In more detail, when there is no error bit among the bits output from the first and second sub-ECC circuits 111 and 112 , the ECC circuit 110 may store selection information about the selection signal transmitted to the output multiplexer circuit 113 .

[0228] When each of the bits output from the first and second sub-ECC circuits 111 and 112 is output with the same value as an input bit input to a corresponding address, the ECC circuit 110 may store selection information about the selection signal transmitted to the output multiplexer circuit 113 .

[0229] In this case, for example, the ECC circuit 110 may store selection information including information on a selection signal transmitted to the output multiplexer circuit 113 in the memory device 120 to control the output multiplexer circuit 113 .

[0230] For example, the ECC circuit 110 may store selection information including information on a selection signal transmitted to the output multiplexer circuit 113 in a one-time programmable (OTP) block included in the memory device 120 .

[0231] Also, in operation S70 , the ECC circuit 110 according to an embodiment may store address information.

[0232] In more detail, the ECC circuit 110 may match “address information including an address value of each of the first error bit and / or the second error bit output from the memory device 120 ” with selection information to be stored in the memory device 120 .

[0233] For example, when an error occurs in the 1-1 bit DQ1[1] and the error is corrected by the first sub-ECC circuit 111 or the second sub-ECC circuit 112, the ECC circuit 110 may store address information including the address value of the 1-1 bit DQ1[1] and selection information including the value of the selection signal for error correction in the memory device 120 correspondingly.

[0234] In this case, for example, the ECC circuit 110 may store address information including an address value of an error bit in which an error occurs among the plurality of bits BT in the memory device 120 (or OTP block).

[0235] In detail, when the ECC circuit 110 controls the output multiplexer circuit 113 to correct an error including an error bit among multiple bits BT, the ECC circuit 110 may store address information of the error bit in which the error occurs and selection information including a value generated for generating a selection signal for controlling the output multiplexer circuit 113 in correspondence with each other.

[0236] According to an embodiment of the present disclosure, the ECC circuit 110 may control the output multiplexer circuit 113 when the number of error bits is less than or equal to the second number, and may store selection information for correcting errors in the error bits and address information of the error bits. In one example, based on the sum of the number of first error bits and the number of second error bits being less than or equal to the second number, the ECC circuit 110 may store the address information of the first error bits and the second error bits in the OTP block in correspondence with the selection information.

[0237] Furthermore, the ECC circuit 110 may control the output multiplexer circuit 113 based on the stored selection information and the stored address information. By doing so, the ECC circuit 110 may correct errors in bits read according to the operation of the memory device 120.

[0238] like Figure 10 As shown in , the ECC circuit 110 according to an embodiment may correct error bits based on selection information and address information stored in the memory device 120 .

[0239] In operation S80 , the ECC circuit 110 may load first selection information and first address information from the memory device 120 .

[0240] In more detail, in response to an operation request for the memory device 120 being input, the ECC circuit 110 may identify first address information corresponding to the operation request among address information stored in the memory device 120 .

[0241] In this case, the operation request includes an address value, and may be understood as a signal (or request) requesting an operation to be performed on an address corresponding to an address value among address information stored in the memory device 120 .

[0242] For example, the operation request may be understood as a write request requesting to store data at a specific address of the memory device 120. In this case, the operation request may include an address value of the address where the data is requested to be stored.

[0243] As another example, the operation request may be understood as a read request requesting to read data stored at a specific address of the memory device 120. In this case, the operation request may include an address value of the address requested to read data.

[0244] However, the type and configuration of the operation request are not limited to the above examples.

[0245] For example, the ECC circuit 110 may identify first address information corresponding to the address value “17′h107” included in the operation request among the address information stored in the memory device 120 .

[0246] In addition, the ECC circuit 110 may load the first address information and the first selection information stored corresponding to the first address information from the memory device 120 .

[0247] In more detail, the ECC circuit 110 may load, from the memory device 120 , first address information corresponding to an address value included in the operation request and first selection information stored corresponding to the first address information.

[0248] In this case, the first selection information may be understood as including data on a selection signal for controlling the output multiplexer circuit 113 to correct an error when an error occurs in data stored at an address included in the first address information.

[0249] For example, the ECC circuit 110 may load, from the memory device 120 , first address information corresponding to the address value “17′h107” included in the operation request and first selection information “32′b100000010000000000000000000000000000000000” stored corresponding to the address value “17′h107” among the address information stored in the memory device 120 .

[0250] Furthermore, in operation S90 , the ECC circuit 110 may control the output multiplexer circuit 113 based on the first selection information.

[0251] In more detail, the ECC circuit 110 may control the output multiplexer circuit 113 based on the first selection information loaded from the memory device 120. Through this, the ECC circuit 110 may correct an error bit that occurs when the memory device 120 operates in response to an operation request.

[0252] For example, the ECC circuit 110 may control at least a portion of the plurality of output multiplexers MUX1 to MUX12 included in the output multiplexer circuit 113 based on the first selection information “32′b100000010000000000000000000000000000000”.

[0253] According to an embodiment of the present disclosure, the ECC circuit 110 may determine first address information and first selection information corresponding to the address value included in the operation request among information stored in the memory device 120 in response to a request requesting an operation on a specific address of the memory device 120.

[0254] Furthermore, the ECC circuit 110 may control the output multiplexer circuit 113 based on the first selection information.

[0255] Thus, the ECC circuit 110 may correct errors including generated error bits when the memory device 120 operates in response to an operation request.

[0256] Therefore, the ECC circuit 110 (or the memory system 100 ) according to an embodiment of the present disclosure may reduce the time required to correct an error bit occurring according to the operation of the memory device 120 .

[0257] Figure 11 is a block diagram illustrating a memory system according to an embodiment. Figure 12 A configuration in which a control logic circuit controls an input multiplexer and an output multiplexer according to an embodiment is shown.

[0258] like Figure 11 and Figure 12 As shown together in FIG, a memory system 100A according to an embodiment may include an ECC circuit 110A and a memory device 120 .

[0259] in this case, Figure 11 and Figure 12 The memory system 100A shown in FIG. 1 can be understood as Figure 1A and Figure 1B Accordingly, the same reference numerals are used for components that are the same as or substantially the same as those described above, and additional descriptions that overlap with those described above will be omitted to avoid redundancy.

[0260] The memory system 100A may include an ECC circuit 110A connected to a memory device 120 .

[0261] According to an embodiment, the ECC circuit 110A may include a first sub-ECC circuit 111 , a second sub-ECC circuit 112 , an output multiplexer circuit 113 , an input multiplexer circuit 115 , a first sub-encoder 161 , a second sub-encoder 162 , and a control logic circuit 114 .

[0262] Control logic circuit 114 may control input multiplexer circuit 115 and output multiplexer circuit 113 .

[0263] like Figure 12 As shown in , the control logic circuit 114 may control the input multiplexer circuit 115 and the output multiplexer circuit 113 by outputting a plurality of selection signals.

[0264] According to an embodiment, the control logic circuit 114 may control the input multiplexer circuit 115 to transmit the plurality of first bits BT1 input through the first sub-encoder 161 and the plurality of second bits BT2 input through the second sub-encoder 162 to the memory device 120 .

[0265] Furthermore, when first error bits exceeding a first number occur in the plurality of first bits BT1 , the control logic circuit 114 according to an embodiment may control the output multiplexer circuit 113 to output at least one of the first error bits to the second sub-ECC circuit 112 .

[0266] For example, when more than a first number of first error bits occur in the plurality of first bits BT1 , the control logic circuit 114 may control at least some of the output multiplexers of the output multiplexer circuit 113 to output at least one of the first error bits to the second sub-ECC circuit 112 .

[0267] Furthermore, the control logic circuit 114 may control the input multiplexer circuit 115 to correspond to the output multiplexer circuit 113 in response to controlling the output multiplexer circuit 113 .

[0268] In more detail, when controlling the output multiplexer circuit 113 , the control logic circuit 114 may control an input multiplexer corresponding to the output multiplexer of the output multiplexer circuit 113 among the input multiplexers of the input multiplexer circuit 115 .

[0269] According to an embodiment, when more than a first number of first error bits occur in a plurality of first bits BT1, and a number of second error bits less than the first number occurs in a plurality of second bits BT2, the control logic circuit 114 may control the output multiplexer circuit 113 to output at least a portion of the first error bits to the second sub-ECC circuit 112.

[0270] In this case, it is assumed that each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 can correct errors including erroneous bits whose number is less than or equal to a first number (eg, “2”).

[0271] When three first error bits (e.g., DQ1[1], DQ1[2], and DQ1[3]) occur in a plurality of first bits BT1, and one second error bit (e.g., DQ2[1]) occurs in a plurality of second bits BT2, the control logic circuit 114 may control the output multiplexer circuit 113 to output 1-3 bits DQ1[3] to the second sub-ECC circuit 112.

[0272] When three first error bits (e.g., DQ1[1], DQ1[2], and DQ1[3]) occur in the plurality of first bits BT1, and one second error bit (e.g., DQ2[1]) occurs in the plurality of second bits BT2, the control logic circuit 114 may input a third selection signal SEL[2] having a value of “1” to the fifth output multiplexer MUX5 and the sixth output multiplexer MUX6.

[0273] By this, the control logic circuit 114 can control the fifth output multiplexer MUX5 to output the 2-3 bits DQ2[3] to the first sub-ECC circuit 111. In addition, the control logic circuit 114 can control the sixth output multiplexer MUX6 to output the 1-3 bits DQ1[3] in which an error occurs to the second sub-ECC circuit 112.

[0274] Furthermore, in addition to this, the control logic circuit 114 may input the third selection signal SEL[ 2 ] having a value of “1” to the fifth input multiplexer IM5 and the sixth input multiplexer IM6 .

[0275] In addition, the control logic circuit 114 may input a selection signal having a value of “0” (excluding the third selection signal SEL[ 2 ]) to the plurality of output multiplexers MUX1 , MUX2 , MUX3 , MUX4 , and MUX7 to MUX12 .

[0276] Furthermore, in addition to this, the control logic circuit 114 may input a selection signal having a value of “0” (excluding the third selection signal SEL[ 2 ]) to the plurality of input multiplexers IM1 , IM2 , IM3 , IM4 , and IM7 to IM12 .

[0277] According to an embodiment of the present disclosure, the control logic circuit 114 may control the output multiplexer circuit 113 so that each of the first and second sub-ECC circuits 111 and 112 corrects errors including error bits whose number is less than or equal to a first number (eg, “2”).

[0278] Through this, the ECC circuit 110A can correct a relatively large number of error bits with a relatively small circuit configuration.

[0279] Therefore, the ECC circuit 110A according to an embodiment of the present disclosure can improve the operating speed of the memory device 120 (or the memory system 100) by having a relatively small circuit configuration. In addition, the ECC circuit 110A can improve the yield of the memory device 120 (or the memory system 100) by increasing the number of bits that can be error corrected.

[0280] Furthermore, in addition to this, the control logic circuit 114 may control the input multiplexers IM1 to IM12 included in the input multiplexer circuit 115 to correspond to the output multiplexers MUX1 to MUX12 included in the output multiplexer circuit 113 .

[0281] In detail, the control logic circuit 114 may control the output multiplexer circuit 113 and the input multiplexer circuit 115 together using a plurality of selection signals SEL[ 0 ] to SEL[ 5 ].

[0282] Therefore, when observed from a system or layer outside the memory system 100A, the control logic circuit 114 can control the output multiplexer circuit 113 and the input multiplexer circuit 115 together so as to determine that each of the multiple bits BT1 and BT2 is written to the memory device 120 and read from the memory device 120 according to a preset address.

[0283] Through this, the memory system 100A according to the embodiment of the present disclosure can prevent address mismatch between the memory system 100A and a system or layer outside the memory system 100A due to a change in a transmission path of bits.

[0284] Figure 13 is a block diagram illustrating a memory system including a memory controller and a memory device according to an embodiment. Figure 14 It shows Figure 13 A block diagram of the configuration of a memory device in FIG.

[0285] like Figure 13 As shown in , a memory system 1000 may include a memory device 1100 and a memory controller 1200 .

[0286] Figure 13 The memory system 1000 may be a resistive memory device based on a resistive memory. For example, the memory device 1100 may be an MRAM, a ReRAM, or a PRAM.

[0287] The memory device 1100 may receive an input / output signal IO from the memory controller 1200 through an input / output line, may receive a control signal CTRL from the memory controller 1200 through a control line, and may receive external power PWR from the memory controller 1200 through a power line.

[0288] The memory system 1000 may store data in the memory device 1100 under the control of the memory controller 1200 .

[0289] According to an embodiment, the memory controller 1200 may include an ECC circuit 110A. In addition, the ECC circuit 110A may include a first sub-ECC circuit 111A and a second sub-ECC circuit 112A.

[0290] in this case, Figure 13 The ECC circuit 110A shown in FIG can be understood as Figure 1A Therefore, descriptions overlapping with those above will be omitted to avoid redundancy.

[0291] According to an embodiment, the ECC circuit 110A may correct error bits included in bits output from the memory device 1100 .

[0292] In more detail, the ECC circuit 110A may correct errors occurring in the process of storing and reading data in and from the memory device 1100 .

[0293] The first sub-ECC circuit 111A according to an embodiment may correct error bits whose number is less than or equal to a first number (eg, “2”). In addition, the second sub-ECC circuit 112A may correct error bits whose number is less than or equal to the first number.

[0294] Therefore, the ECC circuit 110A may correct error bits, the number of which is less than or equal to a second number (eg, “4”), which is twice the first number, among the bits output from the memory device 1100 .

[0295] Memory device 1100 may include a memory cell array 1110 and a peripheral circuit 1115. Memory cell array 1110 may have a planar two-dimensional structure or a vertical three-dimensional structure. Memory cell array 1110 may be composed of a plurality of memory cells. Each memory cell may store single-bit data or multi-bit data.

[0296] In the design layout, the memory cell array 1110 can be located next to or above the peripheral circuit 1115. This structure in which the memory cell array 1110 is located above the peripheral circuit 1115 is called a COP (cell on peripheral) structure. The memory cell array 1110 can be manufactured as a separate chip from the peripheral circuit 1115. The upper chip including the memory cell array 1110 and the lower chip including the peripheral circuit 1115 can be connected to each other using a bonding method. This structure is called a C2C (chip-to-chip) structure.

[0297] The peripheral circuit 1115 may include all analog circuits or digital circuits required to store or read data in the memory cell array 1110. The peripheral circuit 1115 may receive external power PWR input through a power line and may generate various levels of internal power.

[0298] The peripheral circuit 1115 may receive commands, addresses, and data from the memory controller 1200 through input / output lines. The peripheral circuit 1115 may store data in the memory cell array 1110 according to the control signal CTRL. In addition, the peripheral circuit 1115 may read data stored in the memory cell array 1110 and provide the read data to the memory controller 1200.

[0299] According to an embodiment, peripheral circuit 1115 may include output multiplexer circuit 113A.

[0300] The output multiplexer circuit 113A according to an embodiment may transmit at least a portion of data bits (or parity bits) output from the memory cell array 1110 to the ECC circuit 110A.

[0301] like Figure 13 and Figure 14 As shown together, memory device 1100 may include a memory cell array 1110 and peripheral circuits 1115. Peripheral circuits 1115 may include a row decoder 1120, a column decoder 1130, input / output circuits 1140, a word line voltage generator 1150, control logic circuit 114A, and an OTP block 1211.

[0302] Memory cell array 1110 may include a plurality of memory blocks BLK1 to BLKn. Each memory block may be composed of a plurality of memory cells. Each memory cell may store multiple bits of data. Each memory block (e.g., BLK1) may be connected to a plurality of word lines WL1 to WLm. In some embodiments, n and m are positive integers.

[0303] The row decoder 1120 may be connected to the memory cell array 1110 through a plurality of word lines WL1 to WLm. The row decoder 1120 may select a word line during a program operation or a read operation. The row decoder 1120 may receive a word line voltage VWL from a word line voltage generator 1150 and may provide the word line voltage VWL for a program operation or a read operation to a selected word line.

[0304] The column decoder 1130 can be connected to the memory cell array 1110 through source lines SL and / or bit lines BL. The column decoder 1130 can select the source line SL or the bit line BL in response to a selection signal provided from the control logic circuit 114A. The column decoder 1130 can use a plurality of NMOS transistors (not shown) to select the source line SL or the bit line BL.

[0305] The input / output circuit 1140 may be internally connected to the column decoder 1130 through a data line, and may be externally connected to the ECC circuit 110A (or the memory controller 1200 ).

[0306] The input / output circuit 1140 may receive program data from the memory controller 1200 during a program operation. In addition, the input / output circuit 1140 may provide at least a portion of data read from the memory cell array 1110 to the memory controller 1200 during a read operation.

[0307] For example, the input / output circuit 1140 may provide at least a portion of the bits read from the memory cell array 1110 to the ECC circuit 110A through the output multiplexer circuit 113A.

[0308] The input / output circuit 1140 may include a sense amplifier (S / A) 1141 and a write driver (W / D) 1142. The input / output circuit 1140 may provide data to the write driver 1142 in response to a control signal or may output data provided from the sense amplifier 1141 to the outside.

[0309] The sense amplifier 1141 can read data stored in a selected memory cell by sensing the difference between the voltage of the source line SL and a reference voltage Vref during a read operation. In this case, the reference voltage Vref can be provided by a reference voltage generator circuit (not shown). The sense amplifier 1141 can operate in response to a control signal provided by the control logic circuit 114A.

[0310] The write driver 1142 may receive a control signal from the control logic circuit 114A and may provide a programming current I_PGM to the memory cell array 1110. In this case, the programming current I_PGM is used to program a selected memory cell to one of a plurality of states. During a machine learning compiler (MLC) programming operation, the write driver 1142 may provide the programming current I_PGM once or multiple times depending on the plurality of states of the selected memory cell.

[0311] The word line voltage generator 1150 may receive internal power from the control logic circuit 114A and may generate a word line voltage VWL required for reading or writing data. The word line voltage VWL may be provided to a selected word line sWL via the row decoder 1120. The word line voltage generator 1150 may include a plurality of word line drivers 1151 to 115m (e.g., first to mth word line drivers 1151 to 115m).

[0312] The OTP block 1211 may store address information of a memory block or a memory cell in the memory cell array 1110 where an error bit is output during operation of the memory device 1100 .

[0313] For example, when error bits are output from the memory cell array 1110 , the OTP block 1211 may store address information including an address value of each memory block or memory cell in which the error bits are output.

[0314] In addition, when an error bit is output, the OTP block 1211 may store selection information on a selection signal SEL that is transmitted to the output multiplexer circuit 113A to correct the error bit by controlling the output multiplexer circuit 113A.

[0315] For example, when error bits are output from the memory cell array 1110 , when all error bits are corrected by the ECC circuit 110A by controlling the output multiplexer circuit 113A, the OTP block 1211 may store selection information about the selection signal SEL.

[0316] In this case, the selection information may be stored in the OTP block 1211 in correspondence with the address information.

[0317] The control logic circuit 114A may control a read operation and / or a write operation of the memory device 1100 using a command CMD, an address ADDR, and a control signal CTRL provided from the memory controller 1200 (or the ECC circuit 110A). The address ADDR may include a row address for selecting a memory block or a word line, and a column address for selecting a memory cell.

[0318] The control logic circuit 114A may include a register 1212 .

[0319] The control logic circuit 114A may load information stored in the OTP block 1211 through the register 1212 in response to an operation of the memory system 1000 (or the memory device 1100 ).

[0320] In more detail, the control logic circuit 114A may load the address information and selection information stored in the OTP block 1211 through the register 1212 in response to the operation of the memory system 1000 .

[0321] Furthermore, the control logic circuit 114A may control the output multiplexer circuit 113A using the address information and selection information loaded from the OTP block 1211 through the register 1212 .

[0322] For example, when more than a first number of first error bits occur in the plurality of first bits BT1 , the control logic circuit 114A may control the output multiplexer circuit 113A to output at least one of the first error bits to the second sub-ECC circuit 112A.

[0323] In more detail, when more than a first number of first error bits occur in multiple first bits BT1, and a number of second error bits less than the first number occurs in multiple second bits BT2, the control logic circuit 114A can control the output multiplexer circuit 113A to output at least one of the first error bits to the second sub-ECC circuit 112A.

[0324] In this case, it is assumed that each of the first sub-ECC circuit 111A and the second sub-ECC circuit 112A can correct errors including erroneous bits whose number is less than or equal to a first number (eg, “2”).

[0325] When error bits, the number of which is less than or equal to a second number (e.g., “4”) (twice the first number), occur among the plurality of bits BT, the control logic circuit 114A may control the output multiplexer circuit 113A so that each of the first sub-ECC circuit 111A and the second sub-ECC circuit 112A receives and corrects the error bits, the number of which is less than or equal to the first number (e.g., “2”).

[0326] Through this, the ECC circuit 110A can correct a relatively large number of error bits with a relatively small circuit configuration and a relatively small logic depth.

[0327] Therefore, the ECC circuit 110A according to an embodiment of the present disclosure may improve the performance (eg, read speed) and yield of the memory device 1100 (or the memory system 1000 ).

[0328] As described herein, when error bits whose number among the plurality of bits BT is less than or equal to the second number occur, the control logic circuit 114A according to an embodiment of the present disclosure may control the output multiplexer circuit 113A so that each of the first sub-ECC circuit 111 and the second sub-ECC circuit 112 may receive and correct the error bits whose number is less than or equal to the first number.

[0329] In detail, the ECC circuit 110 can correct a relatively large number of error bits through a relatively small circuit configuration.

[0330] Therefore, the ECC circuit 110 according to an embodiment of the present disclosure may improve the operating speed of the memory device 120 (or the memory system 100 ) by having a relatively small circuit configuration.

[0331] Furthermore, the ECC circuit 110 may improve the yield of the memory device 120 (or the memory system 100 ) by increasing the number of bits that can be error corrected.

[0332] Furthermore, the ECC circuit 110 according to an embodiment may determine, in response to a request for requesting an operation regarding a specific address of the memory device 120, first address information and first selection information corresponding to the address value included in the operation request, among the information stored in the memory device 120. Furthermore, the ECC circuit 110 may control the output multiplexer circuit 113 based on the first selection information.

[0333] Through this, the ECC circuit 110 may correct errors including generated error bits when the memory device 120 operates in response to an operation request.

[0334] Therefore, the ECC circuit 110 (or the memory system 100 ) according to an embodiment of the present disclosure may reduce the time required to correct an error bit occurring according to the operation of the memory device 120 .

[0335] According to an embodiment of the present disclosure, an ECC circuit can increase the operating speed of a memory system and the number of bits capable of error correction, thereby improving the yield and performance of a memory device.

[0336] The above description is a specific embodiment for carrying out the present disclosure. Embodiments in which the design is simply changed or embodiments in which the design is easily changed may be included in the present disclosure as well as the above-mentioned embodiments. In addition, technologies that are easily changed and implemented by using the above-mentioned embodiments may be included in the present disclosure. Although the present disclosure has been described with reference to the embodiments of the present disclosure, it will be clear to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. An error correction code circuit connected to a memory device, the error correction code circuit comprising: a first sub-error correction code circuit configured to correct a first error including a first error bit; a second sub-error correction code circuit configured to correct a second error including a second error bit; an output multiplexer circuit configured to output a plurality of bits, wherein a first plurality of bits among the plurality of bits are output to a first sub-error correction code circuit, and wherein a second plurality of bits among the plurality of bits are output to a second sub-error correction code circuit; and a control logic circuit configured to control the output multiplexer circuit, and The control logic circuit is further configured as follows: Based on the number of the first error bits exceeding the first number and the number of the second error bits being less than the first number, the output multiplexer circuit is controlled to output at least one of the first error bits to the second sub-error correction code circuit.

2. The error correction code circuit according to claim 1, wherein The output multiplexer circuit includes: a first output multiplexer configured to receive the 1-1 bit and the 2-1 bit to be output to the first sub-error correction code circuit and the second sub-error correction code circuit; and a second output multiplexer configured to receive the 1-1 bit and the 2-1 bit to be output to the first sub-error correction code circuit and the second sub-error correction code circuit, and The control logic circuit is further configured to: based on the number of the first error bits being less than or equal to the first number and the number of the second error bits being less than or equal to the first number, outputting the 1-1 bit to the first sub-error correction code circuit via the first output multiplexer; and The 2-1 bits are output to the second sub-error correction code circuit through the second output multiplexer.

3. The error correction code circuit according to claim 2, wherein: The control logic circuit is further configured to: based on the first error bits including the 1-1 bit and the second error bits not including the 2-1 bit, and in response to the number of the first error bits exceeding the first number and the number of the second error bits being less than the first number, outputting the 2-1 bit to the first sub-error correction code circuit via the first output multiplexer; and The 1-1 bit is output to the second sub-error correction code circuit through the second output multiplexer.

4. The error correction code circuit according to claim 3, wherein: The output multiplexer circuit also includes: a third output multiplexer configured to receive the 1-2 bit and the 2-2 bit to be output to the first sub-error correction code circuit and the second sub-error correction code circuit; and a fourth output multiplexer configured to receive the 1-2 bit and the 2-2 bit to be output to the first sub-error correction code circuit and the second sub-error correction code circuit, and The control logic circuit is further configured to: based on the value reduced by one from the first number of error bits exceeding the first number and the value increased by one from the second number of error bits being less than the first number, outputting the 2-2 bit to the first sub-error correction code circuit via the third output multiplexer; and The 1-2 bits are output to the second sub-error correction code circuit through the fourth output multiplexer.

5. The error correction code circuit according to claim 3, wherein: The control logic circuit is further configured to: when there is no error bit among the bits output from the first sub-error correction code circuit and the second sub-error correction code circuit, Select information regarding select signals sent to output multiplexer circuits is stored in the memory device.

6. The error correction code circuit according to claim 5, wherein The control logic circuit is further configured to store address information of the first error bit and the second error bit output from the memory device in correspondence with the selection information in the memory device.

7. The error correction code circuit according to claim 6, wherein: The control logic circuit is further configured to: In response to receiving an operation request for the memory device, loading first selection information from the memory device, wherein the first selection information is stored corresponding to first address information, the first address information being associated with an address value included in the operation request; and The output multiplexer circuit is controlled based on the first selection information.

8. The error correction code circuit according to any one of claims 1 to 7, wherein: The control logic circuit is further configured to: identifying a first bit among a first plurality of bits as a first error bit, the first bit having a different data value than a bit having a corresponding address value among a plurality of input bits input to the memory device; and A second bit of the second plurality of bits is identified as a second erroneous bit, the second bit having a different data value than a bit of the plurality of input bits having a corresponding address value.

9. The error correction code circuit according to any one of claims 1 to 7, wherein: the first plurality of bits includes a first plurality of data bits and a first plurality of parity bits, wherein the second plurality of bits includes a plurality of second data bits and a plurality of second parity bits, wherein the first sub-error correction code circuit uses at least a portion of the plurality of first parity bits to correct one or more errors in the input error bits, and The second sub-error correction code circuit uses at least a portion of the plurality of second parity bits to correct one or more errors in the input error bits.

10. The error correction code circuit according to any one of claims 1 to 7, wherein: The first plurality of bits and the second plurality of bits each include the same number of bits.

11. A method of performing error correction on a plurality of bits read from a memory device, the method comprising: storing a plurality of input bits in the memory device; reading from the memory device a plurality of bits stored at addresses corresponding to address values ​​of the plurality of input bits; determining the number of first error bits occurring in a first plurality of bits among the plurality of bits capable of correcting errors by the first sub-error correction code circuit and the number of second error bits occurring in a second plurality of bits among the plurality of bits capable of correcting errors by the second sub-error correction code circuit; as well as Based on the number of the first error bits exceeding the first number and the number of the second error bits being less than the first number, the output multiplexer circuit is controlled to output at least one of the first error bits to the second sub-error correction code circuit.

12. The method of claim 11, further comprising: determining a first bit among the first plurality of bits as a first error bit, the first bit having a different data value than a bit having a corresponding address value among the plurality of input bits; as well as A second bit among the second plurality of bits is determined as a second erroneous bit, the second bit having a different data value from a bit having a corresponding address value among the plurality of input bits.

13. The method of claim 11, further comprising: In response to the number of first error bits exceeding a first number and the number of second error bits being less than a second number, outputting bit 1-1 of the first plurality of bits to the second sub-error correction code circuit via a first output multiplexer in the output multiplexer circuit, and The 2-1 bits of the second plurality of bits are output to the first sub-error correction code circuit through a second output multiplexer in the output multiplexer circuit.

14. The method of claim 13, further comprising: In response to each of a first output bit output from the first sub-error correction code circuit and a second output bit output from the second sub-error correction code circuit having the same value as each of the plurality of input bits having corresponding address values, storing in the memory device selection information regarding a selection signal generated for controlling an output multiplexer circuit; as well as Address information of the first error bit and the second error bit is stored.

15. The method of claim 14, further comprising: In response to receiving an operation request for the memory device, loading first selection information from the memory device, wherein the first selection information is stored corresponding to first address information, and the first address information corresponds to an address value included in the operation request; and The output multiplexer circuit is controlled based on the first selection information.

16. A memory system comprising: a memory device configured to read a plurality of bits; as well as a memory controller configured to control the operation of the memory device, and The memory controller includes an error correction code circuit, which includes: a first sub-error correction code circuit configured to correct a first error including a first error bit, and a second sub-error correction code circuit configured to correct a second error including a second error bit, and The error correction code circuit further includes: an output multiplexer circuit configured to output a plurality of bits, wherein a first plurality of bits among the plurality of bits are output to a first sub-error correction code circuit, and wherein a second plurality of bits among the plurality of bits are output to a second sub-error correction code circuit, and a control logic circuit configured to control the output multiplexer circuit, and The control logic circuit is further configured as follows: Based on the number of the first error bits exceeding the first number and the number of the second error bits being less than the first number, the output multiplexer circuit is controlled to output at least a portion of the first error bits to the second sub-error correction code circuit.

17. The memory system of claim 16, wherein: The output multiplexer circuit also includes: a first output multiplexer configured to receive the 1-1 bit and the 2-1 bit to be output to the first sub-error correction code circuit and the second sub-error correction code circuit; and a second output multiplexer configured to receive the 1-1 bit and the 2-1 bit to be output to the first sub-error correction code circuit and the second sub-error correction code circuit, and The control logic circuit is further configured to: based on the first error bit including the 1-1 bit and the second error bit not including the 2-1 bit, and in response to the number of the first error bits exceeding the first number and the number of the second error bits being less than the first number, The 2-1 bit is output to the first sub-error correction code circuit through the first output multiplexer, and The 1-1 bit is output to the second sub-error correction code circuit through the second output multiplexer.

18. The memory system of claim 16, wherein: The control logic circuit is further configured to: based on the correspondence between the value of each bit output from the first sub-error correction code circuit and the second sub-error correction code circuit and the value of each bit input to the memory device, Selection information regarding a selection signal sent to an output multiplexer circuit is stored in a one-time programmable block.

19. The memory system of claim 18, wherein: The control logic circuit is further configured to: based on the sum of the number of the first error bits and the number of the second error bits being less than or equal to a second number, the second number being twice the first number, Address information of the first error bit and the second error bit is stored in a one-time programmable block corresponding to the selection information.

20. The memory system of claim 19, wherein: The control logic circuit is further configured to: In response to the memory device being driven, obtaining the address information and the selection information stored in the one-time programmable block through a register; In response to an operation request for the memory device being received, loading first selection information stored corresponding to first address information from a register, the first address information corresponding to an address value included in the operation request, the first address information being among the address information; and The output multiplexer circuit is controlled based on the first selection information.

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