Gate side wall manufacturing method and semiconductor device
By forming a sandwich-structured gate sidewall on the sidewall of the gate structure of the MOS device and removing the film layer in a specific area by etching, the parasitic capacitance problem between the gate and the source and drain regions is solved, the response speed of the PMOS is improved, the parasitic capacitance of the NMOS is reduced, and the high-frequency performance of the device is enhanced.
Patent Information
- Application Number
- CN202410299119.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-15
- Publication Date
- 2025-09-19
AI Technical Summary
In the prior art, there is a large parasitic capacitance between the gate and source/drain regions of a MOS device, which affects the response speed of the device under alternating current. In addition, the response speed of PMOS is lower than that of NMOS, making it difficult to improve the performance of both at the same time.
A sandwich-structured gate sidewall is formed on the sidewalls of the gate structure in the NMOS and PMOS regions, including a first film layer and a third film layer with the same inner and outer materials, and a second film layer with a smaller K value. The second film layer and the third film layer in the PMOS region are removed by dry and wet etching, while the sandwich structure in the NMOS region is retained.
The response speed of PMOS is improved, while the parasitic capacitance of NMOS is reduced, the performance of NMOS is kept unchanged, and the switching speed of the device at high frequency is enhanced.
Smart Images
Figure CN120674309A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a gate sidewall manufacturing method and a semiconductor device. Background Art
[0002] As the device size decreases, the lateral electric field and the effective channel electric field in the MOS device increase, causing collision ionization of carriers during transport, generating additional electron-hole pairs, and injecting some hot carriers into the gate oxide layer, which increases the threshold voltage of the device and reduces the saturation current and carrier mobility. This is called the HCl effect.
[0003] The current spacer and lightly doped drain (LDD) process flow uses two spacer structure process steps. The first spacer defines the LDD area, and the second spacer defines the source and drain areas. At the same time, the first spacer can increase the distance between the gate and the source and drain areas, thereby reducing parasitic capacitance and reducing the HCl effect.
[0004] However, the existing first sidewall spacer is generally made of SiCN, which has a large K value. This leads to a large parasitic capacitance between the gate and the source and drain regions, affecting the device's response speed under AC power. At the same time, because the hole mobility is smaller than the electron mobility, the response speed of PMOS will be lower than that of NMOS. If the width of the sidewall spacer is reduced to increase the response speed of PMOS, the HCl effect of NMOS will be aggravated. Summary of the Invention
[0005] The object of the present invention is to provide a method for manufacturing a gate spacer and a semiconductor device to solve one or more problems existing in the prior art.
[0006] In order to solve the above technical problems, the present invention provides a method for manufacturing a gate sidewall, comprising:
[0007] Providing a substrate, the substrate comprising an NMOS region and a PMOS region, wherein a first gate structure is formed on the substrate in the NMOS region, and a second gate structure is formed on the substrate in the PMOS region;
[0008] forming a first gate spacer on a sidewall of the first gate structure, and forming a second gate spacer on a sidewall of the second gate structure, wherein the first gate spacer and the second gate spacer each include a first film layer, a second film layer, and a third film layer sequentially deposited from the inside out, the first film layer and the third film layer are made of the same material, and the K value of the second film layer is smaller than the K value of the first film layer and the third film layer; and
[0009] The second film layer and the third film layer of the second gate sidewall are removed.
[0010] Optionally, in the gate spacer manufacturing method, the step of removing the second film layer and the third film layer of the second gate spacer includes:
[0011] forming a light-reflective coating on the NMOS region, wherein the light-reflective coating covers the first gate structure;
[0012] dry etching the third film layer of the second gate sidewall and stopping on the second film layer;
[0013] The second film layer and the light reflective coating of the second gate sidewall are removed by wet etching.
[0014] Optionally, in the gate sidewall manufacturing method, the gases used in the dry etching include CF4 and O2.
[0015] Optionally, in the gate sidewall manufacturing method, the wet etching uses an etching solution with an etching selectivity ratio of the third film layer to the second film layer of 1:3.6 to 1:1.44.
[0016] Optionally, in the gate sidewall manufacturing method, the etching solution used in the wet etching is a mixture of ammonia water and hydrogen peroxide.
[0017] Optionally, in the gate sidewall manufacturing method, the first film layer, the second film layer and the third film layer are sequentially formed using a furnace atomic layer deposition process.
[0018] The first film layer and the third film layer are both formed by repeatedly performing a first process step, wherein the first process step comprises sequentially introducing various gases in a first gas combination;
[0019] The second film layer is formed by repeatedly performing a second process step, which includes sequentially performing the following steps: repeatedly introducing various gases in a second gas combination multiple times, and then introducing oxygen.
[0020] Optionally, in the gate sidewall manufacturing method, the materials of the first film layer and the third film layer are both SiCN materials, the first gas combination includes: silicon source gas, carbon source gas and nitrogen source gas, and the silicon source gas, the carbon source gas and the nitrogen source gas are introduced in sequence; or,
[0021] The materials of the first film layer and the third film layer are both SiC materials. The first gas combination includes: silicon source gas and carbon source gas, and the silicon source gas and the carbon source gas are introduced sequentially.
[0022] Optionally, in the gate sidewall manufacturing method, the material of the second film layer is SiOCN material, and the second gas combination includes: silicon source gas, carbon source gas and nitrogen source gas, and the silicon source gas, carbon source gas and nitrogen source gas are introduced in sequence; or,
[0023] The material of the second film layer is SiON material, and the second gas combination includes: silicon source gas and nitrogen source gas, and the silicon source gas and the nitrogen source gas are introduced in sequence.
[0024] Optionally, in the gate sidewall manufacturing method, the silicon source gas includes dichlorosilane or hexachlorosilane, the carbon source gas includes propylene, and the nitrogen source gas includes ammonia.
[0025] Optionally, in the gate sidewall manufacturing method, in the first gate sidewall and the second gate sidewall, the thickness of the first film layer is 2.7nm~3.3nm, the thickness of the second film layer is 2.3~2.7nm, and the thickness of the third film layer is 36nm~44nm.
[0026] The present invention further provides a semiconductor device, wherein the gate sidewall of the semiconductor device is manufactured using the method described in any one of the above items.
[0027] In summary, the gate sidewall fabrication method and semiconductor device provided by the present invention, when forming gate sidewalls on the sidewalls of the first gate structure in the NMOS region and the second gate structure in the PMOS region, first form sidewalls each comprising a first film layer, a second film layer, and a third film layer, wherein the K value of the second film layer is less than the K values of the first film layer and the third film layer. Then, the second film layer and the outermost third film layer of the sidewall formed by the second gate structure are removed. This is equivalent to thinning only the thickness of the gate sidewall of the second gate structure in the PMOS region, while the thickness of the gate sidewall of the first gate structure in the NMOS region remains unchanged. Therefore, while improving the response speed of the PMOS, it will not affect the NMOS. Moreover, while the thickness of the gate sidewall of the first gate structure in the NMOS region remains unchanged, the K value of the gate sidewall can be reduced, thereby reducing parasitic capacitance. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 A diagram showing the steps of a method for manufacturing a gate sidewall spacer according to an embodiment of the present invention;
[0029] Figures 2 to 7 for Figure 1 Schematic diagram of the device structure corresponding to each step;
[0030] The descriptions of the reference numerals are as follows:
[0031] 10-substrate; 20-first gate structure; 30-second gate structure; 40-light reflective coating; 41-antireflective coating; 42-photoresist layer;
[0032] 100-first film layer; 200-second film layer; 300-third film layer. DETAILED DESCRIPTION
[0033] The gate sidewall manufacturing method and the semiconductor device proposed in the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different proportions are used. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third" and the like in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.
[0034] like Figure 1 As shown, an embodiment of the present invention provides a method for manufacturing a gate sidewall spacer, comprising the following steps:
[0035] S11, providing a substrate, wherein the substrate includes an NMOS region and a PMOS region, wherein a first gate structure is formed on the substrate in the NMOS region, and a second gate structure is formed on the substrate in the PMOS region;
[0036] S12, forming a first gate spacer on the sidewall of the first gate structure, and forming a second gate spacer on the sidewall of the second gate structure, wherein the first gate spacer and the second gate spacer each include a first film layer, a second film layer, and a third film layer sequentially deposited from the inside out, the first film layer and the third film layer are made of the same material, and the K value of the second film layer is smaller than the K values of the first film layer and the third film layer;
[0037] S13, removing the second film layer and the third film layer of the second gate sidewall.
[0038] Using the gate sidewall fabrication method provided in this embodiment, the sidewalls of the first gate structure ultimately form a sandwich structure sidewall comprising the first film layer, the second film layer, and the third film layer, while the sidewalls of the second gate structure ultimately form a single-layer structure sidewall comprising only the first film layer. Since the K value of the second film layer is lower than the K value of the first film layer / the third film layer, when the thickness is the same, the parasitic capacitance of the sandwich structure sidewall will be lower than the parasitic capacitance of the single-layer structure sidewall formed using the materials of the first film layer / the third film layer, thereby improving the switching speed of the device at high frequencies. At the same time, the materials of the outermost and inner layers of the sandwich structure are the same. Therefore, the improved method for sidewall formation proposed in this embodiment does not require adjustment of other subsequent processes.
[0039] The following combination Figures 2 to 7 The above steps are described in further detail.
[0040] First, execute step S11, as Figure 2 As shown, a substrate 10 is provided. The material of the substrate 10 can be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, or can be silicon-on-insulator or germanium-on-insulator; or it can be other materials, such as gallium arsenide and other III-V compounds. In this embodiment, the material of the substrate 10 is preferably silicon.
[0041] The substrate 10 includes an NMOS region (ie, the PW region shown in the figure) and a PMOS region (ie, the NW region shown in the figure). A first gate structure 20 is formed on the substrate 10 in the NMOS region, and a second gate structure 30 is formed on the substrate 10 in the PMOS region.
[0042] Next, step S12 is performed to form a first gate spacer on the sidewall of the first gate structure 20 , and a second gate spacer on the sidewall of the second gate structure 30 .
[0043] In the prior art, when forming the first gate sidewall, the gate sidewall formed is a single-layer structure including only one material, which can be SiCN material or SiC material with a large K value. In this embodiment, Figure 3 As shown, the first gate sidewall spacer and the second gate sidewall spacer formed in step S12 both include a sandwich structure of a first film layer 100, a second film layer 200, and a third film layer 300 deposited sequentially from the inside to the outside. The first film layer 100 and the third film layer 300 are made of SiCN material or SiC material, while the second film layer 200 is made of a material having a K value smaller than that of SiCN material and SiC material, for example, SiOCN material or SiON material can be used, and the K value can be reduced.
[0044] Furthermore, in step S12, the first film layer 100, the second film layer 200 and the third film layer 300 can be sequentially formed using a furnace atomic layer deposition process. The first film layer and the third film layer are both formed by repeatedly performing the first process step, and the first process step includes sequentially introducing various gases in the first gas combination. Optionally, the materials of the first film layer and the third film layer are both SiCN materials, and the first gas combination includes: silicon source gas, carbon source gas and nitrogen source gas, and the silicon source gas, the carbon source gas and the nitrogen source gas are sequentially introduced; or, the materials of the first film layer and the third film layer are both SiC materials, and the first gas combination includes: silicon source gas and carbon source gas, and the silicon source gas and the carbon source gas are sequentially introduced.
[0045] In particular, the second film layer is formed by repeatedly performing a second process step, which includes sequentially performing the following steps: repeatedly introducing various gases in a second gas combination, and then introducing oxygen. Optionally, the material of the second film layer is SiOCN material, and the second gas combination includes: a silicon source gas, a carbon source gas, and a nitrogen source gas, and the silicon source gas, the carbon source gas, and the nitrogen source gas are introduced in sequence; or, the material of the second film layer is SiON material, and the second gas combination includes: a silicon source gas and a nitrogen source gas, and the silicon source gas and the nitrogen source gas are introduced in sequence.
[0046] Preferably, the first and second gas combinations are identical, i.e., both comprise a silicon source gas, a carbon source gas, and a nitrogen source gas. Thus, without regard to the number of cycles, the second process step is equivalent to the first process step, with only the addition of an oxygen gas introduction step, thereby simplifying the process flow. The K value of the second film layer can be controlled by the oxygen content introduced; a higher oxygen content results in a higher K value.
[0047] In this embodiment, the silicon source gas may optionally include dichlorosilane or hexachlorosilane, the carbon source gas may include propylene, and the nitrogen source gas may include ammonia. In other embodiments, other silicon source gases, carbon source gases, and nitrogen source gases for forming gate sidewalls may also be used.
[0048] In actual operation, it can be designed that when depositing the first film layer 100, the second film layer 200 and the third film layer 300, the flow rate of each gas in the combined gas remains unchanged in each cycle, and the thickness of each corresponding layer is changed by changing the number of times the combined gas is circulated. For example, in each cycle, the combined gas is introduced into the reaction gas in the order of dichlorosilane → propylene → ammonia, and in each cycle, optionally, the dichlorosilane flow rate is 0.8~1.2SLM, the pressure is 63~69Pa, and the time is 10~14S, and the propylene flow rate is 0.8~1.2SLM, the pressure is 63~69Pa, and the time is 10~14S. s, ammonia is 4-5 SLM, pressure is 931 Pa, and time is 18 s; when forming the first film layer 100, only the combined gas is introduced, and the number of times the combined gas is circulated is a, that is, the first film layer 100 is formed according to the step of a times (dichlorosilane → propylene → ammonia); when forming the second film layer 200, the combined gas is first circulated b times, and then oxygen is introduced, and the step of "first circulated b times, and then oxygen is introduced" is repeated c times, that is, according to the step of c times (b times (dichlorosilane → The second film layer 200 is formed by the steps of (propylene → ammonia) → oxygen). After the combined gas is introduced for each b cycles, optionally, the oxygen flow rate is 3 to 5 SLM, the pressure is 590 to 610 Pa, and the time is 9 to 11 seconds. When forming the third film layer 300, only the combined gas is introduced, and the number of times the combined gas is introduced is c, that is, the third film layer 300 is formed according to the steps of c times (dichlorosilane → propylene → ammonia). The thickness of each film layer is changed by changing the number of cycles a, b, c, and d.
[0049] In addition, referring to the thickness of the gate sidewall of the existing MOS device, preferably, in the first gate sidewall and the second gate sidewall, the thickness of the first film layer 100 is 2.7nm~3.3nm, the thickness of the second film layer 200 is 2.3~2.7nm, and the thickness of the third film layer 300 is 36nm~44nm.
[0050] Then, step S13 is performed to remove the third film layer 300 and the second film layer 200 of the second gate spacer. Thus, only the first gate spacer in the NMOS region maintains a sandwich structure, and the second gate spacer in the PMOS region retains only the inner single-layer structure. Compared to the prior art, only the thickness of the gate spacer of the second gate structure in the PMOS region is reduced, while the thickness of the gate spacer of the first gate structure in the NMOS region remains unchanged. Therefore, while improving the response speed of the PMOS, it does not affect the NMOS. Furthermore, while the thickness of the gate spacer of the first gate structure in the NMOS region remains unchanged, the K value can be reduced, thereby reducing parasitic capacitance.
[0051] In step S13, the step of removing the second film layer 200 and the third film layer 300 may specifically include:
[0052] like Figure 5 As shown, a light reflective coating 40 is formed on the NMOS region, and the light reflective coating 40 covers the first gate structure;
[0053] like Figure 6 As shown, the third film layer 300 of the second gate sidewall is dry-etched and stops on the second film layer 200;
[0054] like Figure 7 As shown, the second film layer 200 and the light reflective coating 40 of the second gate spacer are removed by wet etching.
[0055] Among them, such as Figure 4 As shown in , when forming the light-reflective coating 40, the light-reflective coating 40 can be first formed on the substrate 10 in both the PMOS region and the NMOS region, and then the light-reflective coating 40 above the PMOS region can be removed by etching, while the light-reflective coating 40 above the PMOS region remains. The light-reflective coating can be a bottom anti-reflective layer (BARC), that is, the light-reflective coating can include an anti-reflective coating 41 at the bottom and a photoresist layer 42 at the top. The dry etching can use an etching gas including CF4 and O2. Since the second film layer 200 contains oxygen, it can serve as an etch stop layer for etching the third film layer 300 using the etching gas including CF4 and O2. The wet etching can use an etchant with a third film layer / second film layer etching selectivity ratio of 1:3.6 to 1:1.44, for example, an etchant with an etching selectivity of 1:4. The wet etching may use a mixture of ammonia and hydrogen peroxide to remove the light reflective coating 40 while removing the second film layer 200 of the second gate sidewall.
[0056] It should be noted that the first gate sidewall spacer and the second gate sidewall spacer in this embodiment can be understood as the first gate sidewall spacer described above, which serves to define the LDD region and can increase the distance between the gate and the source and drain regions, thereby reducing parasitic capacitance and lowering the HCl effect. Since the first gate sidewall spacer and the second gate sidewall spacer are used to define the LDD region, after performing step S12, the substrate on both sides of the first gate structure and the second gate structure must first be subjected to an LDD process before performing step S13 to prevent the thinning of the second gate sidewall spacer from affecting the position of the LDD region in the PMOS region. In addition, it should be noted that the method for forming a gate sidewall provided in the embodiment of the present invention is not only applicable to forming the first gate sidewall spacer described above, but can also be applied to other improvements to other gate sidewalls, such as the improvement of the second gate sidewall spacer described above. After the second gate sidewall spacer in the PMOS region is thinned using the method provided in this embodiment, ion implantation is performed to form the source and drain regions, which can reduce the distance between the source and drain regions and the gate in the PMOS region, and can also improve the response speed of the PMOS.
[0057] An embodiment of the present invention further provides a semiconductor structure having a gate sidewall spacer fabricated using the gate sidewall fabrication method provided in this embodiment. Thus, compared to the prior art, the semiconductor structure provided by the embodiment of the present invention can reduce the gate sidewall K value and parasitic capacitance, thereby increasing the switching speed of the device at high frequencies.
[0058] In summary, the gate sidewall fabrication method and semiconductor device provided by the embodiments of the present invention, when forming gate sidewalls on the sidewalls of the first gate structure in the NMOS region and the second gate structure in the PMOS region, first form sidewalls each comprising a first film layer, a second film layer, and a third film layer, wherein the K value of the second film layer is less than the K values of the first film layer and the third film layer. Then, the second film layer and the outermost third film layer of the sidewall formed by the sidewall of the second gate structure are removed. This is equivalent to thinning only the thickness of the gate sidewall of the second gate structure in the PMOS region, while the thickness of the gate sidewall of the first gate structure in the NMOS region remains unchanged. Therefore, while improving the response speed of the PMOS, it does not affect the NMOS. Moreover, while the gate sidewall of the first gate structure in the NMOS region remains unchanged, the K value can be reduced, thereby reducing parasitic capacitance.
[0059] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for manufacturing a gate sidewall, characterized in that: include: Providing a substrate, the substrate comprising an NMOS region and a PMOS region, wherein a first gate structure is formed on the substrate in the NMOS region, and a second gate structure is formed on the substrate in the PMOS region; A first gate spacer is formed on the sidewall of the first gate structure, and a second gate spacer is formed on the sidewall of the second gate structure, wherein the first gate spacer and the second gate spacer each include a first film layer, a second film layer, and a third film layer sequentially deposited from the inside to the outside, the first film layer and the third film layer are made of the same material, and the K value of the second film layer is smaller than the K values of the first film layer and the third film layer; as well as, The second film layer and the third film layer of the second gate sidewall are removed.
2. The method for manufacturing a gate spacer according to claim 1, wherein: The step of removing the second film layer and the third film layer of the second gate spacer includes: forming a light-reflective coating on the NMOS region, wherein the light-reflective coating covers the first gate structure; dry etching the third film layer of the second gate sidewall and stopping on the second film layer; The second film layer and the light reflective coating of the second gate sidewall are removed by wet etching.
3. The method for manufacturing a gate spacer according to claim 2, wherein: The gases used in the dry etching include CF4 and O2.
4. The method for manufacturing a gate spacer according to claim 2, wherein: The wet etching adopts an etching solution with an etching selection ratio of the third film layer to the second film layer of 1:3.6 to 1:1.
44.
5. The method for manufacturing a gate spacer according to claim 4, wherein: The etching solution used in the wet etching is a mixture of ammonia water and hydrogen peroxide.
6. The method for manufacturing a gate spacer according to claim 1, wherein: The first film layer, the second film layer and the third film layer are sequentially formed using a furnace atomic layer deposition process, The first film layer and the third film layer are both formed by repeatedly performing a first process step, wherein the first process step comprises sequentially introducing various gases in a first gas combination; The second film layer is formed by repeatedly performing a second process step, which includes sequentially performing the following steps: repeatedly introducing various gases in a second gas combination multiple times, and then introducing oxygen.
7. The method for manufacturing a gate spacer according to claim 6, wherein: The materials of the first film layer and the third film layer are both SiCN materials, the first gas combination includes: silicon source gas, carbon source gas and nitrogen source gas, and the silicon source gas, the carbon source gas and the nitrogen source gas are introduced in sequence; or The materials of the first film layer and the third film layer are both SiC materials. The first gas combination includes: silicon source gas and carbon source gas, and the silicon source gas and the carbon source gas are introduced sequentially.
8. The method for manufacturing a gate spacer according to claim 6, wherein: The material of the second film layer is SiOCN material, and the second gas combination includes: silicon source gas, carbon source gas and nitrogen source gas, and the silicon source gas, the carbon source gas and the nitrogen source gas are introduced in sequence; or The material of the second film layer is SiON material, and the second gas combination includes: silicon source gas and nitrogen source gas, and the silicon source gas and the nitrogen source gas are introduced in sequence.
9. The method for manufacturing a gate spacer according to claim 7 or 8, wherein: The silicon source gas includes dichlorosilane or hexachlorosilane, the carbon source gas includes propylene, and the nitrogen source gas includes ammonia.
10. The method for manufacturing a gate spacer according to claim 1, wherein: In the first gate spacer and the second gate spacer, the thickness of the first film layer is 2.7 nm to 3.3 nm, the thickness of the second film layer is 2.3 nm to 2.7 nm, and the thickness of the third film layer is 36 nm to 44 nm.
11. A semiconductor device, characterized in that: The gate spacer of the semiconductor device is manufactured by the method according to any one of claims 1 to 10.