Semiconductor inspection device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor inspection apparatus which improves classification precision in defect inspection and determines advantages and disadvantages of a semiconductor device with high precision. A semiconductor inspection device (101) includes a first inspection information acquisition unit (10), a second inspection information acquisition unit (20), and a screening unit (30). A first inspection information acquisition unit (10) acquires first image information including irregularity information on the surface of a semiconductor wafer before ion implantation. A second inspection information acquisition unit (20) acquires second image information including photoluminescence information of the semiconductor wafer that has been heat-treated after ion implantation. The screening unit (30) identifies defects included in the semiconductor wafer on the basis of the first image information and the second image information, and determines the quality of a semiconductor chip formed on the semiconductor wafer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor inspection device and a method for manufacturing a semiconductor device. Background Art

[0002] Crystal defects degrade the reliability of semiconductor devices. Therefore, when specific crystal defects occur within a semiconductor wafer, screening technology is required to selectively remove semiconductor chips containing these crystal defects. For example, as described in Patent Documents 1 and 2, semiconductor crystal defects are detected by obtaining the surface topography of the semiconductor wafer or by measuring photoluminescence.

[0003] Patent Document 1: Japanese Patent No. 5713419

[0004] Patent Document 2: Japanese Patent Application Laid-Open No. 2022-163866

[0005] Defects expand or contract due to the thermal treatment process included in wafer processing. If defect inspection is performed before the thermal treatment process is fully completed, the impact of defect expansion or contraction is not reflected in the inspection results. On the other hand, if defect inspection is performed after the thermal treatment process is completed, the contrast caused by the chip pattern formed on the semiconductor wafer and other factors will overlap with the inspection results, thus reducing the accuracy of defect classification. Summary of the Invention

[0006] In order to solve the above-mentioned problems, the present disclosure aims to provide a semiconductor inspection apparatus capable of improving classification accuracy in defect inspection and determining the quality of semiconductor devices with high accuracy.

[0007] The semiconductor inspection apparatus disclosed herein includes a first inspection information acquisition unit, a second inspection information acquisition unit, and a screening unit. The first inspection information acquisition unit acquires first image information. The first image information includes surface unevenness information of a semiconductor wafer before ion implantation. The second inspection information acquisition unit acquires second image information. The second image information includes photoluminescence information of the semiconductor wafer after heat treatment following ion implantation. Based on the first and second image information, the screening unit identifies defects in the semiconductor wafer and determines the quality of semiconductor chips formed on the semiconductor wafer.

[0008] According to the present disclosure, a semiconductor inspection apparatus is provided that improves classification accuracy in defect inspection and determines the quality of a semiconductor device with high accuracy.

[0009] The objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings.

[0010] Explanation of the reference numerals: 1…semiconductor chip; 1A…effective area; 2…inspection area; 3…gate electrode; 10…first inspection information acquisition unit; 20…second inspection information acquisition unit; 30…screening unit; 31…image analysis unit; 32…defect coordinate comparison unit; 33…defect classifier; 34…quality judger; 35…final judger; 40…first learning device; 41…first data acquisition unit; 42…first model generation unit; 50…second learning device; 51…second data acquisition unit; 52…second model generation unit; 60…third learning device; 70…learning device; 71…image synthesis unit; 72…data acquisition unit; 73…model generation unit; 90…processing circuit; 91…processor; 92…memory; 101 to 103…semiconductor inspection device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a diagram showing the structure of a semiconductor inspection apparatus according to the first embodiment.

[0012] Figure 2 This is a diagram showing an example of the configuration of a processing circuit included in a semiconductor inspection apparatus.

[0013] Figure 3 This is a diagram showing another example of the configuration of a processing circuit included in a semiconductor inspection apparatus.

[0014] Figure 4 This is a flowchart showing the method for manufacturing the semiconductor device according to the first embodiment.

[0015] Figure 5 This is a flowchart showing details of the screening process.

[0016] Figure 6 This figure shows the structure of a semiconductor chip and defect inspection areas.

[0017] Figure 7 This figure shows the structure of a semiconductor chip and defect inspection areas.

[0018] Figure 8 This is a diagram showing the structure of a semiconductor inspection apparatus according to a second embodiment.

[0019] Figure 9 This is a diagram showing data processing in a semiconductor inspection device.

[0020] Figure 10 This is a diagram showing the structure of a semiconductor inspection apparatus according to a modified example of the second embodiment.

[0021] Figure 11 This is a diagram showing data processing in a semiconductor inspection device.

[0022] Figure 12This is a diagram showing the structure of a semiconductor inspection device according to a third embodiment.

[0023] Figure 13 This is a diagram showing data processing in a semiconductor inspection device. DETAILED DESCRIPTION

[0024] <Implementation Method 1>

[0025] The semiconductor inspection apparatus disclosed herein inspects a semiconductor wafer during the manufacturing process of a semiconductor device. A plurality of semiconductor chips are formed on the semiconductor wafer. For example, the semiconductor chips are power semiconductor chips formed of Si or SiC.

[0026] Figure 1 1 is a diagram showing a configuration of a semiconductor inspection apparatus 101 according to Embodiment 1. The semiconductor inspection apparatus 101 includes a first inspection information acquisition unit 10 , a second inspection information acquisition unit 20 , and a screening unit 30 .

[0027] The first inspection information acquisition unit 10 acquires first image information. The first image information includes concave-convex information on the surface of the semiconductor wafer before ion implantation. The first image information is, for example, a surface image of the semiconductor wafer acquired by a differential interference optical system.

[0028] The second inspection information acquisition unit 20 acquires second image information. The second image information includes photoluminescence (PL) information of the semiconductor wafer that has been heat-treated after ion implantation. The heat treatment temperature is preferably above 1000°C. The second image information is, for example, a photoluminescence image (PL image) acquired by the PL method.

[0029] The screening unit 30 identifies defects contained in the semiconductor wafer based on the first and second image information, and determines the quality of the semiconductor chips formed on the semiconductor wafer. The screening unit 30 includes an image analysis unit 31, a defect coordinate comparison unit 32, a defect classifier 33, and a quality determiner 34.

[0030] The image analysis unit 31 performs subtraction processing on the contrast related to the ion implantation pattern of the semiconductor wafer in the second image information.

[0031] The defect coordinate comparing unit 32 identifies the position of a defect included in the semiconductor wafer based on the first image information and the second image information.

[0032] The defect classifier 33 determines the type of defect based on the first image information and the second image information whose contrast has been subtracted.

[0033] The quality determiner 34 determines the quality of the semiconductor chip based on the type of defect.

[0034] Figure 2This diagram shows an example of the configuration of a processing circuit 90 included in a semiconductor inspection apparatus 101. The functions of the first inspection information acquisition unit 10, the second inspection information acquisition unit 20, and the screening unit 30 are implemented by the processing circuit 90. In other words, the processing circuit 90 includes the first inspection information acquisition unit 10, the second inspection information acquisition unit 20, and the screening unit 30.

[0035] When the processing circuit 90 is dedicated hardware, the processing circuit 90 is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA, or a similar processor.

[0036] (Field-Programmable Gate Array), or a combination thereof. The functions of the first inspection information acquisition unit 10, the second inspection information acquisition unit 20, and the screening unit 30 may be implemented separately by a plurality of processing circuits or collectively by a single processing circuit.

[0037] Figure 3 This diagram shows another example of the configuration of the processing circuit included in semiconductor inspection apparatus 101. The processing circuit includes a processor 91 and a memory 92. Processor 91 implements the functions of first inspection information acquisition unit 10, second inspection information acquisition unit 20, and screening unit 30 by executing programs stored in memory 92. For example, each function is implemented by processor 91 executing software described as a program. Thus, semiconductor inspection apparatus 101 includes memory 92 for storing programs and processor 91 for executing the programs.

[0038] The program describes the following functions: The semiconductor inspection apparatus 101 acquires first image information containing information about the surface irregularities of a semiconductor wafer before ion implantation, and acquires second image information containing information about photoluminescence within the semiconductor wafer after heat treatment following ion implantation. Based on the first and second image information, the apparatus extracts defects from the semiconductor wafer and determines the quality of semiconductor chips formed on the semiconductor wafer. The program causes a computer to execute the processes or methods of the first inspection information acquisition unit 10, the second inspection information acquisition unit 20, and the screening unit 30.

[0039] The processor 91 is, for example, a CPU (Central Processing Unit). The memory 92 is, for example, a nonvolatile or volatile semiconductor memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), or EEPROM (Electrically Erasable Programmable Read Only Memory). Alternatively, the memory 92 may be, for example, an HDD (Hard Disk Drive).

[0040] The functions of the first inspection information acquisition unit 10, the second inspection information acquisition unit 20, and the screening unit 30 may be partially implemented by dedicated hardware and partially implemented by software. The processing circuit implements the functions described above by a combination of hardware and software.

[0041] Figure 4 1 is a flowchart showing a method for manufacturing a semiconductor device in accordance with Embodiment 1. In this manufacturing method, a defect inspection method using the semiconductor inspection apparatus 101 described above is applied.

[0042] In step S1, a semiconductor wafer is prepared. In step S2, a semiconductor layer is formed on the upper surface of the semiconductor wafer by epitaxial growth. This semiconductor layer is hereinafter referred to as the epitaxial layer. In step S3, a predetermined pattern is formed on the surface of the semiconductor wafer by photolithography (photolithography).

[0043] In step S4, a first inspection is performed. The first inspection is performed using a differential interference optical system after the epitaxial growth step (step S2) and before the ion implantation step (step S5). In this first inspection step, the semiconductor inspection apparatus 101 captures a surface image of the semiconductor wafer.

[0044] In step S5 , ions are implanted into the surface of the semiconductor wafer.

[0045] In step S6, the semiconductor wafer is heat-treated at a temperature of 1000° C. or higher. The ions implanted into the semiconductor wafer are activated by this heat treatment.

[0046] In step S7, a second inspection is performed. The second inspection is based on the PL method and is performed after the heat treatment step (step S6) and before the metal forming step (step S8). In this second inspection step, the semiconductor inspection apparatus 101 measures a PL image of the semiconductor wafer.

[0047] In step S8 , a metal pattern is formed on the surface of the semiconductor wafer.

[0048] In step S9, a wafer test is performed. In this wafer test, the electrostatic characteristics of the semiconductor chips are checked. Semiconductor chips that are found to be out of standard according to the wafer test results are removed and discarded.

[0049] In step S10, the screening unit 30 identifies defects on the semiconductor wafer based on the surface image and PL image, and determines the quality of the semiconductor chips. Based on this quality information, the screening unit 30 removes defective semiconductor chips. In other words, the screening unit 30 screens the semiconductor chips. This removes defective semiconductor chips. Subsequently, the semiconductor chips undergo wiring and other mounting processes, completing the semiconductor device.

[0050] Figure 5 This is a flowchart showing details of the screening process in step S10.

[0051] In step S101 , the first inspection information acquisition unit 10 acquires data of a surface image of a semiconductor wafer as first image information.

[0052] In step S102 , the second inspection information acquisition unit 20 acquires data of a PL image in the semiconductor wafer as second image information.

[0053] In step S103 , the image analysis unit 31 performs subtraction processing on the contrast associated with the ion implantation pattern in the PL image.

[0054] In step S104 , the defect coordinate comparison unit 32 identifies the position of the defect based on the surface image and the PL image whose contrast has been subtracted.

[0055] In step S105 , the defect classifier 33 determines the type of defect based on the surface image and the PL image whose contrast has been subtracted.

[0056] In step S106 , the quality determiner 34 determines the quality of the semiconductor chips formed on the semiconductor wafer based on the information on the type of the defect and the information on the position of the defect.

[0057] The following, Figure 4The details of the defect inspection method based on the semiconductor inspection device 101 shown are described. In the second inspection process (step S7), an inspection based on the PL method is performed. The dislocation plane of the defect formed in the semiconductor crystal does not necessarily reach the surface of the epitaxial layer. However, due to the influence of the charge energy supplied when the semiconductor chip is energized, the defect sometimes expands. The inspection based on the PL method can observe the expansion of the defects generated in the epitaxial layer, which is important from the perspective of capturing defects related to the life of the semiconductor device.

[0058] However, in this PL image, basal plane dislocations (BPDs) and portions of stacking defects (SFs) are sometimes detected as linear defects. In this case, it is difficult to distinguish between BPDs and SFs based on the PL image. Therefore, in addition to the second inspection step (step S7), a first inspection step (step S4) is also performed. The first inspection is based on a differential interference optical system that is sensitive to the surface irregularities of the semiconductor wafer. Based on the surface image obtained by the differential interference optical system, it is possible to distinguish between BPDs (where no irregularities appear on the surface of the semiconductor wafer) and SFs (where irregularities appear).

[0059] The first inspection process (step S4) is performed after the photolithography process (step S3) and before the ion implantation process (step S5). Assuming that the first inspection process is performed after the ion implantation process (step S5), a brightness contrast corresponding to the mask pattern during ion implantation will be generated in the surface image. The detection of defects becomes difficult due to this contrast. Therefore, the first inspection process is performed before the ion implantation process (step S5). In addition, the timing of the second inspection is different from the timing of the first inspection, so when comparing the PL image and the surface image, it is necessary to correct the positional relationship between them. The semiconductor inspection device 101 of embodiment 1 corrects the offset values ​​of the two axis (X axis and Y axis) directions and the rotation direction of each image based on the mark formed in the photolithography process (step S3). Therefore, the first inspection process is performed after the photolithography process (step S3).

[0060] In the wafer testing process (step S9), semiconductor chips with test results that are out of standard are removed and discarded. For semiconductor chips that are out of standard, no processing after step S9 is performed. However, in the wafer testing process (step S9), even semiconductor chips that are judged to be qualified may contain defects in the semiconductor chip that gradually deteriorate the characteristics of the semiconductor device due to the driving current. It is difficult to remove semiconductor chips containing such defects in the wafer testing process (step S9). Therefore, a screening process (step S10) is performed.

[0061] The following, Figure 5The details of the screening process shown in FIG. are described below. In the image analysis process (step S103), the image analysis unit 31 performs image processing to reduce the contrast based on the brightness of the mask pattern during ion implantation, which is superimposed on the PL image. If the contrast variation is longer than the period of the defect size, the image analysis unit 31 performs a subtraction process corresponding to the period. Alternatively, the image analysis unit 31 may specify a contrast value for each pattern area based on the chip pattern data and perform the subtraction process. The subtraction process is performed in any manner.

[0062] In the defect coordinate comparison process (step S104), the defect coordinate comparison unit 32 scans the entire surface of the surface image and the PL image, whose contrast has been subtracted, to obtain the brightness variation coordinates in each image. Based on the marks formed during photoengraving, the defect coordinate comparison unit 32 corrects the two axial directions (X and Y axes) and the rotational direction before comparing the surface image and the PL image. If the brightness variation coordinates in each image are considered identical, the defect coordinate comparison unit 32 determines that a defect exists at that location. The defect coordinate comparison unit 32 then extracts the portion of the image containing the defect.

[0063] In the defect classification process (step S105), the defect classifier 33 obtains data on the partial image of the defect in the surface image and the partial image of the defect in the PL image. The defect classifier 33 determines the type of defect based on these partial images of the defect. For example, based on information on the defect's location, the defect classifier 33 classifies defects located throughout the entire area of ​​the semiconductor chip and determines the type of defect.

[0064] In the determination process (step S106), the quality determination unit 34 determines whether the semiconductor chip contains a defect of a type that affects reliability based on the defect type information and defect location information. If the semiconductor chip contains a defect of a type that affects reliability, the quality determination unit 34 marks the semiconductor chip containing the defect as a defective product. If the semiconductor chip does not contain a defect of a type that affects reliability, the quality determination unit 34 marks the semiconductor chip as a qualified product.

[0065] The semiconductor inspection apparatus 101 performs the same process on all defects detected on the entire surface of the semiconductor wafer, and removes defective products based on the labels of each semiconductor chip at the time of completion of the process.

[0066] In summary, the semiconductor inspection apparatus 101 in Embodiment 1 includes a first inspection information acquisition unit 10, a second inspection information acquisition unit 20, and a screening unit 30. The first inspection information acquisition unit 10 acquires first image information including surface unevenness information on a semiconductor wafer before ion implantation. The second inspection information acquisition unit 20 acquires second image information including photoluminescence information from a semiconductor wafer subjected to heat treatment after ion implantation. Based on the first and second image information, the screening unit 30 identifies defects in the semiconductor wafer and determines the quality of semiconductor chips formed on the semiconductor wafer.

[0067] This semiconductor inspection device 101 improves classification accuracy during defect inspection and accurately determines the quality of semiconductor chips. Even when defects expand or contract due to the energy generated during heat treatment, the semiconductor inspection device 101 determines the quality of the semiconductor chip based on inspection results that reflect the state of the semiconductor crystallization. This improves the accuracy of defect classification, such as by improving the detection accuracy of BPDs, which are difficult to identify in a single inspection process. The semiconductor inspection device 101 accurately screens semiconductor chips that may deteriorate in the future, thereby reducing the proportion of defective products released to the market. Furthermore, by performing a second inspection after heat treatment at temperatures above 1000°C, it is possible to determine the quality of semiconductor chips in a crystallized state close to that of the finished product, improving determination accuracy. Furthermore, by applying contrast reduction processing to the PL image, reflections from the mask pattern are eliminated. This improves defect extraction accuracy and defect classification accuracy.

[0068] (Variation of Embodiment 1)

[0069] Figure 6 and Figure 7 FIG. 1 is a diagram showing the structure of a semiconductor chip 1 and a defect inspection area 2. Figure 6 In FIG, the entire area of ​​the semiconductor chip 1 is included in the defect inspection area 2. Figure 7 Only the effective region 1A in the semiconductor chip 1 is included in the defect inspection region 2. The effective region 1A corresponds to, for example, a region inside the gate electrode 3 provided along the outer periphery of the semiconductor chip 1.

[0070] like Figure 6 As shown, the defect classifier 33 can also classify defects located in the entire area of ​​the semiconductor chip 1 as a classification target and determine the type of the defect. However, when the semiconductor device is driven, current flows only through the active area 1A of the semiconductor chip 1. If defects that are to be removed are included outside the active area 1A, the semiconductor chip 1 that could have been shipped as a qualified product will be discarded, and the yield rate will be reduced. Therefore, if Figure 7As shown, the defect classifier 33 can also classify defects located only within the active area 1A based on information about the defect location and information about the active area 1A of the semiconductor chip 1, and determine the type of defect. This improves the efficiency and accuracy of determining whether the semiconductor chip 1 is good or bad, and also increases the yield rate.

[0071] <Implementation Method 2>

[0072] Figure 8 This is a diagram showing the structure of a semiconductor inspection apparatus 102 in the second embodiment. Figure 9 1 is a diagram showing data processing in the semiconductor inspection apparatus 102. From the perspective of productivity of automatic classification and automatic determination, the defect classifier 33 and the quality determiner 34 of the semiconductor inspection apparatus 102 preferably include a learned model learned by machine learning.

[0073] Semiconductor inspection apparatus 102 includes a first learning device 40 and a second learning device 50. First learning device 40 includes a first data acquisition unit 41 and a first model generation unit 42. Second learning device 50 includes a second data acquisition unit 51 and a second model generation unit 52. Screening unit 30 of semiconductor inspection apparatus 102 includes a final determiner 35 in addition to the configuration of Embodiment 1.

[0074] The first data acquisition unit 41 acquires first learning data based on the first image information and the defect classification result. In Embodiment 2, the first image information is a learning surface image captured by a differential interference optical system. The first learning data includes a partial image of a defect in the learning surface image and data associated with the defect classification result. The defect classification result is, for example, based on visual observation by an operator.

[0075] The first model generating unit 42 performs learning using the first learning data, and generates a first learned model for inferring the type of defects included in the surface image of the semiconductor wafer.

[0076] The defect classifier 33 specifies the type of defect included in the surface image based on the surface image acquired from the first inspection information acquisition unit 10 as a result of the first inspection step and the first learned model.

[0077] Based on the defect type information and defect location information, the quality determiner 34 determines whether the semiconductor chip 1 contains a defect of a type that affects reliability. If the semiconductor chip 1 contains a defect of a type that affects reliability, the quality determiner 34 marks the semiconductor chip 1 as containing a defect that affects reliability. If the semiconductor chip 1 does not contain a defect of a type that affects reliability, the quality determiner 34 marks the semiconductor chip 1 as a qualified product.

[0078] The second data acquisition unit 51 acquires second learning data based on the second image information and the defect classification result. In the second embodiment, the second image information is a learning PL image measured using the PL method. The second learning data includes a partial image of a defect in the learning PL image and data associated with the defect classification result. The defect classification result is, for example, based on visual observation by an operator.

[0079] The second model generating unit 52 performs learning using the second learning data, and generates a second learned model for inferring the type of defects included in the PL image of the semiconductor wafer.

[0080] The defect classifier 33 specifies the type of defect included in the PL image acquired from the second inspection information acquisition unit 20 as a result of the second inspection step, based on the second learned model.

[0081] Based on the defect type information and defect location information, the quality determiner 34 determines whether the semiconductor chip 1 contains a defect of a type that affects reliability. If the semiconductor chip 1 contains a defect of a type that affects reliability, the quality determiner 34 marks the semiconductor chip 1 as containing a defect that affects reliability. If the semiconductor chip 1 does not contain a defect of a type that affects reliability, the quality determiner 34 marks the semiconductor chip 1 as a qualified product.

[0082] Final determiner 35 obtains information about the labels of defects classified by the first learned model and information about the labels of defects classified by the second learned model. Based on this label information and predetermined rules, final determiner 35 determines the quality of semiconductor chip 1. For example, if a semiconductor chip 1 contains at least one defect with a high probability of causing component damage, final determiner 35 determines it as defective. Alternatively, if a semiconductor chip 1 does not have a high probability of causing component damage, but contains three or more defects that affect its characteristics, final determiner 35 determines it as defective.

[0083] As described above, the screening unit 30 determines the quality of the semiconductor chip 1 based on the first image information acquired from the first inspection information acquisition unit 10 , the second image information acquired from the second inspection information acquisition unit 20 , the first learned model, and the second learned model.

[0084] According to such a configuration, compared with classification based on visual observation by an operator, not only is the judgment standard stable, but the judgment accuracy in the automatic process is improved, thereby improving productivity.

[0085] The functions of the first learning device 40, the second learning device 50, and the final determiner 35 are Figure 2 or Figure 3 Each of the first learning device 40, the second learning device 50, and the semiconductor inspection device 102 may have its own processing circuit. For example, the first learning device 40 and the second learning device 50 may be installed in a server.

[0086] (Variation of Embodiment 2)

[0087] The learned model obtained by machine learning can also be applied to the predetermined rules used by the final determiner 35 .

[0088] Figure 10 This is a diagram showing the configuration of a semiconductor inspection apparatus 102A according to a modified example of the second embodiment. Figure 11 This is a diagram showing data processing in the semiconductor inspection apparatus 102A.

[0089] The semiconductor inspection apparatus 102A includes a third learning device 60. The third learning device 60 performs integrated learning based on information on defect types determined by the first learned model, information on defect types determined by the second learned model, and data on degradation of the electrical characteristics of the semiconductor chip 1. Through this integrated learning, the third learning device 60 generates a third learned model for inferring the quality of the semiconductor chip 1. The degradation data on the electrical characteristics of the semiconductor chip 1, for example, corresponds to labels used to determine whether a product is good or bad based on the degradation state of the electrical characteristics after a power-on load test simulating market operation. During this learning process, the defect type information and the labels are correlated with each other.

[0090] The final determiner 35 makes a final determination of whether the semiconductor chip 1 is good or bad based on the third learned model.

[0091] The function of the third learning device 60 is to Figure 2 or Figure 3 The third learning device 60 may also have its own processing circuit. For example, the third learning device 60 may also be installed in a server.

[0092] This structure increases the production volume of semiconductor chips 1 and provides a richer set of learning data, resulting in more accurate judgment results. This variation employs ensemble learning, which is similar to stacking. Ensemble learning can also be applied to various components of the learning device for packaging, boosting, and other applications. While the time and cost required for learning and inference increase, judgment accuracy is improved.

[0093] <Implementation Method 3>

[0094] The semiconductor inspection apparatus 102 of the second embodiment generates a learned model by independently learning defect images extracted during the first and second inspections using a first learning device 40 and a second learning device 50. The machine learning in this second embodiment does not reference color information in the defect images, but only luminance information (PL images inherently lack color information). Using a multi-channel composite image as input for machine learning reduces the number of learning and inference steps.

[0095] Figure 12 This is a diagram showing the structure of a semiconductor inspection apparatus 103 in a third embodiment. Figure 13 This is a diagram showing data processing in the semiconductor inspection apparatus 103 .

[0096] The semiconductor inspection apparatus 103 includes a learning device 70. The learning device 70 includes an image synthesis unit 71, a data acquisition unit 72, and a model generation unit 73. The screening unit 30 includes a final determiner 35 in addition to the configuration of the first embodiment.

[0097] Image synthesis unit 71 generates third image information based on the first and second image information. This third image information is a composite image created by storing the first and second image information in different channels. In other words, the composite image is a multi-channel image, in this case a color image having three RGB channels.

[0098] The image synthesis unit 71 generates a composite image based on the surface image and the PL image. For example, in the RGB channels, the image synthesis unit 71 assigns the surface image from the first inspection, the PL image from the first inspection, and the PL image from the second inspection to the R channel, G channel, and B channel, respectively, to generate a composite image. This captures defects as a color image.

[0099] The data acquisition unit 72 acquires learning data based on the composite image and the defect classification results. The learning data includes, for example, data that correlates a partial image of a defect in the composite image with the defect classification results. The defect classification results are, for example, based on visual observation by an operator.

[0100] The model generation unit 73 performs learning using the learning data and generates a learned model for inferring the type of defects included in the synthetic image.

[0101] The defect classifier 33 determines the type of defect based on the learned model. Then, the quality judge 34 determines whether the semiconductor chip 1 contains defects of a type that affects reliability based on the information on the type of defect and the location of the defect. In the case where the semiconductor chip 1 contains defects of a type that affects reliability, the quality judge 34 marks the semiconductor chip 1 as containing defects that affect reliability. In the case where the semiconductor chip 1 does not contain defects of a type that affects reliability, the quality judge 34 marks the semiconductor chip 1 as a qualified product. The final judge 35 determines the quality of the semiconductor chip 1 based on the information on the defect label. In this way, the screening unit 30 determines the quality of the semiconductor chip 1 based on the learned model.

[0102] The functions of the learning device 70 and the final determiner 35 are Figure 2 or Figure 3 The learning device 70 and the semiconductor inspection device 103 may each have their own processing circuit. For example, the learning device 70 may be installed in a server.

[0103] This structure reduces the number of determinations by the quality determiner 34. This reduces the burden of model management and shortens the time required for learning and inference. Furthermore, the comparison between the surface image in the first inspection and the PL image in the second inspection is reflected in machine learning, improving determination accuracy.

[0104] Furthermore, the various embodiments can be freely combined, or the various embodiments can be appropriately modified or omitted.

[0105] Hereinafter, various aspects of the present disclosure are collectively described as supplementary notes.

[0106] (Note 1)

[0107] A semiconductor inspection device, characterized by comprising:

[0108] a first inspection information acquiring unit that acquires first image information including concavity and convexity information of a surface of a semiconductor wafer before ion implantation;

[0109] a second inspection information acquiring unit that acquires second image information including photoluminescence information of the semiconductor wafer that has been heat-treated after ion implantation; and

[0110] A screening unit identifies defects included in the semiconductor wafer based on the first image information and the second image information, and determines the quality of semiconductor chips formed on the semiconductor wafer.

[0111] (Note 2)

[0112] The semiconductor inspection device according to Supplementary Note 1, wherein:

[0113] The second image information includes information on the photoluminescence of the semiconductor wafer subjected to heat treatment at a temperature of 1000° C. or higher.

[0114] (Note 3)

[0115] The semiconductor inspection device according to Supplementary Note 1 or 2, wherein:

[0116] The screening unit includes:

[0117] an image analyzing unit configured to perform a subtraction process on a contrast in the second image information related to the ion implantation pattern of the semiconductor wafer;

[0118] a defect classifier configured to determine a type of the defect based on the first image information and the second image information after subtracting the contrast; and

[0119] A determiner determines the quality of the semiconductor chip based on the information on the type of the defect.

[0120] (Note 4)

[0121] The semiconductor inspection device according to Supplementary Note 3, wherein:

[0122] The screening unit further includes a defect coordinate comparison unit configured to determine a position of the defect included in the semiconductor wafer based on the first image information and the second image information.

[0123] The defect classifier determines the type of the defect based on the information on the position of the defect, by classifying the defect located in the entire area of ​​the semiconductor chip or the defect located only in the effective area provided in the semiconductor chip.

[0124] (Note 5)

[0125] The semiconductor inspection device according to any one of Supplementary Notes 1 to 4, wherein:

[0126] Also provided are a first learning device and a second learning device,

[0127] The first learning device includes:

[0128] a first data acquisition unit that acquires first learning data based on the first image information and the classification result of the defect; and

[0129] a first model generating unit for generating a first learned model for inferring the type of the defect included in the first image information using the first learning data;

[0130] The second learning device includes:

[0131] a second data acquisition unit that acquires second learning data based on the second image information and the classification result of the defect; and

[0132] a second model generating unit for generating a second learned model for inferring the type of the defect included in the second image information using the second learning data;

[0133] The screening unit determines the quality of the semiconductor chip based on the first image information acquired from the first inspection information acquisition unit, the second image information acquired from the second inspection information acquisition unit, the first learned model, and the second learned model.

[0134] (Note 6)

[0135] The semiconductor inspection device according to Supplementary Note 5, wherein:

[0136] The device further comprises a third learning device that generates a third learned model for inferring the quality of the semiconductor chip by integrated learning based on the information on the type of the defect determined based on the first learned model, the information on the type of the defect determined based on the second learned model, and degradation data of the electrical characteristics of the semiconductor chip.

[0137] The screening unit determines the quality of the semiconductor chip based on the third learned model.

[0138] (Note 7)

[0139] The semiconductor inspection device according to any one of Supplementary Notes 1 to 6, wherein:

[0140] Also provided is a learning device, the learning device comprising:

[0141] an image synthesis unit that generates third image information synthesized by storing the first image information and the second image information in different channels;

[0142] a data acquisition unit that acquires learning data based on the third image information and the classification result of the defect; and

[0143] a model generating unit that generates a learned model for inferring the type of the defect included in the third image information using the learning data;

[0144] The screening unit determines the quality of the semiconductor chip based on the learned model.

[0145] (Note 8)

[0146] A method for manufacturing a semiconductor device, comprising the following steps:

[0147] a step of acquiring first image information including concave-convex information of the surface of the semiconductor wafer before ion implantation;

[0148] a step of acquiring second image information including photoluminescence information of the semiconductor wafer that has been heat-treated after ion implantation; and

[0149] A process of extracting defects included in the semiconductor wafer based on the first image information and the second image information, and determining the quality of semiconductor chips formed on the semiconductor wafer.

[0150] (Note 9)

[0151] The method for manufacturing a semiconductor device according to Supplementary Note 8, further comprising the following step:

[0152] A first inspection step is to take a surface image of the semiconductor wafer;

[0153] an ion implantation step of implanting ions into the semiconductor wafer after the first inspection step;

[0154] a heat treatment step of performing heat treatment on the semiconductor wafer after the ion implantation step; and

[0155] The second inspection process is to measure a photoluminescence image of the semiconductor wafer after the heat treatment process.

[0156] The first image information is the surface image captured in the first inspection process,

[0157] The second image information is the photoluminescence image measured in the second inspection process.

Claims

1. A semiconductor inspection device, characterized in that: have: a first inspection information acquiring unit that acquires first image information including concavity and convexity information of a surface of a semiconductor wafer before ion implantation; a second inspection information acquiring unit for acquiring second image information including photoluminescence information of the semiconductor wafer that has been heat-treated after ion implantation; as well as A screening unit identifies defects included in the semiconductor wafer based on the first image information and the second image information, and determines the quality of semiconductor chips formed on the semiconductor wafer.

2. The semiconductor inspection device according to claim 1, wherein The second image information includes information on the photoluminescence of the semiconductor wafer subjected to heat treatment at a temperature of 1000° C. or higher.

3. The semiconductor inspection device according to claim 1 or 2, characterized in that The screening unit includes: an image analyzing unit configured to perform subtraction processing on a contrast related to an ion implantation pattern of the semiconductor wafer in the second image information; a defect classifier configured to determine a type of the defect based on the first image information and the second image information after subtracting the contrast; and A determiner determines the quality of the semiconductor chip based on the information on the type of the defect.

4. The semiconductor inspection device according to claim 3, wherein The screening unit further includes a defect coordinate comparison unit configured to determine a position of the defect included in the semiconductor wafer based on the first image information and the second image information. The defect classifier determines the type of the defect based on the information on the position of the defect, by classifying the defect located in the entire area of ​​the semiconductor chip or the defect located only in the effective area provided in the semiconductor chip.

5. The semiconductor inspection device according to any one of claims 1 to 4, wherein Also provided are a first learning device and a second learning device, The first learning device includes: a first data acquisition unit that acquires first learning data based on the first image information and the classification result of the defect; and a first model generating unit for generating a first learned model for inferring the type of the defect included in the first image information using the first learning data; The second learning device includes: a second data acquisition unit that acquires second learning data based on the second image information and the classification result of the defect; and a second model generating unit for generating a second learned model for inferring the type of the defect included in the second image information using the second learning data; The screening unit determines the quality of the semiconductor chip based on the first image information acquired from the first inspection information acquisition unit, the second image information acquired from the second inspection information acquisition unit, the first learned model, and the second learned model.

6. The semiconductor inspection device according to claim 5, wherein The device further comprises a third learning device that generates a third learned model for inferring the quality of the semiconductor chip by integrated learning based on the information on the type of the defect determined based on the first learned model, the information on the type of the defect determined based on the second learned model, and degradation data of the electrical characteristics of the semiconductor chip. The screening unit determines the quality of the semiconductor chip based on the third learned model.

7. The semiconductor inspection device according to any one of claims 1 to 6, wherein: Also provided is a learning device, the learning device comprising: an image synthesis unit that generates third image information synthesized by storing the first image information and the second image information in different channels; a data acquisition unit that acquires learning data based on the third image information and the classification result of the defect; and a model generating unit that generates a learned model for inferring the type of the defect included in the third image information using the learning data; The screening unit determines the quality of the semiconductor chip based on the learned model.

8. A method for manufacturing a semiconductor device, characterized in that: With the following processes: a step of acquiring first image information including concave-convex information of the surface of the semiconductor wafer before ion implantation; a step of acquiring second image information including photoluminescence information of the semiconductor wafer that has been heat-treated after ion implantation; as well as A process of extracting defects included in the semiconductor wafer based on the first image information and the second image information, and determining the quality of semiconductor chips formed on the semiconductor wafer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: It also has the following processes: A first inspection step is to take a surface image of the semiconductor wafer; an ion implantation step of implanting ions into the semiconductor wafer after the first inspection step; a heat treatment step of performing heat treatment on the semiconductor wafer after the ion implantation step; as well as The second inspection process is to measure a photoluminescence image of the semiconductor wafer after the heat treatment process. The first image information is the surface image captured in the first inspection process, The second image information is the photoluminescence image measured in the second inspection process.

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