Methods, electronic devices, and media for processing chip manufacturing defect modules

Abstract

The application relates to the chip technical field, in particular to a method for processing chip manufacturing defect modules in stages, electronic equipment and a medium, which comprises the following steps: S1, acquiring a chip module set {B1, B2,..., B n ,...,B M}; S2, acquiring corresponding B1 n , B2 n , B3 n of each B n ; S3, determining corresponding groups C n of B n according to corresponding B1 n , B2 n , B3 n of each B n ; S4, performing design-for-test on each B n according to corresponding groups C n of each B n , and determining corresponding test results of each B n , wherein the test results comprise corresponding group information; and S5, determining chip shielding targets according to corresponding test results of each B n , and setting non-must-run logic in the shielding targets into a shielding state. The application improves the efficiency and accuracy of processing chip manufacturing defect modules.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chips, and particularly to a method for processing chip manufacturing defect modules in stages, an electronic device and a medium. BACKGROUND

[0002] In the process of chip manufacturing, due to chip manufacturing reasons, some manufacturing defects may exist in the chip, and the larger the chip area is, the lower the chip yield is. In order to enable more chips to continue to be used, the defective modules can be disabled for degraded use, so as to reduce the defect rate of the chip and improve the yield of the chip. However, the existing method for processing chip manufacturing defect modules has a complex implementation manner and is prone to errors, resulting in low efficiency and poor accuracy of processing chip manufacturing defect modules. Therefore, how to improve the efficiency and accuracy of processing chip manufacturing defect modules becomes a technical problem to be solved. SUMMARY

[0003] The present application aims to provide a method for processing chip manufacturing defect modules in stages, an electronic device and a medium, which improves the efficiency and accuracy of processing chip manufacturing defect modules.

[0004] According to a first aspect of the present application, a method for processing chip manufacturing defect modules in stages is provided, comprising:

[0005] Step S1, acquiring a chip component module set {B1, B2,..., B n ,...,B M}, B n is the nth chip component module, the value range of n is 1 to N, N is the total number of chip component modules contained by the chip, the chip component module includes necessary running logic and non-necessary running logic, and the chip component module is the smallest unit capable of shielding defects;

[0006] Step S2, acquiring B n , B2 n , B3 n corresponding to each B n 1 n , B1 n is a first-level module identifier corresponding to B n , B2 n is a second-level module identifier corresponding to B n , and B3 n is a preset function identifier corresponding to B n The second-level module includes at least one chip component module, the first-level module includes at least one second-level module, the chip component module is located in the second-level module, or is located in the first-level module and not in the second-level module, or is located outside the first-level module;

[0007] Step S3, according to each B nCorresponding B1 n Corresponding B2 n Corresponding B3 n Corresponding B n Corresponding group C n

[0008] Step S4, according to each B n Corresponding group C n Corresponding B n Performing a test of design for test on each B n Corresponding test result, the test result including corresponding group information;

[0009] Step S5, according to each B n Corresponding test result to determine a chip shielding target, and setting a non-essential running logic in the shielding target to a shielding state.

[0010] According to the second aspect of the present application, an electronic device is provided, comprising: at least one processor; and a memory in communication connection with the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are arranged to execute the method according to the first aspect of the present application.

[0011] According to the third aspect of the present application, a computer readable storage medium is provided, which stores computer executable instructions, and the computer executable instructions are used to execute the method according to the first aspect of the present application.

[0012] Compared with the prior art, the present application has obvious advantages and beneficial effects. By means of the above technical scheme, the method for processing chip manufacturing defect modules, the electronic device and the medium provided by the present application can achieve considerable technical progress and practicality, and have wide industrial utilization value, and at least have the following beneficial effects:

[0013] The present application divides each chip component module into a corresponding group according to the function corresponding to the different levels of the chip component module, performs a test of design for test according to the group to which each chip component module belongs, and determines a chip shielding target based on the test result corresponding to each chip component module and the group information, thereby simplifying the process of processing chip manufacturing defect modules and improving the efficiency and accuracy of processing chip manufacturing defect modules. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor. ​

[0015] Figure 1 A method flowchart for grading processing chip manufacturing defects modules is provided in the embodiments of the present application. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0017] The embodiments of the present application provide a method for grading processing chip manufacturing defects modules, as shown in the following figure, which comprises the following steps. Figure 1

[0018] Step S1, acquiring a chip component module set {B1, B2,..., B n ,...,B M}, B n is the nth chip component module, the value range of n is 1 to N, N is the total number of chip component modules contained by the chip, the chip component module includes necessary running logic and non-necessary running logic, and the chip component module is the smallest unit that can be disabled.

[0019] Wherein, the chip level is divided by disabling the chip component modules (blocks) with manufacturing defects in the chip, and more chips can continue to be used.

[0020] Step S2, acquiring the corresponding B n 1 n , B2 n , B3 n , B1 n is the first-level module identifier corresponding to B n , B2 n is the second-level module identifier corresponding to B n , and B3 n is the preset function identifier corresponding to B n , the second-level module includes at least one chip component module, the first-level module includes at least one second-level module, the chip component module is located in the second-level module, or is located in the first-level module and not in the second-level module, or is located outside the first-level module.

[0021] ​It should be noted that the secondary module is located in the primary module, the sub-module of the secondary module includes the chip component module, the sub-module of the primary module includes the secondary module, and the sub-module of the primary module can also include the chip component module. The chip component module can also be located outside the primary module. For example, the chip component module corresponding to the logic that the chip must run, or some chip component modules with preset functions, etc. Specifically, the secondary module can be a computing unit. The preset function refers to a user-specified function, and the preset function can be an image processing function.

[0022] Step S3, according to each B n Corresponding B1 n , B2 n , B3 n Determine B n Corresponding group C n .

[0023] Step S4, according to each B n Corresponding group C n Each B n Performability design test to determine each B n Corresponding test results, the test results include corresponding group information.

[0024] Step S5, according to each B n Corresponding test results determine the chip shielding target, and set the non-mandatory running logic in the shielding target to a shielding state.

[0025] As an embodiment, the step S2 includes:

[0026] Step S21, if B n Located outside the primary module and does not have a preset function, B1 n , B2 n , B3 n All are set to empty.

[0027] It can be understood that setting B1 n , B2 n , B3 n All to empty specifically refers to setting to an identifier that is empty, and the specific identifier symbol is not limited here.

[0028] Step S22, if B n Located outside the primary module and has a preset function, B1 n , B2 n Set to empty, and set B3 n To a preset function identifier.

[0029] Step S23, if B nIf B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier. n If B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier. n If B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier. n If B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier.

[0030] If B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier. n If B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier. n If B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier. n If B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier. n If B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier.

[0031] If B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier. n If B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier. n If B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier. n If B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier. n If B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier.

[0032] If B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier. n If B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier. n If B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier. n If B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier. n If B is located in the primary module and not in the secondary module, and does not have the preset function, B1 is set as the corresponding primary module identifier, B2 is set as the corresponding primary module identifier, and B3 is set as the preset function identifier.

[0033] It should be noted that through steps S21-S26, according to the location and corresponding function of each B, the corresponding B1, B2, and B3 information of each B is determined. n It should be noted that through steps S21-S26, according to the location and corresponding function of each B, the corresponding B1, B2, and B3 information of each B is determined. n It should be noted that through steps S21-S26, according to the location and corresponding function of each B, the corresponding B1, B2, and B3 information of each B is determined. n It should be noted that through steps S21-S26, according to the location and corresponding function of each B, the corresponding B1, B2, and B3 information of each B is determined. n It should be noted that through steps S21-S26, according to the location and corresponding function of each B, the corresponding B1, B2, and B3 information of each B is determined. n It should be noted that through steps S21-S26, according to the location and corresponding function of each B, the corresponding B1, B2, and B3 information of each B is determined.

[0034] As an embodiment, the embodiment of the present application is divided into six groups, specifically G0, G1, G2, G3, G4, and G5. The step S3 includes:

[0035] If B1, B2, and B3 are empty, C is set as G0. n n n n If B1, B2, and B3 are empty, C is set as G0.

[0036] If B1 and B2 are empty and B3 is not empty, C is set as G3. n n n n If B1 and B2 are empty and B3 is not empty, C is set as G3.

[0037] ​​​​​​Step S33, if B1 n is not null, B2 n is null, B3 n is not null, then set C n =G4.

[0038] Step S34, if B1 n is not null, B2 n is null, B3 n is not null, then set C n =G2.

[0039] Step S35, if B1 n , B2 n is not null, B3 n is null, then set C n =G1.

[0040] Step S36, if B1 n , B2 n , B3 n are all not null, then set C n =G5.

[0041] It should be noted that through steps S31-S36, each B n is divided into a corresponding group according to the B1 n , B2 n , B3 n information corresponding to each B n .

[0042] As an embodiment, each B n includes a plurality of registers, and the step S4 includes:

[0043] Step S41, if the C n corresponding to B n is G0, mark the clock signal corresponding to B n as G0 and input into all registers of B n .

[0044] It should be noted that marking the clock signal corresponding to B n as G0 and inputting into all registers of B n , each register of B n can trace back to the clock signal marked as G0 corresponding to B n , and all registers of B n are also divided into a G0 group.

[0045] Step S42, if the C n corresponding to B n is Gm, m is in the range of 1 to 5, then determine B nIf there is a register of the must-run logic, step S43 is executed, otherwise, step S44 is executed.

[0046] It should be noted that for the division of B n to Gm n , there can be a part of registers corresponding to the must-run logic, which also needs to be marked as G0 group.

[0047] Step S43, mark the clock signal corresponding to B n as G0 and input it to the register of the must-run logic of B n , mark the clock signal corresponding to B n as Gm and input it to the register of the non-must-run logic of B n , and execute step S45.

[0048] It should be noted that through step S43, the registers of the must-run logic of B n can be divided into G0 group, and the registers of the non-must-run logic of B n can be divided into Gm group.

[0049] Step S44, mark the clock signal corresponding to B n as Gm and input it to all registers of B n , and execute step S45.

[0050] Step S45, generate a scan chain based on the registers of B n with the same clock signal mark input, and perform design for test (DFT) based on the scan chain to determine the test result of the scan chain corresponding to B n and the group mark of the clock signal corresponding to the scan chain.

[0051] It should be noted that if the scan test chain is abnormal, it means that the corresponding B n is abnormal.

[0052] As an embodiment, in steps S41 and S43, the marking of the clock signal corresponding to B n as G0 includes:

[0053] Insert a marker buffer for marking G0 at the clock input interface of B n , and mark the clock signal corresponding to B n as G0 after passing through the marker buffer for marking G0.

[0054] In steps S43 and S44, the marking of the clock signal corresponding to B n as Gm includes:

[0055] Insert a marker buffer for marking Gm at the clock input interface of Bn a clock input interface of B n corresponding clock signal is marked as Gm after passing through the marking buffer for marking Gm.

[0056] It can be understood that, if B n corresponding C n is G0, only one marking buffer for marking G0 needs to be inserted into the clock input interface of B n if B n corresponding C n is Gm and there are registers in B n that must run logic, two marking buffers need to be inserted into the clock input interface of B n , one for marking G0 and one for marking Gm. n corresponding C n is Gm and there are no registers in B n that must run logic, only one marking buffer for marking Gm needs to be inserted into the clock input interface of B n .

[0057] As an implementation, the step S5 comprises:

[0058] Step S51, if there is an abnormal G0 corresponding scan chain, it is determined that the chip is not available, the process is ended, otherwise, steps S52 and S53 are executed in parallel.

[0059] It can be understood that the G0 corresponding scan chain refers to a scan chain whose corresponding clock signal group is marked as G0.

[0060] Step S52, if there is an abnormal G3 corresponding scan chain, a chip module with an abnormal G3 scan chain and a chip module with a preset function identifier not empty interacting with the chip module with an abnormal G3 scan chain in the secondary module are determined as chip shielding targets, otherwise, step S54 is executed.

[0061] It can be understood that the G3 corresponding scan chain refers to a scan chain whose corresponding clock signal group is marked as G3.

[0062] Step S53, if there is an abnormal G4 corresponding scan chain and the number of primary modules involved in the abnormal G4 corresponding scan chain is greater than or equal to a first preset threshold, it is determined that the chip is not available, the process is ended, if there is an abnormal G4 corresponding scan chain and the number of primary modules involved in the abnormal G4 corresponding scan chain is less than the first preset threshold, the primary modules involved in the abnormal G4 corresponding scan chain are determined as chip shielding targets, and step S54 is executed.

[0063] It can be understood that the G4 corresponding scan chain refers to the scan chain corresponding to the clock signal group marked as G4.

[0064] Step S54, if the G2 corresponding scan chain exception exists, and the number of the primary modules involved in the G2 corresponding scan chain exception is greater than or equal to the second preset threshold, all the chips with the preset function identification not empty are determined as the chip shielding target, if the G2 corresponding scan chain exception exists, and the number of the primary modules involved in the G2 corresponding scan chain exception is less than the second preset threshold, the primary modules involved in the G2 corresponding scan chain exception are determined as the chip shielding target.

[0065] It can be understood that the G2 corresponding scan chain refers to the scan chain corresponding to the clock signal group marked as G2.

[0066] Step S55, if the G1 corresponding scan chain exception exists, and the number of the secondary modules involved in the G1 corresponding scan chain exception contained in the primary module exceeds the third preset threshold, the primary module is set as the chip shielding target, and the secondary modules involved in the G1 corresponding scan chain exception in the primary module which is not the chip shielding target are set as the chip shielding target.

[0067] It can be understood that the G1 corresponding scan chain refers to the scan chain corresponding to the clock signal group marked as G1.

[0068] Step S56, if the G5 corresponding scan chain exception exists, and the number of the secondary modules involved in the G5 corresponding scan chain exception contained in the primary module exceeds the third preset threshold, the primary module is set as the chip shielding target, and the secondary modules involved in the G5 corresponding scan chain exception in the primary module which is not the chip shielding target are set as the chip shielding target.

[0069] It can be understood that the G5 corresponding scan chain refers to the scan chain corresponding to the clock signal group marked as G5.

[0070] Step S57, all the chip shielding targets are set as the shielding state.

[0071] It should be noted that setting the chip shielding target as the shielding state does not affect the use of the unshielded constituent modules in the chip.

[0072] As an embodiment, the step S3 further comprises:

[0073] Step S10, acquiring the shielding category possibility identification {H1 k ,H2 k ,H3 k} corresponding to each group Gk. k Gk The corresponding primary module shielding possibility identifier, H2 k is G k The corresponding secondary module shielding possibility identifier, H3 k is G k The corresponding preset function shielding possibility identifier, shielding possible and identifier includes R1 and R2, R1 exists shielding possibility, R2 represents that shielding possibility does not exist, and k is 1 to 5.

[0074] It should be noted that according to the group division condition, the shielding category possibility identifier corresponding to each group Gk can be determined, and the specific result is shown in the following table.

[0075]

[0076] Step S20, if B i Can transmit signals to B j , and B i Corresponding group Gk corresponding Hv k is R1, B j Corresponding group Gk corresponding Hv k is R2, and v is 1 to 3, then B i Transmit signals to B j Interface protection unit E ij And protection control unit F ij , E ij Set B i Input security value to B j , F ij For controlling E ij Open and close, F ij Default control E ij Is in the closed state, when B i Be determined as shielding target and B j Be determined as non-shielding target, F ij Control E ij Is in the open state, B i Input security value to B j , B i And B j All are chip set modules in {B1, B2,..., B n ,..., B M}, i≠j.

[0077] It should be noted that B i Corresponding group Gk corresponding Hv k is R1, B j Corresponding group Gk corresponding Hv k is R2 means B iThe corresponding group Gk corresponds to H1 k R1 and B j The corresponding group Gk corresponds to H1 k R2, or B j The corresponding group Gk corresponds to Hv k R2 refers to B i The corresponding group Gk corresponds to H2 k R1 and B j The corresponding group Gk corresponds to H2 k R2, or B j The corresponding group Gk corresponds to Hv k R2 refers to B i The corresponding group Gk corresponds to H3 k R1 and B j The corresponding group Gk corresponds to H3 k is R2. During the chip design phase, F ij Default Control E ij In the closed state. If step S5 determines that B i is a shielded target and B j For non-shielded targets, F ij Control E ij In the open state, B i To B j Enter a safe value so that i After being blocked B i To B j The input interface also outputs the correct value.

[0078] As an embodiment, in order to ensure that the protection logic is set comprehensively, the security set in step S6 may be further verified, and the step S20 may further include:

[0079] Step S30: randomly setting a shielding target and the number of shielding targets for the chip.

[0080] The randomly set shielding targets may be one or more of a chip component module, a primary module, and a secondary module, and the number of shielding targets corresponding to each chip component module may be randomly set.

[0081] Step S40: Set the clock buffer output corresponding to each shielded target to an indeterminate state X for random verification. If the indeterminate state X is transmitted to a non-shielded target, a protection logic missing prompt is generated.

[0082] It should be noted that if the protection logic is fully configured, the indeterminate state X will not be transmitted to the non-shielded target. If it is transmitted to the non-shielded target, it means that the protection logic is missing and the configuration needs to be further checked.

[0083] It is to be understood that some of the example embodiments are described in terms of a process or method depicted as a flowchart. Although a flowchart can describe a process as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps can be re-arranged. A process can be terminated when its operations are completed, but could also occur under some other condition or event, such as in response to a termination instruction. The processes can correspond in part to method steps for implementing the described functionality.

[0084] The embodiment of the present application further provides an electronic device, comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executed by the at least one processor, and the instructions are arranged to execute the method according to the embodiment of the present application.

[0085] The embodiment of the present application further provides a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are used for executing the method according to the embodiment of the present application.

[0086] The embodiment of the present application divides each chip component module into a corresponding group according to the function corresponding to the different levels of the chip component module, performs the test of the design for testability according to the group to which each chip component module belongs, and determines the chip shielding target based on the test result corresponding to each chip component module and the group information corresponding to each chip component module, so that the flow of processing the chip manufacturing defect module is simplified, and the efficiency and accuracy of processing the chip manufacturing defect module are improved.

[0087] The above description is only the preferred embodiment of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed as the above preferred embodiment, it is not intended to limit the present application. Any skilled person in the art can make some changes or modifications to the above disclosed technical content to make equivalent embodiments with equivalent changes, but any simple modification, equivalent change and modification made according to the technical essence of the present application to the above embodiments are still within the scope of the technical solution of the present application.

Claims

1. A method of hierarchically processing chip manufacturing defect modules, the method comprising: Comprising: Step S1, obtaining a chip component module set {B1, B2,..., B n ,...,B M}, B n is the nth chip component module, n ranges from 1 to N, N is the total number of chip component modules contained by the chip, the chip component module includes necessary running logic and non-necessary running logic, and the chip component module is the smallest unit capable of shielding defects; Step S2, obtaining each B n Corresponding B1 n , B2 n , B3 n , B1 n is B n Corresponding primary module identifier, B2 n is B n Corresponding secondary module identifier, B3 n is B n Corresponding preset function identifier, the secondary module includes at least one chip component module, the primary module includes at least one secondary module, the chip component module is located in the secondary module, or is located in the primary module and is not in the secondary module, or is located outside the primary module; Step S3, determine B n Corresponding B1 n , B2 n , B3 n Determine B n Corresponding group C n ; Step S4, according to each B n Corresponding group C n For each B n Performability design test, determine each B n Corresponding test results, test results include corresponding group information; Step S5, according to each B n The corresponding test result determines the chip shielding target, and sets the unnecessary running logic in the shielding target to a shielding state.

2. The method of claim 1, wherein, the step S2 comprises: Step S21, if B n located outside the primary module and not having a preset function, B1 n , B2 n , B3 n are all set to null; Step S22, if B n located outside the primary module and has a predetermined function, B1 n , B2 n is set to empty, B3 n is set to the predetermined function identifier; Step S23, if B n located in the primary module and not in the secondary module, and not having the preset function, B1 n is set to the corresponding primary module identifier, B2 n , B3 n is set to null; Step S24, if B n located in the primary module and not in the secondary module, and has a preset function, B1 n is set to the corresponding primary module identifier, B2 n is set to empty, B3 n is set to the preset function identifier; Step S25, if B n located in the secondary module, and not with the preset function, B1 n is set to the corresponding primary module identifier, B2 n is set to the corresponding secondary module identifier, B3 n is set to empty; Step S26, if B n Located in the secondary module, and has a preset function, will B1 n Set to the corresponding primary module identification, will B2 n Set to the corresponding secondary module identification, will B3 n Set to the preset function identification.

3. The method of claim 1, wherein, the step S3 comprises: Step S31, if B1 n , B2 n , B3 n is empty, then set C n =G0; Step S32, if B1 n , B2 n is empty, B3 n is not empty, then set C n =G3; Step S33, if B1 n is not empty, B2 n , B3 n is empty, set C n =G4; Step S34, if B1 n Not null, B2 n Null, B3 n Not null, set C n =G2; Step S35, if B1 n , B2 n is not empty, B3 n is empty, then set C n = G1; Step S36, if B1 n , B2 n , B3 n are not empty, set C n =G5.

4. The method of claim 3, wherein, the step S4 comprises: Step S41, if B n The corresponding C n For G0, B n The corresponding clock signal is marked G0, input to B n All registers in; Step S42, if B n Corresponding C n If the value range of Gm,m is 1 to 5, it is judged that B n If there is a register that must run logic, if there is, step S43 is executed, otherwise, step S44 is executed; Step S43, B n The corresponding clock signal is marked as G0, input to B n The register that must run the logic, B n The corresponding clock signal is marked as Gm, input to B n The register that does not necessarily run the logic, Step S45; Step S44, B n The corresponding clock signal is marked Gm, input to all registers of B n Step S45 is executed; Step S45, based on B n The clock signal input in the middle marks the same register to generate a scan chain, and the test is performed based on the scan chain. The test result of the corresponding scan chain and the group mark of the clock signal corresponding to the scan chain are determined. n The clock signal input in the middle marks the same register to generate a scan chain, and the test is performed based on the scan chain. The test result of the corresponding scan chain and the group mark of the clock signal corresponding to the scan chain are determined.

5. The method of claim 4, wherein, In the step S41 and the step S43, the B n The corresponding clock signal mark G0 includes: In B n The clock input interface inserts a marker buffer for marking G0, B n The corresponding clock signal is marked as G0 after passing through the marker buffer for marking G0; In the step S43, the step S44, the B n The corresponding clock signal mark Gm, including: In B n The clock input interface of B n The corresponding clock signal is marked as Gm after passing through the mark buffer of Gm.

6. The method of claim 4, wherein, the step S5 comprises: Step S51, if there is a G0 corresponding scan chain exception, it is determined that the chip is not available, the process is ended, otherwise, steps S52 and S53 are executed in parallel; Step S52, if there is a G3 corresponding scan chain exception, the chip module with G3 scan chain exception and the chip module with preset function identifier not empty in the secondary module are determined as chip shielding target, otherwise, step S54 is executed; Step S53, if there is a G4 corresponding scan chain exception, and the number of primary modules involved in the G4 corresponding scan chain exception is greater than or equal to the first preset threshold, it is determined that the chip is not available, and the process is ended, if there is a G4 corresponding scan chain exception, and the number of primary modules involved in the G4 corresponding scan chain exception is less than the first preset threshold, the primary module involved in the G4 corresponding scan chain exception is determined as the chip shielding target, and step S54 is executed; Step S54, if there is a G2 corresponding scan chain exception, and the number of primary modules involved in the G2 corresponding scan chain exception is greater than or equal to the second preset threshold, all chip modules with preset function identifier not empty are determined as chip shielding target, if there is a G2 corresponding scan chain exception, and the number of primary modules involved in the G2 corresponding scan chain exception is less than the second preset threshold, the primary module involved in the G2 corresponding scan chain exception is determined as the chip shielding target; Step S55, if there is a G1 corresponding scan chain exception, and the number of secondary modules involved in the G1 corresponding scan chain exception contained in the primary module exceeds the third preset threshold, the primary module is set as the chip shielding target, and the secondary module involved in the G1 corresponding scan chain exception in the primary module which is not the chip shielding target is set as the chip shielding target; Step S56, if there is a G5 corresponding scan chain exception, and the number of secondary modules involved in the G5 corresponding scan chain exception contained in the primary module exceeds the third preset threshold, the primary module is set as the chip shielding target, and the secondary module involved in the G5 corresponding scan chain exception in the primary module which is not the chip shielding target is set as the chip shielding target; Step S57, all chip shielding targets are set as shielding state.

7. The method of claim 1, wherein, the step S3 further comprises: Step S10, obtaining a shielding category possibility identifier {H1 k ,H2 k ,H3 k} corresponding to each group Gk, H1 k is a first-level module shielding possibility identifier corresponding to G k H2 k is a second-level module shielding possibility identifier corresponding to G k H3 k is a preset function shielding possibility identifier corresponding to G k The shielding possibilities and identifiers include R1 and R2, R1 indicates that there is a shielding possibility, and R2 indicates that there is no shielding possibility, and k ranges from 1 to 5. Step S20, if B i transmits signals to B j , and B i transmits signals to B k , the corresponding group Gk corresponds to Hv j , and B k is R1, v is in the range of 1 to 3, then B i transmits signals to B j , the interface setting protection unit E ij and the protection control unit F ij , E ij sets B i , inputs the security value to B j , F ij controls the opening and closing of E ij , F ij controls E ij to be in the closed state by default, when B i is determined to be a shielding target and B j is determined to be a non-shielding target, F ij controls E ij to be in the open state, B i inputs the security value to B j , B i and B j are chip set modules in {B1, B2,..., B n ,..., B M}, i≠j.

8. The method of claim 7, wherein, the step S20 further comprises: Step S30, randomly setting shielding target and the number of shielding target for the chip; Step S40, setting the clock buffer output corresponding to each shielding target as an indefinite state X for random verification, if the indefinite state X is transmitted to the non-shielding target, a protection logic missing prompt is generated.

9. An electronic device, comprising: Comprise: at least one processor; and a memory connected in communication with the at least one processor; Wherein the memory stores instructions executed by the at least one processor, the instructions are set to execute the method of any one of the preceding claims 1-8.

10. A computer-readable storage medium, characterized in that, Computer executable instructions are stored, the computer executable instructions are used to execute the method of any one of the preceding claims 1-8.

Images