Chip structure and connection method of chip and heat dissipation substrate

Abstract

The embodiment of the invention provides a chip structure and a connection method of a chip and a heat dissipation substrate. The chip structure comprises a chip and a heat dissipation substrate used for conducting heat dissipation on the chip. A first metal layer structure is arranged on the upper surface of the chip, a second metal layer structure is arranged on the lower surface of the heat dissipation substrate, and the first metal layer structure and the second metal layer structure are adjacent and stacked. The chip and the heat dissipation substrate are connected together through alloying reaction of the first metal layer structure and the second metal layer structure. Through the embodiment of the invention, the problem that the reliability of the connection between the chip and the heat dissipation substrate cannot be ensured while the low thermal resistance and high bonding strength of the bonding interface cannot be considered by the existing linking method in the related technology is solved, and the effect of improving the reliability of the connection between the chip and the heat dissipation substrate is achieved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of chip heat dissipation, and in particular to a chip structure and a method for connecting a chip to a heat dissipation substrate. Background Art

[0002] Currently, there are three methods for connecting high-power chips to heat sink substrates: surface activation low-temperature direct bonding, nanoporous metal sintering material bonding, and metal bonding. The surface activation low-temperature direct bonding method requires extremely high surface roughness (Ra < 1nm) between the chip and the heat sink substrate. The polishing technology is extremely difficult, the operation is complex, and the cost is high, making it unfavorable for large-scale application. The nanoporous metal sintering material bonding method faces reliability issues such as nanoporous metal sintering material expansion, electron migration, and delamination. The metal bonding method utilizes metal atom diffusion to achieve the connection between the chip and the heat sink substrate. Although it can achieve low thermal resistance at the bonding interface, it has high requirements for the surface roughness of the chip and the heat sink substrate, resulting in a low product yield. How to reliably connect the chip to the heat sink substrate while taking into account both low thermal resistance and high bonding strength at the bonding interface is an urgent issue that needs to be solved. Summary of the Invention

[0003] An embodiment of the present invention provides a chip structure and a method for connecting the chip to a heat dissipation substrate, so as to at least solve the problem that the existing connection methods in the related art cannot take into account both low thermal resistance and high bonding strength of the bonding interface while ensuring the reliability of the connection between the chip and the heat dissipation substrate.

[0004] According to one embodiment of the present invention, a chip structure is provided, comprising: a chip and a heat dissipation substrate for dissipating heat from the chip; a first metal layer structure is provided on the upper surface of the chip, and a second metal layer structure is provided on the lower surface of the heat dissipation substrate, the first metal layer structure and the second metal layer structure are adjacent to and stacked with each other, and the chip and the heat dissipation substrate are connected together through an alloying reaction between the first metal layer structure and the second metal layer structure.

[0005] According to another embodiment of the present invention, a method for connecting a chip to a heat dissipation substrate is provided, comprising: setting a first metal layer structure on the upper surface of the chip, and setting a second metal layer structure on the lower surface of the heat dissipation substrate; setting the first metal layer structure and the second metal layer structure to be adjacent to and stacked, and applying pressure and temperature to the chip and the heat dissipation substrate to cause an alloying reaction between the first metal layer structure and the second metal layer structure to connect the chip and the heat dissipation substrate.

[0006] Through the above-mentioned embodiments of the present invention, since a first metal layer structure is set on the chip and a second metal layer structure is set on the heat dissipation substrate, the connection between the chip and the heat dissipation substrate can be achieved through the alloying reaction between the first metal layer structure and the second metal layer structure. This connection method has low interface thermal resistance, high bonding strength and reliability. Therefore, it can solve the problem that the existing connection method in the related art cannot take into account the low thermal resistance and high bonding strength of the bonding interface while ensuring the reliability of the connection between the chip and the heat dissipation substrate, thereby achieving the effect of improving the reliability of the connection between the chip and the heat dissipation substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of a chip structure according to an embodiment of the present invention;

[0008] Figure 2 is a schematic diagram of a chip structure according to another embodiment of the present invention;

[0009] Figure 3 is a schematic diagram of a chip structure according to another embodiment of the present invention;

[0010] Figure 4 is a schematic diagram of a chip structure according to another embodiment of the present invention;

[0011] Figure 5 is a schematic diagram of a chip structure according to another embodiment of the present invention;

[0012] Figure 6 is a schematic diagram of a chip structure according to another embodiment of the present invention;

[0013] Figure 7 is a flow chart of a method for connecting a chip to a heat dissipation substrate according to an embodiment of the present invention;

[0014] Figure 8 is a schematic diagram of a chip structure including an alloying reaction layer according to an embodiment of the present invention;

[0015] Figure 9 is a schematic diagram of a semiconductor package structure according to an embodiment of the present invention;

[0016] Figure 10 FIG. 4 is a schematic diagram of a semiconductor package structure according to another embodiment of the present invention. DETAILED DESCRIPTION

[0017] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with embodiments.

[0018] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0019] For chips with high power and heat flux density, if a heat sink substrate with high thermal conductivity is connected to its surface, the chip can be effectively and quickly cooled and the temperature difference on the chip can be reduced. In order to meet the requirements of both chip heat dissipation and connection reliability, the bonding interface between the chip and the heat sink substrate must have low thermal resistance and high bonding strength.

[0020] Currently, there are three methods for connecting high-power chips to heat dissipation substrates:

[0021] Method 1: Surface activation low-temperature direct bonding method, that is, the chip and the heat sink substrate are cleaned, plasma activated, bonded and annealed to achieve the connection between the chip and the heat sink substrate. This connection method can achieve a low interface thermal resistance at the bonding interface, but it has extremely high requirements on the surface roughness of the chip and the heat sink substrate (Ra <1nm), the polishing technology is extremely difficult, the operation is complex, the cost is high, and it is not conducive to large-scale application.

[0022] Method 2: Nanoporous metal sintering material bonding method, such as nanosilver, nanocopper and nanogold sintering materials, that is, two nanometal layers are sputtered on the surface of the chip and the heat dissipation substrate: metal layer 1 and metal layer 2. Metal layer 1 (close to the surface of the chip and the heat dissipation substrate) can be Ti, Cr, Ni, Al, Mo, Ta, W, Fe and Co, etc., and metal layer 2 can be Au and Ag, etc. Then, nanoporous metal sintering material is coated on the surface of metal layer 2. Finally, the chip and the heat dissipation substrate are connected under a certain bonding pressure and temperature. This method can also achieve lower interface thermal resistance and higher bonding strength, but this method needs to face reliability issues such as expansion of nanoporous metal sintering materials, electron migration and delamination.

[0023] Method three, metal bonding method, that is, sputtering two layers of nanometal layers on the surface of the chip and the heat dissipation substrate. The type of metal layer is similar to that of the above method two, and the bonding steps are the same as those of the above method one. It uses the diffusion of metal atoms to achieve the connection between the chip and the heat dissipation substrate. This method has a low thermal resistance of the bonding interface, but has high requirements on the surface roughness of the chip and the heat dissipation substrate, and the resulting product yield is low.

[0024] An embodiment of the present invention proposes a chip structure and connection method, in which a metal layer is sputtered or evaporated on the surface of a heat dissipation substrate and a chip, and the heat dissipation substrate and the chip are bonded through an alloying reaction between the metal layers, thereby achieving low interface thermal resistance, high bonding strength and reliability.

[0025] Figure 1 is a schematic diagram of a chip structure according to an embodiment of the present invention, such as Figure 1As shown, a chip and a heat dissipation substrate for dissipating heat from the chip; a first metal layer structure is provided on the upper surface of the chip, and a second metal layer structure is provided on the lower surface of the heat dissipation substrate, the first metal layer structure and the second metal layer structure are adjacent to and stacked, and the chip and the heat dissipation substrate are connected together through an alloying reaction between the first metal layer structure and the second metal layer structure.

[0026] In the embodiments of the present invention, the terms "upper surface" and "lower surface" are used to describe the spatial relationship between the chip and the heat sink substrate, rather than to define fixed orientations. In some embodiments, the installation or use of the chip and heat sink substrate may cause the definition of "upper surface" and "lower surface" to vary depending on the environment or posture. However, in all cases, these terms are intended to describe a relative positional relationship, namely, the position of one surface relative to another, and this relationship is not affected by changes in the external reference coordinate system.

[0027] In this embodiment, the chip is a bare chip, which may include but is not limited to one of Si, SiC, GaN, and InP.

[0028] A bare chip refers to the product form of a semiconductor component after it is manufactured and before it is packaged. It has an active side and a passive side. The active side is the side where the integrated circuit pattern is located, and the passive side is the side opposite to the active side.

[0029] In an embodiment of the present invention, the first metal layer structure is disposed on the passive surface of the bare chip to prevent the metal layer from affecting the circuit connection of the chip.

[0030] Figure 2 is a schematic diagram of a chip structure according to another embodiment of the present invention. Figure 2 As shown, the first metal layer structure includes a first metal layer, and the second metal layer structure includes a second metal layer. The first metal layer and the second metal layer are adjacent to each other and are stacked. The first metal layer and the second metal layer form an alloying reaction layer through an alloying reaction, so that the chip and the heat dissipation substrate are connected together; wherein the metal materials between the first metal layer and the second metal layer are different.

[0031] In one embodiment, the metal material of the first metal layer includes but is not limited to one of the following: gold, copper, silver, bismuth, and the metal material of the second metal layer includes but is not limited to one of the following: tin, indium; or, the metal material of the first metal layer includes but is not limited to one of the following: tin, indium, and the metal material of the second metal layer includes but is not limited to one of the following: gold, copper, silver, bismuth.

[0032] Figure 3 FIG. 1 is a schematic diagram of a chip structure according to another embodiment of the present invention. Figure 3As shown, the first metal layer structure also includes a third metal layer, which is arranged between the chip and the first metal layer to enhance the adhesion between the first metal layer and the chip; the metal material of the third metal layer is different from the metal material of the first metal layer; the second metal structure also includes a fourth metal layer, which is arranged between the second metal layer and the heat dissipation substrate to enhance the adhesion between the second metal layer and the heat dissipation substrate; the metal material of the second metal layer is different from the metal material of the fourth metal layer.

[0033] In one embodiment, the metal material of the third metal layer or the fourth metal layer includes, but is not limited to, one of the following: titanium, gold, chromium, nickel, aluminum, molybdenum, tantalum, tungsten, iron, and cobalt. The metal materials of the third metal layer and the fourth metal layer may be the same or different.

[0034] In one embodiment, Figure 2 On the basis of, the first metal layer structure further includes a third metal layer; or, the second metal structure further includes a fourth metal layer.

[0035] In one embodiment, the first metal layer structure further includes a fifth metal layer, wherein the fifth metal layer is disposed between the first metal layer and the third metal layer to enhance adhesion between the first metal layer and the third metal layer.

[0036] Figure 4 FIG. 1 is a schematic diagram of a chip structure according to another embodiment of the present invention. Figure 4 As shown, in Figure 3 On the basis of, the first metal layer structure further includes a fifth metal layer.

[0037] In one embodiment, the second metal layer structure includes a sixth metal layer, wherein the sixth metal layer is disposed between the second metal layer and the fourth metal layer to enhance adhesion between the second metal layer and the fourth metal layer. Figure 5 FIG. 1 is a schematic diagram of a chip structure according to another embodiment of the present invention. Figure 5 As shown, in Figure 3 Based on this, the second metal layer structure includes a sixth metal layer.

[0038] In one embodiment, the first metal layer structure further includes a fifth metal layer and the second metal layer structure includes a sixth metal layer. Figure 6 FIG. 1 is a schematic diagram of a chip structure according to another embodiment of the present invention. Figure 6 As shown, in Figure 3 On the basis of this, the first metal layer structure further includes a fifth metal layer and the second metal layer structure includes a sixth metal layer.

[0039] In one embodiment, the metal material of the fifth metal layer is different from the metal materials of the first metal layer and the third metal layer; the metal material of the sixth metal layer is different from the metal materials of the second metal layer and the fourth metal layer. The metal materials of the fifth metal layer and the sixth metal layer can be the same or different.

[0040] In one embodiment, the metal material of the fifth metal layer or the sixth metal layer includes but is not limited to one of the following: titanium, gold, chromium, nickel, aluminum, molybdenum, tantalum, tungsten, iron, and cobalt.

[0041] In one embodiment, the thickness of any metal layer in the first metal layer structure or the second metal layer structure is in the nanometer scale, that is, the thickness of any metal layer in the first to sixth metal layers is in the nanometer scale.

[0042] In one embodiment, the heat dissipation substrate includes but is not limited to one of the following: diamond on silicon substrate, bare diamond, diamond copper metal matrix composite material, diamond aluminum metal matrix composite material, silicon, silicon carbide, and gallium nitride.

[0043] In one embodiment, the silicon-based diamond includes but is not limited to one of the following: silicon-based single crystal diamond, silicon-based polycrystalline diamond, and silicon-based diamond heat sink.

[0044] In one embodiment, the bare diamond includes, but is not limited to, one of the following: single crystal diamond, polycrystalline diamond, and diamond heat sink.

[0045] Through the above steps, since a first metal layer structure is set on the chip and a second metal layer structure is set on the heat dissipation substrate, the connection between the chip and the heat dissipation substrate can be achieved through the alloying reaction between the first metal layer structure and the second metal layer structure. This connection method has low interface thermal resistance, high bonding strength and reliability. Therefore, it can solve the problem that the existing connection method in the relevant technology cannot take into account the low thermal resistance and high bonding strength of the bonding interface while ensuring the reliability of the connection between the chip and the heat dissipation substrate, thereby achieving the effect of improving the reliability of the connection between the chip and the heat dissipation substrate.

[0046] The method for connecting a chip and a heat dissipation substrate provided by an embodiment of the present invention is to sputter or evaporate a nano-metal layer on the surface of both the chip and the heat dissipation substrate, wherein the nano-metal layer is an adhesion layer (for example, the third metal layer, the fourth metal layer, the fifth metal layer, and the sixth metal layer in the above embodiment) and a reaction layer (for example, the first metal layer and the second metal layer in the above embodiment). The adhesion layer is used to improve the adhesion between the metal layer and the substrate, and the reaction layer is used to achieve an alloying reaction between the metal layers. The chip with the sputtered or evaporated nano-metal layer and the heat dissipation substrate are placed under a certain pressure and temperature to achieve bonding between the chip and the diamond silicon surface of the silicon substrate. This method can achieve the advantages of low interface thermal resistance, high bonding strength, and bonding reliability.

[0047] Figure 7 FIG. 1 is a flow chart of a method for connecting a chip to a heat dissipation substrate according to an embodiment of the present invention. Figure 7 As shown, the method includes the following steps:

[0048] Step S702 , providing a first metal layer structure on the upper surface of the chip, and providing a second metal layer structure on the lower surface of the heat dissipation substrate;

[0049] In step S702 of this embodiment, a first metal layer structure is provided on the chip, and a second metal layer structure is provided on the heat dissipation substrate, including: sputtering or evaporating a first metal layer on the chip surface, and sputtering or evaporating a second metal layer on the heat dissipation substrate surface.

[0050] In this embodiment, the metal material of the first metal layer includes but is not limited to one of the following: gold, copper, silver, and bismuth, and the metal material of the second metal layer includes but is not limited to one of the following: tin and indium; or, the metal material of the first metal layer includes but is not limited to one of the following: tin and indium, and the metal material of the second metal layer includes but is not limited to one of the following: gold, copper, silver, and bismuth.

[0051] In one embodiment, a first metal layer structure is set on the chip, and a second metal layer structure is set on the heat dissipation substrate, including: directly sputtering or evaporating a third metal layer on the chip, and then sputtering or evaporating a first metal layer on the third metal layer; directly sputtering or evaporating a fourth metal layer on the heat dissipation substrate, and then sputtering or evaporating a second metal layer on the fourth metal.

[0052] In one embodiment, a first metal layer structure is provided on the chip, and a second metal layer structure is provided on the heat dissipation substrate, further comprising: before sputtering or evaporating the first metal layer on the third metal layer, first sputtering or evaporating the fifth metal layer on the third metal layer, and then sputtering or evaporating the first metal layer on the fifth metal layer.

[0053] Among them, the function of the third metal layer is to improve the adhesion between the chip and the fifth metal layer, and the function of the fifth metal layer is to improve the adhesion between the first metal layer and the third metal layer. According to the selection of the first and third metal layers, the thickness of the fifth metal layer can be 0nm.

[0054] In one embodiment, a first metal layer structure is set on the chip, and a second metal layer structure is set on the heat dissipation substrate, which also includes: before sputtering or evaporating the second metal layer on the fourth metal, first sputtering or evaporating the sixth metal layer on the fourth metal layer, and then sputtering or evaporating the second metal layer on the sixth metal layer.

[0055] Among them, the function of the fourth metal layer is to improve the adhesion between the chip and the sixth metal layer, and the function of the sixth metal layer is to improve the adhesion between the second metal layer and the fourth metal layer. According to the selection of the second and fourth metal layers, the thickness of the sixth metal layer can be 0nm.

[0056] In one embodiment, a first metal layer structure is provided on the chip, and a second metal layer structure is provided on the heat dissipation substrate, further comprising: before sputtering or evaporating the first metal layer on the third metal layer, first sputtering or evaporating the fifth metal layer on the third metal layer, and then sputtering or evaporating the first metal layer on the fifth metal layer; and, before sputtering or evaporating the second metal layer on the fourth metal, first sputtering or evaporating the sixth metal layer on the fourth metal layer, and then sputtering or evaporating the second metal layer on the sixth metal layer.

[0057] In this embodiment, the metal material of the third metal layer, the fourth metal layer, the fifth metal layer or the sixth metal layer includes but is not limited to one of the following: titanium, gold, chromium, nickel, aluminum, molybdenum, tantalum, tungsten, iron, and cobalt.

[0058] In this embodiment, the thickness of the first to sixth metal layers are all in the nanometer level.

[0059] Before step S702 of this embodiment, the method further includes: cleaning the surface of the chip and the heat dissipation substrate.

[0060] In an exemplary embodiment, the surface of the chip and the heat sink substrate are cleaned, including: rinsing the chip and the heat sink substrate surface with deionized water, then cleaning them in a solution of concentrated sulfuric acid: hydrogen peroxide = 4:1, wherein the pickling solution is 150°C for 15 minutes, and finally rinsing with deionized water and drying with N2 gas flow to remove surface contaminants.

[0061] In this embodiment, the chip is a bare chip, which can be made of Si, SiC, GaN, or InP. The first metal layer structure is disposed on the passive surface of the bare chip to prevent the metal layer from affecting the circuit connection of the chip.

[0062] In this embodiment, the heat dissipation substrate is one of bare diamond (including single crystal diamond, polycrystalline diamond, diamond heat sink), silicon-based diamond (including silicon-based single crystal diamond, polysilicon-based crystal diamond and silicon-based diamond heat sink), diamond copper / aluminum metal matrix composite material, Si, SiC, and GaN, among which the thermal conductivity of single crystal diamond, polycrystalline diamond, diamond heat sink and silicon-based diamond is greater than 1000W / (mk), the thermal conductivity of diamond copper and diamond aluminum metal composite material is greater than 300W / (mk), and the thermal conductivity of Si, SiC and GaN is greater than 50W / (mk). The thickness of the above heat dissipation sink materials is in the micron level, the surface roughness is in the nanometer level, and the flatness is in the micron level.

[0063] Compared to bare diamond, silicon-based diamond activates the silicon surface when bonding to a chip. Therefore, silicon-based diamond is more likely to activate the bonding surface, making the bonding surface more hydroxyl groups, improving the quality and strength of the bonding interface. Importantly, to meet the surface roughness required for bonding, silicon-based diamond polishes the silicon surface, significantly reducing the difficulty and cycle time of polishing the bonding surface. The surface processing cycle and cost of silicon-based diamond are only 1 / 2 and 1 / 3 of those of bare diamond, respectively, thus reducing costs.

[0064] Step S704: The first metal layer structure and the second metal layer structure are arranged to be adjacent and stacked, and pressure and temperature are applied to the chip and the heat dissipation substrate to cause an alloying reaction between the first metal layer structure and the second metal layer structure to connect the chip and the heat dissipation substrate.

[0065] In step S704 of this embodiment, the first metal layer structure and the second metal layer structure are arranged adjacent to each other and stacked, and pressure and temperature are applied to the chip and the heat dissipation substrate, including: the first metal layer structure and the second metal layer structure are arranged adjacent to each other and stacked, and a first pressure is applied to the chip and the heat dissipation substrate at a first temperature for a first duration; after the first duration has expired, a second pressure is applied to the stacked chip and heat dissipation substrate at a second temperature for a second duration. The first temperature is lower than the second temperature, the first pressure is lower than the second pressure, and the first duration is lower than the second duration.

[0066] In an exemplary embodiment, the first temperature is not lower than 20°C, the second temperature is not higher than 260°C, and the first temperature is lower than the second temperature; the first pressure is lower than the second pressure, the second pressure does not exceed 50MPa, and the first duration is less than or equal to the second duration. Based on the above parameter settings, the process of heating and pressurizing the chip and the heat dissipation substrate is divided into two stages. For example, in the first stage, the first pressure ranges from 0.1 to 30MPa, the first temperature ranges from 20 to 80°C, and the first duration is 60 to 3600s; in the second stage, the second pressure ranges from 1 to 50MPa, the second temperature ranges from 150 to 260°C, and the second duration is 60 to 3600s. Through the above two stages of heating and pressurizing, a reliable connection between the chip and the heat dissipation substrate can be achieved at a temperature not higher than 260°C and a pressure not exceeding 50MPa. The process conditions are simple and easy to implement.

[0067] Through the above-mentioned method embodiment of the present invention, the chip and the heat dissipation substrate can have both low interface thermal resistance and high bonding strength, and the surface roughness requirements of the chip and the heat dissipation substrate are not high; the bonding between the chip and the heat dissipation substrate can also be completed at a lower temperature while having high bonding reliability.

[0068] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of various embodiments of the present invention.

[0069] To facilitate understanding of the technical solutions provided by the present invention, embodiments of the present invention will be described in detail below with reference to specific scenarios.

[0070] Example 1

[0071] A chip structure is prepared by the following method:

[0072] Step S11, cleaning the chip and the heat dissipation substrate.

[0073] Specifically, the cleaning process is as follows:

[0074] First, rinse with deionized water, then clean in a concentrated sulfuric acid: hydrogen peroxide = 4:1 solution (i.e., pickling solution), where the pickling solution is 150°C and the time is 15 minutes. Finally, rinse with deionized water and blow dry with N2 flow to remove surface pollutants.

[0075] Step S12: sputtering a nano-metal layer, ie, a third metal layer and a fourth metal layer, on the surface of the chip and the heat dissipation substrate respectively. The third metal layer and the fourth metal layer may be 500nm Ti metal layers.

[0076] Step S13: directly sputtering a 360nm Bi first metal layer on the third metal layer of the chip.

[0077] Step S14: directly sputtering a 500nm Sn second metal layer on the fourth metal layer of the heat dissipation substrate.

[0078] The chip structure after setting the metal layer structure is as follows Figure 3 shown.

[0079] Step S15: placing the chip and the heat dissipation substrate in a bonding machine for bonding.

[0080] Specifically, the stacked chip and heat dissipation substrate were maintained at 60° C. for 3600 seconds under a constant pressure of 20 MPa; then the temperature was raised to 150° C., maintained at 150° C. for 3600 seconds, and then cooled.

[0081] Example 2

[0082] A chip structure is prepared by the following method:

[0083] Step S21: Clean the chip and the heat dissipation substrate. The cleaning process is the same as that in Example 1, and will not be described in detail in this embodiment.

[0084] Step S22: sputter a 50nm Al third metal layer on the chip surface, sputter a 50nm Al fourth metal layer on the heat dissipation substrate surface, and then sputter a 50nm Cr sixth metal layer on the fourth metal layer on the heat dissipation substrate surface.

[0085] Step S23 , directly sputtering a 10 nm Cu first metal layer on the third metal layer of the chip.

[0086] Step S24 , directly sputtering a 320 nm In second metal layer on the sixth metal layer of the heat dissipation substrate.

[0087] Step S25: placing the chip and the heat dissipation substrate in a bonding machine for bonding.

[0088] Specifically, a pressure of 30 MPa is applied to the overlapping chips and heat dissipation substrate at 20°C and maintained for 60 seconds; then the temperature is raised to 260°C, and a pressure of 50 MPa is applied to the overlapping heat sink and chip at 260°C and maintained for 60 seconds, and then the temperature is lowered.

[0089] The chip structure after bonding is as follows Figure 8 As shown, after bonding, the first metal layer and the second metal layer undergo an alloying reaction to generate an alloying reaction layer, wherein the alloying reaction layer can be generated by a reaction between a portion of the first metal layer and a portion of the second metal layer.

[0090] Example 3

[0091] A chip structure is prepared by the following method:

[0092] In step S31, the chip and the heat dissipation substrate are first cleaned. The cleaning process is the same as that in embodiment 1, and will not be described in detail in this embodiment.

[0093] Step S32: sputter a 10nm Ti third metal layer on the chip surface, a 10nm Ti fourth metal layer on the heat dissipation substrate surface, and then sputter a 500nm Ni sixth metal layer on the fourth metal layer on the heat dissipation substrate surface.

[0094] Step S33 , continuing to sputter a 50nm Ag first metal layer on the third metal layer of the chip.

[0095] Step S34 , continuing to sputter a 100 nm In second metal layer on the sixth metal layer of the heat dissipation substrate.

[0096] Step S35: placing the chip and the heat dissipation substrate in a bonding machine for bonding.

[0097] Specifically, a pressure of 0.1 MPa is applied to the overlapping chips and heat dissipation substrate at 80°C and maintained for 1800 seconds; then the temperature is raised to 220°C, and a pressure of 10 MPa is applied to the overlapping heat sink and chip at 220°C and maintained for 1800 seconds, and then the temperature is lowered.

[0098] The chip structure obtained according to the above preparation method can be referred to Figure 5 .

[0099] Example 4

[0100] A chip structure is prepared by the following method:

[0101] In step S41, the chip and the heat dissipation substrate are first cleaned. The cleaning process is the same as that in embodiment 1, and will not be described in detail in this embodiment.

[0102] Step S42: sputter a 50nm Ti third metal layer on the chip surface, a 50nm Ti fourth metal layer on the heat dissipation substrate surface, and then sputter a 20nm Ni sixth metal layer on the fourth metal layer on the heat dissipation substrate surface.

[0103] Step S43 , directly sputtering a 70 nm Au first metal layer on the third metal layer of the chip.

[0104] Step S44 , continuing to sputter a 200 nm In second metal layer on the sixth metal layer of the heat dissipation substrate.

[0105] Step S45: placing the chip and the heat dissipation substrate in a bonding machine for bonding.

[0106] Specifically, the stacked chips and heat dissipation substrate are kept at a constant pressure of 1 MPa and 20°C for 60 seconds; then the temperature is raised to 200°C, kept at 200°C for 60 seconds, and then cooled. The chip structure obtained according to the above preparation method can be referred to Figure 5 .

[0107] The chip structure in each of the above embodiments of the present invention can be applied to a semiconductor packaging structure. Figure 9 Schematic diagram of a semiconductor package structure according to an embodiment of the present invention. Figure 9 As shown, the semiconductor packaging structure includes a packaging substrate, a chip, a heat dissipation substrate, a first thermal interface material (TIM1), a heat dissipation cover, a second thermal interface material (TIM2), and a heat sink. The chip is attached to the supporting surface of the packaging substrate with a C4 ball through a bump and an underfill. After the chip and the heat dissipation substrate are connected using the method described in the above embodiment, they are arranged in the semiconductor packaging structure. After the back of the chip and the heat dissipation substrate are connected, they are located between the bump and the TIM1. The TIM1 is arranged on the surface of the heat dissipation substrate, so that the chip after bonding to the heat dissipation substrate is connected to the heat dissipation cover. The heat sink for dissipating the heat generated by the chip is connected to the heat dissipation cover through the TIM2.

[0108] Figure 10 Schematic diagram of a semiconductor package structure according to another embodiment of the present invention. Figure 10 As shown, the semiconductor package structure includes a package substrate, a chip, a heat sink substrate, a thermal interface material (TIM1.5), and a heat sink. The chip is bonded to the supporting surface of the package substrate with a C4 ball via a bump and underfill. After the chip and the heat sink substrate are connected using the method described in the above embodiment, they are placed in the semiconductor package structure. After the back of the chip and the heat sink substrate are connected, they are positioned between the bump and the TIM1.5. The TIM1.5 is placed on the surface of the heat sink substrate, connecting the chip, after bonding to the heat sink substrate, to the heat sink used to dissipate the heat generated by the chip.

[0109] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A chip structure, characterized in that: include: A chip and a heat dissipation substrate for dissipating heat from the chip; a first metal layer structure is provided on the upper surface of the chip, and a second metal layer structure is provided on the lower surface of the heat dissipation substrate, the first metal layer structure and the second metal layer structure are adjacent to and stacked, and the chip and the heat dissipation substrate are connected together through an alloying reaction between the first metal layer structure and the second metal layer structure.

2. The chip structure according to claim 1, characterized in that: The first metal layer structure includes a first metal layer, and the second metal layer structure includes a second metal layer. The first metal layer and the second metal layer are adjacent to each other and are stacked. The first metal layer and the second metal layer form an alloying reaction layer through an alloying reaction, so that the chip and the heat dissipation substrate are connected together; wherein the metal materials between the first metal layer and the second metal layer are different.

3. The chip structure according to claim 1, characterized in that: in, The metal material of the first metal layer includes one of the following: gold, copper, silver, and bismuth, and the metal material of the second metal layer includes one of the following: tin and indium; or, the metal material of the first metal layer includes one of the following: tin and indium, and the metal material of the second metal layer includes one of the following: gold, copper, silver, and bismuth.

4. The chip structure according to claim 1, wherein: in, The first metal layer structure further includes a third metal layer, which is arranged between the chip and the first metal layer to enhance the bonding force between the first metal layer and the chip; the metal material of the third metal layer is different from the metal material of the first metal layer.

5. The chip structure according to claim 4, characterized in that: in, The metal material of the third metal layer includes one of the following: titanium, gold, chromium, nickel, aluminum, molybdenum, tantalum, tungsten, iron, and cobalt.

6. The chip structure according to claim 1, characterized in that: in, The second metal structure also includes a fourth metal layer, which is arranged between the second metal layer and the heat dissipation substrate to enhance the bonding force between the second metal layer and the heat dissipation substrate; the metal material of the second metal layer is different from the metal material of the fourth metal layer.

7. The chip structure according to claim 6, characterized in that: in, The metal material of the fourth metal layer includes one of the following: titanium, gold, chromium, nickel, aluminum, molybdenum, tantalum, tungsten, iron, and cobalt.

8. The chip structure according to claim 4, characterized in that: The first metal layer structure further includes a fifth metal layer, wherein the fifth metal layer is disposed between the first metal layer and the third metal layer to enhance adhesion between the first metal layer and the third metal layer.

9. The chip structure according to claim 8, characterized in that: in, The metal material of the fifth metal layer is different from the metal materials of the first metal layer and the third metal layer; the metal material of the fifth metal layer is one of the following: titanium, gold, chromium, nickel, aluminum, molybdenum, tantalum, tungsten, iron, and cobalt.

10. The chip structure according to claim 6, characterized in that: The second metal layer structure includes a sixth metal layer, wherein the sixth metal layer is disposed between the second metal layer and the fourth metal layer to enhance adhesion between the second metal layer and the fourth metal layer.

11. The chip structure according to claim 10, characterized in that: in, The metal material of the sixth metal layer is different from the metal materials of the second metal layer and the fourth metal layer; the metal material of the sixth metal layer is one of the following: titanium, gold, chromium, nickel, aluminum, molybdenum, tantalum, tungsten, iron, and cobalt.

12. The chip structure according to claim 1, wherein: in, The first metal layer structure or the second metal layer structure includes one or more metal layers, and the thickness of any one of the one or more metal layers is nanometer level.

13. The chip structure according to claim 1, wherein: in, The heat dissipation substrate includes one of the following: silicon-based diamond, bare diamond, diamond-copper metal-based composite material, diamond-aluminum metal-based composite material, silicon, silicon carbide, and gallium nitride.

14. The chip structure according to claim 13, characterized in that: in, The silicon-based diamond includes one of the following: silicon-based single crystal diamond, silicon-based multi-crystal diamond and silicon-based diamond heat sink.

15. The chip structure according to claim 13, characterized in that: in, The bare diamond includes one of the following: single crystal diamond, polycrystalline diamond, and diamond heat sink.

16. A method for connecting a chip to a heat dissipation substrate, characterized in that: include: Disposing a first metal layer structure on the upper surface of the chip and a second metal layer structure on the lower surface of the heat dissipation substrate; The first metal layer structure and the second metal layer structure are arranged adjacent to and stacked, and pressure and temperature are applied to the chip and the heat dissipation substrate to cause an alloying reaction between the first metal layer structure and the second metal layer structure to connect the chip and the heat dissipation substrate.

17. The method according to claim 16, characterized in that: The method comprises: arranging the first metal layer structure and the second metal layer structure to be adjacent to each other and stacking them, and applying pressure and temperature to the chip and the heat dissipation substrate, comprising: Disposing the first metal layer structure and the second metal layer structure adjacent to each other and stacking them, and applying a first pressure of a first duration to the chip and the heat dissipation substrate at a first temperature; When the first period of time has ended, a second pressure is applied to the chip and the heat dissipation substrate at a second temperature for a second period of time.

18. The method according to claim 17, characterized in that in, The first temperature is lower than the second temperature, the first pressure is lower than the second pressure, and the first duration is lower than the second duration.

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