Method for realizing time-shifting critical conduction mode control in digital power supply

Abstract

The invention relates to a method for realizing time-shifted critical conduction mode control in a digital power supply. A method of operating a DC-DC converter includes generating a high-side control signal for a high-side transistor and generating a low-side control signal for a low-side transistor, thereby causing conversion of an input voltage to an output voltage. A time shift is measured between a falling edge of the low-side control signal and a time when a drain-to-source voltage of the low-side transistor becomes higher than a set threshold voltage. The time shift error is determined as a difference between a dead time and the measured time shift, the dead time being a time between a falling edge of the low-side control signal and a rising edge of the high-side control signal. The frequencies of the high-side control signal and the low-side control signal are adjusted based on the time shift error to maintain the DC-DC converter operating in the critical conduction mode.

Description

Technical Field

[0001] The present disclosure relates to the field of switched mode power supplies (SMPS), and more particularly, to control techniques (and associated circuitry) for critical conduction mode (CRM) operation of an SMPS. Background Art

[0002] Switched-mode power supplies (SMPS) are frequently used components in modern electronic systems, providing efficient power conversion and regulation. One operating mode of interest in these systems is critical conduction mode (CRM), which is increasingly preferred in various applications due to its ability to minimize inductor size, increase efficiency, and improve electromagnetic compatibility (EMC) performance. Given these advantages, CRM is widely used in the market, particularly in low-power applications such as AC / DC adapters.

[0003] Traditionally, CRM operation in SMPSs involves precise detection of the inductor current zero crossing point, achieved through a zero current detection (ZCD) circuit, or precise detection of the valley point in the drain-source voltage (VDS) of the power MOS transistor, achieved through a drain-source voltage sensing circuit. Based on the detection of the inductor current zero crossing or the valley point of the VDS of the power MOS transistor, the rising edge of the pulse width modulation (PWM) signal can be synchronized so that the resulting turn-on instant of the power MOS transistor coincides with the inductor current reaching zero.

[0004] However, these conventional approaches have several limitations. One drawback is the need for additional components, such as a ZCD circuit or an auxiliary winding for sensing the VDS of the power MOS. This requirement not only increases complexity but also increases the physical footprint of the power supply design.

[0005] Adding further complexity to practical applications is that it is often desirable to have a mix of continuous conduction mode (CCM), CRM, and discontinuous conduction mode (DCM) to optimize inductor size and achieve high efficiency under varying load conditions. However, existing implementations do not easily allow for dynamic switching between CCM, CRM, and DCM modes. This inflexibility can be a disadvantage in dynamic applications, where load conditions change rapidly and fast mode transitions are required for optimal performance.

[0006] In view of this, there is a need to further develop control techniques (and related circuits) for CRM operation and control techniques (and related circuits) for dynamic switching between CCM, CRM and DCM modes. Summary of the Invention

[0007] Disclosed herein is a method for operating a DC-DC converter, comprising: generating a high-side control signal for a high-side transistor of the DC-DC converter, and generating a low-side control signal for a low-side transistor of the DC-DC converter, thereby causing conversion of an input voltage to an output voltage; measuring a time shift between a falling edge of the low-side control signal and a time when a drain-to-source voltage of the low-side transistor becomes higher than a set threshold voltage; determining a time shift error as a difference between a dead time and the measured time shift, the dead time being the time between a falling edge of the low-side control signal and a rising edge of the high-side control signal; and adjusting the frequencies of the high-side control signal and the low-side control signal based on the time shift error to maintain the DC-DC converter operating in a critical conduction mode.

[0008] When the measured time shift is greater than the dead time, the frequencies of the high-side control signal and the low-side control signal may be adjusted based on the time shift error by reducing the frequencies of the high-side control signal and the low-side control signal.

[0009] The method may further include maintaining the DC-DC converter operating in the critical conduction mode or switching operation of the DC-DC converter to the critical conduction mode based on the measured time shift being greater than the dead time.

[0010] When the measured time shift is less than the dead time, the frequencies of the high-side control signal and the low-side control signal may be adjusted based on the time shift error by increasing the frequencies of the high-side control signal and the low-side control signal.

[0011] Based on the measured time shift being less than the dead time, the DC-DC converter may be maintained to operate in the critical conduction mode.

[0012] The set threshold voltage can be varied, thereby changing the level of negativity of the inductor current that occurs during the dead time.

[0013] The set threshold voltage can be increased, thereby increasing the level of negativity of the inductor current that occurs during the dead time.

[0014] The set threshold voltage can be lowered, thereby reducing the level of negativity of the inductor current occurring during the dead time.

[0015] The present invention also discloses a power converter, comprising: a DC-DC converter, comprising a high-side transistor and a low-side transistor, the DC-DC converter being operable to convert an input voltage into an output voltage; a pulse width modulation (PWM) circuit device, configured to generate a high-side control signal for the high-side transistor and a low-side control signal for the low-side transistor, thereby causing conversion of the input voltage into the output voltage; a comparator, configured to assert its output in response to a drain-to-source voltage of the low-side transistor being greater than a set threshold voltage; a time-shift capture circuit device, configured to measure the time between a falling edge of the low-side control signal and a time when the comparator is asserted. shift; a time-shift control circuit device configured to determine a time-shift error as a difference between a dead time and a measured time shift, the dead time being the time between a falling edge of the low-side control signal and a rising edge of the high-side control signal; a frequency adjustment circuit device configured to generate an output signal indicating the frequencies of the high-side control signal and the low-side control signal based on the time-shift error, the output signal maintaining the DC-DC converter to operate in a critical conduction mode; and a strategy circuit device configured to generate a PWM control signal for the PWM circuit device based on the output signal from the frequency adjustment circuit device; wherein the PWM circuit device operates based on the PWM control signal.

[0016] The coupling clamp circuit may clamp a drain-to-source voltage of the low-side transistor and provide the clamped drain-to-source voltage to the comparator.

[0017] The digital-to-analog converter can generate the set threshold voltage.

[0018] When the measured time shift is greater than the dead time, the frequency adjustment circuit arrangement may adjust the frequencies of the high-side control signal and the low-side control signal by reducing the frequencies of the high-side control signal and the low-side control signal based on the time shift error.

[0019] The strategy circuit arrangement may be further configured to maintain the DC-DC converter operating in the critical conduction mode or switch operation of the DC-DC converter to the critical conduction mode based on the measured time shift being greater than the dead time.

[0020] When the measured time shift is less than the dead time, the frequency adjustment circuitry may adjust the frequencies of the high-side control signal and the low-side control signal by increasing the frequencies of the high-side control signal and the low-side control signal based on the time shift error.

[0021] The strategy circuit arrangement may be further configured to maintain the DC-DC converter operating in the critical conduction mode based on the measured time shift being less than the dead time. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic block diagram of a switch mode power supply (SMPS) disclosed herein.

[0023] Figure 2 It shows Figure 1 Figure 2 shows a graph of the PWM signal, inductor current, and drain-to-source voltage of the low-side transistor of the SMPS DC-DC converter.

[0024] Figure 3 It shows Figure 1 The DC-DC converter Figure 1 Flowchart of the operation of the control circuit device. DETAILED DESCRIPTION

[0025] The following disclosure enables one skilled in the art to make and use the subject matter described herein. The general principles outlined in this disclosure may be applied to embodiments and applications beyond those described above without departing from the spirit and scope of the disclosure. It is not intended that the disclosure be limited to the embodiments shown, but rather that it be accorded the widest scope consistent with the principles and features disclosed or suggested herein.

[0026] Note that in the following description, any resistor or resistance mentioned is a discrete device, unless otherwise specified, and is not simply an electrical lead between two points. Therefore, any resistor or resistance connected between two points has a higher resistance than the lead between the two points, and such a resistor or resistance cannot be interpreted as a lead. Similarly, any capacitor or capacitance mentioned is a discrete device, unless otherwise specified, and is not a parasitic element, unless otherwise specified. In addition, any inductor or inductance mentioned is a discrete device, unless otherwise specified, and is not a parasitic element, unless otherwise specified.

[0027] refer to Figure 1 Disclosed herein is a switched-mode power supply (SMPS) 10 comprising a DC-DC converter 11 and associated control circuitry 12. The DC-DC converter 11 is arranged as a synchronous buck converter and includes: a high-side n-channel metal oxide semiconductor (MOS) field effect transistor MN1, whose drain is coupled to an input DC voltage VIN, whose source is connected to a switch node at a first terminal of an inductor L, and whose gate is coupled to receive a high-side control signal PWM_HS from a PWM generator 27 within the control circuitry 12; a low-side n-channel MOS transistor MN2, whose drain is connected to the switch node at the first terminal of the inductor L, whose source is coupled to ground, and whose gate is coupled to receive a low-side control signal PWM_LS from the PWM generator 27; an output capacitor COUT connected between an output node at a second terminal of the inductor L and ground; and a load (represented by a load resistor) RL also connected between the output node at the second terminal of the inductor and ground. An output voltage VOUT is generated across the output capacitor COUT.

[0028] Generally speaking, and as will be described in detail below, control circuitry 12 monitors the drain-to-source voltage of low-side n-channel transistor MN2 and uses this information when adjusting the dead time between the end of low-side conduction and the beginning of the high-side conduction period.

[0029] Continuing, the control circuitry 12 includes a drain-to-source voltage clamp 15 connected between a switching node at the first terminal of the inductor L and a non-inverting input terminal of the comparator 22. The voltage clamp 15 includes an n-channel MOS transistor MN3, whose drain is connected to the switching node at the first terminal of the inductor L (i.e., at the drain of the transistor MN2), whose source is coupled to the non-inverting input terminal of the comparator 22 through a resistor R, and whose gate is coupled to (i.e., biased at) a turn-on voltage (e.g., 3.3 V).

[0030] A digital-to-analog converter (DAC) 21 generates a reference voltage VREF1 from a digital reference DREF (which is a digital signal representing VREF1) and provides the reference voltage VREF to the inverting input terminal of a comparator 22. Comparator 22 provides its output as an input to drain-to-source edge time-shift capture circuitry 23. Drain-to-source (VDS) edge time-shift capture circuitry 23 provides its output to time-shift control circuitry 24, which in turn provides its output to frequency adjustment circuitry 25 and PWM generator 27. Frequency adjustment circuitry 25 provides its output to the strategy circuitry. Analog-to-digital converter (ADC) 16 receives as inputs the output voltage VOUT at the output node and a voltage representing the output current IOUT, and provides its output to the input of a PID controller 17. PID controller 17 receives as input an additional reference voltage VREF2 and provides its output to the strategy circuitry 26. The strategy circuitry 26 provides an output to the PWM generator 27 which, as described, generates a high-side control signal PWM_HS and a low-side control signal PWM_LS depending on the operating mode (CCM, CRM, DCM).

[0031] In operation, the DC-DC converter 11 effectively steps down a higher DC input voltage VIN to a lower DC output voltage VOUT by alternately switching on and off the high-side transistor MN1 and the low-side transistor MN2, controlled by high-side and low-side pulse-width modulated (PWM) signals PWM_HS and PWM_LS. When high-side transistor MN1 is activated by the assertion of PWM_HS during the high-side on-phase, current flows from the input voltage VIN through inductor L to the output, storing energy in the inductor's magnetic field. During the low-side on-phase, when transistor MN1 is off and transistor MN2 is on, inductor L releases its stored energy to the load RL and the output capacitor COUT. This energy released from inductor L not only provides power to the load RL but also smooths voltage ripple, thereby providing a stable output voltage VOUT. Dead time occurs between the falling edge of PWM_LS and the rising edge of PWM_HS, and between the falling edge of PWM_HS and the rising edge of PWM_LS, during which neither PWM_HS nor PWM_LS is asserted, to prevent shoot-through.

[0032] Control circuitry 12 can operate DC-DC converter 11 in continuous conduction mode (CCM), discontinuous conduction mode (DCM), or critical conduction mode (CRM) by appropriately adjusting the pulse widths of PWM signals PWM_HS and PWM_LS and the dead time between them, depending on load conditions. CCM is typically used under high load conditions, and when operating in CCM, the turn-on timing of high-side transistor MN1 and low-side transistor MN2, as well as the dead time between turning off low-side transistor MN2 and turning on high-side transistor MN1, is adjusted so that the inductor current does not drop to zero. DCM is typically used under lighter load conditions, and when operating in DCM, the turn-on timing of high-side transistor MN1 and low-side transistor MN2, as well as the dead time between turning off low-side transistor MN2 and turning on high-side transistor MN1, is adjusted so that the inductor current drops to zero and remains there during a portion of the cycle. The CRM is used at the boundary between CCM and DCM, and when operating in the CRM, the turn-on timing of the high-side transistor MN1 and the low-side transistor MN2, as well as the dead time between the turn-off of the low-side transistor MN2 and the turn-on of the high-side transistor MN1, are adjusted so that the inductor current is allowed to become negative for a period of time. As described above, operation in the CRM is desirable for reasons of efficiency and inductor size. Details will be provided below.

[0033] It is noted that the purpose of the control circuitry 12 may be to operate the DC-DC converter in a CRM wherever the load conditions make this possible. Figure 2Graph 1 shows the inductor current, the low-side control signal PWM_LS, the high-side control signal PWM_HS, and the drain-source voltage of the low-side transistor MN2. As can be seen, when the low-side control signal PWM_LS is asserted, the inductor current begins to decrease, wherein the low-side control signal PWM_LS transitions to low after the inductor current crosses zero.

[0034] When PWM_LS is asserted, turning on low-side transistor MN2, its drain-to-source voltage, VDS, approaches zero due to the low on-resistance of the MOSFET in a saturated state. Immediately following the falling edge of PWM_LS, when the inductor current goes negative, VDS remains near zero, reflecting the reversal of current through the body diode of low-side transistor MN2 and indicating that energy is being recycled in the loop formed by inductor L and low-side transistor MN2. As inductor L reacts to the abrupt interruption of current flow at the falling edge of PWM_LS by releasing energy in an attempt to maintain current flow, a rise in VDS occurs due to inductive kickback at the node between inductor L and the drain of low-side transistor MN2. Note that the combination of the inductor current falling to a negative value and the relatively slow upward slew rate of VDS indicates operation in CRM. Conversely, if the inductor current does not fall to zero and the upward slew rate of VDS is relatively fast (e.g., higher than the slew rate in CRM), this would indicate operation in CCM.

[0035] After VDS starts to rise, and Figure 2 In the example shown, after comparator 22 is triggered, PWM_HS is asserted, turning on high-side transistor MN1 and connecting input voltage VIN to the drain of low-side transistor MN2. As a result, VDS rises sharply because the drain of MN2 is essentially at VIN and the source of MN2 is at ground level, and the inductor current begins to rise.

[0036] The rising slope of VDS is detected by the comparator 22. When VDS rises to become at least equal to the reference voltage VREF1 ( Figure 2When the VDS edge-shift capture circuit 23 is reset and begins counting at the falling edge of PWM_LS (shown as the VSW edge detection reference in FIG), the output of comparator 22 is asserted (e.g., comparator 22 triggers), and the time between the start of the PWM counter (which is reset and begins counting at the falling edge of PWM_LS) and the assertion of the output of comparator 22 is captured by VDS edge-shift capture circuit 23 and is hereinafter referred to as the sensed or measured time shift. The VDS edge-shift capture circuit 23 is a high-resolution timer capture unit that is reset at the falling edge of PWM_LS and is triggered (stopped) when the output of comparator 22 is asserted. Therefore, the output of the VDS edge-shift capture circuit 23 is the timer value at the time of the triggering of comparator 22. Therefore, the output of the VDS edge-shift capture circuit 23 is a digital value representing the sensed time shift.

[0037] The time shift control circuitry 24 calculates what may be referred to as the time shift error as the difference between the reference time shift (the time period between the falling edge of PWM_LS and the rising edge of PWM_HS) and the sensed time shift. This can be expressed mathematically as:

[0038] ΔTime shift=Reference_Time_Shift-Sensed_Time_Shift

[0039] The time-shift control circuitry 24 filters the time-shift error to reduce the effects of noise and / or parasitic resonance.

[0040] The ADC 16 digitizes the output voltage VOUT or the output current IOUT, and the PID controller 17 compares the output voltage VOUT or the output current IOUT with a second reference voltage VREF2 to generate a duty cycle signal representing the duty cycle of the DC-DC converter 11. The duty cycle signal represents the duty cycle as a percentage (e.g., 0V to 0.99V).

[0041] The purpose of the time-shift control circuit device 24 is to generate a control signal to the frequency adjustment circuit device 25 so that the frequency adjustment circuit device 25 generates a frequency signal representing the PWM frequency of the next switching cycle. When input to the strategy circuit device 26, the frequency signal causes the strategy circuit device 26 to generate a control signal to the PWM generator 27 so that the PWM generator 27 adjusts the frequencies of the PWM signals PWM_HS and PWM_LS accordingly.

[0042] More specifically, when the delta time shift exceeds a set threshold, time shift control circuitry 24 generates a control signal that, when input to strategy circuitry 26, ultimately causes PWM generator 27 to reduce the frequency of the PWM signal. Strategy circuitry 26 maintains or shifts the operation of DC-DC converter 11 to the CRM, depending on the load condition. This operation continues through successive iterations until the frequency of the PWM signal is reduced such that the delta time shift equals the threshold.

[0043] When the delta time shift is less than a set threshold, time-shift control circuitry 24 generates a control signal that, when input to strategy circuitry 26, ultimately causes PWM generator 27 to increase the frequency of the PWM signal. Strategy circuitry 26 maintains DC-DC converter 11 operating in the CRM. This operation continues through successive iterations until the frequency of the PWM signal increases such that the delta time shift equals the threshold.

[0044] Recall that the duty cycle signal output by the PID controller 17 expresses the duty cycle as a percentage (e.g., 0V to 0.99V). A new duty cycle time count can be calculated by the PWM generator 27 from this as the product of the duty cycle signal and the newly calculated period (calculated based on the control signal output by the strategy circuitry 26, remembering that the period is 1 divided by the newly calculated frequency). Mathematically, this can be expressed as:

[0045] Duty cycle time count = period × duty cycle C

[0046] Where period = 1 / frequency

[0047] The transistor on time (Ton) can be calculated as the new duty cycle time count, and the transistor off time (Toff) can be calculated as the difference between the newly calculated period and Ton. Mathematically, this can be expressed as:

[0048] Ton = duty cycle time count

[0049] Toff=cycle×Ton

[0050] Note that by changing the value of the digital reference signal DREF, the output VREF1 of the DAC 21 can be changed, which results in a change in the trigger point of the controller 22. As a result, the sensed time shift changes, and thus the calculation of the sensed time shift error (e.g., Δ time shift) changes. In this way, the negative current flowing in the inductor during the dead time between low-side conduction and high-side conduction can be changed.

[0051] To change from CRM to CCM or DCM, strategy circuitry 26 may change the control signals to PWM circuitry 27 to further appropriately change the transistor on-time Ton and off-time Toff periods (eg, change the timing and duration of PWM signals PWM_HS and PWM_HS).

[0052] More details of the operation of the strategy circuit device 26 will now be provided. In particular, in CCM, the switching period is fixed regardless of the sensed time shift, so time shift control is not enabled. If the load or inductor current is less than a given threshold, the strategy circuit device 26 reduces the frequency and the inductor current slew rate will increase. If the frequency is reduced sufficiently so that the inductor current falls negative between the falling edge of PWM_LS and the rising edge of PWM_HS, CRM mode is enabled. If the load demand increases so that the average inductor current becomes greater than the threshold, the strategy circuit device 26 will increase the switching frequency, which may result in a switch to CCM mode. If the load demand is low enough (e.g., too low for CRM mode), the strategy circuit device 26 will clamp the frequency to a minimum frequency, time shift control will be disabled, and the operating mode will switch to DCM.

[0053] Figure 3 A flow chart 30 is shown of the combined operation of the control circuit arrangement 21. Here, output voltage VOUT or output current IOUT sensing is performed using PID control (box 31), and then the duty cycle of the PWM signal is output (box 32). The duty cycle is fed to the strategy circuit arrangement (box 51). In parallel with this, the edge of the drain-to-source voltage of the low-side transistor MN2 is detected at box 41 (e.g., detecting the triggering of the comparator 22, or in other words, detecting the point at which VDS becomes at least equal to the reference voltage VREF1), the time shift between the falling edge of PWM_LS and the edge of VDS is measured at box 42, and the time shift error between the reference time shift (the time between the falling edge of PWM_LS and the rising edge of PWM_HS) and the sensed time shift (sense at box 42) is calculated at box 43.

[0054] Then, at block 51, an adjustment to be applied to the frequency of the PWM signal is determined based on the duty cycle and the calculated time shift error. More specifically, if the phase shift error is zero (block 51b), operation continues without adjustment (block 52), and the on- and off-periods, Ton, Toff, are not changed (block 53). If the phase shift error indicates that the sensed phase shift is greater than the reference phase shift (block 51a), the frequency of the PWM signal is decreased by one step (block 51b), and the strategy circuit device maintains operation in the CRM or switches from CCM to CRM (block 52), and changes the on- and off-periods, Ton, Toff, accordingly (block 53). If the phase shift error indicates that the sensed phase shift is less than the reference phase shift (block 51c), the frequency of the PWM signal is increased by one step (block 51d), and the strategy circuit device maintains operation in the CRM (block 52), and changes the on- and off-periods, Ton, Toff, accordingly (block 53).

[0055] Advantages of control circuitry 12 include eliminating the need for zero-crossing detection and valley detection (the point at which the inductor current changes from more negative to more negative, or in other words, the point at which the slope of the inductor current changes from negative to positive). As described above, detection of a VDS edge is simple because it is a large signal and is insensitive to noise or parasitic inductance in the sensing loop. Furthermore, given that maintenance in CRM mode is facilitated by control circuitry 12, dynamic switching between CCM, CRM, and DCM becomes possible.

[0056] By maintaining operation in CRM mode, a smaller inductor can be utilized, making the power supply 10 suitable for smaller applications, such as wireless power transfer to devices such as cordless cleaning robots.

[0057] Obviously, modifications and variations may be made to what is described and illustrated herein without departing from the scope of the present disclosure. For example, although the DC-DC converter 11 is illustrated above as a synchronous buck converter, the same control techniques may be applied to any suitable DC-DC converter, and thus control of all such DC-DC converters according to the techniques described above is within the scope of the present disclosure.

[0058] Finally, it should be understood that the PID controller 16, time-shift control circuitry 24, frequency adjustment circuitry 25, and strategy circuitry 26 may be implemented in firmware executed by a microprocessor or other suitable programmable processing circuitry.

[0059] Although the present disclosure has been described with a limited number of embodiments, those skilled in the art having benefit of this disclosure may devise other embodiments that do not depart from the scope of the disclosure. Furthermore, those skilled in the art may devise embodiments that represent various combinations of the embodiments disclosed herein made in various ways.

Claims

1. A method of operating a DC-DC converter, comprising: generating a high-side control signal for a high-side transistor of the DC-DC converter and generating a low-side control signal for a low-side transistor of the DC-DC converter, thereby causing conversion of an input voltage to an output voltage; measuring a time shift between a falling edge of the low-side control signal and a time at which a drain-to-source voltage of the low-side transistor becomes higher than a set threshold voltage; determining a time shift error as a difference between a dead time and the measured time shift, the dead time being the time between a falling edge of the low-side control signal and a rising edge of the high-side control signal; as well as The frequencies of the high-side control signal and the low-side control signal are adjusted based on the time-shift error to maintain the DC-DC converter operating in a critical conduction mode.

2. The method of claim 1 , wherein adjusting the frequencies of the high-side control signal and the low-side control signal based on the time shift error is performed by: When the measured time shift is greater than a dead time, the frequencies of the high-side control signal and the low-side control signal are reduced. 3 . The method of claim 2 , further comprising maintaining the DC-DC converter operating in the critical conduction mode or switching the operation of the DC-DC converter to the critical conduction mode based on the measured time shift being greater than the dead time.

4. The method of claim 2 , wherein adjusting the frequencies of the high-side control signal and the low-side control signal based on the time shift error is performed by: When the measured time shift is less than the dead time, the frequencies of the high-side control signal and the low-side control signal are increased. 5 . The method of claim 4 , further comprising maintaining the DC-DC converter operating in the critical conduction mode based on the measured time shift being less than the dead time. 6 . The method of claim 1 , further comprising changing the set threshold voltage to thereby change a level of negativity of the inductor current occurring during the dead time. 7 . The method of claim 1 , further comprising increasing the set threshold voltage to increase a level of negativity of the inductor current occurring during the dead time. 8 . The method of claim 1 , further comprising lowering the set threshold voltage to reduce a level of negativity of the inductor current occurring during the dead time.

9. A power converter comprising: A DC-DC converter comprising a high-side transistor and a low-side transistor, the DC-DC converter being operable to convert an input voltage into an output voltage; a pulse width modulation (PWM) circuit arrangement configured to generate a high-side control signal for the high-side transistor and a low-side control signal for the low-side transistor, thereby causing conversion of the input voltage to the output voltage; a comparator configured to assert its output in response to a drain-to-source voltage of the low-side transistor being greater than a set threshold voltage; a time-shift capture circuit arrangement configured to measure a time shift between a falling edge of the low-side control signal and a time when the comparator is asserted; a time-shift control circuit arrangement configured to determine a time-shift error as a difference between a dead time and the measured time shift, the dead time being a time between the falling edge of the low-side control signal and a rising edge of the high-side control signal; a frequency adjustment circuit device configured to generate an output signal indicating the frequency of the high-side control signal and the low-side control signal based on the time shift error, the output signal maintaining the DC-DC converter operating in a critical conduction mode; as well as strategy circuitry configured to generate a PWM control signal for the PWM circuitry based on the output signal from the frequency adjustment circuitry; wherein the PWM circuit device operates based on the PWM control signal. 10 . The power converter of claim 9 , further comprising a coupling clamp circuit configured to clamp a drain-to-source voltage of the low-side transistor and provide the clamped drain-to-source voltage to the comparator. 11 . The power converter of claim 10 , further comprising a digital-to-analog converter configured to generate the set threshold voltage.

12. The power converter according to claim 9, wherein When the measured time shift is greater than the dead time, the frequency adjustment circuitry adjusts the frequencies of the high-side control signal and the low-side control signal by reducing the frequencies of the high-side control signal and the low-side control signal based on the time shift error.

13. The power converter of claim 12, wherein the strategy circuit device is further configured to maintain the DC-DC converter operating in the critical conduction mode or switch the operation of the DC-DC converter to the critical conduction mode based on the measured time shift being greater than the dead time.

14. The power converter of claim 12 , wherein the frequency adjustment circuitry adjusts the frequencies of the high-side control signal and the low-side control signal by increasing the frequencies of the high-side control signal and the low-side control signal based on the time shift error when the measured time shift is less than the dead time. 15 . The power converter of claim 14 , wherein the strategy circuitry is further configured to maintain the DC-DC converter operating in the critical conduction mode based on the measured time shift being less than the dead time.

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