Improved bias circuit adopting mutual bias

Abstract

An improved bias circuit adopting mutual bias comprises a first P tube, a second P tube and a third P tube, source electrodes and substrates of the first P tube, the second P tube and the third P tube are all connected with a power supply, a grid electrode and a drain electrode of the second P tube are connected, a drain electrode of the third P tube is connected with a grid electrode of a second N tube, and a drain electrode of the first P tube is connected with a drain electrode of a first N tube; the grid electrode of the first N tube is connected with the drain electrode of the second N tube, the source electrode of the second N tube is connected with the ground, and the first resistor is connected between the grid electrode of the second N tube and the source electrode of the first N tube; one end of the second resistor is connected with the source electrode of the first N tube, and the other end is grounded. On the basis of a traditional mutually-biased VTH biasing circuit, an improved structure is used, the matching precision of branch currents is improved, and meanwhile the area of the circuit is greatly reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog circuits, relates to a bias circuit, and in particular to a mutual bias current bias circuit. Background Art

[0002] The bias circuit is an indispensable basic module in analog integrated circuits (Analog ICs). Its core function is to provide a quiescent operating point (Quiescent Point) for active devices (such as MOS tubes, BJTs, CMOS, etc.) to ensure that the devices operate stably under the predetermined state. In a narrow sense, the bias circuit enables the device to leave the cutoff region and enter the amplification or conduction state by providing a turn-on voltage or current threshold. In a broad sense, it builds the DC working framework of the circuit system and provides current and voltage references for the entire analog system (such as amplifiers, oscillators, regulators, etc.). Its stability directly affects the global performance of the circuit, such as gain, linearity, and power consumption. The existing technology generally adopts the following solutions:

[0003] Figure 2 A conventional V TH Bias circuit, Figure 2 The sources of the first and second P transistors are connected to the power supply, and their gates are connected to form a current mirror. The drain of the second P transistor is connected to the gate. When the width-to-length ratio of the first P transistor is equal to the width-to-length ratio of the second P transistor, the output current is the same as the reference current. The gate of the first N transistor is connected to the drain of the second N transistor, and the gate of the second N transistor is connected to the first resistor. The first N transistor, the second N transistor, and the first resistor jointly determine the magnitude of the current. Where K = μ n C ox W / L,μ n is the electron mobility, C ox is the oxide layer capacitance, and W / L is the width-to-length ratio of the corresponding MOS tube. The current formula is as follows:

[0004]

[0005] Consider I o =I in , the threshold voltage of the NMOS tube is the same, and the current expression can be solved as follows:

[0006]

[0007] Theoretically, the expression of the output current is independent of the power supply voltage. However, there is a mismatch between the currents of the two mutually biased branches, which is mainly due to the V DS The voltages are not strictly equal, and this mismatch is also affected by power supply noise. Summary of the Invention

[0008] In response to the above-mentioned defects in the prior art, the present invention discloses an improved mutual bias current bias circuit, comprising a first P-type transistor, a second P-type transistor, and a third P-type transistor, wherein the source and substrate of the first P-type transistor, the second P-type transistor, and the third P-type transistor are all connected to a power supply, the gate and drain of the second P-type transistor are connected, the drain of the third P-type transistor is connected to the gate of the second N-type transistor, and the drain of the first P-type transistor is connected to the drain of the first N-type transistor; the gate of the first N-type transistor is connected to the drain of the second N-type transistor, the source of the second N-type transistor is connected to ground, a first resistor is connected between the gate of the second N-type transistor and the source of the first N-type transistor; and one end of the second resistor is connected to the source of the first N-type transistor and the other end is connected to ground.

[0009] Optionally, the first P-tube and the second P-tube have the same specifications.

[0010] Optionally, the width-to-length ratio of the third P tube is an integer multiple of the width-to-length ratio of the first P tube.

[0011] The present invention is based on the traditional mutual bias V TH On the basis of the bias circuit, an improved structure is used to improve the matching accuracy of the branch current and greatly reduce the circuit area. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 FIG2 is a schematic diagram showing a specific implementation of the mutual bias current bias circuit of the present invention;

[0013] Figure 2 FIG. 1 is a schematic diagram of a specific implementation of an existing mutual bias current;

[0014] Figure 3 The figure shows a comparison of the resistor layout areas of the traditional and improved mutual bias circuits;

[0015] Figure 4 The figure shows the comparison of the replication accuracy of the traditional and improved mutual bias circuits; DETAILED DESCRIPTION

[0016] In order to more intuitively and clearly describe the specific details of the technical solution of the present invention, a detailed description will be given below in conjunction with specific embodiments and example drawings.

[0017] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely explained below in conjunction with the specific embodiments of the present invention and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0018] like Figure 1As shown, the mutual bias current bias circuit of the present invention is characterized in that the source and substrate of the first P-transistor, the second P-transistor, and the third P-transistor are all connected to a power supply, the gate and drain of the second P-transistor are connected, the drain of the third P-transistor is connected to the gate of the second N-transistor, and the drain of the first P-transistor is connected to the drain of the first N-transistor; the gate of the first N-transistor is connected to the drain of the second N-transistor, the source of the second N-transistor is connected to ground, a first resistor is connected between the gate of the second N-transistor and the source of the first N-transistor; one end of the second resistor is connected to the source of the first N-transistor, and the other end is connected to ground.

[0019] In this embodiment, the width-to-length ratio of the first P transistor is equal to that of the second P transistor, and the width-to-length ratio of the third P transistor is twice that of the first P transistor. In this embodiment, the current flowing through the first P transistor is I1, the current flowing through the second P transistor is I2, and the current flowing through the third P transistor is I3.

[0020] Under normal operating conditions, the first, second, and third P transistors form a current mirror. The width-to-length ratios of the first and second P transistors are equal, and the width-to-length ratio of the third P transistor is twice that of the first. This makes the currents I1 and I2 equal, and the current I3 twice that of I1. The current flowing through the first resistor is I3, and the current flowing through the second resistor is the sum of I3 and I1. The gate voltage of the second N transistor can be expressed as follows:

[0021] V GM2 =(I1+I3)R2+I3R1

[0022] =3I1R2+2I1R1

[0023] At the same time, the expression of I2 current can be obtained from the saturation current formula as follows, where K2 = μ n C ox W / L,μ n is the electron mobility, C ox is the oxide layer capacitance, and W / L is the width-to-length ratio of the corresponding second N-type transistor:

[0024]

[0025] Compared with the traditional mutual bias V TH Bias circuit current expression It can be concluded that when the same output current is obtained, that is, (3R2+2R1)=R1', the resistance values ​​of the resistors required by this embodiment (R2 and R1) are much smaller than the resistance value R1' required by the traditional mutual bias structure. Considering that passive devices occupy more area in the integrated circuit than active devices, this greatly saves chip area.

[0026] In a specific embodiment, using the SIMC_13mmrf_1P6M_30k process library, when the currents of I1 and I2 are 6μA and the current of I3 is 12μA, and polysilicon resistors (rhrpo) are used, the area comparison of the resistors required by the improved bias circuit (R2 = 18.722KΩ and R1 = 56.166KΩ) and the resistor R1' (168.498KΩ) of the traditional mutual bias structure is shown. Figure 3 As shown. Figure 3 In the specific embodiment of the improved structure, the total area of ​​R2 and R1 is 304 μm 2 The area of ​​the traditional structure resistor R1' is 684μm 2 In this embodiment, the reduced resistor area is approximately 56% of the resistor area of ​​the traditional structure, which greatly reduces the chip area.

[0027] Considering the traditional mutual bias V TH The current mirror mismatch problem in the bias circuit is mainly caused by the non-strict matching of the source and drain voltages of the P transistor. In this embodiment, due to the introduction of R1, compared with the traditional bias circuit, the source of the first N transistor and the gate of the second N transistor are not directly connected. The introduction of R1 is equivalent to raising the gate voltage of the second N transistor, that is,

[0028] V GM2 =V SM1 +I3R1

[0029] Under the condition of reasonable design of the same overdrive voltage, the source-drain voltage drop of the second P-tube is reduced by reasonably adjusting the resistance value of R1, so that the source-drain voltage of the first P-tube and the second P-tube are the same, reducing the influence of the channel length modulation effect and increasing the replication accuracy.

[0030] exist Figure 4 In a specific embodiment, using the SIMC_13mmrf_1P6M_30k process library, with the same input current of 6μA, the output current varies with the drain voltage of the first N-transistor. The output current deviation of the conventional bias circuit is greater than that of the improved structure, indicating that the replication accuracy of the improved structure is significantly superior to that of the conventional bias circuit.

[0031] The foregoing are the preferred embodiments of the present invention. Unless the preferred implementation modes in each preferred embodiment are obviously self-contradictory or based on a certain preferred implementation mode, each preferred implementation mode can be arbitrarily superimposed and used in combination. The embodiments and the specific parameters in the embodiments are only for the purpose of clearly describing the inventor's invention verification process, and are not intended to limit the patent protection scope of the present invention. The patent protection scope of the present invention shall still be based on its claims. Any equivalent structural changes made using the contents of the description and drawings of the present invention should also be included in the protection scope of the present invention.

Claims

1. An improved mutual biasing circuit, comprising a first P transistor, a second P transistor, and a third P transistor, wherein the source and substrate of the first P transistor, the second P transistor, and the third P transistor are all connected to a power supply, the gate and drain of the second P transistor are connected, the drain of the third P transistor is connected to the gate of the second N transistor, and the drain of the first P transistor is connected to the drain of the first N transistor; The gate of the first N-type transistor is connected to the drain of the second N-type transistor, the source of the second N-type transistor is connected to the ground, and the first resistor is connected between the gate of the second N-type transistor and the source of the first N-type transistor; One end of the second resistor is connected to the source of the first N transistor, and the other end is connected to the ground. TH On the basis of the bias circuit, an improved structure is used to reduce the circuit area and improve the matching accuracy of the branch current.

2. The mutually biased bias circuit according to claim 1, wherein: The drain of the third P-transistor is connected to the gate of the second N-transistor, and a first resistor is connected between the gate of the second N-transistor and the drain of the first N-transistor.

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