Phase interpolation circuit, circuit device and oscillator

Abstract

The invention provides a phase interpolation circuit, a circuit device and an oscillator, which can improve the linearity of phase division. A phase interpolation circuit that generates an interpolated clock signal obtained by phase interpolation of a clock signal (CK1) and a clock signal (CK2) includes: a current source circuit that is provided between a power supply node (ND) and a node (N1) and that supplies a current (I1) that flows when the clock signal (CK1) is active and a current (I2) that flows when the clock signal (CK2) is active to the node (N1); a discharge transistor that is provided between the node (N1) and the power supply node (NG) and that is turned on when the clock signals (CK1, CK2) are inactive; a current control circuit that sets the current ratio of the currents (I1, I2) on the basis of a phase interpolation signal indicating the phase interpolation ratio of the clock signals (CK1, CK2); and an output circuit that outputs an interpolated clock signal in accordance with a signal of the node (N1).

Description

Technical Field

[0001] The present invention relates to a phase interpolation circuit, a circuit device, an oscillator, and the like. Background Art

[0002] In fractional-N PLL circuits, for example, a phase interpolation circuit is preferably provided to interpolate the phase of a divided clock signal in order to reduce phase noise. For example, Non-Patent Document 1 discloses a phase interpolation circuit that generates an intermediate phase signal of an input signal by connecting phase division units via a pipeline.

[0003] Non-patent document 1: Makihiko Katsuragi, Tn Aravind, Kenichi Okada, Akira Matsuzawa. High-precision implementation of phase tweening loop, Electronic Information and Communications Technology Society Conference, Sept. 2015

[0004] In the case of the phase interpolation circuit of Non-Patent Document 1, in order to n To split the phase, it is necessary to connect n-stage phase splitting units. However, due to variations in the threshold voltages of transistors in each unit of the multi-stage connected phase splitting units, problems such as degradation in the linearity of the phase after division arise. Summary of the Invention

[0005] One embodiment of the present disclosure relates to a phase interpolation circuit that generates an interpolated clock signal by phase interpolating a first clock signal and a second clock signal having a phase different from that of the first clock signal. The phase interpolation circuit includes: a current source circuit disposed between a first power supply node and a first node, and supplying a first current flowing when the first clock signal is valid and a second current flowing when the second clock signal is valid to the first node; a discharge transistor disposed between the first node and a second power supply node, and conducting when the first clock signal and the second clock signal are not valid; a current control circuit that sets a current ratio between the first current and the second current based on a phase interpolation signal indicating the phase interpolation ratio between the first clock signal and the second clock signal; and an output circuit that outputs the interpolated clock signal based on a signal at the first node.

[0006] In addition, other embodiments of the present disclosure relate to a circuit device, comprising: a frequency division circuit, which includes the above-mentioned phase interpolation circuit, outputting the interpolated clock signal from the phase interpolation circuit as a feedback clock signal; a phase comparison circuit, which performs phase comparison between a reference clock signal and the feedback clock signal; a control voltage generation circuit, which generates a control voltage based on the phase comparison result of the phase comparison circuit; and a voltage-controlled oscillation circuit, which generates a clock signal of a frequency corresponding to the control voltage, the phase interpolation circuit generating the interpolated clock signal based on the first clock signal and the second clock signal based on the clock signal.

[0007] Furthermore, another aspect of the present disclosure relates to an oscillator including: the aforementioned circuit device; and an oscillator for generating the reference clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a configuration example of a phase interpolation circuit according to this embodiment.

[0009] Figure 2 It is a signal waveform diagram for explaining the operation of this embodiment.

[0010] Figure 3 It is a signal waveform diagram for explaining the operation of this embodiment.

[0011] Figure 4 This is an example of the structure of a current source circuit and an output circuit.

[0012] Figure 5 This is an example of the structure of a current control circuit.

[0013] Figure 6 This is a truth table illustrating the operation of this embodiment.

[0014] Figure 7 It is a signal waveform diagram for explaining the operation of this embodiment.

[0015] Figure 8 This is an example of the layout configuration of current source transistors and dummy transistors.

[0016] Figure 9 This is a configuration example of a circuit device according to this embodiment.

[0017] Figure 10 This figure explains how to provide a phase interpolation circuit in a PLL circuit.

[0018] Figure 11 This is an example of the phase noise characteristics of a PLL circuit.

[0019] Figure 12 It is an explanatory diagram of a phase interpolation circuit of a comparative example.

[0020] Figure 13 This is a simulation result of phase difference deviation in a comparative example.

[0021] Figure 14 This is a simulation result of the phase difference deviation in this embodiment.

[0022] Figure 15 This is a simulation result of the phase difference deviation in this embodiment.

[0023] Figure 16 This is an example of the configuration of a phase interpolation type frequency dividing circuit.

[0024] Figure 17 This is a signal waveform diagram for explaining the operation of a phase interpolation type frequency dividing circuit.

[0025] Figure 18 This is another configuration example of a current source circuit.

[0026] Figure 19 This is another configuration example of a current control circuit.

[0027] Figure 20 is a truth table that explains the operation of the phase interpolation circuit.

[0028] Figure 21 This is a configuration example of the oscillator according to this embodiment.

[0029] Label Description

[0030] 4: Oscillator; 10: Oscillator; 20: Circuit device; 30: Phase interpolation circuit; 40: Current source circuit; 50: Current control circuit; 60: Output circuit; 72: Phase comparison circuit; 73: Control voltage generation circuit; 74: Charge pump circuit; 75: Loop filter circuit; 76: Voltage-controlled oscillator circuit; 80: Frequency division circuit; 82: Multiphase clock signal generation circuit; 83: Frequency divider; 84: Frequency divider; 86: Multiplexer; 88: Frequency divider; 90: ΔΣ modulation circuit; 92: Arithmetic circuit; 94: Accumulator; 130: Oscillation circuit; 150: PLL circuit; 160: Control circuit; 162 : ΔΣ modulation circuit; 163: operation circuit; 164: accumulator; 180: output circuit; BF1, BF2, IV: buffer circuit; CK1, CK2: clock signal; CP: capacitor; DM0~DM3: dummy transistors; DVCK: divided clock signal; FBCK: feedback clock signal; I1, I2: current; N1: node; ND, NG: power supply node; PI: phase interpolation signal; PICK: interpolation clock signal; SCK0~SKC4: selection clock signal; SL0~SL4: selector; TD, TD1, TD2: transistors for discharge; TS0~TS4: current source transistors. DETAILED DESCRIPTION

[0031] The present embodiment will be described below. The present embodiment described below does not unduly limit the contents of the claims. Furthermore, not all of the structures described in this embodiment are necessarily essential components.

[0032] 1. Phase interpolation circuit

[0033] Figure 1 The following illustrates a configuration example of the phase interpolation circuit 30 of this embodiment. The phase interpolation circuit 30 generates an interpolated clock signal PICK by phase interpolating the clock signal CK1 and the clock signal CK2. The clock signal CK1 is a first clock signal. The clock signal CK2 is a second clock signal, a clock signal having a different phase from that of the clock signal CK1. For example, the phase interpolation circuit 30 generates an intermediate phase signal between the phase of the signal corresponding to the clock signal CK1 and the phase of the signal corresponding to the clock signal CK2 as the interpolated clock signal PICK. The signal corresponding to the clock signal CK1 is, for example, a delayed signal of the clock signal CK1, e.g., a signal resulting from a signal delay of the clock signal CK1 due to circuit delay. Similarly, the signal corresponding to the clock signal CK2 is, for example, a delayed signal of the clock signal CK2, e.g., a signal resulting from a signal delay of the clock signal CK2 due to circuit delay. The delayed signals of the clock signals CK1 and CK2 are signals resulting from a delayed falling edge or rising edge of the clock signals CK1 and CK2. The edge delay time of the delayed signal of clock signal CK1 and the edge delay time of the delayed signal of clock signal CK2 are, for example, the same delay time. For example, clock signals CK1 and CK2 are delayed by circuits having the same structure, resulting in a signal corresponding to clock signal CK1 and a signal corresponding to clock signal CK2.

[0034] The phase interpolation circuit 30 includes a current source circuit 40, a discharge transistor TD, a current control circuit 50, and an output circuit 60. Figure 1 The structure can be modified in various ways, such as omitting some of the structural elements, adding other structural elements, or replacing some of the structural elements with other structural elements.

[0035] The current source circuit 40 is provided between the power supply node ND and the node N1. The power supply node ND is a first power supply node, for example, a node of VDD serving as a high potential side power supply. In addition, the first power supply node may also be a node of a low potential side power supply. The node N1 is a first node, for example, a node between the current source circuit 40 and the transistor TD for discharge. The current source circuit 40 is a circuit that serves as a current source for the phase interpolation circuit 30, and supplies current I1 and current I2 to the node N1. Current I1 is a first current, for example, a current that flows when the clock signal CK1 becomes active. Current I2 is a second current, for example, a current that flows when the clock signal CK2 becomes active. The situation where the clock signals CK1 and CK2 become active refers to the situation where the clock signals CK1 and CK2 change from an inactive level to an active level, for example. The active level is a level of one of a low level and a high level, and the inactive level is a level of the other of a low level and a high level. For example, when clock signal CK1 becomes active, current source circuit 40 delays the current from the time clock signal CK1 becomes active by the circuit's delay time and supplies current I1 to node N1. Furthermore, when clock signal CK2 becomes active, current source circuit 40 delays the current from the time clock signal CK2 becomes active by the circuit's delay time and supplies current I2 to node N1.

[0036] The discharge transistor TD is provided between the node N1 serving as the first node and the power supply node NG. The discharge transistor TD is, for example, an N-type transistor, such as an N-type MOS transistor. The power supply node NG is the second power supply node, such as the node GND serving as the low-potential power supply. The voltage of GND is the ground voltage, which may also be referred to as VSS. Alternatively, the second power supply node may be the node serving as the high-potential power supply. In this case, the discharge transistor is, for example, a P-type transistor. Furthermore, the discharge transistor TD is turned on when the clock signal CK1 and the clock signal CK2 become inactive. That is, when the clock signal CK1 is active, current I1 is supplied from the current source circuit 40 to the node N1, and when the clock signal CK2 is active, current I2 is supplied from the current source circuit 40 to the node N1. Furthermore, when both the clock signal CK1 and the clock signal CK2 become inactive, the discharge transistor TD is turned on, and for example, the charge at the node N1 is discharged toward the power supply node NG. The timing at which the discharge transistor TD is turned on is, for example, a timing delayed by the circuit delay time after the clock signal CK1 and the clock signal CK2 become inactive.

[0037] The current control circuit 50 sets the current ratio between current I1 (a first current) and current I2 (a second current) based on a phase interpolation signal PI between clock signals CK1 and CK2. Phase interpolation signal PI is a signal indicating the interpolation phase ratio between clock signals CK1 and CK2 (a signal indicating the interpolation phase in phase interpolation), and is, for example, a p-bit signal (p is an integer greater than or equal to 2). For example, phase interpolation signal PI indicates the interpolated phase, i.e., the intermediate phase, between the phase of the signal corresponding to clock signal CK1 and the phase of the signal corresponding to clock signal CK2, and is a signal indicating the phase interpolation ratio. This phase interpolation signal PI is input to the current control circuit 50 from a control circuit (not shown). The current control circuit 50 outputs a control signal based on phase interpolation signal PI to the current source circuit 40, thereby setting the current ratio between current I1 and current I2. For example, when phase interpolation signal PI indicates an interpolation phase close to the phase of the signal corresponding to clock signal CK1, i.e., the intermediate phase, the current control circuit 50 outputs a control signal that sets the current ratio such that current I1 is greater than current I2. Furthermore, when the phase interpolation signal PI indicates a phase close to that corresponding to the clock signal CK2 as the interpolated phase, i.e., the intermediate phase, the current control circuit 50 outputs a control signal that sets the current I2 to be greater than the current I1. The current control circuit 50 can be implemented, for example, by a logic circuit.

[0038] The output circuit 60 outputs an interpolated clock signal PICK based on the signal SQ at the node N1. For example, the output circuit 60 outputs an interpolated clock signal PICK such that the interpolated clock signal PICK has a first voltage level when the voltage of the signal SQ is below a predetermined threshold voltage, and has a second voltage level when the voltage of the signal SQ is above the predetermined threshold voltage. The first voltage level is either a high level or a low level, and the second voltage level is the other of the high level and the low level. For example, the output circuit 60 may include a buffer circuit for buffering the signal SQ. The buffer circuit may invert the signal level of the signal SQ or may not invert the signal level.

[0039] Figure 2 3 is a signal waveform diagram showing the operation of the phase interpolation circuit 30 . Figure 2The waveform A1 corresponds to the waveform of signal SQ at node N1 when only clock signal CK1 is active. For example, when clock signal CK1 is active, current I1 from current source circuit 40 is supplied to node N1, charging the node. As a result, the voltage of signal SQ changes as shown in A1. The waveform A2 corresponds to the waveform of signal SQ when only clock signal CK2 is active. For example, when clock signal CK2 is active, current I2 from current source circuit 40 is supplied to node N1, charging the node. As a result, the voltage of signal SQ changes as shown in A2.

[0040] and, Figure 2 The waveform of A3 corresponds to the waveform of the signal SQ when the clock signal CK2 becomes valid after the clock signal CK1 becomes valid. Figure 2 Before the timing of A4, node N1 is charged only by current I1 from current source circuit 40. However, after the timing of A4, node N1 is charged by current I1 and current I2 from current source circuit 40. Therefore, after the timing of A4, as shown in the waveform of A3, the voltage of signal SQ changes at a higher rate of change than the waveform of A1.

[0041] Furthermore, assuming that the waveform of signal SQ is waveform A1, the interpolation clock signal PICK transitions from a high level to a low level at the timing indicated by B1, when the voltage of signal SQ exceeds the threshold voltage VTH in output circuit 60. Threshold voltage VTH is the threshold voltage of the buffer circuit provided in output circuit 60. Furthermore, assuming that the waveform of signal SQ is waveform A2, the interpolation clock signal PICK transitions from a high level to a low level at the timing indicated by B2, when the voltage of signal SQ exceeds the threshold voltage VTH. Furthermore, if the waveform of signal SQ is waveform A3, the interpolation clock signal PICK transitions from a high level to a low level at the timing indicated by B3, when the voltage of signal SQ exceeds the threshold voltage VTH.

[0042] Then, when both clock signals CK1 and CK2 become inactive high, the charge stored in node N1 is discharged by discharging transistor TD, causing signal SQ to become low and interpolation clock signal PICK to transition from low to high.

[0043] from Figure 2 It can be seen that the phase of the interpolation clock signal PICK can be set by setting the current I1 that flows when the clock signal CK1 is active and the current I2 that flows when the clock signal CK2 is active.

[0044] For example, in Figure 2In the example, signal CK1D corresponds to clock signal CK1 and corresponds to a delayed clock signal resulting from delaying the edge of clock signal CK1. Signal CK2D corresponds to clock signal CK2 and corresponds to a delayed clock signal resulting from delaying the edge of clock signal CK2. For example, signals CK1D and CK2D correspond to signals resulting from signal delays in clock signals CK1 and CK2 due to parasitic capacitance at node N1, capacitors provided in output circuit 60, and the like. Furthermore, interpolated clock signal PICK can be said to be a signal having a phase intermediate between the phases of signal CK1D and signal CK2D. For example, interpolated clock signal PICK is a signal obtained by interpolating the phases of signal CK1D, which corresponds to clock signal CK1, and signal CK2D, which corresponds to clock signal CK2, using a ratio of m:n. Here, m and n are, for example, integers greater than or equal to 0. For example, by setting the current ratio of current I1 to current I2 to n:m, phase interpolation circuit 30 generates interpolated clock signal PICK by interpolating the phases of signal CK1D and signal CK2D using a ratio of m:n. For example, signal CK1D is a signal when current I2 is zero, corresponding to a case where the current ratio of I1 to I2 is set to, for example, q:0. q is a constant corresponding to the sum of m and n. Signal CK2D is a signal when current I1 is zero, corresponding to a case where the current ratio of I1 to I2 is set to, for example, 0:q.

[0045] For example, in this embodiment, when a phase interpolation signal PI of an interpolated clock signal PICK that generates a signal corresponding to clock signal CK1 whose phase is closer than that of a signal corresponding to clock signal CK2 is input, the current control circuit 50 sets a current ratio so that current I1 is greater than current I2.

[0046] For example, in Figure 3 In the example, it is assumed that a phase interpolation signal PI is inputted, which generates an interpolation clock signal PICK whose phase is closer to the signal CK1D corresponding to the clock signal CK1 than to the signal CK2D corresponding to the clock signal CK2. In this case, the current control circuit 50 sets the current ratio n:m of the current I1 to the current I2 to n>m so that the current I1 is larger. If the current ratio is set so that the current I1 is larger, as in Figure 2 As described in , the phase of the interpolation clock signal PICK can be brought close to the phase of the signal CK1D corresponding to the clock signal CK1. Therefore, by setting the current ratio between the current I1 and the current I2, the phase of the interpolation clock signal PICK can be variably set.

[0047] In addition, Figure 3In the example, it is assumed that a phase interpolation signal PI is inputted, which generates an interpolation clock signal PICK whose phase is closer to the signal CK2D corresponding to the clock signal CK2 than to the signal CK1D corresponding to the clock signal CK1. In this case, the current control circuit 50 sets the current ratio n:m of the current I1 to the current I2 to n<m so that the current I2 is larger. If the current ratio is set so that the current I2 is larger, as in Figure 2 As described in , the phase of the interpolation clock signal PICK can be brought close to the phase of the signal CK2D corresponding to the clock signal CK2. Therefore, by setting the current ratio of the current I1 to the current I2, the phase of the interpolation clock signal PICK can be variably set.

[0048] That is, in Figure 3 In the embodiment of the present invention, when a phase interpolation signal PI is input, which interpolates the phases of the signal CK1D corresponding to the clock signal CK1 and the signal CK2D corresponding to the clock signal CK2 in an m:n ratio, the current control circuit 50 sets the current ratio of the currents I1 and I2 to n:m. Thus, the current control circuit 50 sets the current ratio of I1 and I2 to n:m, thereby generating an interpolated clock signal PICK, which interpolates the phases of the signal CK1D corresponding to the clock signal CK1 and the signal CK2D corresponding to the clock signal CK2 in an m:n ratio.

[0049] For example, assume that m = 1 and n = 7, and a phase interpolation signal PI is input that brings the phase of the interpolated clock signal PICK close to that of the signal CK1D. In this case, the current control circuit 50 sets the current ratio of current I1 to current I2 to n:m = 7:1. By setting this current ratio, which makes current I1 larger, an interpolated clock signal PICK is generated whose phase is close to that of the signal CK1D. Furthermore, assume that m = 7 and n = 1, and a phase interpolation signal PI is input that brings the phase of the interpolated clock signal PICK close to that of the signal CK2D. In this case, the current control circuit 50 sets the current ratio of current I1 to current I2 to n:m = 1:7. By setting this current ratio, which makes current I2 larger, an interpolated clock signal PICK is generated whose phase is close to that of the signal CK2D. Note that the m and n in the m:n division ratio for phase interpolation and the m and n in the n:m current ratio do not need to be completely identical; they may be substantially identical within a range that takes into account variations.

[0050] Figure 4 The configuration examples of the current source circuit 40 and the output circuit 60 are shown. Figure 4 The structure can be modified in various ways, such as omitting some of its structural elements, adding other structural elements, or replacing some of its structural elements with other structural elements.

[0051] like Figure 4 As shown, the current source circuit 40 includes current source transistors TS0, TS1, TS2, and TS3 connected in parallel between the power supply node ND and the node N1. Figure 4 In the embodiment, the current source transistors TS0, TS1, TS2, and TS3 are, for example, P-type transistors, with their drains connected to the power supply node ND on the high potential side and their sources connected to the node N1. In addition, the current source transistors may also be N-type transistors, in which case the first power supply node becomes the node of the low potential side power supply. Moreover, the gates of the current source transistors TS0, TS1, TS2, and TS3 are input with selection clock signals SCK0, SCK1, SCK2, and SCK3, and are turned on and off by these selection clock signals. The selection clock signals SCK0, SCK1, SCK2, and SCK3 are clock signals selected from the clock signal CK1 or the clock signal CK2 based on the phase interpolation signal PI, and are generated and output by the current control circuit 50, for example. In addition, the clock signal selected as the selection source of the selection clock signal may be the clock signals CK1 and CK2 themselves, or may be a signal obtained by buffering the clock signals CK1 and CK2 through a buffer circuit. Furthermore, for example, a selection clock signal is selected from the clock signal CK1 or the clock signal CK2 according to the logic level of each bit of the p-bit phase interpolation signal PI.

[0052] Moreover, in Figure 4 In the embodiment, the current source transistors TS0 and TS1 whose gates are input with the selection clock signals SCK0 and SCK1 supply, for example, a current of 1I to the node N1 when the selection clock signals SCK0 and SCK1 become valid. Furthermore, the current source transistor TS2 whose gate is input with the selection clock signal SCK2 supplies, for example, a current of 2I to the node N1 when the selection clock signal SCK2 becomes valid. Furthermore, the current source transistor TS3 whose gate is input with the selection clock signal SCK3 supplies, for example, a current of 4I to the node N1 when the selection clock signal SCK3 becomes valid. Figure 4 Here, k corresponds to, for example, the number of unit transistors constituting each current source transistor. Furthermore, current source transistors TS0 and TS1 with k = 1, for example, allow a current of 1I to flow through one unit transistor. Furthermore, current source transistor TS2 with k = 2, for example, allows a current of 2I to flow through two unit transistors, and current source transistor TS2 with k = 4, for example, allows a current of 4I to flow through four unit transistors. Thus, the currents flowing through current source transistors TS0, TS1, TS2, and TS3 are set to current values ​​represented by powers of 2, for example.

[0053] In addition, Figure 4In the current source circuit 40, dummy transistors DM0, DM1, and DM2 are further provided. Dummy transistor DM0 is provided in parallel with current source transistor TS0, and its gate is input with selection clock signal SCK0, which is input to the gate of current source transistor TS0. Furthermore, while the drain of current source transistor TS0 is connected to node N1, the drain of dummy transistor DM0 is not connected to node N1. Furthermore, the source of dummy transistor DM0 is connected to power supply node ND. Thus, the drain of dummy transistor DM0 is not connected to node N1, making it a dummy transistor that does not function as a current source transistor.

[0054] Furthermore, a dummy transistor DM1 is provided in parallel with the current source transistor TS1, and its gate is input with the selection clock signal SCK1 input to the gate of the current source transistor TS1. Furthermore, the drain of the dummy transistor DM1 is not connected to the node N1. Furthermore, a dummy transistor DM2 is provided in parallel with the current source transistor TS2, and its gate is input with the selection clock signal SCK2 input to the gate of the current source transistor TS2. Furthermore, the drain of the dummy transistor DM2 is not connected to the node N1. Furthermore, the sources of the dummy transistors DM1 and DM2 are connected to the power supply node ND.

[0055] Providing these dummy transistors DM0, DM1, and DM2 allows the gate capacitances of the select clock signals SCK0, SCK1, SCK2, and SCK3, which are parasitic capacitances added to the gates of the current source transistors TS0, TS1, TS2, and TS3, to be equal. By making the gate capacitances of the select clock signals SCK0, SCK1, SCK2, and SCK3 equal, the blunting of the signal waveforms of the select clock signals SCK0, SCK1, SCK2, and SCK3 can be made equal. This improves the linearity of the divided phases in the interpolated clock signal PICK.

[0056] For example, current source transistors TS0 and TS1 have k = 1 and consist of one unit transistor, while dummy transistors DM0 and DM1 have k = 3 and consist of three unit transistors. Therefore, the gate capacitance of the select clock signal SCK0 input to the gate of current source transistor TS0 and the gate of dummy transistor DM0 becomes the gate capacitance of four unit transistors. Furthermore, the gate capacitance of the select clock signal SCK1 input to the gate of current source transistor TS1 and the gate of dummy transistor DM1 also becomes the gate capacitance of four unit transistors, similar to the case of the select clock signal SCK0.

[0057] In addition, the current source transistor TS2 has k=2 and is composed of 2 unit transistors, and the dummy transistor DM2 has k=2 and is composed of 2 unit transistors. Therefore, similarly to the case of selecting the clock signals SCK0 and SCK1, the gate capacitance of the selection clock signal SCK2 added to the gate input to the current source transistor TS2 and the gate of the dummy transistor DM2 becomes the gate capacitance of 4 unit transistors. In addition, the current source transistor TS3 has k=4 and is composed of 4 unit transistors. Therefore, similarly to the case of selecting the clock signals SCK0, SCK1, and SCK2, the gate capacitance of the selection clock signal SCK3 added to the gate input to the current source transistor TS3 becomes the gate capacitance of 4 unit transistors. In this way, Figure 4 By providing dummy transistors DM0, DM1, and DM2, the gate capacitances added to the selected clock signals SCK0, SCK1, SCK2, and SCK3 are set to be equal. This allows the waveforms of the selected clock signals SCK0, SCK1, SCK2, and SCK3 to be blunted to be equal, improving the linearity of phase interpolation.

[0058] In addition, Figure 4 In, as Figure 1 The discharge transistor TD includes transistors TD1 and TD2. Transistors TD1 and TD2 are connected in parallel between node N1 and power supply node NG, and a discharge control signal SDS is input to the gate. Figure 4 In the embodiment, the discharge transistors TD1 and TD2 are N-type transistors. However, a modification in which P-type transistors are used as the discharge transistors TD1 and TD2 is also possible.

[0059] The control signal SDS input to the gates of the discharge transistors TD1 and TD2 is generated and output by, for example, the current control circuit 50. For example, the control signal SDS becomes active when the clock signals CK1 and CK2 are inactive. Consequently, when both the clock signals CK1 and CK2 are inactive, the discharge transistors TD1 and TD2 are turned on, and the charge accumulated at the node N1 by the currents I1 and I2 is discharged to the power supply node NG via the discharge transistors TD1 and TD2. This initializes the voltage of the signal SQ at the node N1 to a low level.

[0060] The output circuit 60 includes a capacitor CP and a buffer circuit IV. One end of the capacitor CP is connected to the node N1. The signal SQ of the node N1 is input to the buffer circuit IV. The buffer circuit IV outputs an interpolated clock signal PICK based on the signal SQ. Figure 4In the embodiment, the other end of the capacitor CP is connected to the node of GND, but it can also be connected to a node of a predetermined potential other than GND. As the capacitor CP, for example, a MIM (Metal-Insulator-Metal) capacitor can be used. Alternatively, as the capacitor CP, a MOS capacitor serving as the gate capacitance of a MOS transistor can also be used. In addition, Figure 4 In the embodiment, the capacitor CP is a capacitor with a variable capacitance. For example, by adjusting the capacitance of the capacitor CP, it is possible to make adjustments corresponding to the deviation of the threshold voltage during the manufacture of the transistor. Alternatively, the capacitor CP may be a capacitor with a fixed capacitance. Figure 4 In this embodiment, an inverter circuit is used as the buffer circuit IV of the output circuit 60. By providing the capacitor CP and the buffer circuit IV in the output circuit 60, the capacitance of the capacitor CP at the node N1 can be charged by the current I1 flowing when the clock signal CK1 is active and the current I2 flowing when the clock signal CK2 is active. Then, the signal SQ at the node N1, whose voltage changes due to this charging, can be input to the buffer circuit IV, and the interpolated clock signal PICK can be output. For example, Figure 2 As described in , when the voltage of the signal SQ at the node N1 changes and exceeds the threshold voltage of the buffer circuit IV, the voltage level of the interpolated clock signal PICK changes. This allows the generation of an interpolated clock signal PICK appropriately interpolated to an intermediate phase corresponding to the phase interpolation signal PI.

[0061] Figure 5 The current control circuit 50 is shown as an example of its configuration. Figure 5 The structure can be modified in various ways, such as omitting some of the structural elements, adding other structural elements, or replacing some of the structural elements with other structural elements.

[0062] The current control circuit 50 outputs multiple selected clock signals SCK0, SCK1, SCK2, and SCK3 to the gates of multiple current source transistors TS0, TS1, TS2, and TS3 of the current source circuit 40. For example, the current control circuit 50 outputs each selected clock signal SCK0, SCK1, SCK2, and SCK3, selected from the clock signal CK1 or the clock signal CK2 based on the phase interpolation signal PI, to each current source transistor of TS0, TS1, TS2, and TS3. In this way, the clock signal CK1 or the clock signal CK2 can be selected as the selected clock signal SCK0, SCK1, SCK2, and SCK3 based on the phase interpolation signal PI and input to the gates of the current source transistors TS0, TS1, TS2, and TS3. Furthermore, when the clock signal CK1 is selected as the selected clock signal and input to the gate, the current source transistors are turned on, thereby supplying current I1 to the node N1 of the signal SQ. Furthermore, the current source transistor, whose gate is selected by clock signal CK2 as the selected clock signal and input thereto, is turned on when clock signal CK2 is active, supplying current I2 to node N1 of signal SQ. Consequently, currents I1 and I2 are supplied to node N1 of signal SQ at a current ratio corresponding to phase interpolation signal PI.

[0063] Specifically, if Figure 5 As shown, the current control circuit 50 includes a plurality of selectors SL0, SL1, SL2, and SL3. Furthermore, each of the plurality of selectors SL0, SL1, SL2, and SL3 outputs a selected clock signal SCK0, SCK1, SCK2, and SCK3 to the gates of the current source transistors TS0, TS1, TS2, and TS3. In this way, the selectors SL0, SL1, SL2, and SL3 can select either the clock signal CK1 or the clock signal CK2 as the selected clock signal based on the phase interpolation signal PI and input it to the gates of the current source transistors TS0, TS1, TS2, and TS3.

[0064] For example, in Figure 5 In FIG. 5 , the current control circuit 50 includes buffer circuits BF1 and BF2 and an AND circuit AN. The clock signal CK1 is buffered by the buffer circuit BF1 and input to the selectors SL0, SL1, SL2, and SL3 as the clock signal CK1B. The clock signal CK2 is buffered by the buffer circuit BF2 and input to the selectors SL0, SL1, SL2, and SL3 as the clock signal CK2B. The clock signals CK1 and CK2 are input to the AND circuit AN, which outputs the control signal SDS for discharge. Figure 4As shown, this control signal SDS is input to discharge transistors TD1 and TD2. For example, when clock signals CK1 and CK2 are both inactive (i.e., high), the discharge control signal SDS goes high. This turns on discharge transistors TD1 and TD2, discharging node N1 of signal SQ.

[0065] Phase interpolation signals PI1, PI2, and PI3 are input to selectors SL1, SL2, and SL3 as phase interpolation signal PI. Phase interpolation signals PI1, PI2, and PI3 are signals corresponding to the first, second, and third bits of the three-bit phase interpolation signal PI. Furthermore, when phase interpolation signals PI1, PI2, and PI3 are at a logic level of "0," selectors SL1, SL2, and SL3 select clock signal CK1B. Furthermore, when phase interpolation signals PI1, PI2, and PI3 are at a logic level of "1," clock signal CK2B is selected. In this way, the current control circuit 50 can output the signal selected from clock signals CK1B and CK2B based on phase interpolation signals PI1, PI2, and PI3 as selected clock signals SCK1, SCK2, and SCK3.

[0066] In addition, since the input terminal of the phase interpolation signal PI is set to GND corresponding to "0" in logic level, the selector SL0 always selects the clock signal CK1B. In addition, in this embodiment, the first clock signal selected according to the phase interpolation signal PI can be the clock signal CK1 itself or a clock signal such as Figure 5 The second clock signal selected based on the phase interpolation signal PI may be the clock signal CK2 itself or the clock signal CK2B buffered from the clock signal CK2.

[0067] Figure 6 A truth table illustrating the operation of the phase interpolation circuit 30 is shown. Figure 6 PI<3:1> corresponds to Figure 5 PI3, PI2, and PI1. For example, when PI < 3:1 > = 0, 1, 2, and 3, (PI3, PI2, PI1) = (0, 0, 0), (0, 0, 1), (0, 1, 0), and (0, 1, 1), respectively. Furthermore, when PI < 3:1 > = 4, 5, 6, and 7, (PI3, PI2, PI1) = (1, 0, 0), (1, 0, 1), (1, 1, 0), and (1, 1, 1), respectively.

[0068] For example, Figure 4As shown, the selection clock signal SCK3 is input to the gate of the current source transistor TS3, whereby the current source transistor TS1 flows a current of 4I to the node N1. Figure 6 In the case of PI<3:1>=0, 1, 2, 3, since the third bit PI3 which is the MSB of the phase interpolation signal PI becomes 0, Figure 5 The selector SL3 selects the clock signal CK1B as the selected clock signal SCK3. As a result, the current source transistor TS3 to which the clock signal CK1B is inputted is turned on when the clock signal CK1B is active (low level), and supplies a current I1=4I to the node N1.

[0069] Furthermore, when PI<3:1>=4, 5, 6, or 7, bit PI3 of the third bit of the phase interpolation signal PI is 1, so selector SL3 selects clock signal CK2B as selected clock signal SCK3. Consequently, current source transistor TS3, to which clock signal CK2B is input, is turned on when clock signal CK2B is active, supplying current I2=4I to node N1.

[0070] In addition, if Figure 4 As shown, the selection clock signal SCK2 is input to the gate of the current source transistor TS2, whereby the current source transistor TS2 flows a current of 2I to the node N1. Figure 6 In the case of PI<3:1>=0, 1, 4, 5, since the second bit PI2 of the phase interpolation signal PI becomes 0, Figure 5 The selector SL2 selects the clock signal CK1B as the selected clock signal SCK2. As a result, the current source transistor TS2 to which the clock signal CK1B is input is turned on when the clock signal CK1B is active, and supplies a current I1 = 2I to the node N1.

[0071] Furthermore, when PI<3:1>=2, 3, 6, or 7, bit PI2 of the second bit of the phase interpolation signal PI is 1, so selector SL2 selects clock signal CK2B as selected clock signal SCK2. Consequently, current source transistor TS2, to which clock signal CK2B is input, is turned on when clock signal CK2B is active, supplying current I2=2I to node N1.

[0072] Furthermore, the selection clock signal SCK1 is input to the gate of the current source transistor TS1, whereby the current source transistor TS1 flows a current of 1I to the node N1. Figure 6 In the case of PI<3:1>=0, 2, 4, 6, since PI1 which is the first bit of the LSB of the phase interpolation signal PI becomes 0, Figure 5The selector SL1 selects the clock signal CK1B as the selected clock signal SCK1. As a result, the current source transistor TS1 to which the clock signal CK1B is input is turned on when the clock signal CK1B is active, and supplies a current I1 = 1I to the node N1.

[0073] Furthermore, when PI<3:1>=1, 3, 5, or 7, bit PI1 of the phase interpolation signal PI is 1, so selector SL1 selects clock signal CK2B as selected clock signal SCK1. Consequently, current source transistor TS1, to which clock signal CK2B is input, is turned on when clock signal CK2B is active, supplying current I2=1I to node N1.

[0074] Furthermore, the selection clock signal SCK0 is input to the gate of the current source transistor TS0, whereby the current source transistor TS0 flows a current of 1I to the node N1. Figure 6 In all cases where PI < 3:1 >, Figure 5 The selector SL0 selects the clock signal CK1B as the selected clock signal SCK0. As a result, the current source transistor TS0 to which the clock signal CK1B is input is turned on when the clock signal CK1B is active, and supplies a current I1 = 1I to the node N1.

[0075] For example, in Figure 6 In the example, the phase interpolation signal is PI<3:1>=7. In this case, when the clock signal CK1B is valid, a current of I1=1I is supplied to the node N1 through the current source transistor TS0. When the clock signal CK2B is valid, a current of I2=1I+2I+3I=7I is supplied to the node N1 through the current source transistors TS1, TS2, and TS3. Therefore, the current ratio of I1 to I2 is set to 1:7 by the phase interpolation signal PI<3:1>=7. Figure 3 As described in , the interpolated clock signal PICK is generated by interpolating the phases of CK1D and CK2D at a ratio of 7:1. That is, when the current ratio in which the current I2 is larger is set by the phase interpolation signal PI, the interpolated clock signal PICK having a phase close to CK2D is generated.

[0076] In addition, located in Figure 6In this example, the phase interpolation signal is PI<3:1> = 1. In this case, when clock signal CK1B is active, a current of I1 = 1I + 2I + 4I = 7I is supplied to node N1 from current source transistors TS0, TS2, and TS3. When clock signal CK2B is active, a current of I2 = 1I is supplied to node N1 via current source transistor TS1. Therefore, the phase interpolation signal PI<3:1> = 1 sets the current ratio of I1 to I2 to 7:1. This generates an interpolated clock signal PICK, which interpolates the phases of CK1D and CK2D at a ratio of 1:7. That is, when the phase interpolation signal PI sets a larger current ratio for current I1, an interpolated clock signal PICK with a phase close to that of CK1D is generated. In addition, the signal CK1D corresponding to the clock signal CK1 corresponds to the interpolated clock signal PICK when the current ratio of I1 and I2 is set to, for example, 8:0, and the signal CK2D corresponding to the clock signal CK2 corresponds to the interpolated clock signal PICK when the current ratio of I1 and I2 is set to, for example, 0:8.

[0077] Figure 7 The following diagram shows signal waveform examples of the interpolated clock signal PICK when the current ratio of I1 to I2 is set to 8:0, 7:1, 6:2, ..., and 1:7. By setting the current ratio of I1 to I2 in the current source circuit 40 using the current control circuit 50, the phase interpolation ratio of the interpolated clock signal PICK can be set.

[0078] Figure 8 : is a layout configuration example of current source transistors TS0, TS1, TS2, TS3 and dummy transistors DM0, DM1, DM2. Figure 8 As shown, current source transistor TS0 is composed of k=1 unit transistors, and dummy transistor DM0 is composed of k=3 unit transistors. Similarly, current source transistor TS1 is composed of k=1 unit transistor, and dummy transistor DM1 is composed of k=3 unit transistors. In addition, current source transistor TS2 is composed of k=2 unit transistors, and dummy transistor DM2 is composed of k=2 unit transistors. In addition, current source transistor TS3 is composed of k=4 unit transistors.

[0079] Moreover, if Figure 4As shown, the same selection clock signal SCK0 is input to the gate of current source transistor TS0 (k=1) and the gate of dummy transistor DM0 (k=3). Furthermore, the same selection clock signal SCK1 is input to the gate of current source transistor TS1 (k=1) and the gate of dummy transistor DM1 (k=3). Furthermore, the same selection clock signal SCK2 is input to the gate of current source transistor TS2 (k=2) and the gate of dummy transistor DM2 (k=2). Furthermore, the selection clock signal SCK3 is input to the gate of current source transistor TS3 (k=4). Therefore, the total number of unit transistors whose gates receive each selection clock signal is the same for TS0 and DM0, TS1 and DM1, TS2 and DM2, and TS3, which is k=4, resulting in the same gate area. Consequently, the gate capacitance of the unit transistors contributing to selection clock signals SCK0, SCK1, SCK2, and SCK3 can be made equal, and the blunting of the waveforms of selection clock signals SCK0, SCK1, SCK2, and SCK3 due to the gate capacitance can also be made equal. This can improve the linearity of the phase interpolation of the interpolation clock signal PICK.

[0080] 2. Circuit device

[0081] Figure 9 The following shows a structural example of a circuit device 20 including the phase interpolation circuit 30 of the present embodiment. The circuit device 20 includes a phase comparison circuit 72, a control voltage generation circuit 73, a voltage control oscillation circuit 76, and a frequency division circuit 80. The circuit device 20 of this structure implements a PLL (Phase Locked Loop) circuit. Specifically, a fractional-N type PLL circuit is implemented. The circuit device 20 is, for example, an integrated circuit device called an IC (Integrated Circuit). For example, the circuit device 20 is an IC manufactured by a semiconductor process, and is a semiconductor chip having circuit elements formed on a semiconductor substrate. In addition, the circuit device 20 is not limited to Figure 9 The structure can be modified in various ways, such as omitting some of the structural elements, adding other structural elements, or replacing some of the structural elements with other structural elements.

[0082] Phase comparison circuit 72 compares the phases of reference clock signal RFCK and feedback clock signal FBCK. Reference clock signal RFCK is, for example, an oscillating clock signal. For example, phase comparison circuit 72 compares the phases of reference clock signal RFCK and feedback clock signal FBCK and outputs a signal corresponding to the phase difference between reference clock signal RFCK and feedback clock signal FBCK as the phase comparison result signal. For example, an up signal and a down signal may be output as the phase comparison result signal. Alternatively, phase comparison circuit 72 may be a phase comparison circuit used in a sampling PLL or subsampling PLL. For example, phase comparison circuit 72 may be provided with a sampling circuit that samples a slope signal generated by feedback clock signal FBCK based on reference clock signal RFCK and outputs a sampled voltage to implement phase comparison. In this case, the sampled voltage of the sampling circuit becomes a voltage corresponding to the phase difference between reference clock signal RFCK and feedback clock signal FBCK.

[0083] The control voltage generation circuit 73 generates a control voltage VC based on the phase comparison result of the phase comparison circuit 72. The control voltage generation circuit 73 includes, for example, a charge pump circuit 74 and a loop filter circuit 75. The charge pump circuit 74 performs a charge pump operation based on the signal from the phase comparison result of the phase comparison circuit 72. The loop filter circuit 75 performs a filter process on the output signal QCP of the charge pump circuit 74. This generates a control voltage VC for controlling the oscillation of the voltage-controlled oscillation circuit 76.

[0084] The voltage-controlled oscillation circuit 76 oscillates according to the control voltage VC to generate the clock signal CK. The voltage-controlled oscillation circuit 76 can be implemented, for example, by an LC oscillation circuit using an inductor and a capacitor, or by a ring oscillation circuit comprising a plurality of inverter circuits connected in a ring shape.

[0085] Frequency divider circuit 80 divides the frequency of clock signal CK to generate feedback clock signal FBCK. For example, frequency divider circuit 80 outputs a signal with a frequency obtained by dividing the frequency of clock signal CK by the division ratio set by division ratio setting information SDIV as feedback clock signal FBCK. For example, in this embodiment, a fractional frequency divider is implemented as frequency divider circuit 80 by utilizing digital Σ modulation. For example, if the oscillation frequency of voltage-controlled oscillator circuit 76 is fvco and the division ratio represented by the division ratio setting value is DIV, the frequency of feedback clock signal FBCK is fvco / DIV.

[0086] Furthermore, in this embodiment, the frequency division circuit 80 includes a phase interpolation circuit 30, which outputs an interpolated clock signal PICK from the phase interpolation circuit 30 as the feedback clock signal FBCK. For example, the phase interpolation circuit 30 generates the interpolated clock signal PICK based on the clock signal CK1 and the clock signal CK2 based on the clock signal CK. For example, the phase interpolation circuit 30 uses the clock signal CK and the clock signal XCK obtained by inverting the clock signal CK as the clock signal CK1 and the clock signal CK2, respectively, to generate the interpolated clock signal PICK. In addition, the phase interpolation circuit 30 may also generate the interpolated clock signal PICK using the clock signal obtained by integer frequency division of the clock signal CK as the clock signals CK1 and CK2. In addition, as described later, multiple multi-phase clock signals may also be generated based on the clock signal CK, and the phase interpolation circuit 30 may use two of these multiple multi-phase clock signals as the clock signals CK1 and CK2 to generate the interpolated clock signal PICK.

[0087] Specifically, if Figure 9 As shown, the frequency division circuit 80 includes a frequency divider 88, a ΔΣ modulation circuit 90, an arithmetic circuit 92, and a phase interpolation circuit 30. The arithmetic circuit 92 includes an accumulator 94. The ΔΣ modulation circuit 90 performs ΔΣ modulation based on the fractional part (f) of the frequency division ratio set by the frequency division ratio setting information SDIV. The accumulator 94 of the arithmetic circuit 92 generates a phase interpolation signal PI by integrating the output value of the ΔΣ modulation circuit 90. Furthermore, the frequency divider 88 performs integer division based on the integer part (N) of the frequency division ratio set by the frequency division ratio setting information SDIV. This configuration realizes a fractional-N PLL circuit capable of outputting a clock signal CK having a frequency obtained by multiplying the frequency of the input reference clock signal RFCK by an arbitrary multiplication factor including the fractional part.

[0088] For example, the ΔΣ modulation circuit 90 can be implemented using a differentiator (adder) that obtains the difference between the input value and the feedback value, an integrator that time-integrates the difference result, a quantizer that calculates the quantization error of the integrated result, and a delay device that provides feedback of the output value. For example, a circuit that performs single-, double-, or triple-order ΔΣ modulation can be used as the ΔΣ modulation circuit 90. For example, the frequency divider 88 and the ΔΣ modulation circuit 90 form a fractional frequency divider, which can implement a fractional-N PLL circuit. For example, the ΔΣ modulation circuit 90 performs ΔΣ modulation based on the fractional part of the frequency division ratio of the frequency division ratio setting information SDIV and outputs ΔΣ modulated data. For example, the ΔΣ modulation circuit 90 outputs n-bit ΔΣ modulated data. For example, the ΔΣ modulation circuit 90 outputs 4-bit ΔΣ modulated data through triple-order ΔΣ modulation. In this case, digital data such as (1101) = -3, (1110) = -2, (1111) = -1, (0000) = 0, (0001) = +1, (0010) = +2, (0011) = +3, and (0100) = +4 are output. Accumulator 94 accumulates the values ​​of the ΔΣ modulated data to generate a phase interpolation signal PI. This phase interpolation signal PI indicates, for example, which phase of the interpolated clock signal PICK is in the range of 0 to 2π. Furthermore, when the value of the accumulated ΔΣ modulated data exceeds the phase range of 0 to 2π, accumulator 94 outputs a carry signal. Furthermore, by adding a value based on the carry signal to the integer portion of the division ratio in the division ratio setting information SDIV, the integer division ratio of divider 88 is set.

[0089] For example, Figure 10 D1 is a structural example of a fractional-N PLL circuit using a fractional frequency divider based on ΔΣ modulation. Figure 10 D2 is an example of a fractional-N PLL circuit structure in which a phase interpolation circuit 30 is further provided in the structure of D1. Figure 10 In D1 and D2, PFD, CP, LPF, and VCO correspond to the phase comparison circuit 72, the charge pump circuit 74, the loop filter circuit 75, and the voltage controlled oscillation circuit 76, respectively. In addition, ΔΣMOD corresponds to the ΔΣ modulation circuit 90, and FDIV corresponds to the frequency divider 88. Figure 10 The PIDIV in the structure of D2 corresponds to the phase interpolation circuit 30. Figure 10 In D1 and D2, based on the reference clock signal RFCK of 100 MHz, a frequency division ratio of 25.7 is set as the frequency division ratio setting information SDIV in the frequency division circuit 80, thereby generating a clock signal CK of 2570 MHz.

[0090] And, in Figure 10In the case of the structure of D1, the integer frequency division ratio is ΔΣ modulated by the ΔΣ modulation circuit 90, thereby realizing a fractional frequency divider. For example, ΔΣ modulation is performed so that the average value of the frequency division ratio becomes 25.7. However, in Figure 10 In the case of the D1 structure, only integer division ratio modulation can be performed, so the phase noise is degraded by the quantization noise of ΔΣ modulation. In other words, the phase fluctuation width becomes larger, and the phase noise is degraded.

[0091] On the other hand, Figure 10 In the D2 configuration, an interpolated clock signal, PICK, is generated by phase interpolation of the integer-divided clock signal and output as the feedback clock signal FBCK. Therefore, in the D2 configuration, modulation using a fractional division ratio is performed, reducing the fractional division resolution. Consequently, compared to D1, the phase fluctuation range can be reduced, resulting in lower phase noise.

[0092] For example, Figure 11 C1 is Figure 10 Phase noise characteristics of the case of the D1 structure. In the characteristics of C1, the phase noise in the high frequency band is deteriorated due to the noise of the ΔΣ modulation shown by C2. On the other hand, Figure 11 C3 is Figure 10 The phase noise characteristics of the configuration of D2 are shown in FIG. In the characteristics of C3, as shown in C4, noise due to ΔΣ modulation can be reduced compared to C2, thereby reducing phase noise.

[0093] Figure 12 This is a configuration of a phase interpolation circuit of a comparative example, which corresponds to the phase interpolation circuit of the aforementioned non-patent document 1. In the phase interpolation circuit of the comparative example, for example, in order to n (exist Figure 12 In the example of (n=3), the phase is divided and the phase division units PU are connected in multiple stages. For example, the first stage selector selects two clock signals from the three clock signals (CK1D, CKPI, CK2D) from the three phase division units PU of the first stage based on the selection signal SEL[2]. In addition, the second stage selector selects two clock signals from the three clock signals from the three phase division units PU of the second stage based on the selection signal SEL[1]. In addition, the third stage selector selects one clock signal from the two clock signals from the two phase division units PU of the third stage based on the selection signal SEL[0] and outputs it as the interpolated clock signal PICK.

[0094] exist Figure 12In the comparative example of , the phase division unit PU is connected in multiple stages to form a phase interpolation circuit. Therefore, due to the variation of the threshold voltage of the transistors in each unit of the multi-stage connected phase division unit, the linearity of the phase after division deteriorates. That is, in Figure 12 In the comparative example, the phase division unit that performs phase division is constructed using a pipeline connection. As a result, variations in the threshold voltages of the transistors used in each phase division unit degrade the linearity of the divided phase and increase the variation between samples. Furthermore, the pipelined structure of the phase division units complicates wiring, and variations in parasitic capacitance between the wiring negatively impact the linearity of phase interpolation.

[0095] In this way, Figure 12 In the comparative example of , the phase division unit PU divides the phase difference of the two clock signals into 1 / 2, so that these phase division units PU become j levels (in Figure 12 In the example of j=3), the pipeline connection is realized, thereby achieving (1 / 2) j On the other hand, in this embodiment, for example, one phase interpolation circuit 30 is used to implement (1 / 2) j Phase division. For example, in order to achieve (1 / 2) j Phase splitting, as in Figure 4 As explained in the previous section, the current supply capacity ratio is 1 to 2. (j-1) Current source circuit 40 is composed of current source transistors TS0 to TS3 times the number of transistors (j is a continuous integer greater than or equal to 1). This embodiment, with this configuration, improves the linearity of the phase after division and reduces inter-sample variation compared to the comparative example. Furthermore, wiring is simplified compared to the comparative example, enabling a smaller circuit and lower power consumption.

[0096] For example, Figure 13 yes Figure 12 The simulation results of the phase difference deviation in the case of the comparative example using the Monte Carlo method are shown. Figure 14 、 Figure 15 This is a simulation result of the phase difference deviation in this embodiment using the Monte Carlo method. Figure 13 、 Figure 14 、 Figure 15 The horizontal axis is the number of Monte Carlo trials, and the vertical axis is the phase difference deviation σ. The phase difference deviation is the deviation between the ideal interpolation phase based on phase interpolation and the actual interpolation phase. Figure 13 As shown in FIG, the phase difference deviation is large in the comparative example, whereas Figure 14 、 Figure 15 The phase difference deviation ratio can be made Figure 13 Small. Thus, the phase noise can also be reduced. In addition, Figure 15It is described later Figure 18 、 Figure 19 The simulation results of the structure case are Figure 14 Compared with , it can further reduce the phase difference deviation.

[0097] Figure 16 A more detailed structural example of the frequency dividing circuit 80 is shown. Figure 17 Show instructions Figure 16 An example of a signal waveform of the operation of the frequency divider circuit 80. Figure 16 The frequency division circuit 80 includes a multi-phase clock signal generation circuit 82, a multiplexer 86, and a phase interpolation circuit 30. The multi-phase clock signal generation circuit 82 includes frequency dividers 83 and 84 and five flip-flop circuits FF.

[0098] Frequency divider 83 is an orthogonal clock generation circuit. Specifically, the orthogonal clock generation circuit (83) receives the clock signal CK and the clock signal XCK which is an inverted version of the clock signal CK (with a phase of 180° relative to the clock signal CK) as input, generates orthogonal 90° / 180° clock signals based on these signals, and outputs signals I (0°), Q (90°), IB (180°), and QB (270°). Assuming that the period of the clock signal CK is TVCO, as shown in FIG. Figure 17 As shown, the period of signals I, Q, IB, and QB after frequency division by 2 is 2 × TVCO. In other words, the frequency of signals I, Q, IB, and QB is half the frequency of clock signal CK. Furthermore, signals Q, IB, and QB are phase-delayed by 90 degrees, 180 degrees, and 270 degrees, respectively, relative to signal I. Thus, signals I, Q, IB, and QB are each phase-shifted by 90 degrees.

[0099] Frequency divider 84 is a frequency divider called a feedback divider (FDIV). Specifically, frequency divider 84 divides signal QB by a set integer division ratio N and outputs signal FDIVCLK. Then, signal FDIVCLK is input to the CK terminal of a flip-flop circuit FF, whose D terminal receives signals I, Q, IB, and QB, and is sampled. Then, signal FDIVCLK is output from the Q terminal of the flip-flop circuit FF. Figure 17 The divided clock signals P0, P90, P180, and P270 are shown. In addition, the divided clock signal P0 is input to the D terminal of the flip-flop circuit FF, and the signal FDIVCLK is input to the CK terminal and sampled, and the divided clock signal P360 is output from the Q terminal of the flip-flop circuit FF.

[0100] like Figure 17As shown, divided clock signals P0, P90, P180, P270, and P360 are signals obtained by dividing signals I, Q, IB, QB, and I by an integer division ratio N using frequency divider 84. For example, if the period of signals I, Q, IB, QB, and I is 2×TVCO, the period of divided clock signals P0, P90, P180, P270, and P360 is N×2×TVCO. Furthermore, divided clock signals P0, P90, P180, P270, and P360 change their signal levels at edges corresponding to the edges of signals I, Q, IB, QB, and I. Furthermore, the phase difference between P0 and P90 corresponds to the phase difference between I and Q, and the phase difference between P90 and P180 corresponds to the phase difference between Q and IB. The phase difference between P180 and P270 corresponds to the phase difference between IB and QB, and the phase difference between P270 and P360 corresponds to the phase difference between QB and I.

[0101] In this way, the multi-phase clock signal generating circuit 82 outputs a plurality of divided clock signals P0, P90, P180, P270, and P360 having different phases, which are clock signals obtained by dividing the clock signals CK and XCK by an integer division ratio of N×2.

[0102] For example, Figure 16 The frequency divider 84 etc. corresponds to Figure 9 Frequency divider 88 is configured. For example, ΔΣ modulation circuit 90 performs ΔΣ modulation based on the fractional part of the frequency division ratio in frequency division ratio setting information SDIV, and accumulator 94 accumulates the output value of the ΔΣ modulation circuit. Then, arithmetic circuit 92 outputs an integer frequency division control code that sets the integer frequency division ratio N to frequency divider 84. Furthermore, arithmetic circuit 92 outputs an interpolation control code based on the accumulated value of the accumulator to phase interpolation circuit 30 and multiplexer 86.

[0103] Multiplexer 86 selects the i-th divided clock signal PCK1 and the (i+1)-th divided clock signal PCK2 from the divided clock signals P0, P90, P180, P270, and P360 based on the upper bits of M[4:0], i.e., M[4:3], which is the interpolation control code, from the control circuit. For example, if the upper bits of the interpolation control code, i.e., M[4:3], determine that the signal is in the first quadrant of 0 to 90 degrees, divided clock signals P0 and P90 are selected as PCK1 and PCK2. If the signal is in the second quadrant of 90 to 180 degrees, divided clock signals P90 and P180 are selected as PCK1 and PCK2. In addition, when it is judged that it is the third quadrant of 180 to 270 degrees according to the high bit of the interpolation control code, i.e. M[4:3], P180 and P270 are selected as PCK1 and PCK2. When it is judged that it is the fourth quadrant of 270 to 360 degrees, P270 and P360 are selected as PCK1 and PCK2.

[0104] Phase interpolation circuit 30 then outputs, as divided clock signal DVCK, an interpolated clock signal selected based on the lower bits of M[4:0], for example, M[2:0], which serves as the interpolation control code, from among the multiple interpolated clock signals generated by phase interpolation of the i-th divided clock signal PCK1 and the (i+1)-th divided clock signal PCK2. This interpolated clock signal DVCK corresponds to interpolated clock signal PICK. Here, i is an integer greater than or equal to 1. Furthermore, PCK1 and PCK2 are also included in the interpolated clock signals selected. For example, assuming that quadrant 1 is determined based on the upper bits of the interpolation control code, M[4:3], divided clock signals P0 and P90 are selected as PCK1 and PCK2. In this case, the phase interpolation circuit 30 outputs an interpolation clock signal selected according to the low bit M[2:0] of the interpolation control code from among a plurality of interpolated clock signals generated by 8-division phase interpolation based on the i-th divided clock signal PCK1=P0 and the i+1-th divided clock signal PCK2=P90, as the divided clock signal DVCK.

[0105] In this manner, the phase interpolation circuit 30 selects the divided clock signal DVCK, a clock signal for phase comparison with the reference clock signal RFCK, from among the multiple interpolated clock signals generated by phase interpolation of the i-th divided clock signal PCK1 and the (i+1)-th divided clock signal PCK2 based on the multiple divided clock signals P0, P90, P180, P270, and P360, based on the interpolation control code. This implements a phase interpolation-type frequency divider circuit 80. By using interpolated clock signals that have undergone high-resolution phase division, the phase interpolation-type frequency divider circuit 80 can reduce the magnitude of frequency deviation due to ΔΣ modulation, thereby generating a clock signal CK with reduced phase noise.

[0106] For example, in Figure 16 In the embodiment, the phase is divided into 4 by the multi-phase clock signal generating circuit 82, and the phase is divided into 8 by the phase interpolation circuit 30, thereby performing 32-part phase division. And, by the interpolation control code based on the accumulated value of the accumulator 94 that accumulates the output of the ΔΣ modulation circuit 90, any one of the clock signals of the phases after these 32 divisions is selected and output as the divided clock signal DVCK. In this case, the accumulator 94 that accumulates the output of the ΔΣ modulation circuit 90 accumulates the phase, for example, at the timing of the transition from 31 to 0 in the 32-part phase division, that is, the timing of the phase rotating one circle, as shown in FIG. Figure 17As shown in H1, a carry signal is output from the arithmetic circuit 92 to the frequency divider 84. Consequently, as shown in H2, the integer division ratio of the frequency divider 84 is carried from N to N+1. Furthermore, at the timing of the transition from 0 to 31 during the phase division of 32, a carry-down signal is output from the arithmetic circuit 92 to the frequency divider 84, and the integer division ratio of the frequency divider 84 is decremented.

[0107] In this way, Figure 16 In the embodiment, the phase interpolation circuit 30 performs phase interpolation of the 8 divisions in each of the 1st to 4th quadrants. For example, Figure 16 PCK1 corresponds to the clock signal CK1 as the first clock signal, and PCK2 corresponds to the clock signal CK2 as the second clock signal. Figure 12 When the circuit of the comparative example is used as the phase interpolation circuit 30, as shown in FIG. Figure 13 As shown, the phase difference variation becomes larger and the phase noise deteriorates.

[0108] In this regard, in this embodiment, by Figures 1 to 6 The phase interpolation circuit 30 of the structure described in the above is performed Figure 16 The 8-division phase interpolation in each quadrant of . Thus, as Figure 14 As shown, Figure 13 In comparison, it can reduce phase difference deviation and phase noise.

[0109] Figure 18 and Figure 19 Another configuration example of the phase interpolation circuit 30 is shown. Figure 4 、 Figure 5 This is an example of a structure when performing 8-division phase interpolation. In contrast, Figure 18 、 Figure 19 This is an example of a configuration when performing 16-division phase interpolation.

[0110] exist Figure 18 In, relative to Figure 4 The current source circuit 40 is further provided with a current source transistor TS4 and a dummy transistor DM3. Figure 19 In, relative to Figure 5 The current control circuit 50 is further provided with a selector SL4 which outputs a selection clock signal SCK4. Figure 18 In the example, the number k of unit transistors of the dummy transistors DM0, DM1, and DM2 is different. In DM0 and DM1, k=7, and in DM2, k=6. In addition, the number of unit transistors of the dummy transistor DM3 is k=4. That is, in Figure 4 In the example, the total number KT of the current source transistors and the dummy transistors is KT=4. Figure 18KT = 8. This KT = 8 corresponds to the number of unit transistors of the current source transistor TS4, and the current source transistor TS4 flows a current of 8I to the node N1.

[0111] Figure 20 It is an explanation Figure 18 and Figure 19 The truth table of the operation of the phase interpolation circuit 30 is shown in FIG. Figure 20 As shown, in Figure 18 and Figure 19 In the example, PI<4:1> of 4 bits is input to the current source circuit 40 as the phase interpolation signal PI. Figure 20 In the embodiment, a current source transistor TS4 is further provided, to which the selection clock signal SCK4 is input and through which a current of 8I flows, so that a current ratio of 1:15 to 16:0 is set. This enables 16-part phase interpolation.

[0112] And, according to Figure 18 、 Figure 19 The structure is not set as Figure 16 The multi-phase clock signal generating circuit 82 and the multiplexer 86 for generating the divided clock signal corresponding to each quadrant as shown can be used to reduce the circuit scale. Figure 18 、 Figure 19 In the case of a structure, for example, the clock signals CK1 and CK2 of the divided clock signals based on the integer frequency divider can be input to the phase interpolation circuit 30. Figure 16 The phase division of the first to fourth quadrants, which is 8×4=32, corresponds to the phase division of the first to fourth quadrants, which is 8×4=32, due to the frequency division by the divider 83. Figure 18 、 Figure 19 The structure divides the phase from 0 to 2π (360 degrees) into 16 parts.

[0113] And, in Figure 18 、 Figure 19 In the structure, do not set Figure 16 Such a multi-phase clock signal generating circuit 82 and multiplexer 86 can directly divide the phase of 0 to 2π into 16 parts, thereby reducing the phase difference deviation. Figure 14 is through Figure 16 The simulation results of phase difference deviation when the structure is divided into 8 quadrants, Figure 15 is through Figure 18 、 Figure 19 The simulation results of the phase difference deviation when the structure is directly divided into 16 parts. Figure 18 、 Figure 19 The structure, such as Figure 15 As shown, Figure 14 In comparison, the phase difference deviation can be further reduced and the phase noise can be further reduced.

[0114] As described above, the phase interpolation circuit 30 of this embodiment generates the interpolated clock signal PICK obtained by performing phase interpolation on the clock signal CK1 as the first clock signal and the clock signal CK2 as the second clock signal. Figure 1 As shown, the phase interpolation circuit 30 includes a current source circuit 40, a discharge transistor TD, a current control circuit 50, and an output circuit 60. The current source circuit 40 is provided between the power supply node ND as the first power supply node and the node N1 as the first node, and supplies the first current I1 that flows when the clock signal CK1 becomes valid and the second current I2 that flows when the clock signal CK2 becomes valid to the node N1. The discharge transistor TD is provided between the node N1 and the power supply node NG as the second power supply node, and is turned on when the clock signals CK1 and CK2 are not valid. Figure 4 、 Figure 5 For example, when the clock signals CK1 and CK2 are at an inactive level, i.e., a high level, the control signal SDS becomes a high level, thereby turning on the discharge transistor TD. The current control circuit 50 sets the current ratio of the current I1 to the current I2 based on the phase interpolation signal PI of the clock signals CK1 and CK2. Figure 6 Then, the output circuit 60 outputs the interpolation clock signal PICK according to the signal SQ of the node N1. Figure 4 The output circuit 60 of the structure described in the above etc. outputs the interpolation clock signal PICK.

[0115] Thus, according to this embodiment, when the clock signal CK1 is valid, the current I1 is supplied from the current source circuit 40 to the node N1, and when the clock signal CK2 is valid, the current I2 is supplied from the current source circuit 40 to the node N1. Furthermore, when the clock signals CK1 and CK2 become inactive, the discharge transistor TD is turned on, and discharge at the node N1 is performed. Furthermore, the current control circuit 50 sets the current ratio of the current I1 to the current I2 based on the phase interpolation signal PI. Thus, as Figure 2 、 Figure 3 As described in , the phase interpolation of the clock signals CK1 and CK2 can be performed at a phase division ratio corresponding to the current ratio of the currents I1 and I2. Figure 12 By simply configuring the phase division units as in the comparative example, the linearity of the phase division can be improved and the variation between samples can be reduced. Furthermore, the complex wiring required in the comparative example can be eliminated, which allows for a smaller circuit and lower power consumption.

[0116] Furthermore, for example, it is assumed that the phase interpolation signal PI is input to the phase interpolation circuit 30, that is, the phase interpolation signal PI generates an interpolated clock signal PICK whose phase is closer to the signal corresponding to the clock signal CK1 than the signal corresponding to the clock signal CK2. In this case, the current control circuit 50 sets a current ratio such that the current I1 is larger than the current I2. If the current ratio is set so that the current I1 is larger, as in Figure 2 As described in , the phase of the interpolation clock signal PICK can be brought close to the phase of the signal corresponding to the clock signal CK1. For example, by setting the current ratio of the currents I1 and I2, the phase of the interpolation clock signal PICK can be variably set.

[0117] Furthermore, for example, it is assumed that the phase interpolation signal PI is input to the phase interpolation circuit 30, that is, the phase interpolation signal PI generates an interpolated clock signal PICK whose phase is closer to the signal corresponding to the clock signal CK2 than to the signal corresponding to the clock signal CK1. In this case, the current control circuit 50 sets a current ratio such that the current I2 is larger than the current I1. If the current ratio is set so that the current I2 is larger, as in Figure 2 As described in , the phase of the interpolation clock signal PICK can be made close to the phase of the signal corresponding to the clock signal CK2. For example, by setting the current ratio of the currents I1 and I2, the phase of the interpolation clock signal PICK can be variably set.

[0118] In addition, as in Figure 3 As described in , when the current control circuit 50 receives the phase interpolation signal PI, which interpolates the phases of the signal corresponding to the clock signal CK1 and the signal corresponding to the clock signal CK2 at a ratio of m:n, it sets the current ratio of the currents I1 and I2 to n:m. By setting the current ratio of the currents I1 and I2 to n:m in this manner, an interpolated clock signal PICK can be generated, which is obtained by interpolating the phases of the signal corresponding to the clock signal CK1 and the signal corresponding to the clock signal CK2 at a ratio of m:n.

[0119] In addition, if Figure 4 As shown, output circuit 60 includes a capacitor CP, one end of which is connected to node N1, and a buffer circuit IV to which the signal at node N1 is input. The presence of capacitor CP and buffer circuit IV in output circuit 60 allows the capacitance of capacitor CP at node N1 to be charged using currents I1 and I2, which flow when clock signal CK1 is active and CK2 is active, respectively. Furthermore, signal SQ at node N1 can be input to buffer circuit IV to generate an interpolated clock signal PICK.

[0120] In addition, if Figure 4As shown, the current source circuit 40 includes a plurality of current source transistors TS0 to TS3 connected in parallel between the power supply node ND and the node N1. Figure 5 、 Figure 6 As shown, the current control circuit 50 outputs each of the multiple selected clock signals SCK0 to SCK3, selected from the clock signal CK1 or the clock signal CK2 based on the phase interpolation signal PI, to the gates of the multiple current source transistors TS0 to TS3. This allows the clock signal CK1 or the clock signal CK2 to be selected as the selected clock signals SCK0, SCK1, SCK2, and SCK3 based on the phase interpolation signal PI and input to the gates of the current source transistors TS0, TS1, TS2, and TS3. Furthermore, the current source transistors receiving the clock signal CK1 as the selected clock signal conduct when the clock signal CK1 is active, supplying current I1 to node N1. Furthermore, the current source transistors receiving the clock signal CK2 as the selected clock signal conduct when the clock signal CK2 is active, supplying current I2 to node N1. Consequently, currents I1 and I2 can be supplied to node N1 at a current ratio corresponding to the phase interpolation signal PI.

[0121] In addition, if Figure 5 As shown, the current control circuit 50 includes a plurality of selectors SL0-SL3. Each of the selectors SL0-SL3 outputs a selected clock signal SCK0-SCK3 to the gate of each current source transistor TS0-TS3. In this way, the selectors SL0-SL3 can be used to select either the clock signal CK1 or the clock signal CK2 as the selected clock signal based on the phase interpolation signal PI, and each selected clock signal SCK0-SCK3 is input to the gate of each current source transistor TS0-TS3.

[0122] In addition, if Figure 4 、 Figure 8 As shown, each current source transistor of TS0 to TS3 is composed of one or more unit transistors. For example, when the current source transistor is composed of a first unit transistor and a second unit transistor, the gate width and gate length of the first unit transistor are the same as the gate width and gate length of the second unit transistor. In this way, by forming each current source transistor with unit transistors, the current ratio of multiple current source transistors can be set according to the number of unit transistors. Thus, by setting the number of unit transistors, the current ratio of currents I1 and I2 can be set, and the division ratio of phase interpolation can be set. Moreover, by forming each current source transistor with unit transistors, the setting of the current ratio based on the current source transistor can be achieved more accurately, which can reduce the adverse effects of manufacturing deviations and the like.

[0123] Furthermore, the current source circuit 40 includes: a first current source transistor, a first selected clock signal selected from the clock signal CK1 or the clock signal CK2 according to the phase interpolation signal PI, is input to its gate; and a second current source transistor, a second selected clock signal selected from the clock signal CK1 or the clock signal CK2, is input to its gate. For example, Figure 4 In the embodiment, the first current source transistor is one of the current source transistors TS0 to TS3, and the second current source transistor is the other of the current source transistors TS0 to TS3. In addition, the first selection clock signal is one of the selection clock signals SCK0 to SCK3, and the second selection clock signal is the other of the selection clock signals SCK0 to SCK3. In this way, the current from the first current source transistor whose gate is input with the first selection clock signal and the current from the second current source transistor whose gate is input with the second selection clock signal can be supplied to the node N1. Moreover, when the clock signal CK1 is selected as the first selection clock signal, when the clock signal CK1 is valid, the current I1 from the first current source transistor can be supplied to the node N1. Furthermore, when the clock signal CK2 is selected as the second selection clock signal, when the clock signal CK2 is valid, the current I2 from the first current source transistor can be supplied to the node N1. Similarly, when clock signal CK1 is selected as the second selected clock signal, when clock signal CK1 is active, current I1 from the second current source transistor can be supplied to node N1. Furthermore, when clock signal CK2 is selected as the second selected clock signal, when clock signal CK2 is active, current I2 from the second current source transistor can be supplied to node N1.

[0124] In addition, the current source circuit 40 includes: a first dummy transistor, which is provided in parallel with the first current source transistor, the gate of which is input with the first selection clock signal, and the drain of which is not connected to the node N1; and a second dummy transistor, which is provided in parallel with the second current source transistor, the gate of which is input with the second selection clock signal, and the drain of which is not connected to the node N1. For example, in Figure 4 In the embodiment, the first dummy transistor is one of the dummy transistors DM0 to DM3 , and the second dummy transistor is the other one of the dummy transistors DM0 to DM3 .

[0125] Moreover, if Figure 8As shown, the sum of the gate area of ​​the first current source transistor and the gate area of ​​the first dummy transistor is equal to the sum of the gate area of ​​the second current source transistor and the gate area of ​​the second dummy transistor. Here, the sum of the gate areas is equal as long as the sum of the gate areas is substantially equal, which also includes the case where the sum of the gate areas is approximately equal. In addition, the gate area is determined by the gate width W and gate length L of the transistor, for example, corresponding to W×L. For example, in Figure 8 In this example, the sum of the gate areas of current source transistor TS0 and dummy transistor DM0 is equal to the sum of the gate areas of current source transistor TS2 and dummy transistor DM2. Furthermore, the sum of the gate areas of current source transistor TS1 and dummy transistor DM1 is equal to the sum of the gate areas of current source transistor TS2 and dummy transistor DM2. This makes it possible to make the gate capacitances of the transistors contributing to the selection clock signals SCK0, SCK1, SCK2, and SCK3 equal, and also makes the waveform blunting of the selection clock signals due to the gate capacitances equal. This improves the linearity of the phase interpolation of the interpolated clock signal PICK.

[0126] In addition, if Figure 9 As shown, the circuit device 20 of this embodiment includes a frequency divider circuit 80, which includes a phase interpolation circuit 30 and outputs an interpolated clock signal PICK from the phase interpolation circuit 30 as a feedback clock signal FBCK; and a phase comparison circuit 72, which compares the phases of the reference clock signal RFCK and the feedback clock signal FBCK. Furthermore, the circuit device 20 includes a control voltage generation circuit 73, which generates a control voltage VC based on the phase comparison result of the phase comparison circuit 72; and a voltage-controlled oscillation circuit 76, which generates a clock signal CK having a frequency corresponding to the control voltage VC. Furthermore, the phase interpolation circuit 30 generates the interpolated clock signal PICK based on the clock signal CK1 and the clock signal CK2, which are based on the clock signal CK. Thus, in the PLL circuit composed of the phase comparison circuit 72, the control voltage generation circuit 73, the voltage-controlled oscillation circuit 76, and the frequency divider circuit 80, the interpolated clock signal PICK generated by the phase interpolation circuit 30 can be input to the phase comparison circuit 72 as the feedback clock signal FBCK. This can reduce the frequency division resolution of the fractional frequency division performed by the frequency divider circuit 80, for example. Therefore, the phase variation width can be reduced, and the phase noise of the clock signal CK can be reduced.

[0127] 3. Oscillator

[0128] Figure 21 FIG. 4 shows a configuration example of an oscillator 4 of this embodiment. The oscillator 4 of this embodiment includes a circuit device 20 of this embodiment and an oscillator 10 for generating a reference clock signal RFCK. Figure 21In FIG, the vibrator 10 is electrically connected to the circuit device 20. For example, the vibrator 10 and the circuit device 20 are electrically connected using internal wiring, bonding wires, metal bumps, or the like of a package that houses the vibrator 10 and the circuit device 20.

[0129] The vibrator 10 is an element that generates mechanical vibrations by an electrical signal. The vibrator 10 can be implemented, for example, by a vibrating plate such as a quartz vibrating plate. For example, the vibrator 10 can be implemented by a quartz vibrating plate that performs thickness shear vibration with a cut angle such as AT cut or SC cut, a tuning fork type quartz vibrating plate, or a double tuning fork type quartz vibrating plate. For example, the vibrator 10 can be a vibrator built into an oscillator of an SPXO (Simple Packaged Crystal Oscillator), or a vibrator built into a temperature compensated quartz oscillator (TCXO) without a thermostat, or a vibrator built into an oven-controlled quartz oscillator (OCXO) with a thermostat. In addition, the vibrator 10 of this embodiment can also be implemented by various vibrating plates such as a thickness shear vibration type, a vibrating plate other than a tuning fork type or a double tuning fork type, or a piezoelectric vibrating plate formed of a material other than quartz. For example, as the vibrator 10 , a SAW (Surface Acoustic Wave) resonator, a MEMS (Micro Electro Mechanical Systems) vibrator which is a silicon vibrator formed using a silicon substrate, or the like may be adopted.

[0130] Figure 21 The circuit device 20 includes an oscillation circuit 130 , a PLL circuit 150 , a control circuit 160 , and an output circuit 180 .

[0131] The oscillation circuit 130 is a circuit that causes the oscillator 10 to oscillate. For example, the oscillation circuit 130 generates an oscillation signal by causing the oscillator 10 to oscillate. For example, the oscillation circuit 130 can be implemented by an oscillation drive circuit electrically connected to one end and the other end of the oscillator 10, as well as passive components such as capacitors and resistors. The drive circuit can be implemented, for example, by a CMOS inverter circuit or a bipolar transistor. The drive circuit is the core circuit of the oscillation circuit 130, and the drive circuit drives the oscillator 10 by voltage or current, thereby causing the oscillator 10 to oscillate. As the oscillation circuit 130, various types of oscillation circuits such as inverter type, Pierce type, Colpitts type, or Hartley type can be used. In addition, the connection in this embodiment is an electrical connection. An electrical connection is a connection in a manner that can transmit an electrical signal, and is a connection that can transmit information based on the electrical signal. The electrical connection can also be a connection via passive components, etc.

[0132] The PLL circuit 150 is implemented using circuits such as the phase interpolation circuit 30 of this embodiment. A clock signal based on the oscillation signal generated by the oscillator 10 oscillating the oscillator circuit 130 is input to the PLL circuit 150 as the reference clock signal RFCK. The PLL circuit 150 then compares the phases of the reference clock signal RFCK, which is based on the oscillation signal of the oscillator 10, with the feedback clock signal FBCK, and generates the clock signal CK through charge pump operation and other means. Furthermore, the PLL circuit 150 can perform synchronization operation using the FLL operation when the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK does not fall within the dead zone, and can perform synchronization operation using the SPLL operation when the phase difference falls within the dead zone.

[0133] Control circuit 160 is a logic circuit that performs various control and computational processing. For example, control circuit 160 controls the entire circuit device 20 or controls the operating sequence of circuit device 20. Furthermore, control circuit 160 performs various processes for controlling oscillation circuit 130. Control circuit 160 can be implemented, for example, as an ASIC (Application Specific Integrated Circuit) circuit based on an automated configuration and routing (ACI) such as a gate array.

[0134] Furthermore, the control circuit 160 includes a ΔΣ modulation circuit 162 and an operation circuit 163, and the operation circuit 163 includes an accumulator 164. The ΔΣ modulation circuit 162, the operation circuit 163, and the accumulator 164 correspond to Figure 9 ΔΣ modulation circuit 90, operation circuit 92, and accumulator 94.

[0135] Output circuit 180 buffers the clock signal CK from PLL circuit 150 and outputs an output clock signal CKQ. This output clock signal CKQ becomes the external output clock signal of oscillator 4. Output circuit 180 also receives an external output enable signal OE as input. When output enable signal OE is active, output circuit 180 outputs output clock signal CKQ. Thus, output clock signal CKQ is output to the outside of oscillator 4. On the other hand, when output enable signal OE is inactive, the output terminal of output clock signal CKQ is set to a fixed voltage, such as a low level.

[0136] In addition, Figure 21 In this case, the oscillator 4 is an SPXO oscillator. Specifically, the oscillator 4 is a programmable SPXO that can output an output clock signal CKQ of any frequency according to the frequency division ratio setting code set in the PLL circuit 150. Figure 21In the structure of , a temperature compensation circuit that performs temperature compensation processing based on the temperature detection result of the temperature sensor can also be provided, and the structure of the oscillator 4 of TCXO can be set. In this case, a variable capacitance circuit that controls the capacitance by the temperature compensation voltage from the temperature compensation circuit can be provided in the oscillation circuit 130.

[0137] As described above, the phase interpolation circuit of this embodiment generates an interpolated clock signal by phase interpolating a first clock signal and a second clock signal having a different phase from the first clock signal. Furthermore, the phase interpolation circuit includes: a current source circuit, disposed between a first power supply node and a first node, that supplies a first current to the first node when the first clock signal is valid and a second current to the first node when the second clock signal is valid; and a discharge transistor, disposed between the first node and a second power supply node, that conducts when the first and second clock signals are inactive. The phase interpolation circuit further includes: a current control circuit that sets the current ratio between the first and second currents based on a phase interpolation signal indicating the phase interpolation ratio between the first and second clock signals; and an output circuit that outputs the interpolated clock signal based on the signal at the first node.

[0138] According to this embodiment, when the first clock signal is valid, a first current is supplied from the current source circuit to the first node, and when the second clock signal is valid, a second current is supplied from the current source circuit to the first node. Furthermore, when the first and second clock signals are inactive, the discharge transistor is turned on, causing discharge at the first node. Furthermore, the current control circuit sets the current ratio between the first and second currents based on the phase interpolation signal. This allows the phases of the first and second clock signals to be interpolated at a phase division ratio corresponding to the current ratio between the first and second currents. This improves the linearity of the phase division in the interpolated clock signal, and also enables circuit miniaturization and reduced power consumption.

[0139] In addition, in this embodiment, when a phase interpolation signal that generates an interpolated clock signal whose phase is closer to the signal corresponding to the first clock signal than the signal corresponding to the second clock signal is input, the current control circuit sets a current ratio so that the first current is greater than the second current.

[0140] By setting the current ratio so that the first current is larger, the phase of the interpolation clock signal can be brought closer to the phase of the signal corresponding to the first clock signal, and the phase of the interpolation clock signal can be set by setting the current ratio.

[0141] In addition, in this embodiment, when a phase interpolation signal that generates an interpolated clock signal whose phase is closer to the signal corresponding to the second clock signal than the signal corresponding to the first clock signal is input, the current control circuit sets a current ratio so that the second current is greater than the first current.

[0142] By setting the current ratio so that the second current is larger, the phase of the interpolation clock signal can be brought closer to the phase of the signal corresponding to the second clock signal, and the phase of the interpolation clock signal can be set by setting the current ratio.

[0143] In addition, in this embodiment, when a phase interpolation signal that performs phase interpolation of a signal corresponding to the first clock signal and a signal corresponding to the second clock signal with a ratio of m:n is input, the current control circuit sets the current ratio of the first current to the second current to n:m.

[0144] By setting the current ratio of the first current to the second current to n:m in this manner, an interpolated clock signal can be generated by phase-interpolating the signal corresponding to the first clock signal and the signal corresponding to the second clock signal at m:n.

[0145] Furthermore, in the present embodiment, the output circuit may include a capacitor having one end connected to the first node and a buffer circuit to which the signal of the first node is input.

[0146] In this manner, the capacitance of the capacitor at the first node is charged by the first current and the second current, and the signal at the first node is input to the buffer circuit, thereby generating an interpolated clock signal.

[0147] In addition, in this embodiment, the current source circuit may include a plurality of current source transistors arranged in parallel between the first power supply node and the first node, and the current control circuit outputs each selected clock signal of a plurality of selected clock signals selected from the first clock signal or the second clock signal according to the phase interpolation signal to the gate of each current source transistor of the plurality of current source transistors.

[0148] In this way, the first clock signal or the second clock signal can be selected as the selected clock signal according to the phase interpolation signal, input into the gate of the current source transistor, and the first current when the first clock signal is valid and the second current when the second clock signal is valid are supplied to the first node.

[0149] Furthermore, in this embodiment, the current control circuit may include a plurality of selectors, and each of the plurality of selectors may output a selection clock signal to a gate of each current source transistor.

[0150] In this manner, the selector can be used to select the first clock signal or the second clock signal as the selected clock signal, and each selected clock signal can be input to the gate of each current source transistor.

[0151] In addition, in this embodiment, each current source transistor may be formed of one or more unit transistors.

[0152] In this way, the current ratio of the plurality of current source transistors can be set according to the number of unit transistors.

[0153] In addition, in this embodiment, the current source circuit may include: a first current source transistor, a gate of which is input with a first selected clock signal selected from the first clock signal or the second clock signal based on the phase interpolation signal; and a second current source transistor, a gate of which is input with a second selected clock signal selected from the first clock signal or the second clock signal based on the phase interpolation signal.

[0154] In this manner, the current from the first current source transistor having the first selection clock signal input to the gate and the current from the second current source transistor having the second selection clock signal input to the gate can be supplied to the first node.

[0155] In this embodiment, the current source circuit may include: a first dummy transistor provided in parallel with the first current source transistor, having a gate to which the first selection clock signal is input and a drain not connected to the first node; and a second dummy transistor provided in parallel with the second current source transistor, having a gate to which the second selection clock signal is input and a drain not connected to the first node. Furthermore, the sum of the gate area of ​​the first current source transistor and the gate area of ​​the first dummy transistor may be equal to the sum of the gate area of ​​the second current source transistor and the gate area of ​​the second dummy transistor.

[0156] In this way, the gate capacitances of the transistors added to the first selected clock signal and the second selected clock signal can be made equal to each other, the blunting of the waveforms of the first selected clock signal and the second selected clock signal due to the gate capacitance can also be made equal, and the linearity of the phase interpolation of the interpolated clock signal can be improved.

[0157] Furthermore, the circuit device of this embodiment includes: a frequency divider circuit including the phase interpolation circuit described above, which outputs an interpolated clock signal from the phase interpolation circuit as a feedback clock signal; a phase comparison circuit that compares the phases of a reference clock signal and the feedback clock signal; a control voltage generation circuit that generates a control voltage based on the phase comparison result of the phase comparison circuit; and a voltage-controlled oscillation circuit that generates a clock signal having a frequency corresponding to the control voltage. Furthermore, the phase interpolation circuit generates the interpolated clock signal based on a first clock signal and a second clock signal that are based on the clock signal.

[0158] In this way, in the PLL circuit composed of the phase comparison circuit, the control voltage generation circuit, the voltage-controlled oscillation circuit, and the frequency division circuit, the interpolation clock signal generated by the phase interpolation circuit can be input to the phase comparison circuit as a feedback clock signal.

[0159] Furthermore, the oscillator of this embodiment includes the circuit device described above and an oscillator for generating a reference clock signal.

[0160] In addition, the present embodiment has been described in detail as described above, but those skilled in the art can easily understand that various modifications can be made without substantially departing from the new matters and effects of the present disclosure. Therefore, all such modifications are included in the scope of the present disclosure. For example, in the specification or the drawings, a term that is recorded at least once together with a different term in a broader sense or with the same meaning can be replaced with the different term in any part of the specification or the drawings. In addition, all combinations of the present embodiment and the modifications are also included in the scope of the present disclosure. In addition, the structure and operation of the phase interpolation circuit, circuit device, oscillator, etc. are not limited to the contents described in the present embodiment, and various modifications can be implemented.

Claims

1. A phase interpolation circuit, characterized in that: An interpolated clock signal is generated by phase interpolation between a first clock signal and a second clock signal having a different phase from the first clock signal, the phase interpolation circuit comprising: a current source circuit provided between a first power supply node and a first node, and supplying a first current flowing when the first clock signal is active and a second current flowing when the second clock signal is active to the first node; a discharge transistor provided between the first node and a second power supply node and turned on when the first clock signal and the second clock signal are inactive; a current control circuit configured to set a current ratio between the first current and the second current based on a phase interpolation signal indicating a phase interpolation ratio between the first clock signal and the second clock signal; as well as An output circuit outputs the interpolated clock signal based on the signal of the first node.

2. The phase interpolation circuit according to claim 1, wherein: When the phase interpolation signal generating the interpolation clock signal having a phase closer to the signal corresponding to the first clock signal than the signal corresponding to the second clock signal is input, the current control circuit sets the current ratio so that the first current is greater than the second current.

3. The phase interpolation circuit according to claim 1, wherein: When the phase interpolation signal generating the interpolation clock signal having a phase closer to the signal corresponding to the second clock signal than the signal corresponding to the first clock signal is input, the current control circuit sets the current ratio so that the second current is greater than the first current.

4. The phase interpolation circuit according to claim 1, wherein: When the phase interpolation signal that performs phase interpolation on the signal corresponding to the first clock signal and the signal corresponding to the second clock signal at a ratio of m:n is input, the current control circuit sets the current ratio of the first current to the second current to n:m.

5. The phase interpolation circuit according to claim 1, wherein: The output circuit comprises: a capacitor having one end connected to the first node; and A buffer circuit is provided to which the signal of the first node is input.

6. The phase interpolation circuit according to claim 1, wherein: The current source circuit includes a plurality of current source transistors connected in parallel between the first power supply node and the first node. The current control circuit outputs each of a plurality of selected clock signals selected from the first clock signal or the second clock signal according to the phase interpolation signal to a gate of each of the plurality of current source transistors.

7. The phase interpolation circuit according to claim 6, characterized in that: The current control circuit includes a plurality of selectors, Each of the plurality of selectors outputs the selection clock signal to the gate of each current source transistor.

8. The phase interpolation circuit according to claim 6, wherein: Each of the current source transistors is composed of one or more unit transistors.

9. The phase interpolation circuit according to claim 1, wherein: The current source circuit comprises: a first current source transistor having a gate to which a first selected clock signal selected from the first clock signal or the second clock signal according to the phase interpolation signal is input; as well as A second selected clock signal selected from the first clock signal or the second clock signal based on the phase interpolation signal is input to a gate of the second current source transistor.

10. The phase interpolation circuit according to claim 9, characterized in that: The current source circuit comprises: a first dummy transistor provided in parallel with the first current source transistor, having a gate to which the first selection clock signal is input and a drain not connected to the first node; as well as a second dummy transistor provided in parallel with the second current source transistor, the second selection clock signal being input to a gate thereof and the drain thereof being not connected to the first node; The sum of the gate area of ​​the first current source transistor and the gate area of ​​the first dummy transistor is equal to the sum of the gate area of ​​the second current source transistor and the gate area of ​​the second dummy transistor.

11. A circuit device, characterized in that: The circuit arrangement comprises: a frequency dividing circuit comprising the phase interpolation circuit according to any one of claims 1 to 10, outputting the interpolated clock signal from the phase interpolation circuit as a feedback clock signal; a phase comparison circuit for performing phase comparison between a reference clock signal and the feedback clock signal; a control voltage generating circuit, which generates a control voltage according to a phase comparison result of the phase comparison circuit; as well as a voltage-controlled oscillation circuit that generates a clock signal having a frequency corresponding to the control voltage, The phase interpolation circuit generates the interpolated clock signal based on the first clock signal and the second clock signal which are based on the clock signal.

12. An oscillator, characterized in that: The oscillator contains: The circuit device of claim 11; and An oscillator is used to generate the reference clock signal.

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