Storage array, memory and electronic equipment

Abstract

The invention provides a storage array, a memory and electronic equipment, relates to the technical field of semiconductors, and is used for solving the problem of how to improve the accuracy of acquiring the temperature of an integrated circuit. The storage array comprises a substrate, a storage unit, a sensing transistor and a plurality of first film layers formed on the substrate. The storage unit is arranged on the substrate and comprises a first transistor; the sensing transistor and the first transistor are arranged on the substrate at an interval; the first transistors are formed in the plurality of first film layers, and the sensing transistors are formed in a plurality of first film layers in the plurality of first film layers; the sense transistor is configured to output a first signal related to a temperature of the memory array. The memory array is used for forming a memory and storing data.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a storage array, a memory, and an electronic device. Background Art

[0002] With the advent of the digital economy, integrated circuits (ICs) are widely used in various fields of life. To improve IC performance, such as reducing power consumption, IC integration is becoming increasingly dense. This, in turn, results in an increasing heat generation. Therefore, thermal management of ICs has become an unavoidable issue.

[0003] Thermal management is premised on measuring the integrated circuit's temperature. The more accurate the temperature measurement, the better the thermal management and performance of the integrated circuit. For example, dynamic random access memory (DRAM) requires constant refresh to maintain stored data. The refresh rate is dynamically adjusted based on the measured temperature. In other words, the accuracy of temperature measurement affects the precision of the refresh rate adjustment.

[0004] Therefore, how to improve the accuracy of obtaining the temperature of integrated circuits is an urgent problem to be solved. Summary of the Invention

[0005] Embodiments of the present application provide a storage array, a memory, and an electronic device to solve the problem of how to improve the accuracy of memory temperature detection.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, embodiments of the present application provide a memory array comprising: a substrate, a memory cell, a sensing transistor, and a plurality of first film layers formed on the substrate. The memory cell is disposed on the substrate and includes a first transistor; the sensing transistor is disposed on the substrate with a spacing therebetween; the first transistor is formed in the plurality of first film layers, and the sensing transistor is formed in a plurality of the plurality of first film layers; the sensing transistor is configured to output a first signal, the first signal being related to the temperature of the memory array.

[0008] Because the first transistor is disposed in a plurality of first film layers formed on the substrate, and the sensing transistor is also disposed in some of the plurality of first film layers, that is, the sensing transistor is disposed within the memory array, the sensing transistor can be disposed close to the first transistor, thereby reducing the distance between the sensing transistor and the first transistor. The temperature at the location of the sensing transistor can be closer to the temperature of the memory array, that is, the sensing transistor can more accurately obtain the temperature of the memory array.

[0009] In addition, the refresh frequency of the memory array can be controlled according to the temperature of the memory array. After accurately obtaining the temperature of the memory array, the lowest refresh frequency can be selected for refresh, thereby reducing the power consumption of the memory array. In one possible implementation of the first aspect, the sensing transistor and the first transistor are both formed using a back-end process. In this way, the sensing transistor and the first transistor can be both arranged in a plurality of first film layers formed on the substrate. Moreover, when preparing the memory array, preparing the sensing transistor by a back-end process can improve the process compatibility of preparing the sensing transistor, and can prepare the sensing transistor at the same time as preparing the first transistor, reducing the process steps of the preparation and improving production efficiency.

[0010] In one possible implementation of the first aspect, the sensing transistor includes a source, a channel, a drain, and a gate. The source, channel, and drain are arranged along the thickness of the substrate, and the gate is arranged around the channel. In this way, the sensing transistor can be perpendicular to the substrate, thereby reducing the area occupied by the sensing transistor and facilitating an increase in the number of memory cells in the memory array.

[0011] In one possible implementation of the first aspect, the sensing transistor is a junctionless field-effect transistor. Since the first signal output by the junctionless field-effect transistor has a good linear correlation with temperature, using the junctionless field-effect transistor as a temperature sensing device is beneficial for improving temperature sensing accuracy.

[0012] In one possible implementation of the first aspect, the source and drain of the sensing transistor are connected, and the source and drain are configured to output a first signal. In this manner, the first signal output by the sensing transistor is a gate leakage current, and the logarithm of the gate leakage current of the sensing transistor has a good linear correlation with temperature, thereby improving temperature sensing accuracy.

[0013] In one possible implementation of the first aspect, one of the source and the drain is connected to the gate, and the one of the source and the drain and the gate are configured to output the first signal. In this manner, the first signal output by the junctionless field-effect transistor is a voltage signal, and a curve of the voltage signal varying with temperature is approximately a straight line. Therefore, the first signal output by the junctionless field-effect transistor in this manner can also be used to sense temperature.

[0014] In one possible implementation of the first aspect, there are multiple sensing transistors, each of which is connected in parallel. By providing multiple sensing transistors and summing the signals output by each sensing transistor in parallel to obtain and output the first signal, the magnitude of the output first signal can be increased, facilitating processing of the first signal and improving sensing accuracy.

[0015] In a possible implementation of the first aspect, a plurality of sensing transistors are disposed adjacent to each other, so as to facilitate the arrangement of signal lines for outputting the first signal from the plurality of sensing transistors.

[0016] In one possible implementation of the first aspect, the first transistor includes a source, a channel, a drain, and a gate, wherein the source, channel, and drain are arranged along the thickness of the substrate, and the gate is arranged around the channel. Thus, when the sensing transistor includes a source, a channel, a drain, and a gate, wherein the source, channel, and drain are arranged along the thickness of the substrate, and the gate is arranged around the channel, the first transistor and the sensing transistor have the same structure, and therefore the first transistor and the sensing transistor can be manufactured simultaneously using the same process, thereby reducing the number of manufacturing process steps.

[0017] In one possible implementation of the first aspect, the memory array further includes a second capacitor connected to the sensing transistor; the second capacitor includes a third electrode and a fourth electrode, the third electrode surrounding the fourth electrode, and the fourth electrode extending along the thickness of the substrate. In this manner, the second capacitor can be used to form a circuit that converts the first signal output by the sensing transistor into a digital signal, and the second capacitor can be integrated into the memory array. Furthermore, because the fourth electrode of the second capacitor extends along the thickness of the substrate, the area occupied by the second capacitor can be reduced, thereby increasing the integration density of the memory array.

[0018] In one possible implementation of the first aspect, the memory cell further includes a first capacitor connected to the first transistor; the memory array includes multiple second film layers forming the first capacitors, and the second capacitors are formed in several of the multiple second film layers. In this way, the film layers forming the first capacitors are utilized as the film layers, eliminating the need for additional film layers for forming the second capacitors. This reduces the number of film layers stacked and facilitates improved storage density.

[0019] In one possible implementation of the first aspect, the first capacitor includes a third electrode and a fourth electrode, the third electrode surrounds the fourth electrode, and the fourth electrode extends along the thickness direction of the substrate. Thus, when the second capacitor includes a first electrode and a second electrode, the first electrode surrounds the second electrode, and the second electrode extends along the thickness direction of the substrate, the structure of the first capacitor and the second capacitor are identical, and therefore, the first capacitor and the second capacitor can be manufactured simultaneously.

[0020] In a second aspect, the present application provides a memory device comprising a memory array according to any one of the first aspects and an analog-to-digital conversion circuit; the analog-to-digital conversion circuit is configured to output a first digital signal based on a first signal output by a sensing transistor in the memory array, wherein the first digital signal is related to the temperature of the memory array. Thus, the analog-to-digital conversion circuit converts the first analog signal into the first digital signal, thereby facilitating acquisition of a digital temperature signal from the first digital signal.

[0021] In one possible implementation of the second aspect, the analog-to-digital conversion circuit includes a selector, a comparator, and a control unit connected in sequence; the selector includes multiple input terminals and an output terminal, the selector is configured to receive different reference voltage signals via the multiple input terminals, and output a reference voltage signal corresponding to the input terminal from the output terminal by selecting any input terminal; the comparator is configured to receive a first signal and a reference voltage signal, and output a comparison signal, the comparison signal being used to represent the magnitude relationship between the first signal and the reference voltage signal; the control unit is configured to receive the comparison signal, control the selector to change the selected input terminal, and, upon determining the reference voltage signal corresponding to the first signal, output a voltage digital signal, the voltage digital signal being related to the reference voltage signal corresponding to the first signal. In this way, the reference voltage signal is selected by the selector, the magnitude relationship between the reference voltage signal and the first signal is obtained by the comparator, and the reference voltage signal corresponding to the first signal is determined by the control unit, thereby outputting a voltage digital signal related to the determined reference voltage signal, which is the first digital signal.

[0022] In one possible implementation of the second aspect, the storage array includes a second capacitor, and the analog-to-digital conversion circuit includes a trigger and a time-to-digital converter. The second capacitor is connected to the trigger and to a sensing transistor of the storage array. The trigger is configured to control a first signal to charge the second capacitor based on a charge state of the second capacitor, where the charging time is related to the temperature of the storage array. The time-to-digital converter is configured to convert the charging time into a time digital signal and output the time digital signal. In this manner, the second capacitor, the trigger, and the time-to-digital converter can be used to convert the first signal into a first digital signal, thereby forming a time-domain temperature sensor. The time digital signal is the first digital signal.

[0023] In one possible implementation of the second aspect, the analog-to-digital conversion circuit includes an oscillator, a clock generator, and a second counter; the oscillator is configured to output a first oscillation signal based on a first signal, the first oscillation signal being related to the temperature of the storage array; the clock generator is configured to output a clock signal; and the second counter is configured to output an oscillation frequency digital signal based on the clock signal. In this manner, the first signal can be converted into an oscillation frequency digital signal by the oscillator, the clock generator, and the second counter, thereby forming a frequency-domain temperature sensor, wherein the oscillation frequency digital signal is the first digital signal.

[0024] In one possible implementation of the second aspect, the analog-to-digital conversion circuit includes a second transistor, and the source, drain, and channel of the second transistor are formed in the substrate of the memory array. In this way, at least a portion of the analog-to-digital conversion circuit is integrated into the substrate, reducing the size of the memory.

[0025] In one possible implementation of the second aspect, the memory further includes a processing unit connected to the analog-to-digital conversion circuit, the processing unit being configured to output a temperature digital signal based on the first digital signal. In this manner, the temperature digital signal is obtained from the first digital signal, and the temperature digital signal can be used to control memory operation and improve memory performance.

[0026] In a third aspect, the present application provides an electronic device comprising a printed circuit board and a memory as described in any one of the second aspects, wherein the memory is disposed on the printed circuit board. In this way, since the memory used in the electronic device has good performance, the performance of the electronic device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of an electronic device provided in an embodiment of the present application;

[0028] Figure 2 A schematic diagram of a memory provided in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of the structure of a storage array provided in an embodiment of the present application;

[0030] Figure 4 A schematic diagram of multiple sensing transistors connected in parallel according to an embodiment of the present application;

[0031] Figure 5 A schematic diagram of the structure of another storage array provided in an embodiment of the present application;

[0032] Figure 6 A schematic structural diagram of a junctionless field effect transistor provided in an embodiment of the present application;

[0033] Figure 7 for Figure 6 a graph showing a first signal outputted by the junctionless field effect transistor and temperature;

[0034] Figure 8 A schematic diagram of another junctionless field effect transistor outputting a first signal provided by an embodiment of the present application;

[0035] Figure 9 for Figure 8 a graph showing a first signal outputted by the junctionless field effect transistor and temperature;

[0036] Figure 10 A schematic diagram of obtaining a temperature digital signal based on the output of a sensing transistor according to an embodiment of the present application;

[0037] Figure 11 A schematic diagram of an analog-to-digital conversion circuit provided in an embodiment of the present application;

[0038] Figure 12 A schematic diagram of another analog-to-digital conversion circuit provided in an embodiment of the present application;

[0039] Figure 13 A schematic diagram of another analog-to-digital conversion circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] Unless otherwise defined, the technical or scientific terms used in this application should have the usual meanings understood by those skilled in the art. The terms "first", "second", "third" and similar words used in this specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Thus, features defined as "first", "second", and "third" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, "multiple" means two or more.

[0041] The directional terms such as "left", "right", "up" and "down" are defined relative to the orientation of the device schematically placed in the accompanying drawings. It should be understood that these directional terms are relative concepts. They are used for relative descriptions and clarifications, and they may change accordingly according to changes in the orientation of the chip or semiconductor packaging structure.

[0042] Figure 1 The following is a schematic diagram of an electronic device 200 provided in an embodiment of the present application. The electronic device 200 can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The electronic device 200 may include a printed circuit board (PCB) 250, on which a bus 205 and a system on chip (SoC) 210 connected to the bus 205 may be provided.

[0043] The system on chip 210 can be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the system on chip 210 may include one or more processors, such as an application processor (AP) 211 for processing applications and a graphics processing unit (GPU) 212 for processing image data. The system on chip 210 may also include a first random access memory (RAM) 213 for caching high-speed data. The first random access memory 213 may be electrically connected to the processor of the system on chip 210. The first random access memory 213 may be a static random access memory (SRAM) or an embedded flash memory (EFlash).

[0044] The application processor 211, image processing unit 212, and first random access memory 213 may be integrated into a single die or may be provided on multiple dies. Furthermore, one or more dies integrating the application processor 211, image processing unit 212, and first random access memory 213 may be provided on a printed circuit board 250.

[0045] The electronic device 200 may further include a second random access memory 220 electrically connected to the system-on-chip 210 via the bus 205. The second random access memory 220 may also be disposed on the printed circuit board 250. The second random access memory 220 may be a dynamic random access memory (DRAM). The second random access memory 220 may be used to store volatile data, such as temporary data generated by the system-on-chip 210. The storage capacity of the second random access memory 220 is generally greater than that of the first random access memory 213, but the read speed is generally slower than that of the first random access memory 213.

[0046] In addition, the electronic device 200 may further include a communication chip 230 and a power management chip 240 connected to the system-on-chip 210 via the bus 205. The communication chip 230 may be used for processing the protocol stack, or for amplifying and filtering analog radio frequency signals, or for performing the above functions simultaneously. The power management chip 240 may be used to power other chips. In one embodiment, the system-on-chip 210 and the second random access memory 220 may be packaged in a package structure, such as a 2.5D (dimension) or 3D package, to achieve a faster data transmission rate between chips.

[0047] Also, see Figure 2 , Figure 2 Schematic diagram of a memory 300 provided in an embodiment of the present application. The memory 300 may be as follows Figure 1 The first random access memory 213 shown may also be the second random access memory 220. This application does not limit the application scenario of the memory 300.

[0048] The memory 300 includes a memory array 100 and a controller. The controller may include one or more peripheral circuits such as a decoder 320 , a driver 330 , a timing controller 340 , a buffer 350 , or an input / output driver 360 .

[0049] In one embodiment, the memory array 100 includes a plurality of memory cells 120 arranged in an array. For example, the memory cells 120 may be arranged in a three-dimensional array. The memory cells 120 may include capacitors. For example, the capacitors may be charged and discharged to store 1 bit or multiple bits of data. The memory array 100 may also include signal lines such as word lines (WL) and bit lines (BL). Each memory cell 120 is electrically connected to a corresponding signal line. One or more of the above signal lines can be used to select the memory cells 120 that need to be read and written in the memory array by receiving a control level output by a controller, so as to change the charge and discharge state of the capacitor in the memory cell 120, thereby realizing data reading and writing operations.

[0050] The decoder 320 is used to decode the address of the memory cell 120. The decoder 320 is used to decode the received address to determine the memory cell 120 to be accessed. The driver 330 is used to control the signal line level based on the decoding result generated by the decoder 320, thereby enabling access to the specified memory cell 120. The buffer 350 is used to cache read data, for example, using a FIFO (first-in, first-out) buffer. The timing controller 340 is used to control the timing of the buffer 350 and control the driver 330 to drive the signal lines in the memory array 100. The input / output driver 360 is used to drive transmission signals, such as received data signals and transmitted data signals, so that the data signals can be transmitted over long distances. The memory array 100, decoder 320, driver 330, timing controller 340, buffer 350, and input / output driver 360 can be integrated into a single chip or integrated into multiple chips.

[0051] In addition, the controller can also control the memory 300 to refresh. The memory 300 needs to be refreshed continuously to maintain the stored data. However, if the refresh frequency is too high, the energy consumption of the memory 300 will increase; if the refresh frequency is too low, the data stored in the storage unit 120 will become invalid. Because the length of time that data is stored in the storage unit 120 of the memory 300 is related to temperature, a temperature sensor can be provided in the storage array 100. The temperature detected by the temperature sensor can be used to determine the optimal refresh frequency, thereby improving the performance of the memory 300.

[0052] To improve the accuracy of temperature detection for the storage array 100, an on-chip temperature sensor can be used. CMOS (Complementary Metal Oxide Semiconductor) temperature sensors are widely used in various applications, including systems-on-chip (SoCs), the Industrial Internet of Things (IIoT), and wireless sensor networks, due to their small size, ease of integration, low cost, and ability to directly output digital signals. However, different application scenarios also pose challenges to the design of CMOS temperature sensors.

[0053] In some technologies, a memory array integrates a bipolar junction transistor (BJT) as a CMOS temperature sensor to detect the temperature of the memory array. The memory array includes a substrate, a memory cell, and a BJT disposed in the substrate, wherein the memory cell includes a first transistor and a first capacitor. The component of the memory array that generates the most heat is the first transistor in each memory cell. Therefore, when the BJT is placed close to the first transistor, the temperature of the memory array can be more accurately measured.

[0054] However, in advanced 3D (3D) DRAM, if this technology is continued, the base, collector, and emitter regions of the bipolar transistor are located in the substrate. For example, the base, collector, and emitter regions of a BJT are formed by doping the substrate, while the memory cell of a DRAM is formed by forming film layers on the substrate, and these film layers form components such as the first transistor and / or first capacitor of the memory cell. That is, the bipolar transistor and the first transistor of the memory cell are respectively located in the substrate and in the film layers formed on the substrate. Therefore, the bipolar transistor may be far away from the first transistor, and the temperature at the location of the bipolar transistor may differ from the location that best represents the temperature of the memory array, making it impossible to accurately measure the temperature of the memory array.

[0055] Furthermore, in some new 3D DRAMs, the memory array may use a ferroelectric capacitor as the first capacitor. This capacitor comprises two opposing electrodes and a ferroelectric layer disposed between the two electrodes. The data storage capacity of the ferroelectric capacitor is directly related to the polarization strength of the ferroelectric layer, which degrades at high temperatures. Therefore, for these types of 3D DRAMs, it is necessary to more accurately obtain the temperature near the first capacitor. In other words, with the continuous advancement of memory technology, it is necessary to more accurately obtain the temperature at specific locations on the memory array.

[0056] To do this, see Figure 3 , an embodiment of the present application provides another storage array 100 , which can obtain the temperature of the storage array 100 more accurately.

[0057] Memory array 100 includes a substrate 110, multiple first film layers 111, memory cells 120, and sensing transistors 140. Memory cells 120 include first transistors 121. Multiple first film layers 111 are formed on substrate 110, and first transistors 121 are formed in multiple first film layers 111. Sensing transistors 140 are spaced apart from first transistors 121 on substrate 110 and formed in some of the multiple first film layers 111. Sensing transistors 140 are configured to output a first signal, which is related to the temperature of memory array 100.

[0058] Because the first transistor 121 is disposed in a plurality of first film layers 111 formed on the substrate 110, and the sensing transistor 140 is also disposed in several of the plurality of first film layers 111, that is, the sensing transistor 140 is disposed within the memory array 100, the sensing transistor 140 can be disposed close to the first transistor 121, thereby reducing the distance between the sensing transistor 140 and the first transistor 121, and the temperature at the location of the sensing transistor 140 can be closer to the temperature at the first transistor 121. Furthermore, the first transistor 121 and the sensing transistor 140 can be disposed in the same plurality of first film layers 111. Therefore, the heat generated by the first transistor 121 during operation can be conducted to the sensing transistor 140 through these same first film layers 111. This reduces the number of film layers traversed by the heat conduction path, reduces heat dissipation, and enables the sensing transistor 140 to accurately obtain the temperature at the location of the first transistor 121.

[0059] In addition, the refresh frequency of the memory array 100 can be controlled according to the temperature of the memory array 100 . After accurately obtaining the temperature of the memory array 100 , the lowest refresh frequency can be selected for refreshing, thereby reducing the power consumption of the memory array 100 .

[0060] The substrate 110 may be formed of silicon, or may be formed of other Group III, Group IV, and / or Group V elements. For example, the substrate 110 may be made of a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The substrate 110 may also be made of an alloy semiconductor such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenide phosphide (GaAsP), or gallium indium phosphide (GaInP). The substrate 110 may also be in the form of a semiconductor-on-insulator (SOI), such as silicon on insulator (SOI). A semiconductor-on-insulator substrate may include a substrate body, an insulator layer, and a semiconductor material layer. The insulator layer is formed on the silicon substrate body, and the semiconductor material layer is formed on the insulator layer. The insulator layer may be a buried oxide or the like. The semiconductor material layer may be made of silicon, germanium, or the like.

[0061] Multiple first film layers 111 are formed on the substrate 110. The materials used for the multiple first film layers 111 can be selected according to the structure of the memory cell 120. For example, the multiple first film layers 111 can be alternately stacked insulating dielectric layers and electrode layers. The insulating dielectric layers can be made of silicon oxide (SiO), aluminum oxide (AlO), silicon nitride (SiN), etc. The electrode layers can be made of metals or metal compounds, such as titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride (WN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), ruthenium (Ru), molybdenum (Mo), iridium (Ir), nickel (Ni), platinum (Pt), palladium (Pd), ruthenium oxide (RuO), iridium oxide (IrO), indium tin oxide (ITO), etc.

[0062] The plurality of first film layers 111 can be formed on the substrate 110 by various suitable processes. For example, one or more of the plurality of first film layers 111 can be formed by deposition processes such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and physical vapor deposition (PVD). For example, when the insulating dielectric layer is made of silicon oxide, the silicon oxide material can be deposited by CVD; when the electrode layer is made of tungsten, tungsten can be deposited by PVD.

[0063] The memory cell 120 is disposed on the substrate 110 , and the memory cell 120 may be formed in a plurality of first film layers 111 .

[0064] The memory cell 120 may include a first transistor 121, and the first transistor 121 is formed in a plurality of first film layers 111. The memory array 100 includes a plurality of memory cells 120, each of which includes a first transistor 121. Depending on the specific memory architecture, each memory cell 120 may include one or more first transistors 121. Since the memory array 100 includes a plurality of memory cells, the memory array 100 includes a plurality of first transistors 121. Each first transistor 121 may be formed in one first film layer 111 or in several first film layers 111 among the plurality of first film layers 111. The plurality of first transistors 121 may be arranged in an array in a direction parallel to the substrate and also arranged along the thickness direction of the substrate. That is, the plurality of first transistors 121 may be distributed three-dimensionally in an array in the plurality of first film layers 111.

[0065] The memory cell 120 may further include a first capacitor 122. A plurality of second film layers 112 may be formed on the substrate 110, and the first capacitor 122 is formed in the plurality of second film layers 112. For example, the plurality of second film layers 112 may be the same as the plurality of first film layers 111. For example, the plurality of second film layers 112 may include a plurality of first film layers 111. For example, the plurality of second film layers 112 may be formed on a side of the plurality of first film layers 111 that is close to the substrate 110 or on a side that is away from the substrate 110. The plurality of second film layers 112 may also be formed alternately with the plurality of first film layers 111 on the substrate 110. The plurality of second film layers 112 may also be formed on the substrate 110 using various suitable processes.

[0066] The first capacitor 122 may include a first electrode 123 and a second electrode 124. The first electrode 123 surrounds the second electrode 124. A first insulating layer 125 is provided between the first electrode 123 and the second electrode 124. The first insulating layer 125 may be a ferroelectric material or other insulating material, such as a hafnium oxide-based ferroelectric material. The second electrode 124 extends along the thickness direction of the substrate. For example, a first capacitor 122 may include a second electrode 124 and a plurality of first electrodes 123 arranged along the thickness direction of the substrate 110. Thus, multiple capacitor units are formed along the thickness direction of the substrate 110. In other words, a first capacitor 122 may include multiple capacitor units, and one capacitor unit can be used to form a memory cell. This facilitates the formation of a three-dimensional memory array 100 using semiconductor processes.

[0067] The sensing transistor 140 is spaced apart from the first transistor 121 and is disposed on the substrate 110. The sensing transistor 140 is formed in some of the first film layers 111 among the plurality of first film layers 111. The sensing transistor 140 may be disposed in the same plurality of first film layers 111 as some of the first transistors 121. By way of example, the number of sensing transistors 140 may also be multiple, and the multiple sensing transistors 140 may be arranged in an array in a direction parallel to the substrate 110 and also arranged along the thickness direction of the substrate 110. That is, the multiple sensing transistors 140 may also be disposed three-dimensionally in the first film layer 111. By way of example, the number of first film layers 111 spanned by one sensing transistor 140 may be the same as or different from the number of first film layers 111 spanned by one first transistor 121, thereby facilitating the arrangement of the sensing transistor 140 in the memory array 100.

[0068] The sensing transistor 140 is configured to output a first signal, the first signal being related to the temperature of the memory array 100. Figure 4 The number of sensing transistors 140 can be multiple, and multiple sensing transistors 140 can be connected in parallel. By connecting in parallel, the signals output by each sensing transistor 140 are accumulated to obtain and output a first signal. This can increase the magnitude of the output first signal, thereby facilitating detection of the first signal and improving detection accuracy. Since the first signal is related to the temperature of the memory array 100, the first signal is processed to output a temperature signal, thereby also improving the accuracy of obtaining the temperature of the memory array 100.

[0069] For example, multiple sensing transistors 140 may be disposed adjacent to each other, including being disposed adjacent to each other in a plane parallel to the substrate 110, being disposed adjacent to each other along the thickness direction of the substrate 110, or being disposed adjacent to each other in a plane parallel to the substrate 110 and being disposed adjacent to each other along the thickness direction of the substrate 110. This facilitates the arrangement of signal lines for outputting first signals from multiple sensing transistors 140. Furthermore, multiple sensing transistors 140 may be disposed in the same region of the memory array 100. The first signals output by the multiple sensing transistors 140 can better reflect the temperature of that region, thereby improving the accuracy of sensing the temperature of a specific region of the memory array 100.

[0070] The sensing transistor 140 may be suitable for preparation using a back-end of line (BEOL) process. The back-end of line process is relative to the front-end of line (FEOL) process. In the preparation process of integrated circuits, the preparation process can be divided into a front-end of line process and a back-end of line process. In this application, the operation of forming a metal contact on the substrate 110 for the first time is considered to be the last step of the front-end of line process, and also the first step of the back-end of line process. In the preparation of 3D DRAM, the first transistor 121 of the memory cell 120 can also be prepared using a back-end of line process. In other words, both the sensing transistor 140 and the first transistor 121 can be prepared using a back-end of line process. At this time, preparing the sensing transistor 140 through a back-end of line process can improve the process compatibility of preparing the sensing transistor 140, and preparing the sensing transistor 140 at the same time as preparing the first transistor 121 can reduce the process steps of preparation and improve production efficiency.

[0071] Please continue to see Figure 3 In some embodiments, the sensing transistor 140 includes a source 141, a channel 142, a drain 143, and a gate 144. For example, the gate 144 of the sensing transistor 140 may be arranged around the channel 142, and the source 141, channel 142, and drain 143 may be arranged along the thickness direction of the substrate 110. In other words, the sensing transistor 140 is perpendicular to the substrate 110. The vertical arrangement of the sensing transistor 140 reduces the area occupied by the sensing transistor, which helps increase the number of memory cells in the memory array. Furthermore, the vertical arrangement of the sensing transistor 140 facilitates process implementation. For example, a through-hole can be formed through several of the multiple first film layers 111, and doped semiconductor material can be sequentially deposited in the through-hole to form the source 141, channel 142, and drain 143 of the sensing transistor 140. Furthermore, the through-hole formation process can be included in the fabrication of the 3D DRAM memory cell or in the back-end process, thereby conveniently integrating the fabrication process of the sensing transistor 140.

[0072] See Figure 5 In some embodiments, the memory array 100 may further include a second capacitor 160 connected to the sensing transistor 140 in the memory array 100. Digital signals are easily processed by integrated circuits. The second capacitor 160 can be used to construct an analog-to-digital conversion circuit, which is used to convert the first signal output by the sensing transistor 140 into a first digital signal. Since the first signal is related to the temperature of the memory array 100, the first digital signal is also related to the temperature of the memory array 100. Based on the first digital signal, the temperature of the memory array 100 can be conveniently obtained using an integrated circuit, such as a digital circuit.

[0073] The second capacitor 160 may also be formed in the plurality of second film layers 112 on the substrate 110. The second capacitor 160 may include a third electrode 161 and a fourth electrode 162. The third electrode 161 surrounds the fourth electrode 162. A second insulating layer 163 is provided between the third electrode 161 and the fourth electrode 162. The second insulating layer 163 may be a ferroelectric material or other insulating material, such as a hafnium oxide-based ferroelectric material. The fourth electrode 162 may extend along the thickness direction of the substrate. In other words, the second capacitor 160 is perpendicular to the substrate 110. This reduces the area occupied by the second capacitor 160 and increases the integration density of the memory array 100. For example, the second capacitor 160 may also include a plurality of fourth electrodes 162 arranged along the thickness direction of the substrate 110. Exemplarily, the second capacitor 160 and the first capacitor 122 may be disposed in the same plurality of second film layers 112. Thus, the film layers of the second capacitor 160 utilize the film layers forming the first capacitor 122, eliminating the need for additional film layers for forming the second capacitor 160. This reduces the number of film layers stacked, facilitating improved storage density. Exemplarily, the second capacitor 160 may be fabricated using the same process steps as the first capacitor 122. For example, the second capacitor 160 may be fabricated simultaneously with the first capacitor 122. Simultaneously fabricating the second capacitor 160 and the first capacitor 122 reduces the number of process steps required to fabricate the memory array 100, improving production efficiency.

[0074] The sensing transistor 140 may be a suitable type of transistor that has good temperature sensing performance.

[0075] The inventors of this application have discovered that a junctionless field effect transistor (JLT) has good temperature sensing performance. Therefore, a JLT can be used as the sensing transistor 140. A JLT is a type of field effect transistor. The difference between a JLT and a conventional field effect transistor is that the source, channel, and drain of a JLT have the same doping type. Figure 6 , Figure 6 1 is a schematic structural diagram of a junctionless field-effect transistor 150. The source 141, channel 142, and drain 143 of the junctionless field-effect transistor 150 have the same doping type. The gate 144 of the junctionless field-effect transistor 150 may be disposed around the channel 142, with a gate dielectric layer 145 disposed between the gate 144 and the channel 142. Exemplarily, the source 141 and drain 143 of the junctionless field-effect transistor 150 may be heavily N-type doped, and the channel 142 may be N-type doped. Exemplarily, the source 141 and drain 143 of the junctionless field-effect transistor 150 may also be heavily P-type doped, and the channel 142 may be P-type doped.

[0076] The junctionless field effect transistor can output the first signal related to temperature in various ways.

[0077] For example, please see Figure 6 , the gate 144 of the junctionless field effect transistor 150 is placed at a first voltage V1, and the source 141 and the drain 143 of the junctionless field effect transistor 150 are connected, and the source 141 and the drain 143 are configured to output a first signal. At this time, the first signal is the gate leakage current Igate.

[0078] See Figure 7 , Figure 7 The horizontal axis is the actual temperature of the junctionless field effect transistor 150, the vertical axis is the logarithmic value of the gate leakage current Igate, and the solid line is the curve of the logarithmic value of the gate leakage current Igate output by the junctionless field effect transistor 150 as its temperature changes. The curve is almost a straight line. Figure 7 It can be seen that the gate leakage current Igate of the junctionless field effect transistor 150 has a logarithmic value of about 1e -12 to 1e -10 When the temperature varies within a range of -40°C to 125°C, the corresponding temperature varies within a range of approximately -40°C to 125°C, and the logarithm of the gate leakage current Igate is positively correlated with the temperature. That is, under constant other conditions, the higher the temperature of the junctionless field-effect transistor 150, the larger the logarithm of the output gate leakage current Igate, where the base of the logarithm is 10. Furthermore, the logarithm of the gate leakage current Igate of the junctionless field-effect transistor 150 has a high linear correlation with the temperature. The higher the linear correlation, the more accurately the temperature can be obtained using the logarithm of the gate leakage current Igate.

[0079] For example, see Figure 8 , one of the source 141 and drain 143 of the junctionless field effect transistor 150 is connected to the gate 144 and a first current I1 is passed through. The source 141 and drain 143 and the gate 144 are configured to output a first signal. The other of the source 141 and drain 143 of the junctionless field effect transistor 150 can be placed at a reference voltage V ss , for example, the reference voltage V ss =0, in which case the other of the source 141 and the drain 143 can be directly grounded. Since the current flowing through the junctionless field effect transistor 150 changes with temperature, the current will raise the voltage signal V at the gate 144. PTAT , that is, the voltage signal V PTAT It will also change with the temperature. At this time, the first signal is the voltage signal V PTAT .

[0080] See Figure 9 , Figure 9 The middle horizontal axis is the actual temperature of the junctionless field effect transistor 150, and the vertical axis is the voltage signal V PTAT , the solid line is the curve of the voltage output by the junctionless field effect transistor 150 changing with its temperature, and the dotted line is a straight line. Figure 9 It can be seen that when the temperature changes in the range of about -40°C to 125°C, the voltage signal V output by the junctionless field effect transistor 150 is PTAT The voltage signal V PTAT It is positively correlated with temperature, that is, when other conditions are constant, the higher the temperature of the junctionless field effect transistor 150 is, the higher the output voltage signal V s The curve of the voltage output by the junctionless field effect transistor 150 as it changes with its temperature is also close to a straight line, that is, the voltage signal V output by the junctionless field effect transistor 150 is PTAT It has a certain linear correlation with temperature and can therefore be used for temperature detection.

[0081] See Figure 10 As can be seen from the foregoing, the first signal output by the sensing transistor 140 is an analog signal. To obtain a digital temperature signal, the memory 300 may further include an analog-to-digital conversion circuit 370 and a processing unit 380. The analog-to-digital conversion circuit 370 is configured to output a first digital signal based on the first signal output by the sensing transistor 140 in the memory array 100. The first digital signal is related to the temperature of the memory array 100. The processing unit 380 receives the first digital signal and may obtain a digital temperature signal based on the first digital signal.

[0082] At least a portion of the analog-to-digital conversion circuit 370 is formed in the substrate 110 of the memory array 100. For example, see Figure 3 or Figure 5 The analog-to-digital conversion circuit 370 may include a second transistor 170. The source, drain, and channel of the second transistor 170 are formed in the substrate 110 of the memory array 100. For example, the source, drain, and channel of the second transistor 170 may be formed by doping the substrate 110. The second transistor 170 may be a field-effect transistor (MOSFET), or other type of transistor suitable for forming the analog-to-digital conversion circuit 370. The position of the second transistor 170 on the substrate 110 may at least partially overlap with the projection of the sensing transistor 140 on the substrate 110, thereby facilitating the arrangement of the wiring for the sensing transistor 140 to transmit the first signal to the analog-to-digital conversion circuit 370.

[0083] See Figure 11 , Figure 11: is a schematic diagram of an analog-to-digital conversion circuit 370 provided in an embodiment of the present application. The analog-to-digital conversion circuit 370 may include a selector 373, a comparator 374, and a control unit 375 connected in sequence. For example, the selector 373 may include multiple input terminals and an output terminal, the comparator 374 may include two input terminals and an output terminal, and the control unit 375 may include an input terminal and an output terminal. One input terminal of the comparator 374 is connected to the sensing transistor 140, the other input terminal of the comparator 374 is connected to the output terminal of the selector 373, and the output terminal of the comparator 374 is connected to the input terminal of the control unit 375, thereby realizing the sequential connection of the selector 373, the comparator 374, and the control unit 375. In the present application, the connection between two circuit elements may include a direct connection between the two circuit elements, or an indirect connection between the two circuit elements, that is, other circuit elements may be set between the two circuit elements to achieve the connection, and this application does not specifically limit it.

[0084] The selector 373 is configured to receive different reference voltage signals via a plurality of input terminals, and output a reference voltage signal corresponding to the input terminal from an output terminal by selecting any input terminal.

[0085] For example, to obtain multiple reference voltage signals, the analog-to-digital conversion circuit 370 may further include multiple second resistors 372 arranged in series. The resistance values ​​of the multiple second resistors 372 may be equal. The end of the first second resistor 372 in the series that is not connected to the adjacent second resistor 372 may be connected to the first reference voltage, and the end of the last second resistor 372 in the series that is not connected to the adjacent second resistor 372 may be connected to the second reference voltage. The first reference voltage and the second reference voltage are not equal. For example, the first reference voltage may be 3V and the second reference voltage may be 0V. That is, the end of the last second resistor 372 in the series that is not connected to the adjacent second resistor 372 may be grounded. Thus, the voltage between two adjacent second resistors 372 decreases in magnitude from the first second resistor 372 to the last second resistor 372. The multiple input terminals of the selector 373 may be sequentially connected to these equally decreasing voltages. Therefore, the multiple input terminals can receive different reference voltage signals, and the magnitudes of these reference voltage signals form an arithmetic progression.

[0086] Exemplarily, each input terminal of the selector 373 may correspond to a port code, and the port code may be used to identify the magnitude of the corresponding reference voltage signal. For example, the port codes corresponding to the multiple input terminals of the selector 373 may also increase in value, and the larger the reference voltage received by the input terminal corresponding to the port code, the larger the port code. For example, if the port codes are 0, 1, and 2, and the reference voltage signals are 0.1V, 0.2V, and 0.3V, then port code 0 corresponds to 0.1V, port code 1 corresponds to 0.2V, and port code 2 corresponds to 0.3V.

[0087] The comparator 374 is configured to receive the first signal and the reference voltage signal at its two input terminals respectively, and output a comparison signal through its output terminal, where the comparison signal is used to represent the magnitude relationship between the first signal and the reference voltage signal.

[0088] For example, the first signal output by the sensing transistor 140 may be a current signal. In order to convert the current signal into a voltage signal, a first resistor 371 may be connected between the sensing transistor 140 and the comparator 374. It is easy to understand that the voltage signal is proportional to the magnitude of the current signal.

[0089] The control unit 375 is configured to receive a comparison signal, control the selector 373 to change the selected input terminal, and output a voltage digital signal when determining the reference voltage signal corresponding to the first signal. The voltage digital signal is related to the reference voltage signal corresponding to the first signal, and the voltage digital signal is the first digital signal.

[0090] Exemplarily, the selector 373 can traverse and select from the input end corresponding to the small reference voltage signal to the input end corresponding to the large reference voltage signal in sequence. At this time, when the size relationship represented by the comparison signal is that the reference voltage signal is greater than the voltage signal corresponding to the first signal, the range of the voltage signal corresponding to the first signal can be determined; if after the traversal, the size relationship represented by the comparison signal is always that the reference voltage signal is less than the voltage signal corresponding to the first signal, then the first signal can be determined to be the largest reference voltage signal.

[0091] For example, at the beginning, the reference voltage signal input to the input end of the selector 373 is the minimum. If the comparison signal indicates that the reference voltage signal is greater than the voltage signal corresponding to the first signal, it can be determined that the voltage signal corresponding to the first signal is less than the minimum reference voltage signal. However, the temperature corresponding to the minimum reference voltage signal can be set to be lower than the lowest temperature that the sensing transistor 140 can sense, thereby meeting the temperature sensing requirements.

[0092] When the comparison signal represents that the reference voltage signal is smaller than the voltage signal corresponding to the first signal, the control unit 375 controls the selector 373 to select the next input terminal. At this time, if the comparison signal represents that the reference voltage signal is greater than the voltage signal corresponding to the first signal, it can be determined that the voltage signal corresponding to the first signal is the reference voltage signal corresponding to the currently selected input terminal or the previously selected input terminal.

[0093] For example, the control unit 375 may include a finite state machine (FSM) 376 and a first counter 377. The output of the finite state machine 376 is connected to the input of the first counter 377. The input of the control unit 375 is the input of the finite state machine 376, and the output of the control unit 375 is the output of the first counter 377. The finite state machine 376 may transition to a predetermined state based on the comparison signal input by the comparator 374. That is, when the comparison signal indicates that the reference voltage signal is less than the voltage signal corresponding to the first signal, the finite state machine 376 may control the selector 373 to select the next input terminal and transmit the port code corresponding to the currently selected input terminal to the first counter 377. When the port codes are increasing in equal values, the finite state machine 376 may control the first counter 377 to add the value of the adjacent port code to the increment, thereby transmitting the port code to the first counter 377. When the comparison signal indicates that the reference voltage signal is greater than the voltage signal corresponding to the first signal, the finite state machine 376 controls the first counter 377 to output the port code corresponding to the current input terminal or the port code corresponding to the previous input terminal. Since the port code corresponds one-to-one with the reference voltage signal, the corresponding reference voltage signal can be determined.

[0094] See Figure 12 , Figure 12 is a schematic diagram of another analog-to-digital conversion circuit 370 provided in an embodiment of the present application. The analog-to-digital conversion circuit 370 may include a third capacitor 471, a trigger 472, and a time-to-digital converter (TDC) 473. The third capacitor 471 is connected to the trigger 472 and to the sensing transistor 140 of the memory array 100. The third capacitor 471 may be the second capacitor 160 in the memory array 100 described above. In this way, the third capacitor 471 can be manufactured simultaneously with the first capacitor 122 of the memory cell 120, thereby reducing the number of process steps.

[0095] Exemplarily, the third capacitor 471 includes two electrodes, one of which is connected to both the sensing transistor 140 and the trigger 472, and the other electrode can be grounded. In this way, the sensing transistor 140 can charge the third capacitor 471 via the output first signal. For example, when the first signal is the gate leakage current Igate, a first resistor 371 can be provided between the third capacitor 471 and the third capacitor 471. The first resistor 371 converts the gate leakage current Igate into a voltage signal, and the voltage signal is used to charge the third capacitor 471.

[0096] The trigger 472 is configured to control the first signal to charge the third capacitor 471 according to the charging state of the third capacitor 471. It is easy to understand that since the voltage used to charge the third capacitor 471 is obtained by the first signal output by the sensing transistor 140, the first signal is related to the temperature of the storage array 100, and the charging time is related to the voltage, the charging time is related to the temperature of the storage array 100.

[0097] Exemplarily, trigger 472 may be a Schmitt trigger, the input of which is connected to third capacitor 471. That is, the signal input to the Schmitt trigger is the voltage of third capacitor 471. Analog-to-digital conversion circuit 370 also includes switch 474, which may be disposed between first resistor 371 and third capacitor 471 and controlled by the Schmitt trigger. Thus, when third capacitor 471 is charged to a certain level, the input signal of the Schmitt trigger exceeds a first threshold, controlling switch 474 to open and discharge third capacitor 471. When third capacitor 471 is discharged to a certain level, the input signal of the Schmitt trigger falls below a second threshold, controlling switch 474 to close and charge third capacitor 471, and repeating the cycle. Thus, the time interval between the closing and opening of Schmitt trigger control switch 474 can be obtained, which represents the time required to charge third capacitor 471.

[0098] The time-to-digital converter 473 is configured to convert the charging time into a time digital signal and output the time digital signal, which is the first digital signal. For example, the time-to-digital converter 473 may include an oscillation loop and a counter consisting of an even number of inverters and logic gates, wherein, except for one uneven inverter, the sizes of the other inverters are the same, and the size of the uneven inverter may be several times that of the other inverters. A signal is input into the oscillation loop, and the signal has a certain pulse width. Because an oscillation loop is formed, the signal circulates in the oscillation loop. When the signal passes through the uneven inverter, the pulse width of the signal becomes smaller, and the amplitude of the reduction is equal each time it passes through the uneven inverter until the signal finally disappears, so that the pulse width of the signal is proportional to the number of times the signal circulates in the oscillation loop. Therefore, when the pulse width is the charging time of the third capacitor 471 , the charging time of the third capacitor 471 can be converted into the oscillation frequency of the oscillation loop, and the oscillation frequency can be obtained by a counter, and the oscillation frequency is the time digital signal.

[0099] See Figure 13 , Figure 13is a schematic diagram of another analog-to-digital conversion circuit 370 provided in an embodiment of the present application. The analog-to-digital conversion circuit 370 includes an oscillator 572, a clock generator 574, and a second counter 573. The input of the oscillator 572 can be connected to the sensing transistor 140 and is used to receive the first signal output by the sensing transistor 140. The output of the oscillator 572 is connected to the second counter 573. The clock generator 574 is also connected to the second counter 573.

[0100] The oscillator 572 is configured to output a first oscillation signal based on the first signal, where the first oscillation signal is related to the temperature of the memory array 100. For example, an input terminal of the oscillator 572 receives the first signal output by the sensing transistor 140, and the oscillator 572 is controlled by the first signal. For example, the oscillation frequency of the oscillator 572 is proportional to the magnitude of the first signal. The oscillation frequency of the oscillator 572 is the first oscillation signal. Since the first signal is related to the temperature of the memory array 100, the first oscillation signal is related to the temperature of the memory array 100.

[0101] Oscillator 572 can be a voltage-controlled oscillator or a current-controlled oscillator. The input of a voltage-controlled oscillator is voltage, while the input of a current-controlled oscillator is current. When the voltage or current input to oscillator 572 changes, the oscillation frequency of oscillator 572 also changes accordingly, with a one-to-one correspondence. When the first signal is the gate leakage current Igate, oscillator 572 can also be a voltage-controlled oscillator. In this case, a first resistor 371 can be provided between oscillator 572 and sensing transistor 140. First resistor 371 converts gate leakage current Igate into a voltage signal, and the voltage signal is used to control the oscillation frequency of voltage-controlled oscillator 572.

[0102] The clock generator 574 is configured to output a clock signal. The reference clock generated by the clock generator 574 is independent of temperature. For example, the clock generator 574 may be a crystal oscillator or a system clock generator.

[0103] The second counter 573 is configured to output an oscillation frequency digital signal according to the clock signal, where the oscillation frequency digital signal is the first digital signal. For example, the second counter 573 counts the oscillation frequency of the oscillator 572 within one or more cycles of the clock signal and outputs the count result, where the count result is the oscillation frequency digital signal.

[0104] For example, the analog-to-digital conversion circuit 370 may further include a reference counter 575, which may be connected between the clock generator 574 and the second counter 573. The reference counter 575 counts the clock signal output by the clock generator 574 and outputs a strobe signal. The second counter 573 counts the oscillation frequency of the oscillator 572 within the strobe signal, thereby providing more options for the counting cycle of the second counter 573.

[0105] In some embodiments, the memory 300 further includes a processing unit 380, wherein an input terminal of the processing unit 380 is connected to an output terminal of the analog-to-digital conversion circuit 370, so that the processing unit 380 can receive a first digital signal and process the first digital signal to output a digital temperature signal. For example, when the first signal is the gate leakage current Igate of the sensing transistor 140, since the logarithm of the gate leakage current Igate has a good linear correlation with the temperature of the memory array 100, the processing unit 380 needs to first perform a logarithm operation on the first digital signal before obtaining and outputting the digital temperature signal based on the logarithm of the first digital signal.

[0106] In some embodiments, the controller of the memory 300 is connected to the processing unit 380, so that the processing unit 380 can transmit a digital temperature signal to the controller, and the controller can control the refresh frequency of the memory 300 based on the digital temperature signal. Because the sensing transistor 140 provided in the memory array 100 can obtain an accurate temperature, the controller can refresh the memory cells 120 in the memory array 100 at an appropriate refresh frequency based on the temperature.

[0107] In some embodiments, the memory 300 may further include a cooling unit (not shown in the figure), and the controller may also control the cooling unit to dissipate heat from the memory 300 according to the digital temperature signal.

[0108] The above are only specific embodiments of the present application, but the scope of protection of the application is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A storage array, characterized in that: include: substrate; A memory cell is provided on the substrate, wherein the memory cell comprises a first transistor; a sensing transistor, spaced apart from the first transistor and disposed on the substrate; The memory array includes a plurality of first film layers forming the first transistors, and the sensing transistors are formed in several first film layers among the plurality of first film layers; the sensing transistors are configured to output a first signal, and the first signal is related to the temperature of the memory array.

2. The storage array according to claim 1, wherein: The sensing transistor and the first transistor are both formed by a back-end process.

3. The storage array according to claim 1 or 2, wherein: The sensing transistor includes a source, a channel, a drain, and a gate. The source, the channel, and the drain are arranged along a thickness direction of the substrate, and the gate is arranged around the channel.

4. The storage array according to claim 3, wherein: The sensing transistor is a junctionless field effect transistor.

5. The storage array according to claim 3 or 4, wherein: The source and the drain are connected, and the source and the drain are configured to output the first signal.

6. The storage array according to claim 3 or 4, wherein: One of the source and the drain is connected to the gate, and the one of the source and the drain and the gate are configured to output the first signal.

7. The storage array according to any one of claims 1 to 6, wherein: There are multiple sensing transistors, and the multiple sensing transistors are connected in parallel.

8. The storage array according to claim 7, wherein: A plurality of sensing transistors are adjacently arranged.

9. The storage array according to any one of claims 1 to 8, wherein: The first transistor includes a source, a channel, a drain and a gate. The source, the channel and the drain are arranged along the thickness direction of the substrate, and the gate is arranged around the channel.

10. The storage array according to any one of claims 1 to 9, wherein: Also comprising a second capacitor connected to the sensing transistor; The second capacitor includes a first electrode and a second electrode, the first electrode surrounds the second electrode, and the second electrode extends along a thickness direction of the substrate.

11. The storage array according to claim 10, wherein: The storage unit further includes a first capacitor connected to the first transistor; The memory array includes a plurality of second film layers forming the first capacitors, and the second capacitors are formed in some of the second film layers.

12. The storage array according to claim 11, wherein: The first capacitor includes a third electrode and a fourth electrode, the third electrode surrounds the fourth electrode, and the fourth electrode extends along a thickness direction of the substrate.

13. A memory, characterized in that: comprising a storage array as claimed in any one of claims 1 to 12, and an analog-to-digital conversion circuit; The analog-to-digital conversion circuit is configured to output a first digital signal according to a first signal output by a sensing transistor in the memory array, where the first digital signal is related to a temperature of the memory array.

14. The memory according to claim 13, wherein: The analog-to-digital conversion circuit includes a selector, a comparator and a control unit connected in sequence; The selector includes a plurality of input terminals and an output terminal, and is configured to receive different reference voltage signals via the plurality of input terminals, and output the reference voltage signal corresponding to the input terminal from the output terminal by selecting any one of the input terminals; The comparator is configured to receive the first signal and the reference voltage signal, and output a comparison signal, wherein the comparison signal is used to represent the magnitude relationship between the first signal and the reference voltage signal; The control unit is configured to receive the comparison signal, control the selector to change the selected input terminal, and output a voltage digital signal when determining the reference voltage signal corresponding to the first signal, wherein the voltage digital signal is related to the reference voltage signal corresponding to the first signal.

15. The memory according to claim 13, wherein: The memory array includes a second capacitor, the analog-to-digital conversion circuit includes a trigger and a time-to-digital converter, the second capacitor is connected to the trigger and is connected to the sensing transistor of the memory array; The trigger is configured to control the first signal to charge the second capacitor according to a charging state of the second capacitor, and the charging time is related to the temperature of the storage array; The time-to-digital converter is configured to convert the charging time into a time digital signal and output the time digital signal.

16. The memory according to claim 13, wherein: The analog-to-digital conversion circuit includes an oscillator, a clock generator and a second counter; The oscillator is configured to output a first oscillation signal according to the first signal, wherein the first oscillation signal is related to the temperature of the storage array; The clock generator is configured to output a clock signal; The second counter is configured to output an oscillation frequency digital signal according to the clock signal.

17. The memory according to any one of claims 13 to 16, wherein: The analog-to-digital conversion circuit includes a second transistor, wherein a source, a drain, and a channel of the second transistor are formed in a substrate of the memory array.

18. The memory according to any one of claims 13 to 17, wherein: It also includes a processing unit connected to the analog-to-digital conversion circuit, and the processing unit is configured to output a temperature digital signal according to the first digital signal.

19. An electronic device, characterized in that: The invention comprises a printed circuit board and the memory according to any one of claims 13 to 18, wherein the memory is arranged on the printed circuit board.

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