Compact frequency locked loop architecture for digital clocks

Abstract

Certain aspects of the present disclosure provide a relatively compact frequency locked loop (FLL) that uses a discrete time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows the FLL frequency to be preserved when the reference clock is to be turned off, to maintain a similar frequency during turn-off, and to recover the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner including a first input coupled to an output of the encoder; a digital to analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete time integrator, the discrete time integrator comprising an input coupled to an output of the DAC; a voltage controlled oscillator (VCO), the voltage controlled oscillator (VCO) comprising a control input coupled to an output of the discrete time integrator; and a counter including an input coupled to an output of the VCO, and including an output coupled to a second input of the combiner.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 18 / 177,445, filed on March 2, 2023, which is hereby incorporated by reference into this application. Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic circuits, and more particularly to frequency locked loops (FLLs). Background Art

[0004] A frequency-locked loop (FLL) is an electronic control circuit used to generate an oscillating signal whose frequency is locked to a reference signal. An FLL typically includes a voltage-controlled oscillator (VCO) or digitally controlled oscillator (DCO) that outputs a tunable oscillating signal. The FLL compares the frequency of the tunable oscillating signal with the frequency of a reference signal and automatically controls the VCO or DCO to increase or decrease the frequency of the oscillating signal so that its frequency (but not necessarily its phase) matches that of the reference signal. FLLs can be used in any of a variety of applications to generate one or more signals with a stable frequency. These applications can include computers and telecommunications (for example, wireless communications). Summary of the Invention

[0005] The systems, methods, and devices of the present disclosure each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of the disclosure as expressed by the claims that follow, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled "Detailed Description," one will understand how the features of the present disclosure provide advantages, including reduced area occupied by a frequency-locked loop (FLL) and reduced jitter.

[0006] Certain aspects of the present disclosure provide a FLL circuit. The FLL circuit generally includes: an encoder; a combiner including a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) including an input coupled to the output of the combiner; a discrete-time integrator including an input coupled to the output of the DAC; a voltage-controlled oscillator (VCO) including a control input coupled to the output of the discrete-time integrator; and a counter including an input coupled to the output of the VCO and an output coupled to a second input of the combiner.

[0007] Certain aspects of the present disclosure provide a circuit for generating an oscillating signal. The circuit generally includes: a FLL including a DAC, a discrete-time integrator having an input coupled to an output of the DAC, and a VCO having a control input coupled to an output of the discrete-time integrator; a reference clock generator selectively coupled to one or more clock inputs of the FLL; and an oscillator selectively coupled to the one or more clock inputs of the FLL.

[0008] Certain aspects of the present disclosure provide a method for signal generation. The method generally includes: receiving an output signal from a VCO at an input of a counter; determining, via the counter, a counter output signal representing a frequency of the output signal; determining, via a combiner, an error signal based on a difference between a target frequency and the frequency of the output signal; generating, via a DAC, an analog signal based on the error signal; generating, via a discrete-time integrator, a control voltage by integrating the analog signal; and controlling the VCO via the control voltage.

[0009] Certain aspects of the present disclosure provide an apparatus for signal generation. The apparatus generally includes: means for determining a frequency-indicative signal representing the frequency of an output signal from a VCO; means for determining an error signal based on a difference between a target frequency and the frequency of the output signal; means for generating an analog signal based on the error signal; and means for generating a control voltage, the means for generating the control voltage including means for integrating the analog signal over discrete times, the VCO being controlled via the control voltage.

[0010] To accomplish the foregoing and related ends, one or more aspects include the features fully described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail certain illustrative features of one or more aspects. However, these features are indicative of but a few of the various ways in which the principles of the various aspects may be employed, and this description is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order that the manner in which the above-described features of the present disclosure are understood in detail, a more particular description, briefly summarized above, may be obtained by reference to the various aspects, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only certain typical aspects of the disclosure and are therefore not to be considered limiting of its scope, as the description may admit to other equally effective aspects.

[0012] Figure 1 is a block diagram of an example frequency-locked loop in which aspects of the present disclosure may be practiced.

[0013] Figure 2Ais a block diagram of an example frequency-locked loop using an accumulator and an encoder.

[0014] Figure 2B is a block diagram of an example frequency-locked loop including a discrete-time integrator, according to certain aspects of the present disclosure.

[0015] Figure 3A is a block diagram of an example frequency-locked loop circuit using a switched capacitor integrator, according to certain aspects of the present disclosure.

[0016] Figure 3B Illustrated Figure 3A Example operation of the frequency locked loop circuit.

[0017] Figure 3C is a block diagram of an example frequency-locked loop circuit with a digital signal processor, according to certain aspects of the present disclosure.

[0018] Figure 4 and Figure 5 is a block diagram of an example frequency-locked loop circuit having circuitry for switching a reference frequency signal, according to certain aspects of the present disclosure.

[0019] Figure 6 is a flow diagram of example operations for signal generation according to certain aspects of the present disclosure.

[0020] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0021] Certain aspects of the present disclosure relate to a relatively compact frequency-locked loop (FLL). Conventional FLLs use digital-to-analog conversion circuitry that consumes a significant amount of circuit board real estate to provide the FLL with fine resolution and wide range. Certain aspects of the present disclosure provide an FLL implemented using a digital-to-analog converter (DAC) for generating an analog signal and a discrete-time integrator for integrating the generated analog signal. The discrete-time integrator generates a control voltage for a voltage-controlled oscillator (VCO) that drives the FLL. In this manner, the DAC can be implemented using fewer bits than conventional implementations, thereby allowing the DAC to be smaller in size. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows the FLL frequency to be preserved when a reference clock is disconnected, maintain a similar frequency during the disconnection, and restore the FLL frequency when the reference clock is reconnected.

[0022] Various aspects of the present disclosure are described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to any specific structure or function presented throughout the present disclosure. Rather, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of protection of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings herein, it will be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the disclosure disclosed herein, whether it is implemented independently or in combination with any other aspect of the disclosure. For example, any number of aspects set forth herein may be used to implement an apparatus or practice method. In addition, the scope of the present disclosure is intended to cover such apparatus or method that is practiced using other structures, functionality, or structure and functionality in addition to or different from the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the present claims.

[0023] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0024] As used herein, the term "connected with" in various tenses of the verb "connect" may mean that element A is directly connected to element B or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the context of electronic components, the term "connected with" may also be used herein to mean that wires, traces, or other conductive materials are used to electrically connect element A and element B (and any components electrically connected therebetween).

[0025] Example Frequency-Locked Loop

[0026] Figure 1 An example frequency locked loop (FLL) 100 is illustrated in which aspects of the present disclosure may be practiced. In some aspects, FLL 100 may be used in a frequency synthesizer to generate an oscillating signal for clocking digital circuits. However, FLL 100 may be used to generate an oscillating signal for any suitable application.

[0027] FLL 100 includes a frequency detector (FD) 102, a digital loop filter 104 (labeled "Dig Loop Filter"), a digital-to-analog converter (DAC) 106, a voltage-controlled oscillator (VCO) 108, a frequency divider 110, a counter 112, a spread spectrum clock (SSC) generator 114, and an encoder 116 (labeled "Enc"). As shown, FD 102, digital loop filter 104, frequency divider 110, counter 112, SSC generator 114, and encoder 116 are implemented in the digital domain, while DAC 106 and VCO 108 are implemented in the analog domain. For other aspects, frequency divider 110 may be implemented in the analog domain rather than the digital domain. FLL 100 may be coupled to a reference oscillator 118, which may be implemented, for example, by a crystal oscillator (XO). Reference oscillator 118 may generate a reference frequency oscillation signal (F) for FLL 100. ref ).

[0028] Although the VCO 108 may be implemented as a ring oscillator (RO), such as Figure 1 108 is shown, but the VCO may be implemented by any suitable oscillator circuit having an adjustable output frequency. As illustrated, the VCO 108 is coupled to a counter 112 and may provide a feedback signal to the counter 112. The feedback signal may represent the oscillation signal generated by the VCO 108 or a divided-down version thereof. The counter 112 may determine the reference frequency signal (F ref ) in one cycle of the feedback signal. The counter 112 may generate a counter output signal indicating the number of clock cycles to the FD 102. The FD 102 may also receive a target count signal from the encoder 116. For example, the encoder 116 may receive a set of target values ​​under which the FLL 100 will operate. The set of target values ​​indicates the target frequency of the oscillation signal generated by the VCO 108 based on the reference frequency. The set of target values ​​may include an integer value L and a fractional value α, where the output frequency of the VCO (F out ) satisfies the following formula:

[0029]

[0030] The SSC generator 114 may be coupled to a reference oscillator 118 and may generate a signal from a reference frequency signal (F ref) generates a spread spectrum clock. Encoder 116 may receive the spread spectrum clock from SSC generator 114 and, in turn, generate a target count signal to be provided to FD 102. FD 102 may compare the counter output signal received from counter 112 with the target count signal and output an error signal. This error signal indicates the difference between the actual frequency of the oscillation signal generated by VCO 108 and the target frequency of FLL 100. FD 102 may provide this error signal to digital loop filter 104 for processing, thereby generating a multi-bit frequency control word (FCW). DAC 106 may then convert this FCW into an analog signal, which is used to control VCO 108 to adjust its output frequency, thereby completing the loop to lock the VCO's output frequency to the target frequency. Optionally, the output of VCO 108 may be divided using frequency divider 110 to generate the FLL output signal (labeled "fllOut").

[0031] Figure 2A 2 is a block diagram of an example FLL 200 in which aspects of the present disclosure may be practiced. The FLL 200 may include an SSC generator 114, an input encoder 116, a combiner 204, an accumulator 206, an encoder 208, a DAC 210, a VCO 212, and a counter 112. As illustrated, a feedback signal may be received by the counter 112. The feedback signal may represent an oscillating signal generated by the VCO 212 (e.g., corresponding to the VCO 108). The counter 112 may have a first input coupled to an output of the VCO 212 and a first input configured to receive a reference frequency signal (F ref As described above, the counter 112 can determine the value of F ref The counter 112 may generate a counter output signal indicating the number of clock cycles of the feedback signal in one cycle of . The combiner 204 may also receive a target count signal from the input encoder 116, as described above with respect to Figure 1 described.

[0032] Combiner 204 can compare the output signal of the counter with the target count signal and output an error signal. The error signal is provided to the input of accumulator 206. Accumulator 206 generates an accumulated error signal, which is provided to encoder 208 (e.g., a thermometer encoder) for generating a DAC 210 (e.g., corresponding to the target count signal). Figure 1DAC 210 receives coarse and fine digital inputs from DAC 106 (of the FLL). DAC 210 generates analog control signals for controlling VCO 212. DAC 210 can be designed to have a high nominal resolution (e.g., a specified number of bits) for the FLL. For example, the nominal bit resolution of DAC 210 can be greater than or equal to 12 bits. Consequently, DAC 210 can occupy a large area and dictate the size of FLL 200.

[0033] Example frequency-locked loop with discrete-time integrator

[0034] Certain aspects of the present disclosure provide an FLL with reduced area consumption and reduced low-frequency jitter compared to conventional implementations. For example, certain aspects provide an FLL implemented using a discrete-time integrator (e.g., a switched-capacitor integrator). This integrator enables the use of a DAC with a low nominal bit resolution (e.g., a 1-bit DAC), thereby reducing area consumption compared to FLL 100 or FLL 200. The discrete-time integrator can integrate the output of the small-bit DAC to generate a control signal for the VCO.

[0035] Figure 2B An example FLL 230 according to certain aspects of the present disclosure is illustrated. FLL 230 includes processing circuitry 201 having a DAC 234 and a discrete-time integrator 236. In some aspects, processing circuitry 201 may optionally include digital logic components, such as a digital signal processor (DSP) 232. DSP 232 may process the error signal from combiner 204, as described in greater detail herein. DAC 234 may receive the error signal generated by combiner 204 (or a processed version of the error signal via DSP 232).

[0036] DAC 234 may have a smaller nominal bit resolution than DAC 210 or DAC 106, thereby allowing DAC 234 to have a smaller area compared to DAC 210 or DAC 106. For example, DAC 234 may have a nominal bit resolution of 5 bits or less (e.g., 3 bits or 1 bit). In the case of a 1-bit DAC, DAC 234 may be implemented, for example, by a charge pump. DAC 234 converts the received error signal into an analog signal that is provided to discrete-time integrator 236. Discrete-time integrator 236 integrates the analog signal to form a control signal for controlling VCO 212. As illustrated, discrete-time integrator 236 may have a transfer function in the z-domain that is inversely proportional to z−1.

[0037] Figure 3A is a block diagram of an example FLL circuit 300 according to certain aspects of the present disclosure. Figure 3AAs shown, DAC 234 can be implemented as a 1-bit DAC. In some aspects, such a 1-bit DAC can be implemented using a charge pump circuit, such as Figure 3A In some aspects, the discrete-time integrator 236 can be implemented as a switched capacitor integrator, such as Figure 3A As depicted, any suitable discrete-time integrator circuit may be used. By using an integrator with discrete-time properties, the original FLL ( Figure 2A ) of the desired loop dynamics (e.g., bandwidth dependence). This is because Figure 2B The discrete time integrator 236 shown in FIG can be designed to have Figure 2A The same transfer function of the accumulator 206 is used.

[0038] Based on the count error signal generated by combiner 204, DAC 234 can source current to node n1 using current source 260 by closing switch 262, or sink current from node n1 using current source 264 by closing switch 266. By sourcing and sinking current from node n1, a voltage V is generated at node n1 (e.g., across resistive element Rpp). For example, if combiner 204 generates a positive error signal (e.g., indicating that the frequency of the VCO's oscillation signal is too low), DAC 234 can source current to node n1, thereby generating a positive voltage at node n1 relative to a reference potential node (e.g., electrical ground). Conversely, if combiner 204 generates a negative error signal (e.g., indicating that the frequency of the VCO's oscillation signal is too high), DAC 234 can sink current from node n1, thereby generating a negative voltage at node n1 relative to the reference potential node.

[0039] The discrete-time integrator 236 may receive the voltage V at the node n1 and integrate the voltage to generate a control voltage (Vcntl) for controlling the VCO 212. As a switched capacitor integrator, the discrete-time integrator 236 may include a first switch 381, a second switch 382, ​​a third switch 383, a fourth switch 384, a fifth switch 385, a first capacitive element C1, a second capacitive element C2, and an amplifier 340.

[0040] The second capacitive element C2 can be coupled between the output and the negative input terminal of the amplifier 340. The positive terminal of the amplifier 340 (also referred to herein as the positive input terminal) can be coupled to a reference potential node (e.g., electrically ground). The first terminal of the first capacitive element C1 can be coupled to the node n1 via a first switch 381. The second terminal of the first capacitive element C1 can be coupled to the negative terminal (also referred to herein as the negative input terminal) of the amplifier 340 via a third switch 383. The second switch 382 can be coupled between the first terminal of the first capacitive element C1 at node n2 and the positive input terminal of the amplifier (or the reference potential node). The fourth switch 384 can be coupled between the second terminal of the first capacitive element C1 at node n3 and the reference potential node. The fifth switch 385 can be coupled between the output of the amplifier 340 and the input terminal of the VCO 212.

[0041] The discrete time integrator 236 can be controlled by a non-overlapping clock signal 280 to implement a sampling phase (Φ1) and a charge transfer phase (Φ2). The sampling phase and the charge transfer phase can be controlled by a non-overlapping clock signal 280. ref During each cycle of Figure 3A Shown as T ref F ref Each of the switches may be controlled by clock signals phi_1 and phi_2 provided by a clock generator 338 (labeled “CLKGen”), which is based on F ref The first switch 381 , the fourth switch 384 , and the fifth switch 385 may be controlled by the clock signal phi_1 , and the second switch 382 and the third switch 383 may be controlled by the clock signal phi_2 .

[0042] During the sampling phase (Φ1), phi_1 is logic high and phi_2 is logic low, closing the first, fourth, and fifth switches 381, 384, and 385 while opening the second and third switches 382, ​​383. During the sampling phase, the voltage V at node n1 is sampled (e.g., stored in the first capacitive element C1). After sampling the voltage V at node n1, the clock generator 338 switches phi_1 to logic low and phi_2 to logic high to initiate the charge transfer phase (Φ2). This opens the first, fourth, and fifth switches 381, 384, and 385, and closes the second and third switches 382, ​​383. During the charge transfer phase, the charge stored in the first capacitive element C1 is transferred to the second capacitive element C2. Following the charge transfer phase, another sampling phase begins, during which the second capacitive element C2 is coupled to the VCO, generating a control voltage (Vcntl) for controlling the VCO 212. In this manner, Vcntl is increased or decreased based on the voltage V at node n1.

[0043] For example, assume the error signal is positive. In this case, voltage V may increase by a voltage corresponding to the resolution of DAC 234 (e.g., the resolution associated with one bit of a 1-bit DAC, or, if a multi-bit DAC is used, the resolution associated with the least significant bit (LSB) of the DAC). Voltage V is then integrated, resulting in a corresponding increase in Vcntl. On the other hand, if the error signal is negative, voltage V may decrease by a voltage corresponding to the resolution of DAC 234. Voltage V is then integrated, resulting in a corresponding decrease in Vcntl. Thus, the frequency of the oscillation signal generated by VCO 212 is adjusted within the VCO's frequency range and has a resolution corresponding to the resolution of DAC 234.

[0044] Figure 3B Example values ​​are provided to facilitate Figure 3A As shown in the figure, the current output frequency of VCO 212 may be equal to 1 GHz, and F ref The frequency of may be equal to 20 MHz, thereby generating a count signal (e.g., at the output of counter 112) corresponding to a count value of 50. The set of target values ​​may include a value L 50 and a fractional value α 0.5, thereby generating a target count value of 50.5 corresponding to a target frequency of 1010 MHz (e.g., 1.01 GHz).

[0045] As shown, combiner 204 may receive a count signal corresponding to a feedback count value of 50 from counter 112. Combiner 204 may also receive a target count signal corresponding to a target count value of 50.5 from encoder 116. Because the target count value 50.5 is greater than the feedback count value 50, the error signal generated by combiner 204 is positive (i.e., count error > 0). Therefore, the combiner provides a positive value to DAC 234. Based on the positive value from combiner 204, DAC 234 provides a current to node n1. Consequently, voltage V at node n1 increases (e.g., by an amount equal to the resolution of DAC 234). Voltage V is then integrated by discrete-time integrator 236, and voltage Vcntl increases accordingly, causing the frequency of the oscillating signal at the output of the VCO to increase. This process continues in a frequency-locked loop to maintain the oscillating signal frequency at the target frequency represented by L and α.

[0046] Figure 3C FIG2 is a block diagram of an example FLL circuit 350 including the DSP 232, according to certain aspects of the present disclosure. The DSP 232 may be used to compensate for (or at least reduce) errors (e.g., frequency offset) associated with the discrete-time integrator 236. In other words, a certain amount of error (or drift) may be associated with the analog circuitry used to implement the discrete-time integrator 236. The DSP 232 may be used to reduce this error, thereby improving the accuracy of the FLL circuit 350.

[0047] DSP 232 may include a coefficient multiplier stage 390 (with coefficients kpi) (e.g., a gain stage), a coefficient multiplier stage 392 (with coefficients kpp), a combiner 354, and an optional quantizer 356 (labeled "Quant") (e.g., a requantizer with a multi-bit output). In some aspects, DSP 232 may be implemented as a proportional-integral (PPI) path controller. As shown, the output of combiner 204 is provided to coefficient multiplier stage 390 and coefficient multiplier stage 392. The output of coefficient multiplier stage 390 is provided to digital accumulator 352. Digital accumulator 352 accumulates and stores the error signal at the output of coefficient multiplier stage 390, effectively storing an offset used to compensate for (or at least reduce) the error (e.g., drift) associated with discrete-time integrator 236. The output of digital accumulator 352 and the output of coefficient multiplier stage 392 may be provided to combiner 354. Combiner 354 then generates an error signal that is provided to DAC 234. In some aspects, the combiner 354 provides the error signal to an optional quantizer 356 , which requantizes the digital error signal, thereby generating a requantized error signal at the output of the combiner 354 having fewer bits than the error signal.

[0048] Using a 1-bit DAC for DAC 234 may result in a slow slew rate for the FLL. The slew rate may refer to the maximum rate of change in the frequency of the oscillating signal at the output of the VCO. In some aspects of the present disclosure, a multi-bit DAC may be used for DAC 234 to increase the slew rate of the FLL. For example, a 5-bit DAC or a 3-bit DAC may be used in some scenarios.

[0049] Example state freezing and restoring of an FLL with a discrete-time integrator

[0050] In some cases, the reference frequency signal (F ref ) can be removed or otherwise temporarily made effectively unavailable to the FLL. Certain aspects of the present disclosure provide for ref Techniques and devices to preserve the FLL frequency when it is removed. In this way, the F ref The FLL operating frequency is saved before, and the FLL can maintain a similar frequency during the removal period, and when F ref Returning to the previous FLL operating frequency restores it.

[0051] Figure 4 is a block diagram of an example FLL circuit 400 implemented with an oscillator 402 (also referred to herein as a "supplemental oscillator") according to certain aspects of the present disclosure. Oscillator 402 may be simpler, less accurate, less stable, and / or less expensive than reference oscillator 118. For example, oscillator 402 may be implemented as a resistor-capacitor oscillator (RCO), although any suitable oscillator may be used. Oscillator 402 may generate a signal having a value approximately equal to F ref An oscillating signal with a frequency of (e.g., the same frequency within a 25% tolerance). ref When not provided to the FLL circuit 400 , the oscillation signal generated by the oscillator 402 may be used to operate the FLL circuit 400 .

[0052] As illustrated, a first switch S1 may be coupled between the combiner 204 and the processing circuit 201. A second switch S2 may be coupled between the output of S1 and a digital zero node 290 (e.g., a node providing a digital signal representing a digital value of zero). For certain aspects, the switches S1 and S2 may be multiplexed by a multiplexer ( Figure 4 The third switch S3 may be coupled between the output terminal of the oscillator 402 and the clock input terminal of the counter 112. The fourth switch S4 may be coupled between the output terminal of the oscillator 402 and the clock input terminal of the counter 112. ref Between the reference clock generator 480 (eg, the reference oscillator 118, which may be a crystal oscillator) and the clock input of the counter 112. For certain aspects, the switches S3 and S4 may be connected by one or more multiplexers ( Figure 4 is implemented by

[0053] Switch S3 can be opened and switch S4 can be closed, and F ref is available and used to operate the FLL circuit 400. An indication to remove F may be received ref In response, the oscillating signal generated by oscillator 402 can be used to "freeze" (capture and store) the current state of the FLL (e.g., configure the FLL circuit 400 to a frozen state). For example, switch S1 can be opened and switch S2 can be closed. Thus, the input of processing circuit 201 can be coupled to digital zero node 290. Thus, discrete time integrator 236 can maintain the current voltage Vcntl. Switch S4 can then be opened, thereby providing F ref The reference clock generator 480 is disconnected from the FLL circuit 400. The switch S3 can then be closed to connect the oscillator 402 to the FLL circuit. At this stage, the FLL circuit 400 uses the oscillation signal generated by the oscillator 402 to determine a set of target values ​​L for the frozen state. 冻结 and α 冻结 , as described in more detail herein. Once L is determined 冻结 and α 冻结 , you can store L (for example, in a register) 冻结 and α 冻结 They are used to generate the target count signal that is provided to the combiner 204 .

[0054] The switch S1 can then be closed and the switch S2 can be opened, thereby reconnecting the processing circuit 201 to the output of the combiner 204. The combiner 204 generates a counter based on the target count signal (e.g., based on the L 冻结 and α 冻结 ) to generate an error signal. Vcntl is generated by the discrete time integrator 236 based on the error signal to maintain the frequency of the oscillation signal at the output of the VCO 212 (eg, during the remainder of the frozen state). In other words, the FLL circuit may be ref is removed while maintaining operation at a stable target frequency.

[0055] When F ref When reconnecting to the FLL circuit, switch S3 can be opened and switch S4 can be closed. The original (or new) L and α values ​​can be used instead of L 冻结 Value and α 冻结 In this way, the FLL circuit can quickly reacquire frequency lock.

[0056] Figure 5FIG. 5 is a block diagram of an example FLL circuit 500 implementing a frozen state in which aspects of the present disclosure may be practiced. As shown, the FLL circuit 500 includes a plurality of multiplexers (MUXs), including MUX 502A, MUX 502B, MUX 502C, and MUX 502D. The FLL circuit 500 may also include a FLL control parameter (e.g., L 冻结 and α 冻结 ) register 504. The FLL circuit 500 may further include a control circuit 506 (labeled “freeze control”) configured to control each of the multiplexers.

[0057] MUX 502A may be configured to receive a set of target values ​​(L and α) for normal (eg, non-frozen state) FLL operation and a set of target values ​​(eg, L and α) for frozen state operation. 冻结 and α 冻结 Based on the control signal from the control circuit 506, the MUX 502A provides L to the combiner 204. 冻结 and α 冻结 , or provides L and α to combiner 204. MUX 502B may have a first input coupled to the output of combiner 204 and a second input coupled to digital zero node 290. The output of MUX 502B may be coupled to an input of processing circuit 201 (e.g., to coefficient multiplier stage 390 and coefficient multiplier stage 392).

[0058] MUX 502C may be configured to receive an oscillating signal from oscillator 402 at a first input and an F signal (eg, from reference clock generator 480) at a second input. ref Based on the MUX control signaling from the control circuit 506, the MUX 502C can output F ref or the oscillation signal from the oscillator 402. The output signal of the MUX 502C (eg, F ref_internal ) may be provided to the digital accumulator 352, the quantizer 356, and the discrete-time integrator 236 and used to operate them (eg, via the clock generator 338).

[0059] In some aspects, a frequency divider 510 can be coupled between the output of the oscillator 402 and a first input of a MUX 502D, the second input of which is coupled to the output of the MUX 502C. The frequency divider 510 can divide the frequency of the output signal of the oscillator 402 by N, where N is any integer greater than 1. The frequency of the signal from the oscillator 402 can be divided to increase the L 冻结 and α 冻结The MUX 502D may generate a clock signal for operating the counter 112. For example, the MUX 502D may generate a clock signal from the divider 510 or the F ref_internal Output to the clock input terminal of counter 112.

[0060] During normal operation (e.g., using F ref operation), MUX 502C will F ref Output to the second input terminal of MUX 502D, and MUX 502D converts F ref Output to counter 112. F ref It is also used to operate the digital accumulator 352, the quantizer 356 and the discrete time integrator 236. Therefore, using F as described herein ref To operate the FLL.

[0061] When operating in freeze mode, MUX 502B outputs a digital zero (e.g., from digital zero node 290). Thus, discrete-time integrator 236 can temporarily hold the integrator output state. MUX 502C outputs a signal from oscillator 402 for use in operating digital accumulator 352, quantizer 356, and discrete-time integrator 236. MUX 502D can output the divided signal from divider 510 to counter 112. Counter 112 then generates a count signal that indicates the number of cycles of the oscillating signal from VCO 212 within N cycles of the divided signal from divider 510. The period associated with the N cycles of the divided signal is greater than the period of the signal from oscillator 402. Therefore, using the divided signal to generate the count signal can provide a more accurate frequency measurement. The generated count signal can be divided by N (e.g., where the signal from oscillator 402 is divided by N via divider 510) and used to determine L 冻结 and α 冻结 and stored in register 504. The divided count signal is also provided to combiner 204 (eg, indirectly after encoding).

[0062] As described, L 冻结 and α 冻结 is provided to the second input of MUX 502A. MUX 502A provides L to combiner 204. 冻结 and α 冻结 The combiner 204 is based on the target count signal (eg, based on L 冻结 and α 冻结) and the divided count signal from counter 112 to generate an error signal. MUX 502B then outputs the error signal to processing circuit 201 for use in operating the FLL as described herein. In this way, MUX 502C can be temporarily switched to use the output signal from oscillator 402 instead of F ref To operate.

[0063] In this manner, in an FLL circuit having a discrete-time integrator and a supplemental oscillator (e.g., RCO) tuned approximately to the reference frequency of a reference clock, a sequence of events can be executed using the supplemental oscillator before the reference clock is removed, such that the FLL maintains operation at a stable target frequency once the clock is removed. This is achieved by first determining FLL control parameters associated with the supplemental oscillator when the FLL is operating at the target frequency. These control parameters can then be used with the supplemental oscillator to maintain the FLL output frequency when the reference clock is removed.

[0064] Example Operation

[0065] Figure 6 is a flow diagram illustrating example operations 600 for signal generation in accordance with certain aspects of the present disclosure. Operations 600 may be performed via an FLL circuit, such as FLL 230, FLL circuit 300, FLL circuit 350, FLL circuit 400, or FLL circuit 500.

[0066] At block 602, the FLL circuit receives an output signal from a VCO (e.g., VCO 212) at an input of a counter (e.g., counter 112). At block 604, the FLL circuit determines a counter output signal representing the frequency of the output signal via the counter. At block 606, the FLL circuit determines an error signal based on the difference between the target frequency and the frequency of the output signal via a combiner (e.g., combiner 204). At block 608, the FLL circuit generates an analog signal based on the error signal via a DAC (e.g., DAC 234).

[0067] At block 610, the FLL circuit generates a control voltage (eg, Vcntl for controlling the VCO 212) by integrating the analog signal via a discrete time integrator. In some aspects, the discrete time integrator may be (eg, as described with respect to FIG. Figure 3A At block 612, the FLL circuit controls the VCO via a control voltage (eg, to adjust the frequency of the oscillation signal).

[0068] In some aspects, the FLL circuit also selects (eg, via MUX 502D and / or MUX 502C) a reference clock signal (eg, F ref ) or a clock signal generated via an oscillator (e.g., oscillator 402). The counter output signal may be generated based on this selection. The oscillator may be a resistor-capacitor oscillator. The reference clock generator and the oscillator may be configured to generate signals having similar frequencies (e.g., within a 10% tolerance). In some aspects, the FLL circuit may store an indication of the state of the FLL circuit (e.g., L 冻结 and α 冻结 In some aspects, the FLL circuit may select a set of target values ​​(e.g., L and α) associated with normal operation of the FLL circuit or an indication of the state of the FLL circuit stored in a register. The FLL may generate a target frequency signal representing a target frequency based on the selection (e.g., a target count signal provided to combiner 204), and generate an error signal based on the target frequency signal (e.g., via combiner 204).

[0069] Example aspects

[0070] In addition to the various aspects described above, specific combinations of the various aspects are also within the scope of the present disclosure, the details of some of which are as follows:

[0071] Aspect 1: A frequency-locked loop (FLL) circuit, comprising: an encoder; a combiner, the combiner including a first input coupled to an output of the encoder; a digital-to-analog converter (DAC), the DAC including an input coupled to the output of the combiner; a discrete-time integrator including an input coupled to the output of the DAC; a voltage-controlled oscillator (VCO), the VCO including a control input coupled to the output of the discrete-time integrator; and a counter including an input coupled to the output of the VCO and an output coupled to a second input of the combiner.

[0072] Aspect 2: The FLL circuit according to Aspect 1 further comprises: a reference clock generator, the reference clock generator being selectively coupled to the clock input of the counter; and an oscillator, the oscillator being selectively coupled to the clock input of the counter.

[0073] Aspect 3: The FLL circuit according to aspect 2, wherein the oscillator comprises a resistor-capacitor oscillator.

[0074] Aspect 4: The FLL circuit according to aspect 2 or 3, wherein the reference clock generator and the oscillator are configured to generate signals having the same frequency within a 25% tolerance.

[0075] Aspect 5: According to any one of Aspects 2 to 4, the FLL circuit further includes a register, the register including an input terminal coupled to the output terminal of the counter, and is configured to store the integer value and fractional value of the output signal from the counter when saving the state of the FLL circuit.

[0076] Aspect 6: According to the FLL circuit of Aspect 5, the FLL circuit further includes a multiplexer, the multiplexer including a first set of input terminals configured to receive a set of target values ​​associated with normal operation of the FLL circuit, a second set of input terminals coupled to the output terminals of the register, and a set of output terminals coupled to the input terminals of the encoder.

[0077] Aspect 7: The FLL circuit according to any one of Aspects 1 to 6, further comprising a multiplexer, the multiplexer comprising a first input terminal coupled to the output terminal of the combiner, and comprising an output terminal coupled to the input terminal of the DAC.

[0078] Aspect 8: The FLL circuit of aspect 7, wherein the multiplexer comprises a second input terminal configured to receive a digital signal having a value of zero.

[0079] Aspect 9: The FLL circuit according to any one of aspects 1 to 8, wherein the DAC has a resolution of no more than 3 bits.

[0080] Aspect 10: The FLL circuit according to any one of aspects 1 to 9, wherein the DAC is a 1-bit DAC.

[0081] Aspect 11: The FLL circuit of any one of Aspects 1 to 10, wherein the DAC comprises a charge pump.

[0082] Aspect 12: The FLL circuit according to any one of aspects 1 to 11, further comprising a digital logic component, the digital logic component comprising an input terminal coupled to the output terminal of the combiner, and comprising an output terminal coupled to the input terminal of the DAC.

[0083] Aspect 13: An FLL circuit according to Aspect 12, wherein the digital logic component includes: a first coefficient multiplier, the first coefficient multiplier including an input terminal coupled to the output terminal of the combiner; a digital accumulator, the digital accumulator including an input terminal coupled to the output terminal of the first coefficient multiplier; another combiner, the another combiner including a first input terminal coupled to the output terminal of the digital accumulator; a second coefficient multiplier, the second coefficient multiplier including an input terminal coupled to the output terminal of the combiner and including an output terminal coupled to the second input terminal of the another combiner; and a requantizer, the requantizer including an input terminal coupled to the output terminal of the another combiner and including an output terminal coupled to the input terminal of the DAC.

[0084] Aspect 14: The FLL circuit according to aspect 13, wherein the output terminal of the requantizer is a multi-bit output terminal.

[0085] Aspect 15: The FLL circuit of any one of Aspects 1 to 14, wherein the discrete-time integrator comprises a switched capacitor integrator.

[0086] Aspect 16: An FLL circuit according to Aspect 15, wherein the switched capacitor integrator includes: an amplifier, the amplifier including a negative input terminal, a positive input terminal and an output terminal; a first capacitive element; a second capacitive element, the second capacitive element coupled between the output terminal and the negative input terminal of the amplifier; a first switch, the first switch coupled between the input terminal of the discrete-time integrator and the first terminal of the first capacitive element; a second switch, the second switch coupled between the first terminal of the first capacitive element and the positive input terminal of the amplifier; a third switch coupled between the second terminal of the first capacitive element and the negative input terminal of the amplifier; a fourth switch, the fourth switch coupled between the second terminal of the first capacitive element and the positive input terminal of the amplifier; and a fifth switch coupled between the output terminal of the amplifier and the output terminal of the discrete-time integrator.

[0087] Aspect 17: A circuit for generating an oscillation signal, the circuit comprising: a frequency-locked loop (FLL), the frequency-locked loop (FLL) comprising: a digital-to-analog converter (DAC), a discrete-time integrator having an input coupled to an output of the DAC, and a voltage-controlled oscillator (VCO) having a control input coupled to an output of the discrete-time integrator; a reference clock generator selectively coupled to one or more clock inputs of the FLL; and an oscillator selectively coupled to the one or more clock inputs of the FLL.

[0088] Aspect 18: The circuit of aspect 17, wherein the oscillator comprises a resistor-capacitor (RC) oscillator.

[0089] Aspect 19: The circuit of aspect 17 or 18, wherein the reference clock generator and the oscillator are configured to generate signals having the same frequency within a 25% tolerance.

[0090] Aspect 20: The circuit of any one of aspects 17 to 19, further comprising a register including an input coupled to the FLL and configured to store an indication of a state of the FLL.

[0091] Aspect 21: A method of signal generation, the method comprising: receiving an output signal of a voltage-controlled oscillator (VCO) from a frequency-locked loop (FLL) circuit at an input of a counter; determining a counter output signal representing the frequency of the output signal via the counter; determining an error signal based on a difference between a target frequency and the frequency of the output signal via a combiner; generating an analog signal based on the error signal via a digital-to-analog converter (DAC); generating a control voltage by integrating the analog signal via a discrete-time integrator; and controlling the VCO via the control voltage.

[0092] Aspect 22: The method according to aspect 21, further comprising: selecting a reference clock signal generated via a reference clock generator or a clock signal generated via an oscillator, wherein the counter output signal is generated based on the selection.

[0093] Aspect 23: The method of aspect 22, wherein the oscillator comprises a resistor-capacitor oscillator.

[0094] Aspect 24: The method of aspect 22 or 23, wherein the reference clock generator and the oscillator are configured to generate signals having the same frequency within a 25% tolerance.

[0095] Aspect 25: The method of any one of aspects 21 to 24, further comprising storing an indication of the state of the FLL circuit in a register.

[0096] Aspect 26: The method according to Aspect 25 further includes: selecting a set of target values ​​associated with normal operation of the FLL circuit or the indication of the state of the FLL circuit stored in the register; and generating a target frequency signal representing the target frequency based on the selection, the error signal being generated based on the target frequency signal.

[0097] Aspect 27: The method of any one of aspects 21 to 26, wherein the discrete-time integrator comprises a switched-capacitor integrator.

[0098] Aspect 28: An apparatus for signal generation, the apparatus comprising: a component for determining a frequency indication signal representing the frequency of an output signal of a voltage-controlled oscillator (VCO) from a frequency-locked loop (FLL) circuit; a component for determining an error signal based on a difference between a target frequency and the frequency of the output signal; a component for generating an analog signal based on the error signal; and a component for generating a control voltage, the component for generating the control voltage comprising a component for integrating the analog signal in discrete times, the VCO being controlled via the control voltage.

[0099] Aspect 29: The apparatus according to Aspect 28 further comprises a component for selecting a reference clock signal generated via a reference clock generator or a clock signal generated via an oscillator, wherein the component for determining the frequency indication signal representing the frequency of the output signal from the VCO is controlled based on the selection.

[0100] Additional Notes

[0101] The above description provides examples and does not limit the scope, applicability or examples set forth in the claims. Without departing from the scope of this disclosure, the functions and arrangements of the elements discussed may be changed. Various examples may omit, replace or add various processes or components as appropriate. For example, the methods described may be performed in a different order than described, and various steps may be added, omitted or combined. In addition, the features described with respect to some examples may be combined in some other examples. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of this disclosure is intended to cover such devices or methods practiced using other structures, functional functions or structures and functionality in addition to the various aspects of the disclosure set forth herein or different from the various aspects of the disclosure given herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the present claims. The word "exemplary" is used herein to mean "used as an example, instance, or illustration". Any aspect described herein as "exemplary" is not necessarily to be interpreted as being preferred or having advantages over other aspects.

[0102] The various operations of the methods described above may be performed by any suitable component capable of performing the corresponding functions. Such components may include various hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Generally speaking, where there are operations illustrated in the figures, these operations may have corresponding corresponding components plus functional components. For example, the component for determining the frequency indication signal may include a counter, such as counter 112. The component for determining the error signal may include a combiner, such as combiner 204. The component for generating an analog signal may include a DAC, such as DAC 234. The component for generating a control voltage or the component for integration may include a discrete-time integrator, such as discrete-time integrator 236. The component for selection may include a multiplexer, such as MUX 502A, 502B, 502C, or 502D.

[0103] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). For example, "at least one of a, b, or c" is intended to encompass: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0104] The methods disclosed herein include one or more steps or actions for implementing the described methods. The steps and / or actions of the methods may be interchangeable with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0105] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A frequency-locked loop (FLL) circuit, comprising: encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to the output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage controlled oscillator (VCO) comprising a control input coupled to an output of the discrete time integrator; and A counter includes an input coupled to the output of the VCO and includes an output coupled to the second input of the combiner.

2. The FLL circuit according to claim 1 , further comprising: a reference clock generator selectively coupled to a clock input of the counter; and An oscillator is selectively coupled to the clock input of the counter.

3. The FLL circuit of claim 2, wherein the oscillator comprises a resistor-capacitor oscillator. 4 . The FLL circuit of claim 2 , wherein the reference clock generator and the oscillator are configured to generate signals having the same frequency within a 25% tolerance.

5. The FLL circuit of claim 2 , further comprising a register including an input terminal coupled to the output terminal of the counter and configured to store an integer value and a fractional value of the output signal from the counter when saving a state of the FLL circuit.

6. The FLL circuit of claim 5 , further comprising a multiplexer comprising a first set of input terminals configured to receive a set of target values ​​associated with normal operation of the FLL circuit, a second set of input terminals coupled to output terminals of the register, and a set of output terminals coupled to input terminals of the encoder.

7. The FLL circuit of claim 1, further comprising a multiplexer including a first input coupled to the output of the combiner and including an output coupled to the input of the DAC. 8 . The FLL circuit of claim 7 , wherein the multiplexer comprises a second input terminal configured to receive a digital signal having a value of zero.

9. The FLL circuit of claim 1, wherein the DAC has a resolution of no more than 3 bits.

10. The FLL circuit of claim 1, wherein the DAC is a 1-bit DAC.

11. The FLL circuit of claim 1, wherein the DAC comprises a charge pump.

12. The FLL circuit of claim 1, further comprising a digital logic component including an input coupled to the output of the combiner and including an output coupled to the input of the DAC.

13. The FLL circuit of claim 12 , wherein the digital logic component comprises: a first coefficient multiplier comprising an input coupled to the output of the combiner; a digital accumulator including an input coupled to an output of the first coefficient multiplier; another combiner including a first input coupled to an output of the digital accumulator; a second coefficient multiplier comprising an input coupled to the output of the combiner and comprising an output coupled to a second input of the further combiner; and A requantizer includes an input coupled to the output of the further combiner and includes an output coupled to the input of the DAC.

14. The FLL circuit of claim 13, wherein the output terminal of the requantizer is a multi-bit output terminal.

15. The FLL circuit of claim 1, wherein the discrete-time integrator comprises a switched capacitor integrator.

16. The FLL circuit of claim 15 , wherein the switched capacitor integrator comprises: an amplifier, the amplifier comprising a negative input terminal, a positive input terminal, and an output terminal; a first capacitive element; a second capacitive element coupled between the output terminal and the negative input terminal of the amplifier; a first switch coupled between the input of the discrete-time integrator and a first terminal of the first capacitive element; a second switch coupled between the first terminal of the first capacitive element and the positive input of the amplifier; a third switch coupled between the second terminal of the first capacitive element and the negative input terminal of the amplifier; a fourth switch coupled between the second terminal of the first capacitive element and the positive input of the amplifier; and A fifth switch is coupled between the output terminal of the amplifier and the output terminal of the discrete-time integrator.

17. A circuit for generating an oscillation signal, the circuit comprising: a frequency locked loop (FLL) comprising: a digital-to-analog converter (DAC), a discrete-time integrator having an input coupled to an output of the DAC, and a voltage controlled oscillator (VCO) having a control input coupled to an output of the discrete-time integrator; a reference clock generator selectively coupled to one or more clock inputs of the FLL; and An oscillator is selectively coupled to the one or more clock inputs of the FLL.

18. The circuit of claim 17, wherein the oscillator comprises a resistor-capacitor (RC) oscillator.

19. The circuit of claim 17, wherein the reference clock generator and the oscillator are configured to generate signals having the same frequency within a 25% tolerance.

20. The circuit of claim 17, further comprising a register including an input coupled to the FLL and configured to store an indication of a state of the FLL.

21. A method for generating a signal, the method comprising: receiving an output signal of a voltage controlled oscillator (VCO) from a frequency locked loop (FLL) circuit at an input terminal of the counter; determining, via the counter, a counter output signal representative of a frequency of the output signal; determining, via a combiner, an error signal based on a difference between a target frequency and the frequency of the output signal; generating an analog signal based on the error signal via a digital-to-analog converter (DAC); generating a control voltage by integrating the analog signal via a discrete-time integrator; and The VCO is controlled via the control voltage.

22. The method according to claim 21, further comprising: A reference clock signal generated via a reference clock generator or a clock signal generated via an oscillator is selected, wherein the counter output signal is generated based on the selection.

23. The method of claim 22, wherein the oscillator comprises a resistor-capacitor oscillator.

24. The method of claim 22, wherein the reference clock generator and the oscillator are configured to generate signals having the same frequency within a 25% tolerance.

25. The method of claim 21, further comprising: An indication of a status of the FLL circuit is stored in a register.

26. The method according to claim 25, further comprising: selecting a set of target values ​​associated with normal operation of the FLL circuit or the indication of the state of the FLL circuit stored in the register; as well as A target frequency signal representing the target frequency is generated based on the selection, and the error signal is generated based on the target frequency signal.

27. The method of claim 21, wherein the discrete-time integrator comprises a switched-capacitor integrator.

28. An apparatus for signal generation, the apparatus comprising: means for determining a frequency indicating signal representing the frequency of an output signal from a voltage controlled oscillator (VCO) of a frequency locked loop (FLL) circuit; means for determining an error signal based on a difference between a target frequency and said frequency of said output signal; means for generating an analog signal based on the error signal; and means for generating a control voltage, said means for generating said control voltage comprising means for integrating said analog signal in discrete times, said VCO being controlled via said control voltage.

29. The apparatus of claim 28, further comprising means for selecting a reference clock signal generated via a reference clock generator or a clock signal generated via an oscillator, wherein the means for determining the frequency indication signal representing the frequency of the output signal from the VCO is controlled based on the selection.

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