Satellite-borne power supply chip surge protection test system and method

Abstract

The invention discloses a satellite-borne power supply chip surge protection test system and a satellite-borne power supply chip surge protection test method, which relate to the technical field of surge protection test, and are characterized in that interference waveforms in a surge test process are accurately monitored in a built test environment through a surge waveform simulation monitoring module, and the traceability of a test source is ensured; the surge waveform quality judgment and adjustment module obtains and analyzes waveform quality parameters in real time, dynamically judges whether the waveform quality parameters meet test conditions or not, can eliminate unqualified waveforms in time, avoids invalid tests, and improves the test efficiency; the chip test reliability grading module applies a qualified surge waveform to a to-be-tested chip, collects and analyzes protection test process parameters, and realizes grading processing of test results; according to the system, through modular design, standardization and precision of the whole process of surge testing are achieved, reliability and consistency of testing data are effectively guaranteed, and powerful support is provided for scientific evaluation of the surge protection performance of the satellite-borne power supply chip.

Description

Technical Field

[0001] The present invention relates to the technical field of surge protection testing, and in particular to a system and method for testing surge protection of a satellite-borne power supply chip. Background Art

[0002] The current surge protection test process of satellite-borne power chip mainly revolves around core dimensions such as surge suppression, test architecture, and environmental adaptation: in terms of protection design, a combination of NTC and MOSFET is used, combined with a dedicated integrated chip to achieve dynamic adjustment, which can reduce the surge current peak; in terms of the test system, it is centered on a combination wave generator and high-precision acquisition equipment, combined with electromagnetic shielding, isolation design and an automation platform, to support closed-loop adjustment of surge parameters and machine learning-assisted diagnosis; the test method follows IEC, GJB and other standards, covering basic surge and environmental stress joint tests, and combining load matching and failure analysis to optimize protection performance; for the satellite-borne environment, the focus is on verifying radiation resistance and stability under a wide temperature range, and using technologies such as aluminum nitride substrates to control junction temperature.

[0003] For example, Chinese invention patent publication number CN107727980B discloses a test system for ultra-wideband pulse injection testing of surge protection devices. The proposed test system for ultra-wideband pulse injection testing includes a high-voltage sub-nanosecond pulse source for providing pulse signals to the device under test. The high-voltage sub-nanosecond pulse source utilizes a 50-level MARX circuit to provide the device under test with a pulse signal with a rising edge of 180ps, an amplitude of 3100V, and a half-width of 300ps. The output of the high-voltage sub-nanosecond pulse source is connected to one end of a test fixture. The other end of the test fixture is connected to an oscilloscope via an attenuator and coaxial cable. The high-voltage sub-nanosecond pulse source, coaxial cable, test fixture, and oscilloscope all have the same characteristic impedance of 50Ω.

[0004] For example, the Chinese invention patent with publication number CN120142794A discloses a surge testing method and a surge testing device, including: applying a surge waveform to a protection circuit; the protection circuit is used to constrain the output of the protection circuit within a safe range to protect against the surge waveform; the output of the protection circuit is detected to obtain an output waveform of the protection circuit output; wherein the output waveform is used to determine the test result of the protection circuit, and the test result is used to reflect the protection result of the protection circuit against the surge waveform.

[0005] However, in the process of implementing the embodiments of the present application, the above technology has at least the following technical problems: due to the fluctuation of the characteristics of the surge generation module hardware (energy storage elements, power amplifiers, etc.), changes in load impedance and environmental electromagnetic interference, the quality of the surge interference waveform is unstable; the test conditions are not strictly controlled, the chip preprocessing is not in place, and the surge injection energy transfer efficiency is inconsistent, so that the results cannot reflect the full working condition reliability of the satellite power chip. Summary of the Invention

[0006] To address the technical issues in the prior art, such as unstable surge waveform quality caused by fluctuations in surge generation module hardware characteristics, load and electromagnetic interference, as well as lax test condition control, insufficient chip pre-processing, and inconsistent energy transfer efficiency, which result in the inability to reflect the reliability of onboard power chips under all operating conditions, the present invention provides a system and method for testing surge protection of onboard power chips. The technical solution is as follows: On the one hand, a satellite-borne power chip surge protection test system is provided, including: a surge waveform simulation monitoring module, which is used to monitor the surge interference waveform during the surge test process in the test environment based on a completed test environment; a surge waveform quality judgment and adjustment module, which is used to obtain the quality parameters of the surge interference waveform in real time, analyze the obtained surge interference waveform quality parameters, and thus determine whether the surge interference waveform meets the test conditions; a chip test reliability grading module, which is used to apply the surge interference waveform that meets the test conditions to the satellite-borne power chip to be tested for protection testing, collect and analyze the process parameters of the protection test, and thus grade the surge protection test results of the satellite-borne power chip.

[0007] On the other hand, a method for testing surge protection of a satellite power chip is provided, comprising the following steps: S1. Based on a constructed test environment, monitoring the surge interference waveform during the surge test in the test environment; S2. acquiring quality parameters of the surge interference waveform in real time, analyzing the acquired quality parameters of the surge interference waveform, and thereby determining whether the surge interference waveform meets the test conditions; S3. applying the surge interference waveform that meets the test conditions to the satellite power chip to be tested for protection testing, collecting and analyzing the process parameters of the protection test, and thereby performing graded processing on the surge protection test results of the satellite power chip.

[0008] One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages: 1. The present invention provides a surge protection test system and method for onboard power supply chips, achieving standardization, automation, and precision of the entire surge protection test process. From surge waveform simulation monitoring, to quality judgment and adjustment, to chip protection testing and result grading, a complete closed loop is formed, effectively eliminating human errors and environmental interference during the test process, and greatly improving the reliability and consistency of test data. At the same time, the system can quickly screen out surge waveforms that meet the requirements, avoid invalid tests, and significantly improve test efficiency, providing comprehensive and reliable technical support for the scientific evaluation of the surge protection performance of onboard power supply chips.

[0009] 2. Real-time monitoring of the surge interference waveform based on the established test environment can accurately capture waveform changes during the surge test and ensure the traceability of the surge interference waveform. Through real-time monitoring, waveform anomalies can be discovered in a timely manner, providing original and accurate data basis for subsequent quality judgment, ensuring the effectiveness of the test from the source and avoiding test deviations caused by waveform distortion.

[0010] 3. Real-time acquisition and analysis of the quality parameters of the surge interference waveform can quickly determine whether the waveform meets the test conditions; for waveforms that do not meet the conditions, timely adjustments can be made to ensure that the surge waveform applied to the chip meets the test standards, reducing test result errors caused by waveform quality problems, improving test accuracy, avoiding invalid tests, and saving test resources.

[0011] 4. Surge waveforms that meet the test conditions are strictly screened and applied to the chip under test to avoid interference from unqualified waveforms on the test from the source, ensure the consistency and standardization of the test input, and reduce the result deviation caused by waveform differences; during the protection test, through accurate analysis and comprehensive collection of process parameters, the various response data of the chip under surge impact can be fully recorded, providing a sufficient basis for result analysis and avoiding misjudgment caused by omission of key information; and the reliability grading processing based on standardized processes adopts unified evaluation standards and quantitative indicators, which effectively eliminates the influence of human subjective judgment, makes the test results of different chips comparable, and ensures the objectivity of the grading results; at the same time, the complete parameter records and grading logic are traceable, which facilitates the subsequent review and verification of the test results, further consolidating the reliability foundation of the test results and providing a solid guarantee for the accurate evaluation of the surge protection performance of the onboard power chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A schematic diagram of the module connection of a surge protection test system for a satellite-borne power chip is provided for an embodiment of the present invention; Figure 2 A schematic flow chart of the steps of a surge protection test method for a satellite-borne power supply chip is provided for an embodiment of the present invention; Figure 3 A schematic flow chart of the steps of the method for determining the quality of a surge interference waveform according to the present invention; Figure 4 A schematic flow chart of the method steps for fine-tuning the surge interference waveform of the present invention; Figure 5 A schematic flow chart of the steps of the method for grading surge protection test results according to the present invention; Figure 6 A schematic flow chart of the steps of the method for determining a reliability level change according to the present invention; Figure 7 Schematic diagram of the steps of the method for re-judging the reliability of chip test results of the present invention; Figure 8 This is a schematic diagram of the principle of surge protection test and waveform analysis of the onboard power chip of the present invention. Figure 8 Part (a) is the waveform after ideal surge suppression. Figure 8 Part (b) shows the surge waveform that is not suppressed or fails to be suppressed. DETAILED DESCRIPTION

[0014] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0015] Unless otherwise defined, the technical or scientific terms used in the present invention shall have the usual meaning understood by persons of ordinary skill in the field to which the present invention belongs. The words "first", "second" and similar terms used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the presence of at least one. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0016] It should be noted that the terms "up", "down", "left", "right", "front" and "back" used in the present invention are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0017] The present invention provides a system and method for testing surge protection of a satellite-borne power supply chip. Figure 1As shown, an embodiment of the present invention provides a satellite-borne power chip surge protection test system, including: a surge waveform simulation monitoring module, a surge waveform quality judgment and adjustment module, a chip test reliability grading module and a test database.

[0018] The surge waveform simulation monitoring module is connected to the surge waveform quality judgment and adjustment module, which is connected to the chip test reliability grading module. The surge waveform simulation monitoring module, the surge waveform quality judgment and adjustment module, and the chip test reliability grading module are all connected to a test database; the above-mentioned test database is used to store various parameters involved in a surge protection test system for a satellite-borne power chip.

[0019] The surge waveform simulation monitoring module is used to monitor the surge interference waveform during the surge test in the test environment based on the established test environment; the surge waveform quality judgment and adjustment module is used to obtain the quality parameters of the surge interference waveform in real time, analyze the obtained surge interference waveform quality parameters, and thus determine whether the surge interference waveform meets the test conditions; the chip test reliability grading module is used to apply the surge interference waveform that meets the test conditions to the onboard power chip to be tested for protection testing, collect and analyze the process parameters of the protection test, and thus grade the surge protection test results of the onboard power chip.

[0020] The above-mentioned test environment, based on the completed construction, refers to the standardized basic conditions constructed for the surge protection test of satellite-borne power chips, which includes three core elements: hardware, software and environmental control. In terms of hardware, it is equipped with a calibrated surge generation module, high-speed monitoring equipment (such as an oscilloscope), a chip mounting platform (including a vacuum chamber) and an impedance matching circuit to ensure stable transmission of surge signals; in terms of software, it integrates automatic control programs, data acquisition and analysis systems and test databases to store preset thresholds and historical data to ensure accurate parameter calculation and judgment logic; in terms of environment, external interference is eliminated through electromagnetic shielding, temperature and humidity control, and grounding treatment; this integrated platform provides a stable, controllable and traceable operating basis for modules such as surge waveform simulation monitoring, quality judgment and adjustment, and chip test reliability grading, ensuring the accuracy and consistency of the entire test process.

[0021] In this embodiment, whether the surge interference waveform meets the test conditions is judged. The specific judgment process is: analyzing the obtained surge interference waveform quality parameters to obtain the surge interference waveform quality index, and comparing it with the surge interference waveform quality threshold preset in the test database.

[0022] The above-mentioned surge interference waveform quality threshold refers to the minimum value of the surge interference waveform quality index within a specified range.

[0023] If the surge interference waveform quality index is greater than or equal to the surge interference waveform quality threshold, it is determined that the surge interference waveform meets the test conditions. At the same time, the parameters of the surge interference waveform that meets the test conditions are fine-tuned to determine the stability of the surge interference waveform. If the surge interference waveform quality index is less than the surge interference waveform quality threshold, it is determined that the surge interference waveform does not meet the test conditions. Based on the surge interference waveform quality index and the surge interference waveform quality threshold, a surge quality deviation value is obtained. Based on the surge quality deviation value, the trigger pulse amplitude increase coefficient is matched to increase the amplitude of the trigger pulse, thereby enhancing the instantaneous excitation intensity of the energy storage element in the surge generation module, such as the high-voltage capacitor, to ensure that the stored energy is quickly and fully released, accelerate the conduction speed of the discharge circuit, reduce the circuit delay, make the rising edge of the surge waveform steeper, that is, reduce the rise time deviation, and avoid the problem of slow waveform oscillation caused by insufficient trigger energy. In addition, a stable high-amplitude trigger pulse can reduce random fluctuations in the initial stage of the waveform, make the overshoot amplitude closer to the target value, and reduce waveform distortion caused by inconsistent triggering, for example Initial oscillation anomalies are detected, thereby improving the initial characteristics of the surge waveform at the source and laying the foundation for subsequent waveform stability. The power amplification factor of the driving circuit is matched based on the surge quality deviation value, thereby increasing the power of the driving circuit and enhancing the continuous energy supply capability of the surge generation module. On the one hand, higher driving power can compensate for loop losses, such as line resistance, ensuring that the peak amplitude of the surge waveform meets the design standard and avoiding amplitude reduction due to insufficient energy supply. On the other hand, stable driving power can precisely control the oscillation decay rate of the waveform. By adjusting the dynamic response of the power output, the oscillation amplitude of the waveform after the overshoot decays according to a preset pattern, such as an exponential decay curve, reducing decay disturbances caused by power fluctuations, such as sudden acceleration or deceleration. In addition, sufficient driving power can resist external load changes, such as interference from impedance fluctuations of the chip under test, maintaining the stability of the surge waveform throughout the entire sustained phase, thereby improving the waveform's sustained characteristics and enhancing overall quality consistency. The system also utilizes historical operating data of the surge generation module to automatically recommend parameter combinations.

[0024] The above-mentioned acquisition of the surge quality deviation value refers to the result of subtracting the surge interference waveform quality index from the surge interference waveform quality threshold. The above-mentioned matching of the trigger pulse amplitude increase coefficient based on the surge quality deviation value is a specific matching process: the trigger pulse amplitude increase coefficient corresponding to each surge quality deviation value interval is stored in the test database, and the obtained surge quality deviation value is input into the test database. The test database can match the corresponding surge quality deviation value interval, and the trigger pulse amplitude increase coefficient corresponding to the interval is the required increase coefficient. The obtained trigger pulse amplitude increase coefficient is multiplied by the original trigger pulse amplitude, and the result is the trigger pulse amplitude that needs to be adjusted; the above-mentioned trigger pulse amplitude increase coefficient is greater than 1, indicating that the trigger pulse amplitude needs to be increased by a multiple.

[0025] The above-mentioned matching of the driving circuit power increase coefficient based on the surge quality deviation value is carried out in the following specific matching process: the driving circuit power increase coefficient corresponding to each surge quality deviation value interval is stored in the test database, and the obtained surge quality deviation value is input into the test database. The test database can match the corresponding surge quality deviation value interval, and the driving circuit power increase coefficient corresponding to the interval is the required increase coefficient. The obtained driving circuit power increase coefficient is multiplied by the original driving circuit power, and the result is the driving circuit power that needs to be adjusted; the above-mentioned driving circuit power increase coefficient is greater than 1, which indicates that the driving circuit power needs to be increased by a multiple of the value.

[0026] The above-mentioned call of the historical operating data of the surge generation module refers to the automatic recommendation of various parameter combinations through machine learning algorithms, such as random forest analysis of the correlation between the current deviation value and historical unqualified cases, thereby shortening the parameter debugging cycle. The above-mentioned automatically recommended parameter combinations refer to the correction value of the energy storage voltage, the gain correction value of the drive circuit, etc.

[0027] The surge interference waveform quality index is re-obtained and marked as a surge quality review index, so as to determine whether to issue an early warning for the surge interference waveform.

[0028] In one specific embodiment, real-time monitoring of the surge interference waveform within a pre-established test environment accurately captures every waveform change during the test, ensuring traceability. Furthermore, this real-time monitoring mechanism promptly detects waveform anomalies, providing original and accurate data support for subsequent quality assessments. This ensures the effectiveness of the entire process from the very beginning and effectively avoids test deviations caused by waveform distortion.

[0029] In this embodiment, the surge interference waveform quality index is specifically analyzed as follows: the quality parameters of the surge interference waveform include the overshoot amplitude factor of the surge interference waveform, the rising edge steepness factor of the surge interference waveform, and the oscillation attenuation rate factor of the surge interference waveform.

[0030] The above-mentioned overshoot amplitude factor characterizes the deviation relationship between the overshoot amplitude of the surge interference waveform and its corresponding reference value; the above-mentioned rising edge steepness factor characterizes the deviation relationship between the rising edge steepness of the surge interference waveform and its corresponding reference value; the above-mentioned oscillation attenuation rate factor characterizes the deviation relationship between the oscillation attenuation rate of the surge interference waveform and its corresponding reference value.

[0031] In the test database, the corresponding action intensity coefficients of the overshoot amplitude factor, rising edge steepness factor, and oscillation attenuation rate factor are set to quantify the contribution of each factor to the surge interference waveform quality index. Finally, the surge interference waveform quality index is obtained by weighted comprehensive analysis of the contribution values. The surge interference waveform quality index indicates the quality of the surge generated by the surge generation module. The specific evaluation method is as follows: ; ; ; ; Wherein, SOI is the surge interference waveform quality index, OAF is the overshoot amplitude factor of the surge interference waveform, OA is the overshoot amplitude of the surge interference waveform, DOA is the reference overshoot amplitude preset in the test database, RSF is the rising edge steepness factor of the surge interference waveform, RS is the rising edge steepness of the surge interference waveform, DRS is the reference rising edge steepness preset in the test database, ODRF is the oscillation attenuation rate factor of the surge interference waveform, ODR is the oscillation attenuation rate of the surge interference waveform, DODR is the reference oscillation attenuation rate preset in the test database, gc is the action intensity coefficient corresponding to the overshoot amplitude factor preset in the test database, gh is the action intensity coefficient corresponding to the rising edge steepness factor preset in the test database, and gp is the action intensity coefficient corresponding to the oscillation attenuation rate factor preset in the test database.

[0032] It should be explained that the above-mentioned reference overshoot amplitude refers to the reference value of the overshoot amplitude within the specified range; the above-mentioned reference rising edge steepness refers to the reference value of the rising edge steepness within the specified range; the above-mentioned reference oscillation attenuation rate refers to the reference value of the oscillation attenuation rate within the specified range.

[0033] The overshoot amplitude of the above-mentioned surge interference waveform refers to the additional amplitude value of the surge waveform exceeding the preset peak value after the surge waveform reaches the preset peak value. The instantaneous peak data of the waveform is collected in real time through the surge waveform simulation monitoring module, and the preset target peak value is subtracted from the maximum instantaneous value collected to obtain the overshoot amplitude; the rising edge steepness of the above-mentioned surge interference waveform refers to the speed at which the surge waveform rises from the starting value (such as 0) to the preset peak value. The shorter the time, the higher the steepness. It is obtained by recording the time interval for the waveform to rise from 10% of the peak value to 90% of the peak value; the oscillation decay rate of the above-mentioned surge interference waveform refers to the rate at which the oscillation waveform generated by energy release or circuit characteristics after the surge waveform reaches the peak value decays over time. It is obtained by calculating the time ratio of the peak values ​​of adjacent oscillation cycles after the peak value.

[0034] The higher the rising edge steepness, the shorter the rise time, the more rapid the energy release, and the more likely it is to cause the overshoot amplitude to increase; the larger the overshoot amplitude, the higher the initial surge energy, and the slower the subsequent oscillation decays, that is, the lower the decay rate; the higher the rising edge steepness, the stronger the sudden energy release, the more violent the oscillation after the overshoot and the slower the decay, that is, the lower the decay rate.

[0035] The action intensity coefficient corresponding to the above-mentioned overshoot amplitude factor indicates the corresponding degree of change of the surge interference waveform quality index when the factor undergoes a unit change; the action intensity coefficient corresponding to the above-mentioned rising edge steepness factor indicates the corresponding degree of change of the surge interference waveform quality index when the factor undergoes a unit change; the action intensity coefficient corresponding to the above-mentioned oscillation attenuation rate factor indicates the corresponding degree of change of the surge interference waveform quality index when the factor undergoes a unit change; the test database stores the mapping relationship between the overshoot amplitude factor and its corresponding action intensity coefficient, the mapping relationship between the rising edge steepness factor and its corresponding action intensity coefficient, and the mapping relationship between the oscillation attenuation rate factor and its corresponding action intensity coefficient; for example, the overshoot amplitude factor, the rising edge steepness factor and the oscillation attenuation rate factor are input into the test database, and the test database will generate the corresponding action intensity coefficient corresponding to the overshoot amplitude factor, the action intensity coefficient corresponding to the rising edge steepness factor and the action intensity coefficient corresponding to the oscillation attenuation rate factor based on the preset mapping rules, and the numerical range of each action intensity coefficient is strictly controlled between 0 and 1.

[0036] A larger overshoot amplitude factor means that the waveform peak value exceeds or falls more significantly below the reference standard. If the overshoot amplitude is too high, it may exceed the designed surge resistance threshold of the chip under test, resulting in distortion of the test scenario. If the overshoot amplitude is too low, it cannot simulate the impact intensity of the actual surge, resulting in a lower surge interference waveform quality index. A larger rising edge steepness factor may result in a rise time that is too long (insufficient steepness) or too short (excessive steepness). A long rise time will cause the surge energy release rhythm to deviate from the actual scenario, making it impossible to test the chip's response to fast shocks. A short rise time may expose the chip to transient stress beyond actual operating conditions, resulting in a lower surge interference waveform quality index. A larger oscillation decay rate factor may result in too fast or too slow energy release. Too fast release will result in insufficient surge impact duration, making it impossible to test the chip's protection performance under long-term interference. Too slow release will cause the energy to remain on the chip for too long, potentially causing unnecessary cumulative damage. Both situations will lead to a decrease in the surge interference waveform quality index.

[0037] In a specific example embodiment, the surge quality threshold preset in the test database is 0.8, and the quality index range is 0 to 1. The closer the value is to 1, the better the waveform quality. If the surge interference waveform quality index obtained by the current analysis is 0.65, then the surge quality deviation value is equal to the surge quality threshold minus the current surge interference waveform quality index, that is, 0.8 minus 0.65, and the result is 0.15; the correspondence between the preset deviation value interval and the coefficient in the test database, for example, the deviation value is between 0.1 and 0.2, the trigger pulse amplitude increase coefficient is 1.2, because the current deviation value is 0.15, which belongs to the range of 0.1 to 0.2, so the increase coefficient is matched to 1.2. If the original trigger pulse amplitude is 5V, the adjusted amplitude is 5V multiplied by 1.2, and the final result is 6V.

[0038] In this embodiment, whether to issue an early warning for the surge interference waveform is determined. The specific judgment process is: comparing the surge quality review index with the surge interference waveform quality threshold; if the surge quality review index is greater than or equal to the surge interference waveform quality threshold, it is determined that no early warning is issued for the surge interference waveform, and at the same time, the surge interference waveform parameters that meet the test conditions are fine-tuned to determine the stability of the surge interference waveform. If the surge quality review index is less than the surge interference waveform quality threshold, it is determined that an early warning is issued for the surge interference waveform.

[0039] It should be explained that the above-mentioned fine-tuning of the surge interference waveform parameters that meet the test conditions refers to the surge interference waveform parameters that meet the test conditions, such as peak voltage, which, without exceeding the upper or lower limit of the parameter specified in the range, is adjusted by a small amplitude to achieve the stability judgment of the surge interference waveform and avoid the subsequent test deviation caused by excessive fluctuation of the parameters within the qualified range; the above-mentioned early warning of the surge interference waveform refers to the generation of a real-time waveform comparison chart, marking the parameter interval with excessive deviation in red, such as the overshoot peak segment, to intuitively display the waveform distortion position and assist in quickly locating the problem; the above-mentioned small amplitude is usually controlled within ±1% to ±10%.

[0040] In a specific embodiment, the quality parameters of the surge interference waveform are collected and analyzed to quickly determine whether the waveform meets the test conditions. For waveforms that do not meet the conditions, adjustments can be made in a timely manner to ensure that the surge waveform applied to the chip meets the test standards, reduce test result errors caused by waveform quality problems, and improve test accuracy. At the same time, this process can also avoid invalid tests and save valuable test resources.

[0041] like Figure 3As shown in the flowchart of the method steps for judging the quality of a surge interference waveform of the present invention, the process begins with a well-established test environment. The surge generation module simulates the surge interference waveform according to preset parameters, analyzes its quality to obtain a surge interference waveform quality index, and if the surge interference waveform quality index is greater than or equal to the surge interference waveform quality threshold, it is determined that the surge meets the test conditions; if it is less than the surge interference waveform quality threshold, the trigger pulse amplitude is increased and the driving circuit power is enhanced. At the same time, the historical operation data of the surge generation module is called to automatically recommend a parameter combination, and a surge quality review index is obtained. If the surge quality review index is greater than or equal to the surge interference waveform quality threshold, it is determined that the test conditions are met. Otherwise, a surge interference waveform warning is issued.

[0042] In this embodiment, the stability of the surge interference waveform is judged, and the specific analysis process is as follows: obtaining the surge interference waveform quality index after fine-tuning and marking it as the surge interference waveform fine-tuning quality index; if the surge interference waveform fine-tuning quality index is greater than or equal to the surge interference waveform quality threshold, then it is judged that the surge interference waveform is stable; if the surge interference waveform fine-tuning quality index is less than the surge interference waveform quality threshold, then it is judged that the surge interference waveform is not stable, and an early warning is issued to the surge generation module, and at the same time, an instruction is generated to check the linearity of the surge generation equipment.

[0043] It should be explained that the above-mentioned early warning of the surge generating module refers to sending the early warning information to the operation and maintenance platform; the above-mentioned generation of the instruction for checking the linearity of the surge generating device is directed to the surge generating device, and the instruction content usually includes checking the nonlinearity of the power amplifier, the temperature drift of the energy storage element, etc.

[0044] like Figure 4 As shown in the flowchart of the method steps for fine-tuning the surge interference waveform of the present invention, after the test conditions are met, the surge interference waveform parameters are fine-tuned and the surge fine-tuning quality index is obtained: if the surge fine-tuning quality index is greater than or equal to the surge interference waveform quality threshold, it is determined that the surge is stable, and the data is analyzed in real time to generate a chip test reliability index; otherwise, an early warning is issued for the surge occurrence module and an instruction is generated to check the linearity of the equipment.

[0045] In this embodiment, the surge protection test results of the onboard power chip are graded. The specific analysis process is: analyzing the protection test process parameters, obtaining the chip test reliability index, and comparing it with the first reliability index and the second reliability index preset in the test database. It should be noted that the first reliability index is greater than the second reliability index.

[0046] The first reliability index is the numerical value used to divide reliability levels from level 1 and level 2; the second reliability index is the numerical value used to divide reliability levels from level 2 and level 3. If the chip test reliability index is greater than the first reliability index, the chip test result is marked as level 1 reliability, and the chip's stable on-orbit operating time in a satellite-based environment is predicted. The above-mentioned prediction of the chip's stable on-orbit operating time in a satellite-based environment refers to the accelerated aging test of qualified satellite-based power supply chips based on the level 1 reliability test results. Combined with the parameter attenuation trend during the aging process, the Weibull distribution model is used to predict the chip's stable on-orbit operating time in a satellite-based environment. The above-mentioned accelerated aging test refers to 1,000 repeated shocks at 1.2 times the rated surge energy.

[0047] If the chip test reliability index is less than or equal to the first reliability index and greater than or equal to the second reliability index, the chip test result is marked as level 2 reliability, and the chip test process is optimized. If the chip test reliability index is less than the second reliability index, the chip test result is marked as level 3 reliability, and the chip test process is improved. It should be noted that level 1 reliability is better than level 2 reliability, which is better than level 3 reliability. The chip test reliability index is re-obtained and marked as the final chip test reliability value to determine whether to issue a warning on the reliability of the chip test result.

[0048] In a specific embodiment, qualified surge waveforms are strictly screened and applied to the chip to prevent interference from unqualified waveforms at the source, ensuring consistent test input and reducing test result deviation. As shown in Table 1, the test data recorder records relevant data from a single surge test, covering three categories: surge waveform parameters (input), chip response parameters (output), and environmental and system parameters. Surge waveform parameters (input) include surge peak voltage, surge rise time, surge half-peak time, and surge energy, and characterize the input surge signal. Chip response parameters (output) record the transient voltage at the chip input port and the fluctuation amplitude of the chip output voltage, reflecting the chip's response to the surge. Environmental and system parameters involve the peak junction temperature inside the chip, chip recovery time after surge, chip leakage current change, test environment temperature, test loop impedance, and data acquisition frequency. They provide support for surge impact test analysis from the dimensions of the environment, system, and chip status itself, and comprehensively present the performance of the chip and system in a single surge impact test through multi-dimensional data; during the test, the acquisition process parameters are accurately analyzed and the chip response data is completely recorded to provide sufficient basis for analysis and avoid missing and misjudgment of key information; relying on standardized process grading, unified evaluation standards and quantitative indicators are adopted to eliminate subjective influences and ensure comparable and objective results; complete records and grading logic are traceable, which is convenient for review and verification, consolidates the reliability of the results, and provides solid guarantees for the evaluation of chip surge protection performance.

[0049] Table 1 Test data record table

[0050] like Figure 5 As shown in the flowchart of the method steps for grading the surge protection test results of the present invention, if the chip test reliability index is greater than the first reliability index, it is marked as the first-level reliability and the stable working time on orbit is predicted; if the chip test reliability index is between the first and second reliability indexes, it is marked as the second-level reliability and the surge injection phase deviation is reduced, and the final value of the chip test reliability is obtained at the same time; if the chip test reliability index is less than the second reliability index, it is marked as the third-level reliability and the cutoff frequency of the input filter network is increased, and the final value of the chip test reliability is obtained at the same time.

[0051] In this embodiment, the process parameters of the protection test are analyzed. The specific analysis process is: the process parameters of the protection test include the impedance mutation rate factor of the surge injection point during the protection test, the thermal gradient attenuation rate factor inside the chip after the surge, and the transient common mode voltage factor between the chip pins; and the comprehensive index of the surge interference waveform quality is obtained.

[0052] The above-mentioned impedance mutation rate factor characterizes the ratio of the impedance mutation rate at the surge injection point to its corresponding limit value; the above-mentioned thermal gradient decay rate factor characterizes the deviation relationship between the thermal gradient decay rate inside the chip after the surge and its corresponding reference value; the above-mentioned transient common-mode voltage factor characterizes the ratio of the transient common-mode voltage between the chip pins to its corresponding limit value; the above-mentioned surge interference waveform quality comprehensive index refers to the surge interference waveform quality index of the surge interference waveform that ultimately meets the test conditions.

[0053] In the test database, the corresponding action intensity coefficients of the impedance mutation rate factor, thermal gradient attenuation rate factor, transient common mode voltage factor, and surge interference waveform quality comprehensive index are set to quantify the contribution of each factor to the chip test reliability index. Finally, the chip test reliability index is obtained by weighted comprehensive contribution of each factor. The chip test reliability index refers to the reliability of the chip test results. The specific evaluation method is as follows: ; ; ; ; Where CTRI is the chip test reliability index, SOI_Z is the comprehensive index of surge interference waveform quality, ICRF is the impedance mutation rate factor at the surge injection point, ICR is the impedance mutation rate at the surge injection point, DICR is the defined impedance mutation rate preset in the test database, TGODF is the thermal gradient decay rate factor inside the chip after surge, TGOD is the thermal gradient decay rate inside the chip after surge, DTGOD is the reference thermal gradient decay rate preset in the test database, TCMVF is the transient common mode voltage factor between chip pins, TCMV is the transient common mode voltage between chip pins, DTCMV is the defined transient common mode voltage preset in the test database, fp is the action intensity coefficient corresponding to the impedance mutation rate factor preset in the test database, fr is the action intensity coefficient corresponding to the thermal gradient decay rate factor preset in the test database, fw is the action intensity coefficient corresponding to the transient common mode voltage factor preset in the test database, and fq is the action intensity coefficient corresponding to the comprehensive index of surge interference waveform quality preset in the test database.

[0054] It should be explained that the above-mentioned definition of impedance mutation rate refers to the maximum value of the impedance mutation rate at the surge injection point within the specified range; the above-mentioned reference thermal gradient decay rate refers to the reference value of the thermal gradient decay rate inside the chip after a surge; the above-mentioned definition of transient common-mode voltage refers to the maximum value of the transient common-mode voltage between chip pins within the specified range.

[0055] The impedance mutation rate at the surge injection point refers to the rate of change of the impedance value in a very short period of time when the surge signal is injected into the chip test circuit. This is obtained by collecting the impedance values ​​before and after the injection point at the moment of surge injection, and calculating the impedance change at the moment of injection divided by the time interval. The thermal gradient decay rate inside the chip after the surge refers to the decay rate over time of the spatial temperature gradient generated by the concentrated surge energy inside the chip after the surge interference ends. After the surge ends, the temperature changes in different areas inside the chip are continuously monitored using infrared thermal imaging and other means, and the decrease in the thermal gradient per unit time is calculated to obtain the value. The transient common-mode voltage between the chip pins refers to the instantaneous common-mode potential difference generated by each chip pin, such as the power pin, relative to the common reference ground, i.e., the test system ground, during the surge interference. This is obtained by synchronously collecting the voltage between each chip pin and the reference ground when the surge occurs with the help of a high-speed oscilloscope, and calculating the transient change of the voltage difference between the pins.

[0056] An increase in the impedance mutation rate at the surge injection point will exacerbate the instability of energy transfer, triggering greater transient voltage fluctuations and increasing the transient common-mode voltage between chip pins. At the same time, unstable energy injection may cause uneven distribution of surge energy absorbed within the chip, increasing local heat accumulation and reducing the thermal gradient decay rate. When the transient common-mode voltage between chip pins increases, it is easily converted into additional heat through internal parasitic parameters such as resistance, exacerbating the temperature distribution differences within the chip and thereby slowing the thermal gradient decay rate.

[0057] The action intensity coefficient corresponding to the above-mentioned impedance mutation rate factor indicates the corresponding degree of change of the chip test reliability index when the factor undergoes a unit change; the action intensity coefficient corresponding to the above-mentioned thermal gradient attenuation rate factor indicates the corresponding degree of change of the chip test reliability index when the factor undergoes a unit change; the action intensity coefficient corresponding to the above-mentioned transient common mode voltage factor indicates the corresponding degree of change of the chip test reliability index when the factor undergoes a unit change; the action intensity coefficient corresponding to the above-mentioned surge interference waveform quality comprehensive index indicates the corresponding degree of change of the chip test reliability index when the comprehensive index undergoes a unit change; the test database stores the mapping relationship between the impedance mutation rate factor and its corresponding action intensity coefficient, and the thermal gradient attenuation rate factor and its corresponding The mapping relationship between the action intensity coefficient, the mapping relationship between the transient common-mode voltage factor and its corresponding action intensity coefficient, and the mapping relationship between the surge interference waveform quality comprehensive index and its corresponding action intensity coefficient; for example, the impedance mutation rate factor, the thermal gradient attenuation rate factor, the transient common-mode voltage factor and the surge interference waveform quality comprehensive index are input into the test database, and the test database will generate the action intensity coefficient corresponding to the impedance mutation rate factor corresponding to the corresponding edge positioning error factor, the action intensity coefficient corresponding to the thermal gradient attenuation rate factor, the action intensity coefficient corresponding to the transient common-mode voltage factor, and the action intensity coefficient corresponding to the surge interference waveform quality comprehensive index based on the preset mapping rules, and the numerical range of each action intensity coefficient is strictly controlled between 0 and 1.

[0058] A larger impedance mutation rate factor indicates that the actual mutation rate exceeds the acceptable range, the more unstable the surge energy transfer is, and the higher the risk of impact on the chip. Therefore, the chip test reliability index decreases as the factor increases. A smaller thermal gradient decay rate factor indicates that the chip can quickly eliminate continuous thermal stress and avoid chronic damage caused by long-term temperature differences without exceeding the thermal shock tolerance threshold of the chip material, such as the thermal shock coefficient of silicon. Therefore, the chip test reliability index increases. A larger transient common-mode voltage factor indicates that the transient voltage between pins exceeds the safe range, which can easily cause internal circuit malfunction or breakdown. Therefore, the chip test reliability index decreases as the factor increases. A higher surge interference waveform quality comprehensive index indicates that the surge waveform more meets the test conditions, such as waveform parameters, energy transfer, and interference intensity. The surge impact the chip withstands can more truly reflect its protection capabilities, and the reliability foundation of the test results is more solid. Therefore, the chip test reliability index increases as the factor increases.

[0059] In this embodiment, the chip testing process is optimized. The specific optimization process is: based on the chip test reliability index and the first reliability index, a first reliability deviation value is obtained, and based on the first reliability deviation value, the surge injection phase deviation reduction is matched, thereby reducing the phase deviation of the surge injection. Targeted matching of the phase deviation reduction can make the surge impact more in line with the typical working conditions in the actual application of the chip, such as surge interference under the target phase. The consistency between the test conditions and the real scene is improved, avoiding over-testing or under-testing due to phase deviation, and enhancing the accuracy of the results in characterizing the actual reliability of the chip.

[0060] The above-mentioned acquisition of the first reliability deviation value refers to the result of subtracting the chip test reliability index from the first reliability index; the above-mentioned matching of the surge injection phase deviation reduction based on the first reliability deviation value, the specific matching process is: the test database stores the surge injection phase deviation reduction corresponding to each first reliability deviation value interval, and the obtained first reliability deviation value is input into the test database. The test database can match the corresponding surge injection phase deviation reduction, thereby reducing the phase deviation of the surge injection.

[0061] In a specific example embodiment, the first reliability index preset in the test database is 0.9, the second reliability index is 0.7, and the reliability index range is 0 to 1. The higher the value, the better the reliability. Taking a chip to be tested as an example, its initial chip test reliability index is 0.85, which is in the second reliability range, and the reliability needs to be improved through an optimization process; the first reliability index is subtracted from the chip test reliability index, that is, 0.9 is subtracted from 0.85, and the result 0.05 is the first reliability deviation value; the correspondence between the deviation value interval and the phase deviation reduction amount preset in the test database, for example, when the first reliability deviation value is between 0.03 and 0.07, the surge injection phase deviation reduction amount is 2°. Since the current first reliability deviation value 0.05 belongs to this interval, the phase deviation reduction amount is matched to 2°.

[0062] The chip testing process is improved. The specific improvement process is: based on the chip test reliability index and the second reliability index, a second reliability deviation value is obtained, and based on the second reliability deviation value, the input filter network cutoff frequency increase coefficient is matched, thereby increasing the chip's input filter network cutoff frequency. On the one hand, increasing the cutoff frequency can reduce the excessive attenuation of high-frequency transient components in the surge, so that the surge signal applied to the chip is closer to the interference characteristics in the actual working conditions, avoids signal distortion caused by excessive filtering, and improves the accuracy of the test characterization of the chip's true surge resistance. On the other hand, by matching the adjustment coefficient with the second reliability deviation value, the cutoff frequency of the filter network can be accurately matched with the chip's anti-interference design target, reducing the test discreteness caused by unstable filtering characteristics, avoiding "excessive filtering to cover up defects" or "insufficient filtering to introduce noise" caused by misjudgment, and ultimately making the test results more stable and reliable, providing a reliable basis for the evaluation of the chip's surge resistance performance.

[0063] The above-mentioned acquisition of the second reliability deviation value refers to the result of subtracting the chip test reliability index from the second reliability index; the above-mentioned matching of the input filter network cutoff frequency increase coefficient based on the second reliability deviation value, the specific matching process is: the input filter network cutoff frequency increase coefficient corresponding to each second reliability deviation value interval is stored in the test database, and the obtained second reliability deviation value is input into the test database. The test database can match the corresponding second reliability deviation value interval, and the input filter network cutoff frequency increase coefficient corresponding to the interval is the required increase coefficient. The obtained input filter network cutoff frequency increase coefficient is multiplied by the original input filter network cutoff frequency, and the result obtained is the input filter network cutoff frequency that needs to be adjusted; the above-mentioned input filter network cutoff frequency increase coefficient is greater than 1, indicating that the input filter network cutoff frequency needs to be increased by a multiple.

[0064] In this embodiment, it is determined whether to issue a warning for the reliability of the chip test results. The specific judgment process is: the final value of the chip test reliability is compared with the first reliability index and the second reliability index to obtain different levels of reliability, and based on the changes in different levels of reliability, it is determined whether to issue a warning for the reliability of the chip test results; if the second-level reliability is changed to the first-level reliability or the third-level reliability is changed to the first-level reliability, it is determined that no warning is issued for the reliability of the chip test results, and the stable on-orbit working time of the chip in the onboard environment is predicted at the same time; if the second-level reliability is maintained or the third-level reliability is maintained or the second-level reliability is changed to the third-level reliability, it is determined that a warning is issued for the reliability of the chip test results; the above-mentioned warning for the reliability of the chip test results refers to sending the warning information to the operation and maintenance platform.

[0065] like Figure 6As shown in the flowchart of the method steps for determining reliability level changes of the present invention, after obtaining the final value of chip test reliability, the level change is determined as follows: when the second-level reliability or the third-level reliability rises to the first-level reliability, no warning is issued and the on-orbit time is predicted; when the second-level reliability is maintained, the third-level reliability is maintained, or the second-level reliability is reduced to the third-level reliability, a reliability warning is issued; when the third-level reliability rises to the second-level reliability, the chip test reliability improvement rate is calculated.

[0066] If the third-level reliability is changed to the second-level reliability, the chip test reliability improvement rate is obtained based on the chip test reliability final value and the chip test reliability index, and the input filter network cutoff frequency quadratic increase coefficient is matched based on the chip test reliability improvement rate, thereby further increasing the input filter network cutoff frequency of the chip, and at the same time, the chip test reliability index is re-obtained and marked as the chip test reliability re-judgment index; the above-mentioned chip test reliability improvement rate is obtained, which refers to the result of subtracting the chip test reliability index from the chip test reliability final value and dividing it by the chip test reliability index; the above-mentioned matching of the input filter network cutoff frequency quadratic increase coefficient based on the chip test reliability improvement rate, the specific matching process The test database stores the quadratic increase coefficient of the input filter network cutoff frequency corresponding to each chip test reliability improvement rate interval, and inputs the obtained chip test reliability improvement rate into the test database. The test database can match the corresponding chip test reliability improvement rate interval, and the quadratic increase coefficient of the input filter network cutoff frequency corresponding to the interval is the required quadratic increase coefficient. The obtained quadratic increase coefficient of the input filter network cutoff frequency is multiplied by the original input filter network cutoff frequency, and the result is the input filter network cutoff frequency that needs to be adjusted; the above-mentioned quadratic increase coefficient of the input filter network cutoff frequency is greater than 1, indicating that the input filter network cutoff frequency needs to be further increased by a multiple.

[0067] The chip test reliability re-judgment index is compared with the first reliability index and the second reliability index to obtain the reliability level result; if it is the first level reliability, it is judged that no warning is issued for the reliability of the chip test result, and the stable on-orbit working time of the chip in the onboard environment is predicted at the same time; the above-mentioned different levels of reliability are consistent with the analysis process of grading the surge protection test results of the onboard power chip in the previous article; if it is the second level reliability or the third level reliability, it is judged that a warning is issued for the reliability of the chip test result, and the above-mentioned prediction of the stable on-orbit working time of the chip in the onboard environment is consistent with the process of predicting the stable on-orbit working time of the chip in the onboard environment in the previous article.

[0068] In a specific embodiment, the present invention provides a surge protection test system for satellite-borne power chips, thereby achieving standardization, automation, and precision of the entire surge protection test process; from simulation monitoring of surge waveforms, to quality judgment and adjustment, to chip protection testing and result grading, a complete closed loop is formed, which effectively eliminates human errors and environmental interference in the test process, and greatly improves the reliability and consistency of test data; at the same time, the system can quickly screen out surge waveforms that meet the requirements, avoid invalid tests, and significantly improve test efficiency, providing comprehensive and reliable technical support for the scientific evaluation of the surge protection performance of satellite-borne power chips.

[0069] like Figure 7 As shown in the flowchart of the method steps for re-judging the reliability of chip test results of the present invention, the input filter network cutoff frequency is further increased based on the chip test reliability improvement rate to obtain the chip test reliability re-judgment index; if the re-judgment is level one reliability, no warning is issued and the duration is predicted; if it is level two or level three reliability, a warning is issued, and finally the entire test process is completed.

[0070] Reference Figure 2 As shown, the second aspect of the present invention provides a surge protection test method for a satellite power chip, including: S1. Based on a completed test environment, in the test environment, monitoring the surge interference waveform during the surge test; S2. Acquiring the quality parameters of the surge interference waveform in real time, analyzing the acquired surge interference waveform quality parameters, and thus determining whether the surge interference waveform meets the test conditions; S3. Applying the surge interference waveform that meets the test conditions to the satellite power chip to be tested for protection testing, collecting and analyzing the process parameters of the protection test, and thus performing graded processing on the surge protection test results of the satellite power chip.

[0071] Reference Figure 8 , as shown in the principle diagram of the onboard power chip surge protection test and waveform analysis of the present invention, the left figure is the logic diagram of the surge protection test circuit, and its core components include surge waveform, protection circuit and protected equipment; wherein the surge waveform simulates the transient high voltage or large current interference that may occur in the onboard environment, such as cosmic rays, equipment start-stop shock, etc.; the protection circuit is the surge protection core of the onboard power chip, and its function is to shunt or suppress surge energy; the protected equipment is the power module in the actual onboard scenario, such as onboard computers, sensors, etc., which need to be verified for their reliability under surge shock; its working logic is: after the surge waveform is input, the protection circuit will first absorb the dangerous energy, and the remaining energy will reach the protected equipment, so as to verify the protection effect of the protection circuit on the protected equipment, and the core is to test the surge energy interception capability of the protection circuit. The right figure is a comparison of surge waveform characteristics, Figure 8Part (a) shows the waveform after ideal surge suppression, characterized by a stable amplitude and controllable duration. This indicates that the protection circuit is working effectively, limiting the surge energy to a safe range, and ensuring stable operation of the protected equipment. Figure 8 Part (b) shows an unsuppressed or failed surge waveform, characterized by a sudden change in amplitude, short duration, and concentrated energy. This indicates that the protection circuit fails to effectively intercept the surge energy, and the protected device will be subjected to a spike impact, potentially causing chip damage and performance degradation.

[0072] There are a few points to note: (1) The drawings of the embodiments of the present invention only relate to the structures related to the embodiments of the present invention. Other structures may refer to conventional designs.

[0073] (2) For the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present invention are exaggerated or reduced, that is, these drawings are not drawn to scale. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly on" or "under" the other element or intervening elements may be present.

[0074] (3) In the absence of conflict, the embodiments of the present invention and the features therein may be combined with each other to form new embodiments.

[0075] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A surge protection test system for a satellite-borne power chip, characterized by: Includes the following modules: The surge waveform simulation monitoring module is used to monitor the surge interference waveform during the surge test in the established test environment. The surge waveform quality determination and adjustment module is used to obtain the quality parameters of the surge interference waveform in real time, analyze the obtained surge interference waveform quality parameters, and thus determine whether the surge interference waveform meets the test conditions; The chip test reliability grading module is used to apply a surge interference waveform that meets the test conditions to the onboard power chip to be tested for protection testing, collect and analyze the process parameters of the protection test, and thus grade the surge protection test results of the onboard power chip.

2. The onboard power chip surge protection test system according to claim 1, characterized in that: The specific judgment process of judging whether the surge interference waveform meets the test conditions is as follows: Analyze the acquired surge interference waveform quality parameters to obtain a surge interference waveform quality index, and compare it with the surge interference waveform quality threshold preset in the test database; If the surge interference waveform quality index is greater than or equal to the surge interference waveform quality threshold, the surge interference waveform is judged to meet the test conditions, and the parameters of the surge interference waveform that meets the test conditions are fine-tuned to judge the stability of the surge interference waveform; If the surge interference waveform quality index is less than the surge interference waveform quality threshold, it is determined that the surge interference waveform does not meet the test conditions. Based on the surge interference waveform quality index and the surge interference waveform quality threshold, a surge quality deviation value is obtained. Based on the surge quality deviation value, a trigger pulse amplitude increase coefficient is matched, thereby increasing the amplitude of the trigger pulse. Based on the surge quality deviation value, a drive circuit power increase coefficient is matched, thereby increasing the power of the drive circuit. At the same time, historical operation data of the surge generation module is called to automatically recommend various parameter combinations. The surge interference waveform quality index is re-obtained and marked as a surge quality review index, so as to determine whether to issue an early warning for the surge interference waveform.

3. The onboard power chip surge protection test system according to claim 2, characterized in that: The specific analysis process of the surge interference waveform quality index is as follows: The quality parameters of the surge interference waveform include an overshoot amplitude factor of the surge interference waveform, a rising edge steepness factor of the surge interference waveform, and an oscillation attenuation rate factor of the surge interference waveform; In the test database, the corresponding action intensity coefficients of the overshoot amplitude factor, rising edge steepness factor, and oscillation attenuation rate factor are set to quantify the contribution of each factor to the surge interference waveform quality index. Finally, the surge interference waveform quality index is obtained by weighted comprehensive analysis of the contribution values. The surge interference waveform quality index indicates the quality of the surge generated by the surge generation module.

4. The onboard power chip surge protection test system according to claim 2, characterized in that: The specific process of judging whether to issue an early warning for the surge interference waveform is as follows: Compare the surge quality review index with the surge interference waveform quality threshold; If the surge quality review index is greater than or equal to the surge interference waveform quality threshold, no early warning will be issued for the surge interference waveform. At the same time, the surge interference waveform parameters that meet the test conditions will be fine-tuned to determine the stability of the surge interference waveform. If the surge quality review index is less than the surge interference waveform quality threshold, it is determined that an early warning is issued for the surge interference waveform.

5. The onboard power chip surge protection test system according to claim 4, characterized in that: The specific analysis process for judging the stability of the surge interference waveform is as follows: Obtaining a surge interference waveform quality index after fine-tuning and marking it as a surge interference waveform fine-tuning quality index. If the surge interference waveform fine-tuning quality index is greater than or equal to a surge interference waveform quality threshold, it is determined that the surge interference waveform is stable. If the surge interference waveform fine-tuning quality index is less than the surge interference waveform quality threshold, it is determined that the surge interference waveform is not stable, an early warning is issued to the surge generation module, and an instruction is generated to check the linearity of the surge generation device.

6. The onboard power chip surge protection test system according to claim 1, characterized in that: The surge protection test results of the onboard power chip are graded and analyzed as follows: Analyze the protection test process parameters to obtain the chip test reliability index, and compare it with the first reliability index and the second reliability index preset in the test database; If the chip test reliability index is greater than the first reliability index, the chip test result is marked as level one reliability, and the chip's stable on-orbit working time in a spaceborne environment is predicted. If the chip test reliability index is less than or equal to the first reliability index and the chip test reliability index is greater than or equal to the second reliability index, the chip test result is marked as level 2 reliability and the chip test process is optimized; If the chip test reliability index is less than the second reliability index, the chip test result is marked as level 3 reliability, and the chip test process is improved; The chip test reliability index is re-obtained and marked as the chip test reliability final value, so as to determine whether to issue an early warning on the reliability of the chip test result.

7. The onboard power chip surge protection test system according to claim 1, characterized in that: The process parameters of the protection test are analyzed, and the specific analysis process is as follows: The process parameters of the protection test include the impedance mutation rate factor of the surge injection point during the protection test, the thermal gradient decay rate factor inside the chip after the surge, and the transient common mode voltage factor between the chip pins; Obtain the comprehensive index of surge interference waveform quality; In the test database, the corresponding action intensity coefficients of the impedance mutation rate factor, thermal gradient attenuation rate factor, transient common mode voltage factor and surge interference waveform quality comprehensive index are set to quantify the contribution value of each factor to the chip test reliability index. Finally, the chip test reliability index is obtained by weighted comprehensive analysis of the contribution values. The chip test reliability index refers to the reliability of the chip test results.

8. The onboard power chip surge protection test system according to claim 6, characterized in that: The chip testing process is optimized, and the specific optimization process is as follows: Obtaining a first reliability deviation value based on the chip test reliability index and the first reliability index, and matching a surge injection phase deviation reduction amount based on the first reliability deviation value, thereby reducing the surge injection phase deviation; The chip testing process is improved, and the specific improvement process is: based on the chip test reliability index and the second reliability index, a second reliability deviation value is obtained, and based on the second reliability deviation value, an input filter network cutoff frequency increase coefficient is matched, thereby increasing the input filter network cutoff frequency of the chip.

9. The onboard power chip surge protection test system according to claim 6, characterized in that: The specific process of determining whether to issue a warning on the reliability of the chip test result is as follows: Comparing the final chip test reliability value with the first reliability index and the second reliability index to obtain different levels of reliability, and determining whether to issue a warning on the reliability of the chip test result based on the changes in the different levels of reliability; If the reliability level changes from Level 2 to Level 1 or from Level 3 to Level 1, it is determined that no warning will be issued regarding the reliability of the chip test results. At the same time, the stable operating time of the chip in the on-orbit environment is predicted. If the reliability level remains at level 2 or level 3, or the reliability level changes from level 2 to level 3, then the reliability of the chip test result is judged and an early warning is issued; If the reliability level is changed from the third level to the second level, the chip test reliability improvement rate is obtained based on the chip test reliability final value and the chip test reliability index. The quadratic increase coefficient of the input filter network cutoff frequency is matched based on the chip test reliability improvement rate, thereby further increasing the input filter network cutoff frequency of the chip. At the same time, the chip test reliability index is re-obtained and marked as the chip test reliability re-judgment index; Comparing the chip test reliability re-judgment index with the first reliability index and the second reliability index to obtain a reliability grade result; If the reliability is level 1, no warning will be issued regarding the reliability of the chip test results. At the same time, the chip's stable operating time in orbit in a spaceborne environment will be predicted. If it is level 2 reliability or level 3 reliability, the reliability of the chip test result is judged and an early warning is issued.

10. A method for testing surge protection of a satellite-borne power chip, using a system for testing surge protection of a satellite-borne power chip according to any one of claims 1 to 9, characterized in that: include: S1. Based on the established test environment, monitor the surge interference waveform during the surge test in the test environment; S2. Real-time acquisition of quality parameters of the surge interference waveform, analysis of the obtained surge interference waveform quality parameters, and thus determine whether the surge interference waveform meets the test conditions; S3. Apply a surge interference waveform that meets the test conditions to the onboard power chip to be tested for protection testing, collect and analyze the process parameters of the protection test, and thus perform graded processing on the surge protection test results of the onboard power chip.

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