Test method of programmable logic device, electronic equipment and computer readable medium

Abstract

The invention discloses a test method of a programmable logic device, electronic equipment and a computer readable medium, and belongs to the technical field of basic circuits, and the test method comprises the following steps: obtaining at least one test design file associated with each functional module in the programmable logic device, the test design file being used for representing a test purpose; at least two first modules meeting a preset merging condition are screened out from the multiple function modules, decoupling exists between the first modules, and at least one test design file which is not merged exists in test design files associated with the first modules; correspondingly merging at least one unmerged test design file associated with each first module, and taking the merged file as a target test file; and if a bit stream file is obtained by performing layout wiring based on the target test file, burning the bit stream file to the programmable logic device for testing to obtain a test result. The time consumed for testing the programmable logic device is shortened, and the testing efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and more specifically, to a testing method for a programmable logic device, an electronic device, and a computer-readable medium. Background Art

[0002] Field Programmable Gate Arrays (FPGAs), one of the four major general-purpose integrated circuit chips, are widely used in a variety of key fields, including communications equipment, medical devices, and video image processing. Their unique feature is the ability to reconfigure hardware logic circuits through programming, adapting them to different application scenarios and implementing specific digital logic functions. Before FPGAs are officially put into use, they must be tested. However, traditional methods for testing FPGAs are time-consuming and costly. Summary of the Invention

[0003] The present application proposes a testing method for a programmable logic device, an electronic device, and a computer-readable medium to improve the above-mentioned defects.

[0004] In a first aspect, the present application provides a testing method for a programmable logic device, which is applied to a processor of an electronic device, the method comprising: obtaining at least one test design file associated with each functional module in the programmable logic device, each test design file corresponding to two identifiers, namely, merged or unmerged, and the test design file is used to characterize the test purpose; screening out at least two first modules that meet preset merging conditions from a plurality of the functional modules, each of the first modules being decoupled, and at least one unmerged test design file being present in the test design files associated with the first modules; merging the at least one unmerged test design file associated with each first module, and using the merged file as a target test file; if a bitstream file is obtained by performing layout and routing based on the target test file, then burning the bitstream file into the programmable logic device for testing to obtain a test result.

[0005] Optionally, for a possible implementation, if a bitstream file is obtained by layout and routing based on the target test file, then the bitstream file is burned to the programmable logic device for testing. After the test results are obtained, it also includes: marking each unmerged test design file corresponding to the target test file as merged, returning to execute the step of screening out at least two first modules that meet the preset merging conditions from the multiple functional modules and subsequent operation steps, until the number of screened out first modules that meet the preset merging conditions is less than 2.

[0006] Optionally, for a possible implementation, the screening out of at least two first modules that meet preset merging conditions from the multiple functional modules includes: based on the test design files associated with each functional module, screening out multiple second modules from the multiple functional modules, the simulation test platforms corresponding to each second module are the same and are all preset simulation test platforms, and each second module is decoupled; if there are at least two second modules whose associated test design files include unmerged test design files, then screening out at least two first modules from the multiple second modules, and the test design files associated with the first modules include unmerged test design files.

[0007] Optionally, for a possible implementation, the merging of at least one unmerged test design file associated with each first module and using the merged file as the target test file includes: merging an unmerged test design file associated with each first module and using the merged file as the target test file.

[0008] Optionally, for a possible implementation method, merging an unmerged test design file associated with each first module and using the merged file as the target test file includes: accumulating the contents of an unmerged test design file associated with each first module into one file, and using the accumulated file as the target test file.

[0009] Optionally, for a possible implementation, it also includes: if an error prompt message is obtained when performing layout and routing based on the target test file, a third module is screened out from the first module, and the total number of the third modules is less than the total number of the first modules; the third module is used as a new first module, and if the number of the first modules is greater than or equal to 2, the operation of merging at least one unmerged test design file associated with each first module and using the merged file as the target test file and subsequent operation steps is returned.

[0010] Optionally, for a possible implementation, if an error prompt message is obtained when performing layout and routing based on the target test file, a third module is filtered out from the first module, including: if an error prompt message is obtained when performing layout and routing based on the target test file, the number of test design files associated with each first module is obtained as the first value corresponding to each first module; the first module corresponding to the smallest first value among the first values ​​corresponding to each first module is used as the fourth module, and the first module in the first module other than the fourth module is used as the third module.

[0011] Optionally, for a possible implementation, if an error prompt message is obtained during layout and routing based on the target test file, a third module is screened out from the first module, including: if an error prompt message is obtained during layout and routing based on the target test file, a value of the peripheral circuit resources occupied by each first module is obtained as the second value corresponding to each first module; among the second values ​​corresponding to each first module, the first module corresponding to the largest second value is used as the fourth module, and the first module in the first module other than the fourth module is used as the third module.

[0012] Optionally, for a possible implementation, if an error prompt message is obtained during layout and routing based on the target test file, a third module is screened out from the first module, including: if an error prompt message is obtained during layout and routing based on the target test file, the highest clock frequency corresponding to each first module is obtained as the third value corresponding to each first module; among the third values ​​corresponding to each first module, the first module corresponding to the maximum third value is used as the fourth module, and the first module in the first module other than the fourth module is used as the third module.

[0013] In a second aspect, the present application also provides an electronic device comprising: one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory, the one or more applications are configured to be executed by the one or more processors, and the one or more applications are configured to execute the above method.

[0014] In a third aspect, the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a program code executable by a processor, and when the program code is executed by the processor, the processor executes the above method.

[0015] The solution provided by the present application is as follows: first, at least one test design file associated with each functional module in the programmable logic device is obtained, each test design file corresponds to two identifiers: merged or unmerged, and the test design file is used to characterize the test purpose; then, at least two first modules that meet the preset merging conditions are screened out from the multiple functional modules, each of the first modules is decoupled, and there is at least one unmerged test design file in the test design files associated with the first modules; secondly, at least one unmerged test design file associated with each first module is merged, and the merged file is used as the target test file; finally, if a bitstream file is obtained by layout and routing based on the target test file, the bitstream file is burned into the programmable logic device for testing to obtain the test results. The present application reduces the number of bitstream files by merging test design files, thereby reducing the total time consumed in loading and configuring bitstream files and the total time consumed in test stimuli. This greatly reduces the time consumed in testing programmable logic devices and improves test efficiency.

[0016] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A flow chart of a method for testing a programmable logic device provided in an embodiment of the present application is shown;

[0019] Figure 2 A flow chart of a method for testing a programmable logic device provided in another embodiment of the present application is shown;

[0020] Figure 3 A structural block diagram of an electronic device provided in an embodiment of the present application is shown;

[0021] Figure 4 A structural block diagram of a computer-readable storage medium provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for which protection is claimed, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work fall within the scope of protection of the present application.

[0023] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0024] Field Programmable Gate Arrays (FPGAs), one of the four major general-purpose integrated circuit chips, are widely used in a variety of key fields, including communications equipment, medical devices, and video image processing. Their unique feature is the ability to reconfigure hardware logic circuits through programming, adapting them to different application scenarios and implementing specific digital logic functions. Before FPGAs are officially put into use, they must be tested. However, traditional methods for testing FPGAs are time-consuming and costly.

[0025] Therefore, in an embodiment of the present application, a method for testing a programmable logic device, an electronic device, and a computer-readable medium are provided to solve or partially solve the above-mentioned problems.

[0026] See also Figure 1 , which shows a flow chart of a testing method for a programmable logic device provided in an embodiment of the present application. The method is applied to a processor of an electronic device and specifically includes steps S101 to S104.

[0027] Step S101: obtaining at least one test design file associated with each functional module in the programmable logic device, wherein each test design file has two corresponding identifiers: merged or not merged, and the test design file is used to represent a test purpose.

[0028] It should be noted that a programmable logic device (PLD) is a type of chip that can be configured to implement custom digital circuits. Its characteristic is that internal logic functions are defined by generating a bitstream file using a hardware description language (HDL) or graphical tools. PLDs can be FPGAs or complex programmable logic devices (CPLDs).

[0029] Functional modules include but are not limited to logic modules, dedicated hardware modules, etc. The functional modules in FPGA include programmable logic units, storage units, embedded dedicated hard cores, and input and output units, etc.

[0030] Each functional module in a programmable logic device is associated with at least one test design file. This file is determined by R&D personnel based on test requirements. This file contains information about configuring and testing circuits. A functional module can be associated with multiple test design files, each corresponding to different test objectives.

[0031] It is understandable that developers design test design files associated with each functional module in the programmable logic device based on actual needs, and then store the designed test design files and corresponding functional modules in the database. To this end, at least one test design file associated with each functional module in the programmable logic device can be obtained from the database.

[0032] Exemplarily, the programmable logic device is an FPGA, and the functional modules in the FPGA are at least one of a configurable logic block (CLB), interconnect resources, an I / O block, a digital signal processor (DSP) unit, and a block random access memory (BRAM). When performing FPGA testing, at least some of the functional modules are associated with at least one test design file.

[0033] Step S102: selecting at least two first modules that meet a preset merging condition from the plurality of functional modules, wherein each of the first modules is decoupled, and at least one unmerged test design file exists among the test design files associated with the first modules.

[0034] It should be noted that the traditional test method for programmable logic devices is to obtain a corresponding bitstream file based on each test design file, and then load and configure the bitstream file corresponding to each test design file respectively, and then perform a stimulus test to obtain the test result. This method takes too long to test programmable logic devices, and the test efficiency is low. The role of the stimulus test is to verify whether the designed function is correct by simulating input signals (such as clock, reset, data) and observing the output. That is, when performing FPGA testing, it is necessary to first load the bitstream file to configure the FPGA, and then perform a test stimulus on the configured FPGA to obtain the verification result of the design. To this end, loading and configuring the bitstream file takes a while, and testing the stimulus also takes a while. If the number of bitstream files can be reduced, the test time can be reduced.

[0035] The present application reduces the number of overall test design files by merging the test design files, and simultaneously reduces the number of bitstream files, thereby reducing the total time required to load and configure the bitstream files and the total time required to test the stimulus, thereby shortening the test time. Therefore, it is necessary to select at least two first modules that meet the preset merging conditions from multiple functional modules.

[0036] Although a programmable logic device includes multiple functional modules, not all test design files associated with each functional module can be merged. It is understandable that different functional modules are associated with different test design files. If there is no decoupling between the two modules, resource conflicts will occur after merging the test design files of the two functional modules. For example, the test design file associated with functional module A uses the trigger of functional module B, and the test design file associated with functional module B also uses the trigger of functional module B. This means that the test design file associated with functional module A cannot be merged with the test design file associated with functional module B. To this end, the preset merging condition is that there is decoupling between each of the first modules, and there is at least one unmerged test design file among the test design files associated with the first modules.

[0037] Decoupling between two functional modules means that the two functional modules do not occupy each other's resources. For example, if the circuit of functional module B is not used when testing functional module A, and the circuit of functional module A is not used when testing functional module B, then functional module A and functional module B are decoupled.

[0038] It should be noted that when multiple functional modules are decoupled from each other, it means that the multiple functional modules are decoupled. For example, if functional module A and functional module B are decoupled, functional module A and functional module C are decoupled, and functional module B and functional module C are decoupled, then functional module A, functional module B, and functional module C are determined to be decoupled.

[0039] In step S102 , the specific steps of selecting at least two first modules that meet the preset merging condition from the plurality of functional modules include steps S1021 to S1022 .

[0040] Step S1021: Based on the test design file associated with each functional module, multiple second modules are selected from multiple functional modules. The simulation test platforms corresponding to each second module are the same and are all preset simulation test platforms. Each second module is decoupled.

[0041] It should be noted that the FPGA test process includes RTL code writing, RTL functional simulation (pre-simulation), synthesis, layout and routing, timing simulation (post-simulation), and board-level testing (loading the bitstream file into the FPGA for testing). The functional simulation before layout and routing is called pre-simulation. The pre-simulation is to find logical errors in the RTL code (such as state machine jump errors, data path errors) to avoid high modification costs in the later stage. Simulation tools such as ModelSim, VCS, and Xcelium are usually used for pre-simulation. The timing simulation after layout and routing is called post-simulation. The post-simulation is to check whether the timing constraints (such as setup time and hold time) are met. If the simulation test platforms used for the pre-simulation and post-simulation are different, the post-simulation cannot correctly read the files associated with the pre-simulation, nor can the post-simulation be implemented. For this reason, it is necessary to screen out the second module from multiple functional modules. The simulation test platform corresponding to each of the second modules is the same and is a preset simulation test platform, and each second module is decoupled.

[0042] It is understandable that the test design file includes not only relevant information about the test purpose, but also information about the simulation test platform and resource usage information of each functional module. Multiple second modules can be screened out from multiple functional modules based on the test design file.

[0043] Step S1022: If there are at least two second modules whose associated test design files include unmerged test design files, then at least two first modules are selected from the plurality of second modules, and the test design files associated with the first modules include unmerged test design files.

[0044] It should be noted that each test design file includes identifiers indicating whether it has been merged or not. Each test design file is initially identified as not being merged. If a second module is associated with an unmerged test design file, this indicates that the test design files in that second module can still be merged. If at least two second modules are associated with test design files that include unmerged test design files, at least two first modules are selected from the plurality of second modules.

[0045] Step S103: Merge at least one unmerged test design file associated with each first module, and use the merged file as the target test file.

[0046] It should be noted that one unmerged test design file associated with each first module can be merged to obtain one target test file, or multiple unmerged test design files associated with each first module can be merged to obtain multiple target test files.

[0047] In an optional embodiment, an unmerged test design file associated with each first module is merged, and the merged file is used as the target test file. For example, three first modules are detected, namely the first module A, the first module B, and the first module C. The first module A is associated with three unmerged test design files, the first module B is associated with six unmerged test design files, and the first module C is associated with seven unmerged test design files. Then, the unmerged test design file associated with the first module A, the unmerged test design file associated with the first module B, and the unmerged test design file associated with the first module C are merged to obtain one file, and the merged file is used as the target test file. The original (3+6+7)=16 test design files can be reduced to (2+5+6+1)=14 test design files, that is, the number of bitstream files is reduced, thereby shortening the test time of the programmable logic device.

[0048] Specifically, the contents of an unmerged test design file associated with each first module are accumulated into one file, and the accumulated file is used as the target test file. It should be noted that the test design file includes hardware description language.

[0049] In an optional embodiment, multiple unmerged test design files associated with each first module are correspondingly merged, and the merged files are used as target test files to obtain multiple target test files. For example, three first modules are detected, namely the first module A, the first module B, and the first module C. The first module A is associated with three unmerged test design files, namely test design files a1, a2, and a3. The first module B is associated with six unmerged test design files, namely test design files b1, b2, b3, b4, b5, and b6. The first module C is associated with seven unmerged test design files, namely test design files c1, c2, c3, c4, c5, c6, and c7. The three unmerged test design files associated with the first module A, the three unmerged test design files associated with the first module B, and the three unmerged test design files associated with the first module C are correspondingly merged to obtain three target test files, namely M1, M2, and M3.

[0050] Specifically, the test design file a1 associated with the first module A, the test design file b1 associated with the first module B, and the test design file c1 associated with the first module C are merged to obtain a target test file M1; the test design file a2 associated with the first module A, the test design file b2 associated with the first module B, and the test design file c2 associated with the first module C are merged to obtain a target test file M2; and the test design file a3 associated with the first module A, the test design file b3 associated with the first module B, and the test design file c3 associated with the first module C are merged to obtain a target test file M3. The original (3+6+7)=16 test design files can be reduced to (3+4+3)=10 test design files, that is, the number of bitstream files is reduced, thereby shortening the test time of the programmable logic device. Moreover, according to the above embodiment, it can be seen that the more test design files are merged, the fewer the number of bitstream files obtained, the shorter the test time of the programmable logic device, and the more conducive to improving test efficiency.

[0051] Step S104: If a bitstream file is obtained by performing layout and routing based on the target test file, the bitstream file is burned into the programmable logic device for testing to obtain a test result.

[0052] It should be noted that the test result represents the verification result of the target test file, and the test result may represent the verification result of each test design file corresponding to the target design file.

[0053] If a target test file exists, layout and routing is performed based on the target test file. If a bitstream file is obtained, indicating that the timing simulation after layout and routing meets the requirements, the bitstream file is burned into the programmable logic device for testing to obtain the test results. If multiple target test files exist, layout and routing is performed based on each target test file. For a target test file, if a bitstream file is obtained by layout and routing based on the target test file, the bitstream file is burned into the programmable logic device for testing to obtain the test results.

[0054] In an exemplary embodiment, three first modules are detected, namely the first module A, the first module B, and the first module C. The first module A is associated with three unmerged test design files, the first module B is associated with six unmerged test design files, and the first module C is associated with seven unmerged test design files. Then, one unmerged test design file associated with the first module A, one unmerged test design file associated with the first module B, and one unmerged test design file associated with the first module C are merged to obtain one file, and the merged file is used as the target test file. Based on the target test file, layout and routing are performed to obtain a bitstream file, and the bitstream file is burned into the programmable logic device for testing to obtain test results. Before merging, the programmable module is associated with a total of 16 test design files, so 16 bitstream files need to be generated. If the loading configuration time of each test design file is 50ms and the stimulus test time of each test design file is 20ms, then the test time of the programmable logic device is 16*(50ms+20ms)=1120ms. After the merger, only 14 test design files are needed, corresponding to only 14 bitstream files that need to be loaded and configured. The test time of the programmable logic device is 14*(50ms+20ms)=980ms. It can be seen from this that the application merges the unmerged test design files associated with the first module to reduce the time consumption of programmable logic device testing. Moreover, the more test design files are merged, the less time is consumed in testing the programmable logic device.

[0055] The present application selects at least two first modules that meet preset merging conditions from multiple functional modules, merges at least one unmerged test design file associated with each first module, and uses the merged file as the target test file; performs layout and routing based on the target test file to obtain a bitstream file, then burns the bitstream file into a programmable logic device for testing to obtain test results. The present application reduces the number of bitstream files by merging test design files, thereby reducing the total time consumed for loading and configuring bitstream files and the total time consumed for test stimuli. This greatly reduces the time consumed for testing programmable logic devices and improves test efficiency.

[0056] In an optional embodiment, in step S104: if a bitstream file is obtained by performing layout and routing based on the target test file, the bitstream file is burned into the programmable logic device for testing, and after the test result is obtained, it further includes.

[0057] Mark each unmerged test design file corresponding to the target test file as merged, and return to execute the step of screening out at least two first modules that meet the preset merging conditions from the multiple functional modules and subsequent operation steps until the number of screened out first modules that meet the preset merging conditions is less than 2.

[0058] It is understandable that each unmerged test design file corresponding to the target test file represents each unmerged test design file of the target test file that is merged. If a bitstream file is obtained by performing layout and routing based on the target test file, it indicates that the target test file merge is valid, and each unmerged test design file corresponding to the target test file is marked as merged to ensure that it will not be merged again during the next merge. Return to execute the step of screening out at least two first modules that meet the preset conditions from multiple functional modules and subsequent steps. If the number of screened out first modules that meet the preset merging conditions is less than 2, it indicates that the merge cannot continue. Each unmerged test design file is separately laid out and routed to obtain multiple bitstream files, and then each bitstream file is separately burned to the programmable logic device for testing to obtain test results, thereby completing the test of the programmable logic device.

[0059] This application merges all test design files that can be merged in a programmable logic device, which can maximize the shortening of the test time of the programmable logic device.

[0060] See also Figure 2 , which shows a flow chart of a testing method for a programmable logic device provided in an embodiment of the present application. The method is applied to a processor of an electronic device and specifically includes steps S201 to S206.

[0061] Step S201: obtaining at least one test design file associated with each functional module in the programmable logic device, wherein each of the test design files has two corresponding identifiers: merged or not merged, and the test design file is used to represent a test purpose.

[0062] Step S202: Filter out at least two first modules that meet preset merging conditions from the plurality of functional modules, wherein each of the first modules is decoupled, and there is at least one unmerged test design file among the test design files associated with the first modules.

[0063] Step S203: Merge at least one unmerged test design file associated with each first module, and use the merged file as the target test file.

[0064] Step S204: If a bitstream file is obtained by performing layout and routing based on the target test file, the bitstream file is burned into the programmable logic device for testing to obtain a test result.

[0065] Among them, steps S201 to S204 have been described in detail in the above embodiments and will not be repeated here.

[0066] Step S205: If an error message is obtained by performing layout and routing based on the target test file, a third module is screened out from the first modules, and the total number of the third modules is less than the total number of the first modules.

[0067] If an error message is obtained when performing layout and routing based on the target test file, it means that the target test file is invalid and needs to be adjusted. This can reduce the number of test design files that are merged to obtain the target test file. In this case, the third module is selected from the first module, and the total number of the third modules is less than the total number of the first modules.

[0068] Step S206: Use the third module as the new first module. If the number of the first modules is greater than or equal to 2, return to execute the operation of merging at least one unmerged test design file associated with each first module, and use the merged file as the target test file and subsequent operation steps.

[0069] If the number of first modules is greater than or equal to 2 after the number of test design files is reduced, it means that the merge can continue, and the process returns to execute the operation of merging at least one unmerged test design file associated with each first module, using the merged file as the target test file, and subsequent operation steps. If the number of first modules is less than 2 after the number of test design files is reduced, indicating that the merge condition is not met, each unmerged test design file is separately laid out and routed to obtain multiple bitstream files, and each bitstream file is then burned into the programmable logic device for testing to obtain test results, thereby completing the test of the programmable logic device.

[0070] In an embodiment of the present application, when an error message is obtained during layout and routing based on a target test file, adjustments can be made to obtain a target test file that meets the conditions, thereby shortening the testing time of the programmable logic device.

[0071] In an optional embodiment, if an error prompt message is obtained by performing layout and routing based on the target test file in step S205 , a third module is filtered out from the first module, including steps S2051 to S2052 .

[0072] Step S2051: If error prompt information is obtained when performing layout and routing based on the target test file, the number of test design files associated with each first module is obtained as a first value corresponding to each first module.

[0073] Step S2052: Among the first values ​​corresponding to each first module, the first module corresponding to the smallest first value is used as the fourth module, and the first modules among the first modules except the fourth module are used as the third module.

[0074] It should be noted that if an error message is displayed during layout and routing based on the target test file, the first module with the fewest test design files is removed to obtain a new first module. Based on the new first module, the process returns to merge at least one unmerged test design file associated with each first module, using the merged file as the target test file, and subsequent steps. This can reduce the testing time of the programmable logic device.

[0075] In an optional embodiment, if an error message is obtained by performing layout and routing based on the target test file in step S205 , a third module is filtered out from the first module, including steps S2053 to S2054 .

[0076] Step S2053: If error information is obtained when performing layout and routing based on the target test file, a value of the peripheral circuit resources occupied by each first module is obtained as a second value corresponding to each first module.

[0077] Step S2054: Among the second values ​​corresponding to each first module, the first module corresponding to the largest second value is used as the fourth module, and the first modules among the first modules except the fourth module are used as the third module.

[0078] It should be noted that if an error message is generated during layout and routing based on the target test file, the first module occupying the most peripheral circuit resources is removed to obtain a new first module. Based on the new first module, the operation of merging at least one unmerged test design file associated with each first module and using the merged file as the target test file, as well as subsequent steps, is performed. This can reduce the testing time of the programmable logic device.

[0079] In an optional embodiment, if an error prompt message is obtained by performing layout and routing based on the target test file in step S205, a third module is filtered out from the first module, including steps S2055 to S2056.

[0080] Step S2055: If an error message is obtained when performing layout and routing based on the target test file, the highest clock frequency corresponding to each first module is obtained as the third value corresponding to each first module.

[0081] Step S2056: Among the third values ​​corresponding to each first module, the first module corresponding to the largest third value is used as the fourth module, and the first modules in the first modules except the fourth module are used as the third module.

[0082] It should be noted that if an error message is displayed during placement and routing based on the target test file, the first module with the highest clock frequency is removed to obtain a new first module. Based on the new first module, the operation of merging at least one unmerged test design file associated with each first module and using the merged file as the target test file, as well as subsequent steps, can be performed. This can reduce the testing time of the programmable logic device.

[0083] For example, for module 1 of a programmable logic device, loading and configuring a test design file on the machine takes 50ms, and the stimulus test takes 20ms. Module 1 requires 10 test design files to be tested on the machine, so the time required to complete the test on the machine for module 1 is (50ms*10+20ms*10)=700ms. Module 2 has 12 test design files. Each test design takes the same amount of time to configure on the machine as module 1, but the stimulus test takes 10ms. Therefore, the time required to complete the test on the machine for module 2 is (50ms*12+10ms*12)=720ms. Therefore, the total time required to complete the test on the machine for modules 1 and 2 is 1420ms. After adopting the method of the present application, since module 1 and module 2 are decoupled and meet the preset merging conditions, the two modules are placed in the same design for testing. Then, the machine needs (50ms*12+20ms*10+10ms*2)=820ms to complete the test of this module, thereby saving 42% of the test time. If more test modules are added to the same design, the time required for the machine to complete the test of all modules can save more than 42% of the traditional test time, thereby significantly saving testing costs.

[0084] It should be noted that when testing a single module D, the overall load is small and the module D tests normally. When testing module D together with multiple other modules, the overall load is large and the module D may not test normally. This application can discover such problems, that is, this application can better stimulate module defect problems that a single module cannot stimulate.

[0085] As an example, a programmable logic device needs to test module 1, module 2 and module 3. Module 1 and module 2 meet the preset merging conditions, and module 3 does not meet the preset merging conditions. Testing module 1 requires 10 test designs, testing module 2 requires 10 test designs, and testing module 3 requires 5 test designs. According to the logic of traditional serial testing, testing modules 1, 2, and 3 require a total of 25 test designs.

[0086] This application merges the test design files associated with module 1 and module 2 (only 10 test designs are required to test modules 1 and 2). After the merger, a total of 15 test designs are required to test modules 1, 2, and 3, reducing the number of test design files and thus shortening the test time of the programmable logic device.

[0087] Furthermore, module 1 and module 2 are complementary, that is, testing module 1 will use the configuration points of module 3 (which can be understood as testing the three test designs of module 3 when testing module 1), and testing module 2 will use the remaining two configuration points of module 3 (which can be understood as testing the remaining two test designs of module 3 when testing module 2). In this case, a total of 10 test designs are required to test modules 1, 2, and 3 (the test design corresponding to module 3 does not need to be tested additionally). To this end, the test design of modules 1 and 2 is input into the test machine, which not only completes the testing of modules 1 and 2, but also completes the testing of module 3, reducing the number of test designs for module 3. This further reduces the number of test design files and shortens the testing time of programmable logic devices.

[0088] Please refer to Figure 3 , which shows a structural block diagram of an electronic device 700 provided in an embodiment of the present application. The electronic device 700 may be a vehicle-mounted system, which may be installed in a vehicle. The electronic device 700 in the present application may include one or more of the following components: a processor 711, a memory 712, and one or more application programs, wherein the processor 711 is electrically connected to the memory 712, and the one or more application programs are configured to execute the methods described in the various embodiments of the aforementioned testing method.

[0089] The processor 711 may include one or more processing cores. The processor 711 utilizes various interfaces and circuits to connect various components within the electronic device 700. It executes instructions, programs, code sets, or instruction sets stored in the memory 712, and accesses data stored in the memory 712 to perform various functions and process data within the electronic device 700. Optionally, the processor 711 may be implemented using at least one of the following hardware forms: a digital signal processing (DSP), a field-programmable gate array (FPGA), or a programmable logic array (PLA). The processor 711 may integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. The CPU primarily processes the operating system, user interface, and computer programs; the GPU is responsible for rendering and drawing display content; and the modem handles wireless communications. It is understood that the modem may not be integrated into the processor 711 but may be implemented separately via a communications chip. Specifically, the methods described in the aforementioned embodiments may be executed by one or more processors 711.

[0090] In some embodiments, the memory 712 may include a random access memory (RAM) or a read-only memory (ROM). The memory 712 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 712 may include a program storage area and a data storage area. The program storage area may store instructions for implementing an operating system, instructions for implementing at least one function, instructions for implementing the various method embodiments described below, and the like. The data storage area may also store data created by the electronic device 700 during use.

[0091] Please refer to Figure 4 , which shows a block diagram of a computer-readable medium provided in an embodiment of the present application. The computer-readable medium 800 stores program code, which can be called by a processor to execute the method described in the above method embodiment.

[0092] The computer-readable medium 800 can be an electronic memory such as a flash memory, an EEPROM (Electrically Erasable Programmable Read-Only Memory), an EPROM, a hard disk, or a ROM. Alternatively, the computer-readable medium 800 includes a non-transitory computer-readable storage medium. The computer-readable medium 800 has storage space for program code 810 for executing any of the method steps described above. These program codes can be read from or written to one or more computer program products. The program code 810 can be compressed, for example, in a suitable form.

[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for testing a programmable logic device, characterized in that: A processor applied to an electronic device, the method comprising: Obtain at least one test design file associated with each functional module in the programmable logic device, each test design file corresponding to two identifications: merged or not merged, and the test design file is used to represent a test purpose; Screening out at least two first modules that meet a preset merging condition from the plurality of functional modules, wherein each of the first modules is decoupled from each other, and at least one test design file associated with the first modules is not merged; Merge at least one unmerged test design file associated with each first module, and use the merged file as the target test file; If a bitstream file is obtained by performing layout and routing based on the target test file, the bitstream file is burned into the programmable logic device for testing to obtain a test result.

2. The method according to claim 1, characterized in that If a bitstream file is obtained by performing layout and routing based on the target test file, the bitstream file is burned into the programmable logic device for testing, and after the test result is obtained, the method further includes: Mark each unmerged test design file corresponding to the target test file as merged, and return to execute the step of screening out at least two first modules that meet the preset merging conditions from the multiple functional modules and subsequent operation steps until the number of screened out first modules that meet the preset merging conditions is less than 2.

3. The method according to claim 1, characterized in that The step of selecting at least two first modules that meet a preset merging condition from the plurality of functional modules includes: Based on the test design file associated with each functional module, a plurality of second modules are selected from the plurality of functional modules, wherein the simulation test platforms corresponding to each of the second modules are the same and are all preset simulation test platforms, and each of the second modules is decoupled; If there are at least two second modules whose associated test design files include unmerged test design files, then at least two first modules are selected from the plurality of second modules, and the test design files associated with the first modules include unmerged test design files.

4. The method according to claim 1, wherein The step of merging at least one unmerged test design file associated with each first module and using the merged file as a target test file includes: An unmerged test design file associated with each first module is merged, and the merged file is used as the target test file.

5. The method according to claim 4, characterized in that The step of merging an unmerged test design file associated with each first module and using the merged file as a target test file includes: The contents of an unmerged test design file associated with each first module are accumulated into one file, and the accumulated file is used as a target test file.

6. The method according to claim 1, characterized in that Also includes: If an error message is obtained by performing layout and routing based on the target test file, a third module is selected from the first module, and the total number of the third modules is less than the total number of the first modules; Use the third module as the new first module. If the number of the first modules is greater than or equal to 2, return to execute the operation of merging at least one unmerged test design file associated with each first module, and use the merged file as the target test file and subsequent operation steps.

7. The method according to claim 6, characterized in that If an error message is obtained by performing layout and routing based on the target test file, a third module is selected from the first module, including: If an error message is obtained by performing layout and routing based on the target test file, obtaining the number of test design files associated with each first module as a first value corresponding to each first module; Among the first values ​​corresponding to each first module, the first module corresponding to the minimum first value is used as the fourth module, and the first modules among the first modules except the fourth module are used as the third module.

8. The method according to claim 6, characterized in that If an error message is obtained by performing layout and routing based on the target test file, a third module is selected from the first module, including: If an error message is obtained by performing layout and routing based on the target test file, a value of peripheral circuit resources occupied by each first module is obtained as a second value corresponding to each first module; Among the second values ​​corresponding to each first module, the first module corresponding to the largest second value is used as the fourth module, and the first modules among the first modules except the fourth module are used as the third module.

9. The method according to claim 6, characterized in that If an error message is obtained by performing layout and routing based on the target test file, a third module is selected from the first module, including: If an error message is obtained by performing layout and routing based on the target test file, obtaining a maximum clock frequency corresponding to each first module as a third value corresponding to each first module; Among the third values ​​corresponding to each first module, the first module corresponding to the largest third value is used as the fourth module, and the first modules among the first modules except the fourth module are used as the third module.

10. An electronic device, characterized in that: include: one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory, the one or more applications are configured to be executed by the one or more processors, and the one or more applications are configured to execute the method according to any one of claims 1 to 9.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores program code, which can be called by a processor to execute the method according to any one of claims 1 to 9.

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