OPC correction method

Abstract

The invention provides an OPC (Optical Proximity Correction) method, which comprises the following steps of: intercepting graphs of all error reporting positions and peripheral preset areas by utilizing scripts, independently carrying out OPC and OPCV on the error reporting positions and the peripheral preset areas, carrying out OPC on the whole original OPC layout after eliminating all errors of the OPCV through multiple iterations, and carrying out OPC on the intercepted error reporting positions and the peripheral areas of the intercepted error reporting positions. According to the method, the surrounding environment of an error reporting position is reserved, and meanwhile, the size of a layout file is greatly reduced, so that resource occupation is reduced, the operand and the running time during each OPC and OPCV iterative operation are reduced, the running time and resources of the whole OPC are greatly reduced, and the OPC development and publishing efficiency is improved; besides, a complete script does not need to be disclosed, and only the intercepted OPCV hot spot needs to be shared, so that other people can assist in handling the hot spot problem, and better confidentiality is achieved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing, and in particular relates to an OPC correction method. Background Art

[0002] Photolithography is a crucial technology in semiconductor manufacturing, enabling the transfer of patterns from a mask onto the surface of a silicon wafer to create semiconductor products that meet design requirements. As integrated circuit feature sizes continue to shrink, the design dimensions of semiconductor devices become increasingly precise, approaching the limits of photolithography imaging systems. The diffraction effect of light becomes increasingly pronounced, causing the image on the silicon wafer to gradually deviate from the pattern on the mask, resulting in severe distortion. This distortion continues until the period is smaller than the minimum resolvable size, at which point the image disappears completely. Consequently, optical proximity correction (OPC) has become an essential step in layout correction. For example, sub-resolution auxiliary patterns are added to improve linewidth uniformity and expand the photolithography process window, ensuring consistency between the final pattern on the silicon wafer and the designed pattern, ensuring that the resulting pattern after photolithography is close to the target pattern actually desired by the user.

[0003] The conventional OPC correction process involves using a recipe for OPC correction, then performing Optical Proximity Correct Verification (OPCV), and then adjusting the recipe based on the OPCV results until all OPCV errors are corrected. During this process, each recipe modification requires running OPC on the entire layout to verify that all errors have been corrected. This correction process requires significant time and resources, severely impacting OPC development and publishing efficiency. This is especially true for silicon photonics patterns containing curves, as OPC correction takes even longer due to the need to segment these curves. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide an OPC correction method to solve the problem that the OPC correction process in the prior art requires a long correction time and a lot of operating resources, which seriously affects the efficiency of OPC development and publication.

[0005] To achieve the above-mentioned and other related purposes, the present invention provides an OPC correction method, which comprises the following steps:

[0006] S1, import the entire original layout sample into the OPC program, run OPC and OPCV, and get the error result;

[0007] S2, using a script to obtain a graphic of the error location and a preset area around the error location, and intercepting the graphic;

[0008] S3, modify the recipe of the graphic intercepted in step S2, and run OPC and OPCV on the graphic intercepted in step S2 to obtain an error result;

[0009] S4, determine whether the error result obtained in step S3 is cleared; if the error result obtained in step S3 is no, repeat step S3; if the error result obtained in step S3 is yes, continue to step S5;

[0010] S5, run OPC and OPCV on the entire original layout sample and get an error result;

[0011] S6, judging whether the error result obtained in step S5 is cleared; if the error result obtained in step S5 is no, returning to step S2; if the error result obtained in step S5 is yes, the OPC correction is ended.

[0012] Optionally, the preset area around the error reporting position in step S2 is an area within a range of 1 μm to 5 μm around the error reporting position.

[0013] Furthermore, the preset area around the error reporting position in step S2 is an area within a range of 3 μm to 4 μm around the error reporting position.

[0014] Optionally, OPC includes rule-based OPC or model-based OPC.

[0015] Optionally, OPCV includes inspection items to verify critical dimensions of opens and shorts.

[0016] Optionally, the file format of the original layout sample in step S1 is a gds file or an oas file; the file format of the intercepted graphics in step S2 is a gds file or an oas file; and the file format of the script in step S2 is a .sh file.

[0017] Optionally, the OPC correction method is applicable to the OPC development and publication process of silicon photonics, BCD and CMOS.

[0018] Optionally, in step S3, the recipe of the graphic intercepted in step S2 is modified based on experience.

[0019] As described above, the OPC correction method of the present invention, by utilizing a script, extracts the graphics of all error positions and their surrounding preset areas, and performs OPC and OPCV on these error positions and their surrounding preset areas separately, and after multiple iterations, eliminates all OPCV errors and then performs OPC on the entire original OPC layout. The extracted error positions and their surrounding areas not only retain the surrounding environment of the error positions, but also greatly reduce the layout file size, thereby reducing resource usage and reducing the amount of calculation and running time of each OPC and OPCV iterative operation, thereby greatly reducing the running time and resources of the entire OPC correction, and improving the efficiency of OPC development and publishing; in addition, there is no need to disclose the complete script, but only the extracted OPCV hotspots need to be shared to facilitate others to assist in dealing with hotspot issues, which has better confidentiality. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram showing an original layout in an example of the OPC correction method of the present invention.

[0021] Figure 2 A schematic diagram showing a cutout layout of an example of the OPC correction method of the present invention is shown.

[0022] Figure 3 A schematic diagram showing an example of an OPCV error in the OPC correction method of the present invention is shown.

[0023] Figure 4 A schematic diagram showing an error position and a predetermined area around the error position in an example of the OPC correction method of the present invention is shown.

[0024] Figure 5 Shown as Figure 4 A graphical diagram showing the error location and the graphics of the preset area around the error location.

[0025] Figure 6 Shown is a flow chart of the OPC correction method of the present invention.

[0026] Component number description

[0027] 10 Original layout

[0028] 11 The captured layout

[0029] 110 Error location

[0030] 111 Preset area around the error location

[0031] 12 OPCV error

[0032] 13 Graphics before capture

[0033] 14 The intercepted image

[0034] Steps S1 to S7 DETAILED DESCRIPTION

[0035] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] See also Figures 1 to 6 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0037] like Figure 6 As shown, this embodiment provides an OPC correction method, which includes the following steps:

[0038] S1, import the entire original layout sample into the OPC program, run OPC and OPCV, and get the error result;

[0039] S2, using a script to obtain a graphic of the error location and a preset area around the error location, and intercepting the graphic;

[0040] S3, modify the recipe of the graphic intercepted in step S2, and run OPC and OPCV on the graphic intercepted in step S2 to obtain an error result;

[0041] S4, determine whether the error result obtained in step S3 is cleared; if the error result obtained in step S3 is no, repeat step S3; if the error result obtained in step S3 is yes, continue to step S5;

[0042] S5, run OPC and OPCV on the entire original layout sample and get an error result;

[0043] S6, judging whether the error result obtained in step S5 is cleared; if the error result obtained in step S5 is no, returning to step S2; if the error result obtained in step S5 is yes, the OPC correction is ended.

[0044] The OPC correction method of this embodiment uses a script to extract the graphics of all error positions and their surrounding preset areas, and performs OPC and OPCV on these error positions and their surrounding preset areas separately. After eliminating all OPCV errors through multiple iterations, OPC is performed on the entire original OPC layout. The extracted error positions and their surrounding areas not only retain the surrounding environment of the error positions, but also greatly reduce the layout file size, thereby reducing resource usage and reducing the amount of calculation and running time of each OPC and OPCV iterative operation, thereby greatly reducing the running time and resources of the entire OPC correction and improving the efficiency of OPC development and publishing. In addition, there is no need to disclose the complete script, but only the extracted OPCV hotspots need to be shared to facilitate others to assist in handling hotspot issues, which has better confidentiality.

[0045] As a specific example, Figure 1 The schematic diagram of an example original layout 10 is shown. After running OPC and OPCV on the entire original layout 10, the OPCV error 12 result is as follows: Figure 3 As shown, the size of the OPC layout sample file at this time is 157665998. Figure 2 The example of step S2 of this embodiment is to use a script to intercept the error position 110 and the preset area 111 around the error position (eg Figure 2 The intercepted layout 11 obtained by the method (as shown in the figure) has three error positions 110, and the size of the layout sample file is 8192. Compared with the two, the resource usage is greatly reduced. In addition, the running time of running OPC and OPCV on the entire original layout 10 is about 27 minutes, while the running time of running OPC and OPCV after intercepting the error position 110 and the preset area 111 around the error position in this embodiment is only about 40 seconds, which greatly reduces the running time.

[0046] As a step of layout correction, OPC is mainly used to overcome the influence of the diffraction effect of light in the photolithography process on the photolithography imaging system. Generally, when the size of semiconductor devices reaches the μm level, the diffraction effect of light will appear. Therefore, in this embodiment, when intercepting the preset area 111 around the error position, the area within the μm level around the error position 110 is generally selected; preferably, the area within the range of 1μm to 5μm around the error position is selected; further, the area within the range of 3μm to 5μm around the error position is selected; optimally, the area within the range of about 3μm around the error position is selected, such as Figure 4 FIG2 shows two error positions 110 and the surrounding areas of the two error positions before being cut off. The cutting method of step S2 in the OPC correction method of this embodiment is used to cut off the error position 110. Figure 4The intercepted graphic 14 obtained by intercepting the two error reporting positions 110 and the preset area 111 around the two error reporting positions is as shown in FIG. Figure 5 As shown, the preset area 111 around the error position is an area within 3 μm around the error position, and the interception method is to intercept the area within 3 μm on both sides perpendicular to the extension direction of the error position according to the shape of the error position.

[0047] As an example, the original layout sample in step S1 can be implemented by an electronic design automation (EDA) tool language, and the file format of the obtained original layout sample is a gds file or an oas file. The file format of the graphics intercepted in step S2 can also be a gds file or an oas file. However, it is not limited to this, and the appropriate text format is selected according to the actual tool chain and design stage. In addition, the script of step S2 of this embodiment is selected to run on a Linux or Unix system, and its text format is a .sh file, but it is not limited to this, and other suitable operating environments are also acceptable.

[0048] As an example, the OPC of this embodiment can be rule-based OPC or model-based OPC. Rule-based OPC relies on a predefined rule base and directly corrects the mask pattern through summarized geometric correction rules (such as line width adjustment amount, corner compensation shape); the basic principle of model-based OPC is to simulate the original layout or target layout by establishing an exposure model based on specific lithography conditions to obtain simulation errors, and then segment the original layout according to certain rules, offset compensate the fragments according to the simulation errors and re-simulate, and obtain the simulation results and the target layout after several rounds of simulation and correction. Figure 1 The revised layout;

[0049] As an example, in OPCV, it is generally necessary to verify common check items such as pinch and bridge of critical dimensions (CD).

[0050] The OPC correction method of this embodiment is applicable to the development and publication of OPC for silicon photonics, BCD, and CMOS, and is universally applicable across multiple platforms. Silicon photonics patterns, in particular, exhibit long runtimes due to their curved nature. Each time a recipe is modified, OPC and OPCV are performed on the entire layout, requiring significant time. However, the OPC correction method of this embodiment, which only captures the pattern at the error location and its surrounding preset area for OPC and OPCV, significantly reduces runtime and resource usage.

[0051] As an example, when modifying the recipe of the graphic captured in step S2 in step S3, the recipe is generally modified based on experience.

[0052] like Figure 6 As shown, in step S6, if the error result obtained in step S5 is determined to be yes, the OPC correction is completed, and the subsequent step S7 of product tape out (tape out integration) can be performed.

[0053] In summary, the present invention provides an OPC correction method. By using a script, all error positions and the graphics of the surrounding preset areas are intercepted, and OPC and OPCV are performed separately on these error positions and the surrounding preset areas. After multiple iterations to eliminate all OPCV errors, OPC is performed on the entire original OPC layout. The intercepted error positions and their surrounding areas not only retain the surrounding environment of the error positions, but also greatly reduce the layout file size, thereby reducing resource usage and reducing the amount of calculation and running time during each OPC and OPCV iterative operation, thereby greatly reducing the running time and resources of the entire OPC correction and improving the efficiency of OPC development and publishing. In addition, there is no need to disclose the complete script, but only the intercepted OPCV hotspots need to be shared to facilitate others to assist in handling hotspot issues, which has better confidentiality. Therefore, the present invention effectively overcomes the various shortcomings of the existing technology and has high industrial utilization value.

[0054] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. An OPC correction method, characterized in that: The OPC correction method comprises the following steps: S1, import the entire original layout sample into the OPC program, run OPC and OPCV, and get the error result; S2, using a script to obtain a graphic of the error location and a preset area around the error location, and intercepting the graphic; S3, modify the recipe of the graphic intercepted in step S2, and run OPC and OPCV on the graphic intercepted in step S2 to obtain an error result; S4, determine whether the error result obtained in step S3 is cleared; if the error result obtained in step S3 is no, repeat step S3; if the error result obtained in step S3 is yes, continue to step S5; S5, run OPC and OPCV on the entire original layout sample and get an error result; S6, judging whether the error result obtained in step S5 is cleared; if the error result obtained in step S5 is no, returning to step S2; if the error result obtained in step S5 is yes, the OPC correction is ended.

2. The OPC correction method according to claim 1, wherein: The preset area around the error reporting position in step S2 is an area within a range of 1 μm to 5 μm around the error reporting position.

3. The OPC correction method according to claim 2, wherein: The preset area around the error reporting position in step S2 is an area within a range of 3 μm to 4 μm around the error reporting position.

4. The OPC correction method according to claim 1, wherein: OPC includes rule-based OPC or model-based OPC.

5. The OPC correction method according to claim 1, wherein: OPCV includes inspection items to verify the critical dimensions of open circuits and short circuits.

6. The OPC correction method according to claim 1, wherein: The file format of the original layout sample in step S1 is a gds file or an oas file; the file format of the intercepted graphics in step S2 is a gds file or an oas file; the file format of the script in step S2 is a .sh file.

7. The OPC correction method according to claim 1, wherein: The OPC correction method is applicable to the OPC development and publication process of silicon photonics, BCD and CMOS.

8. The OPC correction method according to claim 1, wherein: In step S3, the recipe of the graph intercepted in step S2 is modified based on experience.

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