System-on-chip control method, monitoring method, control system and vehicle

Abstract

The invention provides a control method, a monitoring method, a control system and a vehicle of a system-on-chip, the method is applied to the field of vehicles, a read-only memory in the system-on-chip is provided with a target interface, and the method comprises the following steps: in response to a starting instruction of the system-on-chip, controlling the read-only memory to start, when it is detected that sampling of the read-only memory is completed, the current state of the read-only memory is synchronized to the external device through the target interface. According to the method, the external equipment can obtain the state of the system-on-chip in the starting process, so that waste of interaction time between the external equipment and the system-on-chip is reduced.

Description

Technical Field

[0001] The present application relates to the field of vehicles, and more particularly, to a system-on-chip control method, a monitoring method, a control system, and a vehicle. Background Art

[0002] With the increasing popularity of automobiles, the concept of smart cockpits in vehicles is gradually becoming more widely recognized. To achieve this, domain controllers are becoming increasingly integrated and feature-rich. For example, system-on-chips (SOCs) are often used as cockpit controllers, intelligent driving controllers, or central computing units to achieve intelligent vehicle functions.

[0003] In related technologies, after the SoC is booted up, it interacts with external devices through the communication interface within the SoC. However, this approach often results in a waste of interaction time. Therefore, how to enable external devices to obtain the SoC's current state during the boot process, thereby reducing the waste of interaction time between the external device and the SoC, has become an urgent problem to be solved. Summary of the Invention

[0004] The present application provides a control method, a monitoring method, a control system and a vehicle for a system-on-chip, which enables an external device to obtain the status of the system-on-chip during startup, thereby reducing the waste of interaction time between the external device and the system-on-chip.

[0005] In a first aspect, a control method for a system-on-chip is provided, wherein a read-only memory in the system-on-chip is provided with a target interface, the method comprising:

[0006] In response to a startup instruction of the system-on-chip, controlling the read-only memory to start up;

[0007] When it is detected that the sampling of the read-only memory is completed, the current state of the read-only memory is synchronized to an external device through the target interface.

[0008] The above technical solution controls the startup of the read-only memory in response to the startup instruction of the system-on-chip. When the read-only memory sampling is detected to be complete, the current state of the read-only memory is synchronized to the external device via the target interface. Compared with the prior art in which the system-on-chip synchronizes the state to the external device when the system-on-chip is in the configurable state of the general input / output interface, the present application provides a target interface in the read-only memory of the system-on-chip. When the read-only memory sampling is detected to be complete, the current state of the read-only memory is synchronized to the external device via the target interface, so that the external device can obtain the state of the system-on-chip during the startup process. In addition, during the startup process of the system-on-chip, because the configurable state of the general input / output interface is later than the read-only memory sampling completion state, by synchronizing the current state of the read-only memory to the external device earlier, it is possible to reduce the waste of interaction time between the external device and the system-on-chip, and realize data interaction between the external device and the system-on-chip earlier.

[0009] With reference to the first aspect, in some possible implementations, the current state is sampling completion or startup completion, and synchronizing the current state of the read-only memory to the external device through the target interface includes:

[0010] A sampling completion signal or a start completion signal is sent to the external device through the target interface, so that the external device and the system-on-chip perform data exchange.

[0011] In the above technical solution, when the current state is sampling completion or startup completion, a sampling completion signal or a startup completion signal is sent to the external device through the target interface, so that the external device and the system-level chip can exchange data; because the read-only memory is provided with a target interface, the sampling completion signal or the startup completion signal is sent to the external device through the target interface, so that the external device can obtain the startup state of the read-only memory, so as to achieve the purpose of synchronizing the startup state of the read-only memory to the external device, thereby reducing the waste of interaction time between the external device and the system-level chip and enabling the external device to exchange data with the system-level chip.

[0012] In combination with the first aspect and the above implementation manner, in some possible implementation manners, the target interface includes a first interface and a second interface, and when detecting that the read-only memory sampling is completed, synchronizing the current state of the read-only memory to an external device through the target interface includes:

[0013] When it is detected that the sampling of the read-only memory is completed, sending a sampling completion signal to the external device through the first interface;

[0014] When it is detected that the booting of the read-only memory is completed, a booting completion signal is sent to the external device through the second interface.

[0015] In the above technical solution, the target interface includes a first interface and a second interface. When it is detected that the sampling of the read-only memory is completed, a sampling completion signal is sent to the external device through the first interface. When it is detected that the startup of the read-only memory is completed, a startup completion signal is sent to the external device through the second interface. Since the read-only memory is provided with the first interface and the second interface, the sampling completion signal is sent to the external device through the first interface and the startup completion signal is sent to the external device through the second interface. This enables the external device to obtain the startup state of the read-only memory, thereby achieving the purpose of synchronizing the startup state of the read-only memory (system-on-chip) to the external device on the system-on-chip, thereby reducing the waste of interaction time between the external device and the system-on-chip.

[0016] In combination with the first aspect and the above implementation manner, in some possible implementation manners, when detecting that the read-only memory is booted up, sending a boot completion signal to the external device through the second interface includes:

[0017] When detecting that the read-only memory is started up, determining whether the interactive data sent by the external device is received;

[0018] When the interactive data sent by the external device is not received, the startup completion signal is sent to the external device through the second interface.

[0019] The above technical solution, when detecting that the read-only memory has completed startup, determines whether interactive data sent by the external device has been received. If no interactive data has been received, a startup completion signal is sent to the external device via the second interface. When the SoC receives interactive data from the external device, there is no need to send the startup completion signal to the external device. This achieves synchronization of the SoC startup status with the external device while reducing the waste of communication resources during the SoC startup process. Sending the startup completion signal to the external device via the second interface only when the SoC has not received interactive data from the external device achieves synchronization of the SoC startup status with the external device.

[0020] In combination with the first aspect and the above implementation manner, in some possible implementation manners, the method further includes:

[0021] When it is detected that the system-on-chip is in a boot loading state, the target interface is reused for data configuration.

[0022] The above technical solution synchronizes the current state of the ROM to an external device via the target interface during the ROM startup process. When the SoC is detected to be in the boot loading state, the target interface is reused for data configuration, improving data configuration efficiency while reducing the duration of the SoC startup process.

[0023] In a second aspect, a method for monitoring a system-on-chip is provided, wherein a read-only memory in the system-on-chip is provided with a target interface, the method comprising:

[0024] During the booting process of the read-only memory, monitoring a current state of the read-only memory based on the target interface;

[0025] Based on the current state, determining whether the system-on-chip is successfully started;

[0026] When the system-on-chip is successfully started, data interaction is performed with the system-on-chip based on the target interface.

[0027] The above technical solution monitors the current state of the read-only memory based on the target interface during the read-only memory startup process, determines whether the system-on-chip has successfully started based on the current state, and exchanges data with the system-on-chip based on the target interface when the system-on-chip has successfully started. Furthermore, by setting the target interface to monitor the current state of the read-only memory in the system-on-chip, the system-on-chip's current state during the startup process can be obtained. Furthermore, during the system-on-chip startup process, because the configurable state of the general input / output interface is later than the read-only memory startup completion state, when the system-on-chip successfully starts, data is exchanged with the system-on-chip based on the target interface. This reduces the time wasted in interacting with the system-on-chip and enables data interaction between the external device and the system-on-chip earlier.

[0028] With reference to the second aspect, in some possible implementations, determining whether the system-on-chip is successfully started based on the current state includes:

[0029] When the current status indicates that the read-only memory is started up successfully, it is determined that the system-on-chip is started up successfully.

[0030] The above technical solution determines that the system-level chip has been successfully started when the current status indicates that the read-only memory startup is completed; monitors the startup status of the system-level chip (read-only memory) through the target interface, and determines that the system-level chip has been successfully started when the current status indicates that the read-only memory startup is completed, thereby realizing the monitoring of the system-level suction cup startup process.

[0031] In combination with the second aspect and the above implementation manner, in some possible implementation manners, when the current status indicates that the read-only memory is started up, determining that the system-on-chip is started up successfully includes:

[0032] When the current state indicates that the read-only memory startup is complete, determining a target duration for completing the read-only memory startup;

[0033] When the target duration is greater than a preset duration, determining that the system-on-chip startup has timed out;

[0034] When the target duration is less than or equal to the preset duration, it is determined that the system-on-chip is successfully started.

[0035] The above technical solution, when the current status indicates that the read-only memory startup is completed, determines the target duration used for the read-only memory startup to be completed. When the target duration is greater than the preset duration, it is determined that the system-level chip startup has timed out. When the target duration is less than or equal to the preset duration, it is determined that the system-level chip startup has been successful. By comparing the preset duration with the target duration used for the read-only memory startup to be completed, the accuracy of determining the success of the system-level chip startup can be improved, thereby improving the user experience.

[0036] In a third aspect, a system-on-chip control system is provided, comprising a system-on-chip and an external device; wherein the system-on-chip is configured to execute the system-on-chip control method of the first aspect or any possible implementation of the first aspect;

[0037] The external device is used to execute the system-on-chip monitoring method in the above-mentioned second aspect or any possible implementation of the second aspect.

[0038] In a fourth aspect, a control device for a system-level chip is provided, which includes a control module and a detection module. The control module is used to control the start-up of the read-only memory in response to the startup instruction of the system-level chip; the detection module is used to synchronize the current state of the read-only memory to an external device through the target interface when it detects that the sampling of the read-only memory is completed.

[0039] With reference to the fourth aspect, in some possible implementations, the current state is sampling completed or startup completed, and the detection module is specifically configured to:

[0040] A sampling completion signal or a start completion signal is sent to the external device through the target interface, so that the external device and the system-on-chip perform data exchange.

[0041] In combination with the fourth aspect and the above implementations, in some possible implementations, the target interface includes a first interface and a second interface, and the detection module is specifically configured to:

[0042] When it is detected that the sampling of the read-only memory is completed, sending a sampling completion signal to the external device through the first interface;

[0043] When it is detected that the booting of the read-only memory is completed, a booting completion signal is sent to the external device through the second interface.

[0044] In combination with the fourth aspect and the above implementations, in some possible implementations, the detection module is specifically configured to:

[0045] When detecting that the read-only memory is started up, determining whether the interactive data sent by the external device is received;

[0046] When the interactive data sent by the external device is not received, the startup completion signal is sent to the external device through the second interface.

[0047] In combination with the fourth aspect and the above implementations, in some possible implementations, the detection module is further configured to:

[0048] When it is detected that the system-on-chip is in a boot loading state, the target interface is reused for data configuration.

[0049] In a fifth aspect, a monitoring device for a system-level chip is provided, and the monitoring device for the system-level chip includes a monitoring module, a determination module and an interaction module; the monitoring module is used to monitor the current state of the read-only memory based on the target interface during the startup process of the read-only memory; the determination module is used to determine whether the system-level chip is successfully started based on the current state; the interaction module is used to interact with the system-level chip for data based on the target interface when the system-level chip is successfully started.

[0050] In conjunction with the fifth aspect, in some possible implementations, the determining module is specifically configured to:

[0051] When the current status indicates that the read-only memory is started up successfully, it is determined that the system-on-chip is started up successfully.

[0052] In combination with the fifth aspect and the above implementations, in some possible implementations, the determination module is specifically configured to:

[0053] When the current state indicates that the read-only memory startup is complete, determining a target duration for completing the read-only memory startup;

[0054] When the target duration is greater than a preset duration, determining that the system-on-chip startup has timed out;

[0055] When the target duration is less than or equal to the preset duration, it is determined that the system-on-chip is successfully started.

[0056] In a sixth aspect, a vehicle is provided, comprising a memory and a processor, the memory being used to store executable program code; the processor being used to call and run the executable program code from the memory, so that the vehicle executes the control method of the system-level chip in the above-mentioned first aspect or any possible implementation of the first aspect, and / or executes the monitoring method of the system-level chip in the above-mentioned second aspect or any possible implementation of the second aspect.

[0057] In the seventh aspect, a computer-readable storage medium is provided, which stores a computer program code. When the computer program code runs on a computer, the computer executes the control method of the system-level chip in the above-mentioned first aspect or any possible implementation of the first aspect, and / or executes the monitoring method of the system-level chip in the above-mentioned second aspect or any possible implementation of the second aspect.

[0058] In an eighth aspect, a computer program product is provided, comprising: a computer program code, which, when executed on a computer, enables the computer to execute the control method of the system-level chip in the above-mentioned first aspect or any possible implementation of the first aspect, and / or, execute the monitoring method of the system-level chip in the above-mentioned second aspect or any possible implementation of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 This is an interactive schematic diagram of a SOC startup method provided in an embodiment of the present application;

[0060] Figure 2 This is an interactive diagram of another SOC startup method provided in an embodiment of the present application;

[0061] Figure 3 This is a schematic diagram of a framework of a system-on-chip control system provided in an embodiment of the present application;

[0062] Figure 4 This is a node diagram of a SOC startup process provided by an embodiment of the present application;

[0063] Figure 5 This is a control timing diagram of a SOC startup method provided by an embodiment of the present application;

[0064] Figure 6 is a schematic flow chart of a control method of a system-on-chip provided in an embodiment of the present application;

[0065] Figure 7 is a schematic flow chart of a system-on-chip monitoring method provided in an embodiment of the present application;

[0066] Figure 8 This is a schematic structural diagram of a control device for a system-on-chip provided in an embodiment of the present application;

[0067] Figure 9 This is a schematic structural diagram of a system-on-chip monitoring device provided in an embodiment of the present application;

[0068] Figure 10 It is a structural schematic diagram of a vehicle provided in an embodiment of the present application. DETAILED DESCRIPTION

[0069] The following will clearly and thoroughly describe the technical solutions in this application in conjunction with the accompanying drawings. In the description of the embodiments of this application, unless otherwise specified, " / " means or, for example, A / B can mean A or B: "and / or" in the text is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more than two.

[0070] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to imply or suggest relative importance or implicitly indicate the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features.

[0071] As cars gradually evolve toward intelligent systems, domain controllers are becoming increasingly integrated and feature-rich. System-on-a-chip (SOCs), or systems-on-a-chip (SoCs), are essential for applications such as cockpit controllers, intelligent driving controllers, and central computing units (CCUs). Existing SOC startup control methods use general-purpose input / output (GPIO) interfaces to control timing and interact with microcontroller units (MCUs) and other device resources. However, due to the relatively late controllable time window of GPIOs, other devices face monitoring timing blind spots and experience long wait times.

[0072] Figure 1 This is an interactive schematic diagram of a SOC startup method provided in an embodiment of the present application.

[0073] For example, Figure 1 As shown, the MCU is connected to the Reset pin of the SOC (the GPIO pin in the MCU is connected to the Reset pin of the SOC), while the GPIO 1 in the SOC is connected to the MCU, and the GPIO 2 is connected to other devices.

[0074] When the MCU sends a reset release signal to the SoC through the reset pin, the SoC starts booting. During the SoC boot process, the read-only memory (BOOT ROM) is first booted. After the BOOT ROM boot is complete, the extensible boot loader (XBL) is loaded and the GPIO configuration in the SoC is initialized.

[0075] In addition, the SoC includes non-volatile flash memory (Nor flash), universal flash storage (UFS), and double data rate synchronous dynamic random access memory (DDR). Nor flash, UFS, and DDR can provide boot code, data storage, and runtime support for the SoC. Among them, Nor flash is used to store firmware and key code, UFS is used for large-capacity storage, and DDR is used for runtime memory. It can achieve two data transfers in one clock cycle, improving data transmission efficiency.

[0076] It is understandable that only after the GPIO configuration is completed can the MCU and other devices obtain the startup status of the SOC and exchange data with the SOC.

[0077] During the Boot ROM startup phase, the MCU and other devices cannot see the Boot ROM startup status (and therefore the SoC startup status). Since the MCU cannot monitor the Boot ROM startup process, and the time from Boot ROM startup to GPIO configuration typically takes hundreds of milliseconds, the MCU and other devices are forced to wait, wasting interaction time between external devices (the MCU and other devices) and the SoC.

[0078] In view of this, the present application provides a control method, a monitoring method, a control system and a vehicle for a system-level chip, which enables an external device to obtain the status of the system-level chip during the startup process, thereby reducing the waste of interaction time between the external device and the system-level chip.

[0079] Figure 2 This is an interactive schematic diagram of another SOC startup method provided in an embodiment of the present application.

[0080] For example, Figure 2As shown, the MCU is connected to the Reset pin of the SOC (the GPIO pin in the MCU is connected to the Reset pin of the SOC), and the BOOT ROM in the SOC is configured with a sample finished interface (such as a GPIO pin) and a boot flag interface (such as a GPIO pin). The BOOT ROM communicates with the MCU and other devices through the sample finished interface, and the BOOT ROM communicates with the MCU and other devices through the boot flag interface.

[0081] When the MCU sends a reset release signal to the SoC through the reset pin, the SoC starts booting. During the boot process, the BIOS boots up the BIOS first. During the boot process, the MCU and other devices can monitor the boot status of the BIOS through the sample finished interface and the boot flag interface.

[0082] Specifically, when the Boot ROM completes sampling, the sample finished flag is set, sending a sampling completion signal through the sample finished interface. This allows the MCU and other devices to obtain the SOC's boot status, allowing the MCU and other devices to exchange data with the SOC. Furthermore, when the Boot ROM completes execution, the boot flag is set, sending a boot completion signal through the bootflag interface.

[0083] In addition, the SoC includes Nor flash, UFS, and DDR, which provide boot code, data storage, and runtime support. Nor flash is used to store firmware and critical code, UFS is used for mass storage, and DDR is used for runtime memory. This allows for two data transfers within a single clock cycle, improving data transfer efficiency.

[0084] Since the MCU and other devices can exchange data with the SOC after the Boot ROM sampling is completed, compared with the MCU and other devices waiting until the GPIO configurable stage, the sample finished interface and boot flag interface set in the Boot ROM can not only enable the MCU and other devices to obtain the startup status of the SOC, but also shorten the interaction time between the MCU, other devices and the SOC by at least 200ms, which saves the time from the Boot ROM sampling completion stage to the GPIO configurable stage.

[0085] Figure 3 This is a schematic diagram of a framework of a system-on-chip control system provided in an embodiment of the present application.

[0086] For example, Figure 3 As shown, the control system of the SoC includes a SoC 310 and an external device 320 , and the SoC 310 and the external device 320 are communicatively connected.

[0087] Optionally, the external device 320 may be an MCU, a screen, or the like.

[0088] In this embodiment, the external device is explained by taking MCU as an example, and other devices can be deduced accordingly, which will not be described in detail here.

[0089] For example, when the SOC receives a boot command, it controls the Boot ROM to boot and monitors the Boot ROM's boot status. When it detects that the Boot ROM sampling is complete, it sets the sample finished (target interface) bit, i.e., configures the sample finished interface to a high level. This high level sends a sampling completion signal to the MCU, allowing the MCU to detect that the Boot ROM is in the sampling completion state and to exchange data with the SOC.

[0090] Furthermore, when it is detected that the BOOT ROM startup is completed (or called the operation is completed), the boot flag (target interface) is set, that is, the boot flag interface is configured to a high level to send a sampling completion signal to the MCU through a high level, so that the MCU obtains that the BOOT ROM is in the startup completion state.

[0091] Exemplarily, the sample finished interface and the boot flag interface can be GPIO pins or PIN pins configured in the Boot ROM. Therefore, the Boot ROM startup status can be transmitted to the MCU via a set bit or a high or low level signal. It is understood that the sample finished interface is used to synchronize the Boot ROM sampling completion status with the MCU, and the boot flag interface is used to synchronize the Boot ROM startup completion status with the MCU.

[0092] For example, the MCU can also determine whether the Boot ROM has timed out when detecting that the sample finished bit is set. For example, assuming that the time from the Boot ROM booting to the sampling completion is 50ms, the MCU obtains the target time from the Boot ROM booting to the sampling completion when detecting that the sample finished bit is set. If the target time is greater than 55ms (with a 5ms error range), the Boot ROM boot timeout is determined.

[0093] Of course, the MCU can also determine whether the Boot ROM has a boot timeout when it detects the boot flag is set. For example, assuming that the time from the normal Boot ROM boot to the boot completion is 100ms, the MCU obtains the target boot time from the start of the Boot ROM boot to the boot completion when it detects the boot flag is set. If the target time is greater than 105ms (with a 5ms error range), it is determined that the Boot ROM has timed out.

[0094] Figure 4 This is a node diagram of a SOC startup process provided in an embodiment of the present application.

[0095] For example, Figure 4 (a) is a node diagram of the SOC startup process. Figure 4 (b) is another node schematic diagram of the SOC startup process.

[0096] For example, Figure 4 As shown in (a) of the figure, after the SOC is powered on (startup command), it prepares to start. 5ms after power-on, the reset is released, the system reset is complete, and the SOC enters the startup phase. The Boot ROM starts and loads. After the Boot ROM boot is complete, the XBL begins running. When the XBL is loaded into memory, the GPIO can be configured. Initialization is complete after 300ms, and the kernel is then loaded and booted. After 500ms, the XBL completes.

[0097] Furthermore, the operating system (OS) is initialized and starts necessary services, and the application (APP) begins to load and run at a time of 3000ms. When the application is fully loaded, the system enters a normal working state.

[0098] It is understandable that only after the GPIO configuration is completed can the MCU and other devices obtain the startup status of the SOC and exchange data with the SOC.

[0099] For example, Figure 4As shown in (b) of the figure, after the SOC is powered on (startup command), the SOC prepares to start. 5ms after power-on, the reset is released, the system reset is complete, and the SOC enters the startup phase. The BOOT ROM starts and loads the execution. After 50ms, the BOOT ROM completes sampling and sets the sample finished bit. This signals the sampling completion through the sample finished interface, allowing the MCU and other devices to obtain the SOC's startup status. At this point, the MCU and other devices can exchange data with the SOC. When the BOOT ROM completes execution, the boot flag bit is set, and a boot completion signal is sent through the boot flag interface.

[0100] After the BOOT ROM is started, the XBL starts running, reusing the sample finished interface and the boot flag interface to load the XBL. At the same time, the GPIO (GPIO in the SOC) can be configured, and then the kernel is loaded and booted until the XBL is completed at 400ms.

[0101] Furthermore, the operating system (OS) is initialized and starts necessary services, and at a time of 2800ms, the application (APP) begins to load and run. When the application is fully loaded, the system enters a normal working state.

[0102] It should be noted that the BOOT ROM in the SOC is provided with target interfaces, including a sample finished interface and a boot flag interface. For example, the sample finished interface and the boot flag interface are GPIO pins.

[0103] It can be understood that by sending a sampling completion signal to the external device through the sample finished interface, the external device and the SOC can exchange data; of course, by sending a sampling completion signal to the external device through the boot flag interface, the external device and the SOC can also exchange data.

[0104] In the above technical solution, since the external device can exchange data with the SOC after the Boot ROM sampling is completed, compared with the external device waiting until the GPIO configurable stage, the sample finished interface and boot flag interface set in the Boot ROM can not only enable the external device to obtain the startup status of the SOC, but also shorten the interaction time between the external device and the SOC by at least 200ms, that is, saving the time from the Boot ROM sampling completion stage to the GPIO configurable stage.

[0105] Figure 5 This is a control timing diagram of a SOC startup method provided in an embodiment of the present application.

[0106] For example, Figure 5 As shown, at time 0ms, the SOC power is turned on and reaches a stable state. At time 5ms, the Reset signal is released, the system reset is complete, the SOC starts operating, and the Boot ROM (boot read-only memory) is loaded. Boot IO sampling is performed at time 20ms. Boot IO sampling is used to determine the boot device and / or obtain boot configuration information. At time 50ms, Boot ROM sampling is completed (or called sampling end), and the sample finished bit is set, that is, the sampling completion signal is sent through the sample finished interface. At time 100ms, the Boot ROM operation is completed, and the boot flag bit is set, that is, the boot completion signal is sent through the boot flag interface.

[0107] At 200ms, the XBL begins running, reusing the sample finished interface and the boot flag interface to load the XBL. Simultaneously, the GPIO (in the SoC) is configured, and the kernel is loaded and booted. XBL completes at 400ms. The OS then initializes and starts necessary services. At 2800ms, the app begins loading and running. Once the application is fully loaded, the system enters normal operation.

[0108] The above technical solution establishes a target interface in the ROM within the SoC. Upon detecting that the ROM sampling is complete, the target interface is used to synchronize the current state of the ROM to an external device, allowing the external device to obtain the current state of the SoC during its startup. Furthermore, during the SoC startup process, since the configurable state of the general purpose input / output interface is later than the completion state of the ROM sampling, synchronizing the current state of the ROM to the external device earlier can reduce the time wasted in interacting with the SoC, enabling earlier data exchange between the external device and the SoC.

[0109] Figure 6 This is a schematic flow chart of a system-on-chip control method provided in an embodiment of the present application.

[0110] For example, Figure 6 The method shown is performed by a system-on-chip.

[0111] For example, Figure 6 As shown, the control method 600 of the system-on-chip includes steps S610 - S620 .

[0112] S610 , in response to a startup instruction of the system-on-chip, controlling the read-only memory to start up.

[0113] Exemplarily, when a startup instruction of the SOC is received, the BOOT ROM in the SOC is controlled to start.

[0114] Optionally, receipt of the SOC startup instruction is determined when the SOC is powered on; receipt of the SOC startup instruction is determined when a reset release signal from the MCU is received. Alternatively, receipt of the SOC startup instruction is determined when a reset signal is received. The triggering method for the startup instruction can be determined based on actual circumstances and is not specifically limited here.

[0115] S620: When it is detected that the ROM sampling is completed, the current state of the ROM is synchronized to the external device through the target interface.

[0116] For example, in response to a boot instruction from the SOC, the BOOT ROM is controlled to start up, and the boot status of the BOOT ROM is monitored. When the BOOT ROM sampling is detected to be complete, the current status of the BOOT ROM is synchronized to an external device via a target interface, so that the external device can obtain the boot status of the SOC and the boot status of the BOOT ROM.

[0117] Optionally, the external device may be an MCU, a screen, etc. The external device may be determined according to actual conditions and is not specifically limited here.

[0118] Alternatively, a GPIO pin can be configured in the Boot ROM and used as the target interface. Alternatively, a PIN pin can be configured in the Boot ROM and used as the target interface. The target interface setting method can be determined based on actual conditions and is not specifically limited here.

[0119] In one example, in response to a boot instruction from the SOC, the BOOT ROM is controlled to boot and the current state of the BOOT ROM is monitored. When it is detected that the BOOT ROM sampling is complete, and when the current state of the BOOT ROM is sampling complete or boot complete, a sampling completion signal or a boot completion signal is sent to an external device via a target interface, so that the external device and the system-on-chip can exchange data.

[0120] Exemplarily, the BOOT ROM is provided with a target interface, which is a GPIO pin.

[0121] For example, in response to the startup instruction of the SOC, the BOOT ROM is controlled to start and the startup status of the BOOT ROM is monitored. When it is detected that the BOOT ROM sampling is completed, the target interface is controlled to be set, that is, the target interface is configured to a high level to send a sampling completion signal to the external device through the target interface, so that the external device can obtain that the BOOT ROM in the SOC is in the sampling completion stage.

[0122] Alternatively, in response to the startup instruction of the SOC, the BOOT ROM is controlled to start and the startup status of the BOOT ROM is monitored. When it is detected that the BOOT ROM startup is completed, the target interface is controlled to be set, that is, the target interface is configured to a high level to send a startup completion signal to the external device through the target interface, so that the external device can obtain that the BOOT ROM in the SOC is in the startup completion stage.

[0123] It is understood that during the boot ROM boot process, when the boot ROM is in the sampling completion state, the boot ROM runs until the operation is completed, and the boot ROM boot is completed. Therefore, when the target interface is a GPIO pin, the target interface can send a sampling completion signal or a boot completion signal.

[0124] In the above technical solution, when the current state is sampling completion or startup completion, a sampling completion signal or a startup completion signal is sent to the external device through the target interface, so that the external device and the system-level chip can exchange data; because the read-only memory is provided with a target interface, the sampling completion signal or the startup completion signal is sent to the external device through the target interface, so that the external device can obtain the startup state of the read-only memory, so as to achieve the purpose of synchronizing the startup state of the read-only memory to the external device, thereby reducing the waste of interaction time between the external device and the system-level chip and enabling the external device to exchange data with the system-level chip.

[0125] In another example, a first interface and a second interface are provided in the BOOT ROM. In response to a boot instruction from the SoC, the BOOT ROM is controlled to boot and its current status is monitored. Upon detecting that BOOT ROM sampling is complete, a sampling completion signal is sent to an external device via the first interface. Upon detecting that BOOT ROM booting is complete, a boot completion signal is sent to the external device via the second interface, enabling data exchange between the external device and the SoC.

[0126] Exemplarily, the BOOT ROM is provided with a target interface, the target interface includes a first interface and a second interface, and both the first interface and the second interface are GPIO pins.

[0127] For example, in response to a startup instruction from the SOC, the BOOT ROM is controlled to start and the startup status of the BOOT ROM is monitored. When it is detected that the BOOT ROM sampling is completed, the first interface is controlled to be set, that is, the first interface is configured to be a high level, so as to send a sampling completion signal to the external device through the first interface, so that the external device can obtain that the BOOT ROM in the SOC is in the sampling completion stage. When it is detected that the BOOT ROM startup is complete, the second interface is controlled to be set, that is, the second interface is configured to be a high level, so as to send a startup completion signal to the external device through the second interface, so that the external device can obtain that the BOOT ROM in the SOC is in the startup completion stage.

[0128] In the above technical solution, the target interface includes a first interface and a second interface. When it is detected that the sampling of the read-only memory is completed, a sampling completion signal is sent to the external device through the first interface. When it is detected that the startup of the read-only memory is completed, a startup completion signal is sent to the external device through the second interface. Since the read-only memory is provided with the first interface and the second interface, the sampling completion signal is sent to the external device through the first interface and the startup completion signal is sent to the external device through the second interface. This enables the external device to obtain the startup state of the read-only memory, thereby achieving the purpose of synchronizing the startup state of the read-only memory (system-on-chip) to the external device on the system-on-chip, thereby reducing the waste of interaction time between the external device and the system-on-chip.

[0129] In order to reduce the waste of communication resources during the SOC startup process, whether to perform signal synchronization can be determined based on the data interaction between the SOC and the external device.

[0130] Exemplarily, the target interface includes a first interface and a second interface. When it is detected that the sampling of the read-only memory is completed, a sampling completion signal is sent to the external device through the first interface; when it is detected that the startup of the read-only memory is completed, it is determined whether the interactive data sent by the external device is received. When the interactive data sent by the external device is not received, a startup completion signal is sent to the external device through the second interface.

[0131] Specifically, when it is detected that the BOOT ROM sampling is complete, a sampling completion signal is sent to the external device via the first interface, so that the external device can obtain the information that the BOOT ROM is in the sampling completion stage and can exchange data with the SOC. Furthermore, when it is detected that the BOOT ROM startup is complete, it is determined whether the interaction data sent by the external device has been received. When the interaction data sent by the external device is received, it indicates that the external device has obtained the current state of the SOC to be a state in which data interaction can be carried out, and there is no need to synchronize the startup state of the SOC with the external device. When the interaction data sent by the external device is not received, it indicates that the external device may not have obtained the current state of the SOC. By synchronizing the startup completion signal, the external device can obtain the current state of the SOC, so that the external device and the SOC can exchange data.

[0132] Optionally, the external device may include one device or multiple devices.

[0133] Exemplarily, when the external device includes multiple devices, upon detecting that the BOOT ROM has completed startup, it is determined whether interaction data sent by the external device has been received. If interaction data sent by the external device has not been received, a startup completion signal is sent to the external device via the second interface. If interaction data sent by the external device has been received, a target device that has not sent interaction data is determined, and a startup completion signal is sent to the target device via the second interface.

[0134] The above technical solution, when detecting that the read-only memory has completed startup, determines whether interactive data sent by the external device has been received. If no interactive data has been received, a startup completion signal is sent to the external device via the second interface. When the SoC receives interactive data from the external device, there is no need to send the startup completion signal to the external device. This achieves synchronization of the SoC startup status with the external device while reducing the waste of communication resources during the SoC startup process. Sending the startup completion signal to the external device via the second interface only when the SoC has not received interactive data from the external device achieves synchronization of the SoC startup status with the external device.

[0135] In order to reduce the time taken for the SOC startup process, the target interface in the BOOT ROM can be reused.

[0136] Exemplarily, in response to a startup instruction of the system-on-chip, the read-only memory is controlled to start up, and when it is detected that the read-only memory sampling is completed, the current state of the read-only memory is synchronized to the external device through the target interface. Specifically, when it is detected that the read-only memory sampling is completed, a sampling completion signal is sent to the external device through the first interface, and when it is detected that the read-only memory startup is completed, a startup completion signal is sent to the external device through the second interface. Furthermore, when it is detected that the system-on-chip is in the boot loading state (after the read-only memory startup is completed), the target interface is reused for data configuration, thereby improving the data configuration efficiency while reducing the duration of the system-on-chip startup process.

[0137] The above technical solution synchronizes the current state of the ROM to an external device via the target interface during the ROM startup process. When the SoC is detected to be in the boot loading state, the target interface is reused for data configuration, improving data configuration efficiency while reducing the duration of the SoC startup process.

[0138] For example, when Boot ROM sampling is detected to be complete, a sampling completion signal is sent to the external device via the first interface. When Boot ROM startup is detected to be complete, a startup completion signal is sent to the external device via the second interface. When the SOC is detected to be in the XBL loading state, hardware data is configured via the first and second interfaces, which can reduce the XBL usage time.

[0139] The above technical solution controls the startup of the read-only memory in response to the startup instruction of the system-on-chip. When the read-only memory sampling is detected to be complete, the current state of the read-only memory is synchronized to the external device via the target interface. Compared with the prior art in which the system-on-chip synchronizes the state to the external device when the system-on-chip is in the configurable state of the general input / output interface, the present application provides a target interface in the read-only memory of the system-on-chip. When the read-only memory sampling is detected to be complete, the current state of the read-only memory is synchronized to the external device via the target interface, so that the external device can obtain the state of the system-on-chip during the startup process. In addition, during the startup process of the system-on-chip, because the configurable state of the general input / output interface is later than the read-only memory sampling completion state, by synchronizing the current state of the read-only memory to the external device earlier, it is possible to reduce the waste of interaction time between the external device and the system-on-chip, and realize data interaction between the external device and the system-on-chip earlier.

[0140] Figure 7 This is a schematic flow chart of a system-on-chip monitoring method provided in an embodiment of the present application.

[0141] For example, Figure 7 The method shown is executed by an external device, such as a microcontroller unit.

[0142] For example, Figure 7 As shown, the system-on-chip monitoring method 700 includes steps S710 - S730 .

[0143] S710 , during the ROM startup process, monitor the current state of the ROM based on the target interface.

[0144] For example, during the boot ROM startup process in the SOC, the current state of the boot ROM is monitored based on the target interface. Specifically, when a sampling completion signal (e.g., a high level) is detected from the SOC via the first interface, it indicates that the boot ROM in the SOC is in the sampling completion state (or referred to as the sampling completion state); when a boot completion signal is detected from the SOC via the second interface, it indicates that the boot ROM in the SOC is in the boot completion state.

[0145] For example, two GPIO pins are configured in the BOOT ROM, with one GPIO pin used as the first interface and the other as the second interface. The BOOT ROM in the SOC can synchronize its startup state by controlling the high and low levels of the first and second interfaces. When the BOOT ROM sampling is detected to be complete, the BOOT ROM sets the first interface to a high level, allowing external devices to obtain the information that the BOOT ROM in the SOC is in the sampling completion state; when the BOOT ROM startup is detected to be complete, the BOOT ROM sets the second interface to a high level, allowing external devices to obtain the information that the BOOT ROM in the SOC is in the startup completion state.

[0146] S720: Determine whether the system-on-chip is successfully started based on the current state.

[0147] For example, when the target interface is one interface, the current state may be sampling completed or startup completed. When the target interface includes a first interface and a second interface, the current state monitored through the first interface is sampling completed, and the current state monitored through the second interface is startup completed.

[0148] In one example, the current state of the read-only memory is monitored based on the target interface, and when the current state indicates that the read-only memory startup is complete, it is determined that the system-on-chip startup is successful.

[0149] Specifically, the current state of the BOOT ROM is monitored based on the target interface, and when the current state is sampling completed, data is exchanged with the SOC. When the current state is startup completed, it is determined that the SOC startup is successful.

[0150] The above technical solution determines that the system-level chip has been successfully started when the current status indicates that the read-only memory startup is completed; monitors the startup status of the system-level chip (read-only memory) through the target interface, and determines that the system-level chip has been successfully started when the current status indicates that the read-only memory startup is completed, thereby realizing the monitoring of the system-level suction cup startup process.

[0151] In another example, the current status of the BOOT ROM is monitored based on the target interface, and when the current status indicates that the BOOT ROM startup is completed, the target duration for the BOOT ROM startup to be completed is determined, and it is determined whether the target is greater than the preset duration. When the target duration is greater than the preset duration, it is determined that the SOC startup has timed out. When the target duration is less than or equal to the preset duration, it is determined that the SOC startup has been successful.

[0152] Optionally, the preset duration may be 101ms, 103ms, 105ms, etc. The preset duration may be determined based on actual conditions and is not specifically limited here.

[0153] For example, when the target duration is greater than the preset duration and the SOC startup timeout is determined, a prompt message is output on the screen to remind the user that the SOC startup timeout has occurred and maintenance is required to avoid the inconvenience caused by SOC failure.

[0154] The above technical solution, when the current status indicates that the read-only memory startup is completed, determines the target duration used for the read-only memory startup to be completed. When the target duration is greater than the preset duration, it is determined that the system-level chip startup has timed out. When the target duration is less than or equal to the preset duration, it is determined that the system-level chip startup has been successful. By comparing the preset duration with the target duration used for the read-only memory startup to be completed, the accuracy of determining the success of the system-level chip startup can be improved, thereby improving the user experience.

[0155] S730: When the system-on-chip is successfully started, data is exchanged with the system-on-chip based on the target interface.

[0156] Exemplarily, when the system-on-chip is successfully started, data interaction is performed with the system-on-chip based on the target interface.

[0157] The above technical solution monitors the current state of the read-only memory based on the target interface during the read-only memory startup process, determines whether the system-on-chip has successfully started based on the current state, and exchanges data with the system-on-chip based on the target interface when the system-on-chip has successfully started. Furthermore, by setting the target interface to monitor the current state of the read-only memory in the system-on-chip, the system-on-chip's current state during the startup process can be obtained. Furthermore, during the system-on-chip startup process, because the configurable state of the general input / output interface is later than the read-only memory startup completion state, when the system-on-chip successfully starts, data is exchanged with the system-on-chip based on the target interface. This reduces the time wasted in interacting with the system-on-chip and enables data interaction between the external device and the system-on-chip earlier.

[0158] It should be understood that the above examples are intended to help those skilled in the art understand the embodiments of the present application, and are not intended to limit the embodiments of the present application to the specific numerical values ​​or specific scenarios illustrated. Those skilled in the art can obviously make various equivalent modifications or variations based on the above examples, and such modifications or variations also fall within the scope of the embodiments of the present application.

[0159] Combined with the above Figures 1 to 6 The control method of the system-on-chip provided by the embodiment of the present application is described in detail. Figure 7 The system-on-chip monitoring method provided by the embodiment of the present application is described in detail; Figure 8 and Figure 10 The device embodiments of the present application are described in detail. It should be understood that the devices in the embodiments of the present application can execute the various methods of the aforementioned embodiments of the present application, that is, the specific working processes of the following various products can refer to the corresponding processes in the aforementioned method embodiments.

[0160] Figure 8 This is a structural diagram of a system-on-chip control device provided in an embodiment of the present application.

[0161] The read-only memory in the system-on-chip is provided with a target interface.

[0162] For example, Figure 8 As shown, the control device 800 of the system-on-chip includes:

[0163] Control module 810: for controlling the read-only memory to start in response to a startup instruction of the system-on-chip;

[0164] Detection module 820: configured to synchronize the current state of the read-only memory to an external device via a target interface when detecting that the read-only memory sampling is completed.

[0165] Optionally, as an embodiment, the current state is sampling completed or startup completed, and the detection module 820 is specifically configured to:

[0166] A sampling completion signal or a start completion signal is sent to the external device through the target interface, so that the external device and the system-level chip can perform data exchange.

[0167] Optionally, as an embodiment, the target interface includes a first interface and a second interface, and the detection module 820 is specifically configured to:

[0168] When it is detected that the sampling of the read-only memory is completed, a sampling completion signal is sent to the external device through the first interface;

[0169] When it is detected that the read-only memory is started up completely, a start-up completion signal is sent to the external device through the second interface.

[0170] Optionally, as an embodiment, the detection module 820 is specifically configured to:

[0171] When it is detected that the read-only memory is started up, determining whether interaction data sent by the external device is received;

[0172] When no interactive data sent by the external device is received, a startup completion signal is sent to the external device through the second interface.

[0173] Optionally, as an embodiment, the detection module 820 is further configured to:

[0174] When it is detected that the system-level chip is in the boot loading state, the target interface is reused for data configuration.

[0175] It should be noted that the control device 800 of the system-on-chip is implemented in the form of a functional unit. The term "module" here can be implemented in the form of software and / or hardware, and is not specifically limited to this.

[0176] Figure 9 This is a schematic diagram of the structure of a system-on-chip monitoring device provided in an embodiment of the present application.

[0177] The read-only memory in the system-on-chip is provided with a target interface.

[0178] For example, Figure 9 As shown, the system-on-chip monitoring device 900 includes:

[0179] Monitoring module 910: used to monitor the current state of the read-only memory based on the target interface during the read-only memory startup process;

[0180] Determining module 920: used to determine whether the system-on-chip is successfully started based on the current state;

[0181] Interaction module 930: used for performing data interaction with the system-on-chip based on the target interface when the system-on-chip is successfully started.

[0182] Optionally, as an embodiment, the determining module 920 is specifically configured to:

[0183] When the current status indicates that the read-only memory startup is completed, it is determined that the system-on-chip startup is successful.

[0184] Optionally, as an embodiment, the determining module 920 is specifically configured to:

[0185] When the current status indicates that the read-only memory startup is complete, determining a target duration for the read-only memory startup to be complete;

[0186] When the target duration is greater than the preset duration, it is determined that the system-level chip startup timeout has occurred;

[0187] When the target duration is less than or equal to the preset duration, it is determined that the system-on-chip is successfully started.

[0188] It should be noted that the system-on-chip monitoring device 900 is implemented in the form of a functional unit. The term "module" herein can be implemented in the form of software and / or hardware, and is not specifically limited thereto.

[0189] For example, a "module" may be a software program, a hardware circuit, or a combination of the two that implements the aforementioned functionality. The hardware circuit may include an application specific integrated circuit (ASIC), an electronic circuit, a processor (e.g., a shared processor, a dedicated processor, or a group processor) and memory for executing one or more software or firmware programs, combined logic circuits, and / or other suitable components that support the described functionality.

[0190] Therefore, the units of each example described in the embodiments of this application can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0191] Figure 10 It is a structural schematic diagram of a vehicle provided in an embodiment of the present application.

[0192] For example, Figure 10As shown, the vehicle 1000 includes: a memory 1010 and a processor 1020, wherein the memory 1010 stores an executable program code 1030, and the processor 1020 is used to call and execute the executable program code 1030 to execute a system-level chip control method and / or a system-level chip monitoring method.

[0193] Exemplarily, the memory 1010 can be used to store the control method of the system-level chip provided in the embodiments of the present application, and / or the related programs of the monitoring method of the system-level chip; the processor 1020 can call the control method of the system-level chip, and / or the related programs of the monitoring method of the system-level chip stored in the memory 1010 to execute the control method of the system-level chip, and / or the monitoring method of the system-level chip in the embodiments of the present application; for example, in response to the startup instruction of the system-level chip, control the startup of the read-only memory; when it is detected that the sampling of the read-only memory is completed, synchronize the current state of the read-only memory to the external device through the target interface.

[0194] In this embodiment, the device can be divided into functional modules based on the above-described method examples. For example, each functional module can be mapped to a specific functional module, or two or more functions can be integrated into a single processing module. The integrated module can be implemented in hardware. It should be noted that the module division in this embodiment is illustrative and represents only a logical functional division. In actual implementation, other division methods may be used.

[0195] In the case of dividing the functional modules into corresponding functional modules, the device may further include a control module, a detection module, a monitoring module, a determination module, an interaction module, etc. It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0196] It should be understood that the device provided in this embodiment is used to execute the above-mentioned system-on-chip control method and / or system-on-chip monitoring method, and thus can achieve the same effect as the above-mentioned implementation method.

[0197] In the case of an integrated unit, the device may include a processing module and a storage module. When the device is used in a vehicle, the processing module may be used to control and manage the vehicle's movements, while the storage module may be used to support the vehicle's execution of relevant program codes.

[0198] The processing module may be a processor or controller that implements or executes the various exemplary logic blocks, modules, and circuits described in conjunction with the present disclosure. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processing (DSP) and a microprocessor, and the storage module may be a memory.

[0199] In addition, the device provided in the embodiments of the present application can specifically be a chip, component or module, and the chip may include a connected processor and memory; wherein the memory is used to store instructions, and when the processor calls and executes the instructions, the chip can execute a system-level chip control method provided in the above embodiments, and / or a system-level chip monitoring method.

[0200] The present application also provides a computer-readable storage medium, which stores computer program code. When the computer program code runs on a computer, the computer executes the above-mentioned related method steps to implement a system-level chip control method and / or a system-level chip monitoring method provided in the above-mentioned embodiment. Among them, computer-readable storage media may include, but are not limited to, any type of disk, including floppy disks, optical disks, Digital Video Discs (DVDs), Compact Disc Read-Only Memory (CD-ROMs), microdrives and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAMs), Erasable Programmable Read-Only Memory (EPROMs), Electrically Erasable Programmable Read-Only Memory (EEPROMs), Dynamic Random Access Memory (DRAMs), Video Random Access Memory (VRAMs), flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs), or any type of medium or device suitable for storing instructions and / or data.

[0201] The present application also provides a computer program product, which, when executed on a computer, enables the computer to execute the above-mentioned related steps to implement a system-on-chip control method and / or a system-on-chip monitoring method provided in the above-mentioned embodiment.

[0202] Among them, the vehicle, computer-readable storage medium, computer program product or chip provided in this application are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0203] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0204] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0205] The above content is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A control method for a system-on-chip, characterized in that: The read-only memory in the system-on-chip is provided with a target interface, and the method comprises: In response to a startup instruction of the system-on-chip, controlling the read-only memory to start up; When it is detected that the sampling of the read-only memory is completed, the current state of the read-only memory is synchronized to an external device through the target interface.

2. The method according to claim 1, characterized in that The current state is sampling completion or startup completion, and synchronizing the current state of the read-only memory to an external device through the target interface includes: A sampling completion signal or a start completion signal is sent to the external device through the target interface, so that the external device and the system-on-chip perform data exchange.

3. The method according to claim 1, characterized in that The target interface includes a first interface and a second interface, and when it is detected that the read-only memory sampling is completed, synchronizing the current state of the read-only memory to an external device through the target interface includes: When it is detected that the sampling of the read-only memory is completed, sending a sampling completion signal to the external device through the first interface; When it is detected that the booting of the read-only memory is completed, a booting completion signal is sent to the external device through the second interface.

4. The method according to claim 3, characterized in that When detecting that the read-only memory is started up, sending a start-up completion signal to the external device through the second interface includes: When detecting that the read-only memory is started up, determining whether the interactive data sent by the external device is received; When the interactive data sent by the external device is not received, the startup completion signal is sent to the external device through the second interface.

5. The method according to any one of claims 1 to 4, characterized in that After synchronizing the current state of the read-only memory to an external device through the target interface, the method further includes: When it is detected that the system-on-chip is in a boot loading state, the target interface is reused for data configuration.

6. A system-on-chip monitoring method, characterized in that: The read-only memory in the system-on-chip is provided with a target interface, and the method comprises: During the booting process of the read-only memory, monitoring a current state of the read-only memory based on the target interface; Based on the current state, determining whether the system-on-chip is successfully started; When the system-on-chip is successfully started, data interaction is performed with the system-on-chip based on the target interface.

7. The method according to claim 6, characterized in that The determining, based on the current state, whether the system-on-chip is successfully started includes: When the current status indicates that the read-only memory is started up successfully, it is determined that the system-on-chip is started up successfully.

8. The method according to claim 7, characterized in that When the current status indicates that the read-only memory is started up successfully, determining that the system-on-chip is started up successfully includes: When the current state indicates that the read-only memory startup is complete, determining a target duration for completing the read-only memory startup; When the target duration is greater than a preset duration, determining that the system-on-chip startup has timed out; When the target duration is less than or equal to the preset duration, it is determined that the system-on-chip is successfully started.

9. A system-on-chip control system, characterized in that: Including system-level chips and external devices; Wherein, the system-level chip is used to execute the control method of the system-level chip according to any one of claims 1 to 5; The external device is used to execute the system-on-chip monitoring method according to any one of claims 6 to 8.

10. A vehicle, characterized in that: The vehicle comprises: a memory for storing executable program code; A processor, configured to call and run the executable program code from the memory so that the vehicle executes the control method of the system-on-chip as described in any one of claims 1 to 5, and / or executes the monitoring method of the system-on-chip as described in any one of claims 6 to 8.

Images