High-stability KVM switcher based on FPGA architecture

Abstract

The invention discloses a high-stability KVM (Keyboard Video Mouse) switcher based on an FPGA (Field Programmable Gate Array) architecture, which relates to the technical field of switchers and comprises a main control module, a display interface module, a signal switching module, an EDID (Extended Display Identifier) processing module, a power management module and a communication control module, according to the main control module, a Xilinx Zynq-7020 FPGA chip is adopted as a control core, functional module programming is achieved through a hardware description language, and IP cores with different functions are supported to be dynamically loaded. The display interface module is connected with the main control module, adopts a TI TPS65987DP controller to realize a full-link native DP1.4a interface, and comprises a dual-channel HBR3 high-speed transmission link and a self-adaptive equalizer; the signal switching module is connected with the display interface module, and adopts an Analog Devices ADG7336 switching chip to realize the switching of a plurality of paths of signals; the EDID processing module is connected with the main control module and adopts a self-developed EDID analysis engine to realize an intelligent EDID self-learning function; and the power management module is connected with the main control module, and 9-36V DC wide voltage input is realized by adopting a TI TPS5430 power chip.

Description

Technical Field

[0001] The present invention relates to the technical field of switches, and in particular to a high-stability KVM switch based on FPGA architecture. Background Art

[0002] A KVM switch is a technology that allows users to control multiple computers using a single keyboard, mouse, and monitor. Therefore, how to use advanced technologies to improve the intelligence and security of switches has become one of the most pressing issues to be addressed.

[0003] In the field of switches, most KVM switches on the market currently use ASIC chip + MCU control solutions. The expansion of architectural functions relies on the technical support of the original manufacturer, making it difficult to quickly respond to the needs of domestic transformation such as air traffic control systems. In addition, existing mainstream products use HDMI to DP conversion modules to achieve interface adaptation. During the conversion process, they are easily affected by electromagnetic interference, resulting in signal delays or screen tearing. At the same time, the resolution adaptive support for new displays such as 4K is weak and requires manual configuration. It cannot automatically identify EDID parameters in multi-brand mixed access scenarios. The operation is highly complex and display anomalies are prone to occur. Summary of the Invention

[0004] In view of the above existing problems, the present invention is proposed.

[0005] Therefore, the present invention provides a high-stability KVM switch based on FPGA architecture to solve the problem that existing mainstream products achieve interface adaptation through HDMI to DP conversion module, which is easily affected by electromagnetic interference during the conversion process, resulting in signal delay or screen tearing. At the same time, the resolution adaptive support for new displays such as 4K is weak, and manual configuration is required. It cannot automatically identify EDID parameters in multi-brand mixed access scenarios, the operation is highly complex and display abnormalities are prone to occur.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a high-stability KVM switch based on an FPGA architecture, comprising:

[0008] Main control module, display interface module, signal switching module, EDID processing module, power management module, communication control module;

[0009] The main control module uses the Xilinx Zynq-7020 FPGA chip as the control core, realizes the programmability of functional modules through hardware description language, and supports dynamic loading of different functional IP cores;

[0010] The display interface module is connected to the main control module and uses the TITPS65987 DP controller to implement a full-link native DP1.4a interface, including a dual-channel HBR3 high-speed transmission link and an adaptive equalizer;

[0011] The signal switching module is connected to the display interface module and uses the Analog Devices ADG7336 switching chip to achieve multi-channel signal switching;

[0012] The EDID processing module is connected to the main control module and uses a self-developed EDID parsing engine to realize intelligent EDID self-learning function;

[0013] The power management module is connected to the main control module and uses the TITPS5430 power chip to achieve a 9-36V DC wide voltage input and has overvoltage and overcurrent protection functions;

[0014] The communication control module is connected to the main control module and supports four control modes: RS232 serial port, network port, front panel buttons and keyboard hot keys to achieve seamless switching of KVM signals.

[0015] As a preferred solution of the high-stability KVM switch based on FPGA architecture described in the present invention, the FPGA chip of the main control module directly drives the DP transmitter / receiver module through the GTX high-speed serial interface, avoiding the use of an intermediate conversion chip;

[0016] The circuit board of the main control module adopts a 6-layer PCB design, wherein:

[0017] Layers 1 and 6 are signal layers, where key high-speed signal lines are arranged;

[0018] Layers 2 and 5 are power supply layers, providing stable power distribution;

[0019] The third and fourth layers are ground layers, forming a complete electromagnetic shield;

[0020] The DP signal line adopts differential pair wiring, with impedance controlled to 100Ω±10%, line width of 4mil and line spacing of 8mil;

[0021] A ground guard ring with a width of ≥20 mil is set around the key signal lines. The guard ring is connected to the ground layer through a via array with a via spacing of ≤50 mil.

[0022] As a preferred solution of the high-stability KVM switch based on FPGA architecture described in the present invention, the hardware circuit of the display interface module includes:

[0023] Adopt TVS diode array, an ESD protection device that meets the IEC 61000-4-2 Level 4 standard;

[0024] Supports 0-12dB programmable equalization compensation, which can compensate for the signal attenuation of cables over 15 meters;

[0025] Clock data recovery circuit with jitter tolerance ≤ 0.15UI;

[0026] The display interface module supports HBR3 transmission rate, single channel rate 8.1Gbps, four channel aggregate bandwidth 32.4Gbps, and its built-in EDID hardware cache module adopts I 2 C interface EEPROM, capacity 256 bytes, supports VESA EDID 2.0 standard, the display interface module uses forward error correction FEC technology to achieve a bit error rate of ≤ 10 -12 signal transmission.

[0027] As a preferred solution of the high-stability KVM switch based on FPGA architecture described in the present invention, the signal switching module implements multi-channel signal switching, and the specific steps are as follows:

[0028] Adopt 4:1 analog switch matrix for video signal switching, and support 4-channel DP1.4 input and 2-channel DP1.4 output;

[0029] Adopt USB3.0 dedicated switching chip for USB signal switching, and support 4-way USB3.0 input and 1-way USB3.0 output;

[0030] Use low-noise audio switches for audio signal switching, and support 4 line inputs and 1 line output;

[0031] Use full-duplex RS232 switch to switch RS232 signals, and support 4-way DB9 interface input and 1-way DB9 interface output;

[0032] The signal switching module has a switching delay of ≤100μs, supports hot plug detection function, has a detection response time of ≤10ms, and has a crosstalk suppression of -50dB@1GHz and an isolation of ≥60dB.

[0033] As a preferred solution of the high-stability KVM switch based on FPGA architecture described in the present invention, the three-level adaptive mechanism of the EDID processing module specifically includes:

[0034] The first level is the EDID capture stage, which is used to automatically capture the complete EDID data of the display, including 128 bytes of basic data and 128 bytes of extended data. CRC check is used to ensure data integrity, and erroneous data is automatically retransmitted.

[0035] The second stage is the parameter calculation stage, which calculates the optimal display parameters based on the PAP pixel alignment algorithm, including: resolution matching score, refresh rate compatibility analysis and color space conversion matrix;

[0036] The third level is the configuration and application stage, which supports automatic adaptation of more than 200 resolutions, covering a range from 1024×768 to 8192×4320, with a learning cycle of ≤200ms / new device, and 1000 sets of configuration information can be saved.

[0037] As a preferred solution of the high-stability KVM switch based on FPGA architecture of the present invention, wherein: the power management module realizes 9-36V DC wide voltage input, the specific steps are as follows:

[0038] Use voltage sampling circuit to monitor dual AC inputs in real time to obtain power status data;

[0039] The PFC correction circuit is used to compensate the power factor of the input AC power to obtain DC power with a ripple factor of ≤5%;

[0040] The power management module also includes a DC-DC step-down module for performing hierarchical conversion on the 36V intermediate voltage and obtaining +12V / +5V / +3.3V system voltages;

[0041] The overvoltage protection circuit compares the output voltage threshold and automatically triggers the protection action when it exceeds 120% of the nominal value;

[0042] The PID algorithm is used to perform closed-loop control of the cooling fan speed to achieve a cooling effect that matches the temperature curve.

[0043] As a preferred solution of the high-stability KVM switch based on FPGA architecture of the present invention, the four operation modes of the keyboard hotkey of the communication control module are specifically implemented as follows:

[0044] In Scroll mode, quickly press "Scroll", "Scroll", "1" in sequence to switch to signal source 1, and quickly press "Scroll", "Scroll", "→" in sequence to switch to the next signal source;

[0045] In Caps mode, quickly press "Caps", "Caps", "2" in sequence to switch to signal source 2, and quickly press "Caps", "Caps", "←" in sequence to switch to the previous signal source;

[0046] In Num mode, quickly press "Num", "Num", and "3" in sequence to switch to signal source 3;

[0047] And Ctrl+Shift mode, press "Ctrl"+"Shift"+"4" at the same time to switch to signal source 4;

[0048] The above modes can be switched between each other through specific key combinations, and the switching response time is ≤50ms.

[0049] As a preferred solution of the high-stability KVM switch based on FPGA architecture described in the present invention, the PID algorithm is used to perform closed-loop control on the speed of the cooling fan, and the specific steps are as follows:

[0050] The temperature sampling circuit is used to collect the surface temperature of the FPGA chip in real time to obtain the current temperature value;

[0051] A subtractor is used to perform a difference operation between the set temperature threshold and the current temperature value to obtain the instantaneous temperature error e(t);

[0052] Set the proportional coefficient, use the multiplier to perform proportional gain amplification on the temperature error e(t) to obtain the proportional term output, and set the integral coefficient, use the accumulator to perform integration operation on the historical temperature error to obtain the integral term output;

[0053] A differential circuit is used to perform differential operation on the temperature change rate to obtain the differential output Dout, which is expressed as:

[0054]

[0055] Where Kd is the differential coefficient, e(t) is the instantaneous temperature error;

[0056] The three outputs are superimposed to obtain the final control quantity.

[0057] As a preferred solution of the high-stability KVM switch based on FPGA architecture described in the present invention, wherein: the EDID self-learning algorithm is used to adaptively configure the display parameters, and the specific steps are as follows:

[0058] Adopt I 2 The C bus reads data from the EDID memory of the display to obtain the original EDID data;

[0059] Verify the integrity of the read EDID data and remove abnormal data frames with a bit error rate greater than 5%;

[0060] And analyze the valid EDID data to calculate the optimal display parameters The expression is:

[0061]

[0062] Among them, R is the resolution set supported by the display, Stiming Score the timing matching, C color is the color space compatibility score, w1 and w2 are weight coefficients.

[0063] As a preferred solution of the high-stability KVM switch based on FPGA architecture described in the present invention, wherein: the redundant power supply switching circuit is used to provide fault protection for the dual input power supplies, and the specific steps are as follows:

[0064] A voltage comparator is used to monitor the input voltage of the main power supply and the backup power supply in real time to obtain a voltage status flag signal;

[0065] When the main power voltage is lower than 180VAC, a switching control signal is generated;

[0066] Use solid-state relays to quickly switch the backup power path, with a switching delay of ≤10ms, expressed as:

[0067] t switch =t detect +t isolate +t connect ;

[0068] Among them, t detect is the fault detection time, t isolate is the fault isolation time, t connect The time to establish a new path, t switch Indicates the time taken for the entire process from when the main power supply fails to when the backup power supply is fully connected.

[0069] The beneficial effects of the present invention are as follows: by adopting the Xilinx Zynq-7020 FPGA chip as the control core and using the hardware description language to realize the programmability of functional modules, it supports dynamic loading of different functional IP cores, and realizes a highly flexible and scalable system architecture, so that the KVM switch can quickly respond to technology upgrade needs, directly drive the DP transmit / receive module through the GTX high-speed serial interface, avoid the use of intermediate conversion chips, and reduce the risk of signal loss. The 6-layer design of the circuit board effectively reduces electromagnetic interference and improves signal integrity and stability. By adopting the TVS diode array to meet the ESD protection device of IEC61000-4-2 Level 4 standard, support 0-12dB programmable equalization compensation and jitter tolerance ≤0.15UI clock data recovery circuit, the anti-interference ability and signal quality of the display interface module are significantly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0071] Figure 1 This is a module connection diagram of the high-stability KVM switch based on FPGA architecture in Example 1.

[0072] Figure 2 This is a flow chart of capturing EDID in Example 1.

[0073] Figure 3 This is a flow chart of EDID processing in Example 1.

[0074] Figure 4 Schematic diagram of the video processing process in Example 1. DETAILED DESCRIPTION

[0075] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0076] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0077] Secondly, the term "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in various places throughout this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive of other embodiments.

[0078] Example 1, with reference to Figure 1 - Figure 4 , which is the first embodiment of the present invention, provides a high-stability KVM switch based on FPGA architecture, comprising:

[0079] Main control module, display interface module, signal switching module, EDID processing module, power management module, communication control module;

[0080] The main control module uses the Xilinx Zynq-7020 FPGA chip as the control core, realizes the programmability of functional modules through hardware description language, and supports dynamic loading of different functional IP cores;

[0081] Furthermore, the FPGA chip of the main control module directly drives the DP transmit / receive module through the GTX high-speed serial interface, avoiding the use of intermediate conversion chips;

[0082] The main control module's circuit board adopts a 6-layer PCB design, including:

[0083] Layers 1 and 6 are signal layers, where key high-speed signal lines are arranged;

[0084] Layers 2 and 5 are power supply layers, providing stable power distribution;

[0085] The third and fourth layers are ground layers, forming a complete electromagnetic shield;

[0086] The DP signal line adopts differential pair wiring, with impedance control of 100Ω±10%, line width of 4mil and line spacing of 8mil;

[0087] Set a ground guard ring with a width of ≥20mil around the key signal lines. Connect the guard ring to the ground through a via array with a via spacing of ≤50mil.

[0088] It should be noted that the main control module uses an FPGA chip to directly drive the DP transmit / receive module through the GTX high-speed serial interface, eliminating the intermediate conversion bridge required in the traditional architecture. This not only reduces the system complexity and potential failure points, but also significantly improves the signal transmission efficiency and stability. Combined with a 6-layer PCB design, the high-speed signal lines are arranged on the 1st and 6th layers, and the reasonable layout of the power layer and the ground layer forms a good power distribution network and electromagnetic shielding environment. At the same time, the DP differential pair wiring strictly controls the impedance to 100Ω±10%, and adopts a 4mil line width and 8mil line spacing to ensure the integrity of high-frequency signals; a ground protection ring with a width of ≥20mil is set around the key signal lines and connected to the ground layer through a via array, which further suppresses high-frequency noise interference and improves the system's electromagnetic compatibility and long-term operation reliability.

[0089] The display interface module is connected to the main control module and uses the TITPS65987 DP controller to implement a full-link native DP1.4a interface, including a dual-channel HBR3 high-speed transmission link and an adaptive equalizer;

[0090] Furthermore, the hardware circuit of the display interface module includes:

[0091] Adopt TVS diode array, an ESD protection device that meets the IEC 61000-4-2 Level 4 standard;

[0092] Supports 0-12dB programmable equalization compensation, which can compensate for the signal attenuation of cables over 15 meters;

[0093] Clock data recovery circuit with jitter tolerance ≤ 0.15UI;

[0094] The display interface module supports HBR3 transmission rate, single channel rate 8.1Gbps, four channel aggregate bandwidth 32.4Gbps, and its built-in EDID hardware cache module adopts I 2 C interface EEPROM, capacity 256 bytes, supports VESA EDID 2.0 standard, the display interface module uses forward error correction FEC technology to achieve a bit error rate of ≤ 10 -12 signal transmission;

[0095] It should be noted that the display interface module uses the TI TPS65987 DP controller to implement a full-link native DP1.4a interface, supports dual-channel HBR3 transmission mode, a single-channel rate of 8.1Gbps, and a four-channel aggregate bandwidth of 32.4Gbps, which can meet the needs of 8K ultra-high-definition video transmission. The module integrates a TVS diode array and has IEC 61000-4-2 Level 4 electrostatic protection capability, which effectively improves the anti-interference performance of the equipment in complex electromagnetic environments; supports 0-12dB programmable equalization compensation function, which can compensate for the signal attenuation caused by cables over 15 meters long, thereby extending the transmission distance and applicable scenarios; the clock data recovery circuit with a jitter tolerance of ≤0.15UI ensures stability under high-speed transmission; built-in I 2 The C-port EEPROM is used for EDID buffering, with a capacity of up to 256 bytes, and is fully compatible with the VESA EDID2.0 standard. It also uses forward error correction (FEC) technology to reduce the bit error rate to ≤10 -12 , significantly improving image quality and suitable for application scenarios with high-precision visual requirements.

[0096] The signal switching module is connected to the display interface module and uses the Analog Devices ADG7336 switching chip to achieve multi-channel signal switching;

[0097] Furthermore, the signal switching module implements multi-channel signal switching. The specific steps are as follows:

[0098] Adopt 4:1 analog switch matrix for video signal switching, and support 4-channel DP1.4 input and 2-channel DP1.4 output;

[0099] Adopt USB3.0 dedicated switching chip for USB signal switching, and support 4-way USB3.0 input and 1-way USB3.0 output;

[0100] Use low-noise audio switches for audio signal switching, and support 4 line inputs and 1 line output;

[0101] Use full-duplex RS232 switch to switch RS232 signals, and support 4-way DB9 interface input and 1-way DB9 interface output;

[0102] The switching delay of the signal switching module is ≤100μs, supports hot plug detection function, detection response time is ≤10ms, and crosstalk suppression reaches -50dB@1GHz, and isolation is ≥60dB;

[0103] A redundant power switching circuit is used to protect the dual input power supplies from failures. The specific steps are as follows:

[0104] A voltage comparator is used to monitor the input voltage of the main power supply and the backup power supply in real time to obtain a voltage status flag signal;

[0105] When the main power voltage is lower than 180VAC, a switching control signal is generated;

[0106] Use solid-state relays to quickly switch the backup power path, with a switching delay of ≤10ms, expressed as:

[0107] t switch =t detect +t isolate +t connect ;

[0108] Among them, t detect is the fault detection time, t isolate is the fault isolation time, t connect The time to establish a new path, t switch Indicates the time taken for the entire process from the occurrence of a main power failure to the full connection of the backup power supply;

[0109] It should be noted that the signal switching module utilizes the Analog Devices ADG7336 switching chip as its core, building a multi-channel analog switch matrix to enable switching of various peripheral signals, including DP1.4 video signals. Specifically, the module supports four DP1.4 inputs and two outputs, four USB 3.0 inputs and one output, four audio inputs and one output, and four RS232 DB9 interface inputs and one output, meeting the needs of centralized control of multiple hosts and peripherals. Its switching latency is ≤100μs, ensuring rapid response. Its hot-swap detection response time is ≤10ms, ensuring that users can complete device replacement without interrupting other operations. Crosstalk suppression reaches -50dB at 1GHz, and isolation is ≥60dB, significantly reducing mutual interference between signals. Combined with a redundant power switching circuit, when the main power supply voltage falls below 180VAC, a voltage comparator generates a switching control signal, prompting a solid-state relay to quickly activate the backup power path, with a switching latency of ≤10ms.

[0110] The EDID processing module is connected to the main control module and uses a self-developed EDID parsing engine to achieve intelligent EDID self-learning function;

[0111] Furthermore, the three-level adaptive mechanism of the EDID processing module specifically includes:

[0112] The first level is the EDID capture stage, which is used to automatically capture the complete EDID data of the display, including 128 bytes of basic data and 128 bytes of extended data. CRC check is used to ensure data integrity, and erroneous data is automatically retransmitted.

[0113] The second stage is the parameter calculation stage, which calculates the optimal display parameters based on the PAP pixel alignment algorithm, including: resolution matching score, refresh rate compatibility analysis and color space conversion matrix;

[0114] The third level is the configuration and application stage, which supports automatic adaptation of more than 200 resolutions, covering a range from 1024×768 to 8192×4320, with a learning cycle of ≤200ms / new device, and can save 1000 sets of configuration information;

[0115] Adopt EDID self-learning algorithm to adaptively configure display parameters. The specific steps are as follows:

[0116] Adopt I 2 The C bus reads data from the EDID memory of the display to obtain the original EDID data;

[0117] Verify the integrity of the read EDID data and remove abnormal data frames with a bit error rate greater than 5%;

[0118] And analyze the valid EDID data to calculate the optimal display parameters The expression is:

[0119]

[0120] Among them, R is the resolution set supported by the display, S timing Score the timing matching, C color is the color space compatibility score, w1 and w2 are weight coefficients;

[0121] It should be noted that the EDID processing module adopts a self-developed parsing engine to realize intelligent EDID self-learning function, which includes a three-level adaptive mechanism. The first level automatically captures the complete EDID data of the display (basic + extended 256 bytes in total), and uses CRC check to ensure data integrity, and automatically retransmits error frames to prevent configuration failure due to communication errors; the second level calculates parameters based on the PAP pixel alignment algorithm, and comprehensively integrates resolution matching score, refresh rate compatibility analysis and color space conversion matrix to achieve precise adaptation; the third level configuration application stage supports automatic matching of more than 200 resolutions, covering a wide range from 1024×768 to 8192×4320, with a learning cycle of ≤200ms / new device, and configuration information can be saved up to 1000 groups, which greatly improves device compatibility and deployment efficiency. In addition, the EDID self-learning algorithm is used to realize I 2 C bus reading, abnormal data elimination, and optimal display parameter analysis.

[0122] The power management module is connected to the main control module and uses the TITPS5430 power chip to achieve a wide voltage input of 9 to 36V DC and has overvoltage and overcurrent protection functions;

[0123] Furthermore, the power management module implements a wide voltage input range of 9 to 36V DC. The specific steps are as follows:

[0124] Use voltage sampling circuit to monitor dual AC inputs in real time to obtain power status data;

[0125] The PFC correction circuit is used to compensate the power factor of the input AC power to obtain DC power with a ripple factor of ≤5%;

[0126] The power management module also includes a DC-DC step-down module for performing hierarchical conversion on the 36V intermediate voltage to obtain +12V / +5V / +3.3V system voltages;

[0127] The overvoltage protection circuit compares the output voltage threshold and automatically triggers the protection action when it exceeds 120% of the nominal value;

[0128] The PID algorithm is used to perform closed-loop control of the cooling fan speed to achieve a cooling effect that matches the temperature curve;

[0129] The temperature sampling circuit is used to collect the surface temperature of the FPGA chip in real time to obtain the current temperature value;

[0130] A subtractor is used to perform a difference operation between the set temperature threshold and the current temperature value to obtain the instantaneous temperature error e(t);

[0131] Set the proportional coefficient, use the multiplier to perform proportional gain amplification on the temperature error e(t) to obtain the proportional term output, and set the integral coefficient, use the accumulator to perform integration operation on the historical temperature error to obtain the integral term output;

[0132] A differential circuit is used to perform differential operation on the temperature change rate to obtain the differential output Dout, which is expressed as:

[0133]

[0134] Where Kd is the differential coefficient, e(t) is the instantaneous temperature error;

[0135] The three outputs are superimposed to obtain the final control quantity;

[0136] It should be noted that the power management module uses the TITPS5430 power chip, which supports a wide voltage input of 9 to 36V DC and is suitable for various power supply environments. It is especially suitable for occasions with large voltage fluctuations such as industrial sites or vehicles. The voltage sampling circuit monitors the dual AC input status in real time and combines with the PFC power factor correction circuit to make the input power ripple coefficient ≤5%, thereby improving the energy efficiency of the whole machine. The DC-DC step-down module converts the intermediate voltage into +12V / +5V / +3.3V system voltage to meet the power supply requirements of various functional modules. The overvoltage protection circuit compares the output voltage threshold and immediately triggers the protection action once it exceeds 120% of the nominal value to avoid hardware damage. The PID closed-loop control algorithm is introduced for heat dissipation. The temperature sampling circuit collects the FPGA surface temperature in real time and obtains the final control quantity through the superposition of proportional, integral and differential operations to accurately adjust the fan speed to achieve the best balance between temperature control and energy consumption, which not only extends the equipment life but also reduces the noise impact.

[0137] The communication control module is connected to the main control module and supports four control modes: RS232 serial port, network port, front panel buttons and keyboard hot keys, realizing seamless switching of KVM signals.

[0138] Furthermore, the four operation modes of the keyboard hotkeys of the communication control module are specifically implemented as follows:

[0139] In Scroll mode, quickly press "Scroll", "Scroll", "1" in sequence to switch to signal source 1, and quickly press "Scroll", "Scroll", "→" in sequence to switch to the next signal source;

[0140] In Caps mode, quickly press "Caps", "Caps", "2" in sequence to switch to signal source 2, and quickly press "Caps", "Caps", "←" in sequence to switch to the previous signal source;

[0141] In Num mode, quickly press "Num", "Num", and "3" in sequence to switch to signal source 3;

[0142] And Ctrl+Shift mode, press "Ctrl"+"Shift"+"4" at the same time to switch to signal source 4;

[0143] The above modes can be switched between each other through specific key combinations, and the switching response time is ≤50ms;

[0144] It should be noted that the communication control module provides four control methods: RS232 serial port, network port, front panel buttons, and keyboard hotkeys. These fully take into account local and remote operation requirements and enhance the flexibility of human-computer interaction. Keyboard hotkeys support four operation modes: Scroll, Caps, Num, and Ctrl+Shift. Users can quickly switch signal sources through specific combinations. For example, pressing "ScrollScroll 1" in sequence switches to signal source 1, and pressing "ScrollScroll→" switches to the previous signal source. Similarly, Caps and Num modes support digital number selection and direction switching, respectively; Ctrl+Shift mode implements shortcut key locking and advanced switching functions. The response time for all hotkey switches is ≤50ms, ensuring smooth and delay-free operation. Switching between modes is supported through specific key combinations, greatly enhancing operational convenience and system controllability. This makes it suitable for professional applications that require frequent switching of signal sources.

[0145] In summary, the present invention adopts the Xilinx Zynq-7020 FPGA chip as the control core, uses hardware description language to realize programmability of functional modules, supports dynamic loading of different functional IP cores, and realizes a highly flexible and scalable system architecture, so that the KVM switch can quickly respond to technology upgrade needs, directly drives the DP transmit / receive module through the GTX high-speed serial interface, avoids the use of intermediate conversion chips, and reduces the risk of signal loss. The 6-layer design of the circuit board effectively reduces electromagnetic interference and improves signal integrity and stability. By adopting TVS diode arrays to meet the ESD protection device of IEC 61000-4-2 Level 4 standard, supporting 0-12dB programmable equalization compensation and a clock data recovery circuit with a jitter tolerance of ≤0.15UI, the anti-interference ability and signal quality of the display interface module are significantly improved.

[0146] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A high-stability KVM switch based on FPGA architecture, characterized by: include: Main control module, display interface module, signal switching module, EDID processing module, power management module, communication control module; The main control module uses the Xilinx Zynq-7020 FPGA chip as the control core, realizes the programmability of functional modules through hardware description language, and supports dynamic loading of different functional IP cores; The display interface module is connected to the main control module and uses the TITPS65987 DP controller to implement a full-link native DP1.4a interface, including a dual-channel HBR3 high-speed transmission link and an adaptive equalizer; The signal switching module is connected to the display interface module and uses the Analog Devices ADG7336 switching chip to achieve multi-channel signal switching; The EDID processing module is connected to the main control module and uses a self-developed EDID parsing engine to realize intelligent EDID self-learning function; The power management module is connected to the main control module and uses the TITPS5430 power chip to achieve a 9-36V DC wide voltage input and has overvoltage and overcurrent protection functions; The communication control module is connected to the main control module and supports four control modes: RS232 serial port, network port, front panel buttons and keyboard hot keys to achieve seamless switching of KVM signals.

2. The high-stability KVM switch based on FPGA architecture according to claim 1, characterized in that: The FPGA chip of the main control module directly drives the DP transmit / receive module through the GTX high-speed serial interface, avoiding the use of an intermediate conversion chip; The circuit board of the main control module adopts a 6-layer PCB design, wherein: Layers 1 and 6 are signal layers, where key high-speed signal lines are arranged; Layers 2 and 5 are power supply layers, providing stable power distribution; The third and fourth layers are ground layers, forming a complete electromagnetic shield; The DP signal line adopts differential pair wiring, with impedance controlled to 100Ω±10%, line width of 4mil and line spacing of 8mil; A ground guard ring with a width of ≥20 mil is set around the key signal lines. The guard ring is connected to the ground layer through a via array with a via spacing of ≤50 mil.

3. The high-stability KVM switch based on FPGA architecture as claimed in claim 2, characterized in that: The hardware circuit of the display interface module includes: Adopt TVS diode array, an ESD protection device that meets the IEC 61000-4-2 Level 4 standard; Supports 0-12dB programmable equalization compensation, which can compensate for the signal attenuation of cables over 15 meters; Clock data recovery circuit with jitter tolerance ≤ 0.15UI; The display interface module supports HBR3 transmission rate, single channel rate 8.1Gbps, four channel aggregate bandwidth 32.4Gbps, and its built-in EDID hardware cache module adopts I 2 C interface EEPROM, capacity 256 bytes, supports VESA EDID 2.0 standard, the display interface module uses forward error correction FEC technology to achieve a bit error rate of ≤ 10 -12 signal transmission.

4. The high-stability KVM switch based on FPGA architecture as claimed in claim 3, characterized in that: The signal switching module implements multi-channel signal switching, and the specific steps are as follows: Adopt 4:1 analog switch matrix for video signal switching, and support 4-channel DP1.4 input and 2-channel DP1.4 output; Adopt USB3.0 dedicated switching chip for USB signal switching, and support 4-way USB3.0 input and 1-way USB3.0 output; Use low-noise audio switches for audio signal switching, and support 4 line inputs and 1 line output; Use full-duplex RS232 switch to switch RS232 signals, and support 4-way DB9 interface input and 1-way DB9 interface output; The signal switching module has a switching delay of ≤100μs, supports hot plug detection function, has a detection response time of ≤10ms, and has a crosstalk suppression of -50dB@1GHz and an isolation of ≥60dB.

5. The high-stability KVM switch based on FPGA architecture as claimed in claim 4, characterized in that: The three-level adaptive mechanism of the EDID processing module specifically includes: The first level is the EDID capture stage, which is used to automatically capture the complete EDID data of the display, including 128 bytes of basic data and 128 bytes of extended data. CRC check is used to ensure data integrity, and erroneous data is automatically retransmitted. The second stage is the parameter calculation stage, which calculates the optimal display parameters based on the PAP pixel alignment algorithm, including: resolution matching score, refresh rate compatibility analysis and color space conversion matrix; The third level is the configuration and application stage, which supports automatic adaptation of more than 200 resolutions, covering a range from 1024×768 to 8192×4320, with a learning cycle of ≤200ms / new device, and 1000 sets of configuration information can be saved.

6. The high-stability KVM switch based on FPGA architecture according to claim 5, characterized in that: The power management module realizes 9-36V DC wide voltage input, and the specific steps are as follows: Use voltage sampling circuit to monitor dual AC inputs in real time to obtain power status data; The PFC correction circuit is used to compensate the power factor of the input AC power to obtain DC power with a ripple factor of ≤5%; The power management module also includes a DC-DC step-down module for performing hierarchical conversion on the 36V intermediate voltage and obtaining +12V / +5V / +3.3V system voltages; The overvoltage protection circuit compares the output voltage threshold and automatically triggers the protection action when it exceeds 120% of the nominal value; The PID algorithm is used to perform closed-loop control of the cooling fan speed to achieve a cooling effect that matches the temperature curve.

7. The high-stability KVM switch based on FPGA architecture according to claim 6, characterized in that: The four operation modes of the keyboard hotkeys of the communication control module are specifically implemented as follows: In Scroll mode, quickly press "Scroll", "Scroll", "1" in sequence to switch to signal source 1, and quickly press "Scroll", "Scroll", "→" in sequence to switch to the next signal source; In Caps mode, quickly press "Caps", "Caps", "2" in sequence to switch to signal source 2, and quickly press "Caps", "Caps", "←" in sequence to switch to the previous signal source; In Num mode, quickly press "Num", "Num", and "3" in sequence to switch to signal source 3; And Ctrl+Shift mode, press "Ctrl"+"Shift"+"4" at the same time to switch to signal source 4; The above modes can be switched between each other through specific key combinations, and the switching response time is ≤50ms.

8. The high-stability KVM switch based on FPGA architecture according to claim 7, characterized in that: The PID algorithm is used to perform closed-loop control on the speed of the cooling fan. The specific steps are as follows: The temperature sampling circuit is used to collect the surface temperature of the FPGA chip in real time to obtain the current temperature value; A subtractor is used to perform a difference operation between the set temperature threshold and the current temperature value to obtain the instantaneous temperature error e(t); Set the proportional coefficient, use the multiplier to perform proportional gain amplification on the temperature error e(t) to obtain the proportional term output, and set the integral coefficient, use the accumulator to perform integration operation on the historical temperature error to obtain the integral term output; A differential circuit is used to perform differential operation on the temperature change rate to obtain the differential output Dout, which is expressed as: Where Kd is the differential coefficient, e(t) is the instantaneous temperature error; The three outputs are superimposed to obtain the final control quantity.

9. The high-stability KVM switch based on FPGA architecture according to claim 8, characterized in that: The EDID self-learning algorithm is used to adaptively configure the display parameters. The specific steps are as follows: Adopt I 2 The C bus reads data from the EDID memory of the display to obtain the original EDID data; Verify the integrity of the read EDID data and remove abnormal data frames with a bit error rate greater than 5%; And analyze the valid EDID data to calculate the optimal display parameters The expression is: Among them, R is the resolution set supported by the display, S timing Score the timing matching, C color is the color space compatibility score, w1 and w2 are weight coefficients.

10. The high-stability KVM switch based on FPGA architecture according to claim 9, characterized in that: The redundant power supply switching circuit is used to provide fault protection for the dual input power supplies. The specific steps are as follows: A voltage comparator is used to monitor the input voltage of the main power supply and the backup power supply in real time to obtain a voltage status flag signal; When the main power voltage is lower than 180VAC, a switching control signal is generated; Use solid-state relays to quickly switch the backup power path, with a switching delay of ≤10ms, expressed as: t switch =t detect +t isolate +t connect ; Among them, t detect is the fault detection time, t isolate is the fault isolation time, t connect The time to establish a new path, t switch Indicates the time taken for the entire process from when the main power supply fails to when the backup power supply is fully connected.

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