Memory error correction method, server system, electronic device and storage medium

Abstract

This application discloses a memory error correction method, server system, electronic device, and storage medium, relating to the field of storage software technology. The method includes: when a memory generates a currently uncorrectable error, based on the evolution law of uncorrectable errors, extracting a set of target historical correctable errors from a historical error record file that match the memory address of the currently uncorrectable error, attempting to correct the set of target historical correctable errors; once the set of target historical correctable errors is successfully processed, the currently uncorrectable error has the opportunity to transform into a derived correctable error, thus changing the root cause or pattern of the currently uncorrectable error. At this time, the memory error handling mechanism can play a role again. Subsequently, the derived correctable errors are corrected, fundamentally resolving the currently uncorrectable error. This solves the problem that when uncorrectable errors occur in memory, multiple errors cannot be effectively corrected, leading to data loss and decreased server system stability.

Description

Technical Field

[0001] This application relates to the field of storage software technology, and in particular to memory error correction methods, server systems, electronic devices, and storage media. Background Technology

[0002] Memory errors are a common problem in the stable operation of servers, mainly divided into correctable errors (CE) and uncorrectable errors (UCE). CE is usually caused by single-bit errors and can be automatically corrected by the ECC (Error Checking and Correcting) mechanism. However, UCE involves multi-bit errors, exceeding the correction capability of ECC, causing its correction capability to fail, leading to data corruption or server system crashes. Summary of the Invention

[0003] This application provides a memory error correction method, a server system, an electronic device, and a storage medium to at least solve the problem in the related art that when uncorrectable memory errors occur, multiple bit errors cannot be effectively corrected, leading to data loss and decreased server system stability.

[0004] This application provides a memory error correction method, comprising: when a current uncorrectable error occurs in memory, extracting a set of target historical correctable errors from a historical error record file that match the memory address parameters of the current uncorrectable error; the current uncorrectable error is derived from the spread of the set of target historical correctable errors; correcting the set of target historical correctable errors; wherein, after the set of target historical correctable errors is corrected, the current uncorrectable error is converted into a derived correctable error; and when the set of target historical correctable errors is corrected, correcting the derived correctable errors converted from the current uncorrectable error to correct the current uncorrectable error.

[0005] This application also provides a server system, including: memory for storing data; a memory controller for reading the data stored in the memory and, in the event of a current uncorrectable error in the memory, sending an uncorrectable error interrupt to a basic input / output system; the basic input / output system for reporting the uncorrectable error interrupt to an operating system; the operating system for starting an exception handler, generating a system interrupt after the exception handler detects the current uncorrectable error, and feeding back the system interrupt to the basic input / output system; the basic input / output system is also used to send a data acquisition instruction to a baseboard management controller to obtain a historical error log file. The system stores historical correctable errors; the baseboard management controller is configured to respond to the data acquisition instruction and feed back a set of target historical correctable errors that match the memory address parameters of the current uncorrectable error in the historical error record file to the basic input / output system; the basic input / output system is further configured to correct the set of target historical correctable errors; wherein, after the set of target historical correctable errors is corrected, the current uncorrectable error is converted into a derived correctable error; when the set of target historical correctable errors is corrected, the derived correctable errors converted from the current uncorrectable error are corrected to correct the current uncorrectable error.

[0006] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described memory error correction methods when executing the computer program.

[0007] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described memory error correction methods.

[0008] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described memory error correction methods.

[0009] This application proposes a method to address the current uncorrectable error in memory. Based on the evolution of uncorrectable errors, a set of target historical correctable errors matching the memory address of the current uncorrectable error are extracted from the historical error log file. This set of target historical correctable errors is used as the starting point for repairing the current uncorrectable error. An attempt is made to correct the set of target historical correctable errors. Once the set of target historical correctable errors is successfully processed, the current uncorrectable error has the opportunity to transform into a derived correctable error, thus changing the root cause or pattern of the current uncorrectable error. At this point, the ECC mechanism can be put into function again. Subsequently, the derived correctable errors are corrected to fundamentally resolve the current uncorrectable errors and restore the originally damaged data. Unlike related hard-handling methods for uncorrectable errors, such as system restart or hardware replacement, this application proposes a feedback process that attempts to correct the current uncorrectable error by using a set of target historical correctable error information that matches the memory address of the current uncorrectable error. This greatly reduces the possibility of data loss, ensures data integrity and server system stability, and demonstrates a new error recovery approach. That is, without changing the hardware configuration or disrupting the existing system operation, it dynamically repairs uncorrectable errors, improves the error tolerance and data recovery capability of the server system, significantly enhances the flexibility and efficiency of error recovery, and solves the problem in related technologies where multiple bit errors cannot be effectively corrected when uncorrectable errors occur in memory, leading to data loss and decreased server system stability. Attached Figure Description

[0010] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is an application environment diagram for a memory error correction method provided in an embodiment of this application.

[0012] Figure 2 This is a flowchart of a memory error correction method provided in an embodiment of this application.

[0013] Figure 3 This is a schematic diagram of the structure of an encoded word provided in an embodiment of this application.

[0014] Figure 4 An example diagram illustrating an advanced ECC method for correcting multi-bit errors in a single token, provided as an embodiment of this application.

[0015] Figure 5This is a schematic diagram illustrating how an advanced ECC cannot correct errors in multiple notations, as provided in an embodiment of this application.

[0016] Figure 6 This is an example diagram illustrating the evolution direction of a memory cell failure as provided in an embodiment of this application.

[0017] Figure 7 This is a structural diagram of a server system provided in an embodiment of this application.

[0018] Figure 8 This is a flowchart illustrating the error correction process of a server system provided in an embodiment of this application.

[0019] Figure 9 This is a diagram illustrating an coded character provided in an embodiment of this application.

[0020] Figure 10 This is a schematic diagram of a memory array provided in an embodiment of this application.

[0021] Figure 11 This is a schematic diagram illustrating a set of target historical correctable errors that match the memory address parameters of a currently uncorrectable error, as provided in an embodiment of this application.

[0022] Figure 12 A flowchart of another memory error correction method provided in an embodiment of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0024] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0025] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] ECC: Error Checking and Correcting, a data protection technology.

[0027] CE: Correctable Error, also known as ECC, refers to errors that can be corrected.

[0028] UCE: Uncorrectable Error, which is an error that is beyond the repair capabilities of ECC.

[0029] DRAM: Dynamic Random Access Memory, is the mainstream memory type.

[0030] CPU: Central Processing Unit, the core of a computer's processing power.

[0031] Chipkill: An ECC technology that can correct errors in a single DRAM device.

[0032] SDDC: Single Device Data Correction, a form of ECC.

[0033] SSC-DSD: Single Symbol Correcting - Double Symbol Detecting, is a type of ECC algorithm.

[0034] Cache Line: The basic unit of data storage in the CPU cache.

[0035] Code Word: The basic unit for data verification and recovery in ECC.

[0036] Cell: Abbreviated as storage unit, it is the basic unit for storing data in DRAM.

[0037] DIMM: Dual In-line Memory Module, a type of memory module.

[0038] Rank: Short for memory class, it refers to a group of independently addressable memory chips on a single DIMM. A DIMM contains one or more Ranks.

[0039] Device: Abbreviated as memory device, it refers to a single memory chip. A Rank contains multiple Devices.

[0040] Bank: Abbreviated as memory bank, it is an independent data storage area in memory. A device is internally divided into multiple banks.

[0041] Column: Also known as a memory column, it is a vertical data channel in a storage array. A Bank is a storage array that contains rows and columns.

[0042] Row: Abbreviated as memory row, it is a horizontal data channel in a storage array.

[0043] SMI: System Management Interrupt, is used to handle system management events.

[0044] SW SMI: Short for Software Triggered System Management Interrupt, it is generated by software instructions and used for special management functions.

[0045] IMC: Integrated Memory Controller, or simply memory controller, is a built-in component of the processor that manages memory access.

[0046] BIOS: Basic Input Output System, which initializes the hardware and loads the operating system.

[0047] BMC: Baseboard Management Controller, which monitors and manages server hardware.

[0048] OS: Operating System, which manages computer hardware and software resources.

[0049] Soft PPR: Soft Post Package Repair, also known as software-based repair, is a method of fixing memory errors at the software level.

[0050] DDR: Double Data Rate, refers to a technology that increases the speed of memory data transfer. DDR is widely used in different versions of dynamic random access memory (DRAM), such as DDR1, DDR2, DDR3, DDR4, and DDR5, to significantly improve system memory performance.

[0051] According to one aspect of the embodiments of this application, a memory error correction method is provided. Optionally, in this embodiment, the above-described memory error correction method may be applied to, but is not limited to, methods such as... Figure 1The hardware environment shown includes terminal device 102 and server 104. Server 104 can be connected to terminal device 102 via a network and can be used to provide services (e.g., application services, etc.) to terminal device 102 or clients installed on terminal device 102. A database can be set up on server 104 or independently of server 104 to provide data storage services for server 104.

[0052] The aforementioned network may include, but is not limited to, at least one of the following: wired network and wireless network. The aforementioned wired network may include, but is not limited to, at least one of the following: wide area network (WAN), metropolitan area network (MAN), and local area network (LAN). The aforementioned wireless network may include, but is not limited to, at least one of the following: Wi-Fi (Wireless Fidelity) and Bluetooth. Terminal device 102 may be, but is not limited to, PC (Personal Computer), mobile phone, tablet computer, etc. Server 104 may be, but is not limited to, a cloud server, server cluster, or other server types.

[0053] The memory error correction method in this application embodiment can be executed by server 104. Figure 2 This is a flowchart illustrating an optional memory error correction method according to an embodiment of this application, as shown below. Figure 2 As shown, the process of this method may include the following steps:

[0054] Step S202: In the case of a current uncorrectable error in memory, extract a set of target historical correctable errors from the historical error record file that match the memory address parameters of the current uncorrectable error; the current uncorrectable error is obtained by the propagation of a set of target historical correctable errors.

[0055] Step S204: Correct a set of target historical correctable errors; wherein, after a set of target historical correctable errors are corrected, the current uncorrectable errors are converted into derived correctable errors.

[0056] Step S206: If a set of target historical correctable errors have been corrected, the derived correctable errors converted from the current uncorrectable errors are corrected in order to correct the current uncorrectable errors.

[0057] This application provides a memory error correction method, applied in the field of server technology, specifically for memory error correction scenarios. Memory errors can be categorized into soft errors and hard errors.

[0058] Soft errors are transient in nature and are often caused by electrical interference in components of the memory subserver system. These interferences can occur in any of many locations within the memory subserver system, including the processor memory controller, processor internal bus, processor cache, processor socket or connector, motherboard bus traces, discrete memory buffer chips (if present), DIMM connectors, or individual DRAM components on DIMMs. Simple soft errors can be corrected through memory retry mechanisms (retrying to read or write data again after error detection), memory inspection mechanisms, etc. A small number of soft errors will not affect the reliability of the server system.

[0059] Hard errors are inherently persistent and cannot be resolved over time or by resetting or restarting the server system. This type of error can be caused by: a) inherent faults (i.e., aging of a single channel on the bus or a single memory cell in a DRAM component), b) failure of the entire device (e.g., connectors, processor, memory buffer (a region used to temporarily store data), or DRAM component), or c) incorrect bus initialization or memory power supply problems. Faults within a DRAM component can include entire device failures, bank (memory storage array) area failures, pin failures, column or cell failures. Hard errors can be caused by physical component damage, ESD (Electrostatic Discharge), electrical overcurrent conditions, excessively high temperatures, or non-standard manufacturing or module assembly of the processor or DRAM.

[0060] The aforementioned soft and hard errors ultimately lead to two types of memory errors: Correctable Errors (CE) and Uncorrectable Errors (UCE). Correctable errors are those that can be detected and corrected by the server platform. These are typically single-bit errors, but depending on CPU and memory configuration, they can also be certain types of multi-bit errors (corrected by Advanced ECC). Correctable errors can be caused by both soft and hard errors and do not disrupt server operation. Uncorrectable errors are multi-bit errors that the server platform cannot correct. These errors can be caused by any combination of soft or hard errors, but are usually caused by multiple hard errors. Memory UCE is a very serious error; because it is uncorrectable, it leads to data loss and typically results in Kernel Panic (a state the system enters when encountering a serious error) and system crashes. However, not all multi-bit errors are uncorrectable; CPUs supporting Advanced ECC can correct certain types of multi-bit errors, depending on the bit error pattern.

[0061] To reduce the occurrence of memory UCEs (Unique Errors Caused by Errors), server systems typically implement Advanced ECC (ECC). Advanced ECC is a Reliability and Analysis System (RAS) feature that provides error correction for single-bit and multi-bit faults of up to 4 bits (half a byte) in memory access. In memory, error checking and correction (ECC) mechanisms are crucial for ensuring data integrity. Memory is the physical medium for storing data, and a cache line is the basic unit of data transfer between memory and the CPU. At a higher level of abstraction, data and ECC bits in a cache line are organized into code words. These code words are the smallest unit of ECC error correction processing, meaning that when performing a read operation, ECC typically reads the entire code word for error detection and correction. A code word contains not only the actual data bits but also additional check bits. The code word is further subdivided into multiple symbols, each typically containing a fixed data bit width (e.g., 8 bits, 32 bits, or more), which are the direct objects of ECC verification and correction in actual operation. This means that whenever the CPU reads data from memory, the ECC checks the validity of the data on a token-by-total basis, performing error detection and potential error correction on the data in each token.

[0062] When used in conjunction with DIMMs based on x4 DRAM devices, Advanced ECC can provide error correction for the entire single DRAM device. This device-wide error correction takes several forms, such as Chipkill and Single Device Data Correction (SDDC). Advanced ECC is a highly complex feature based on Single Symbol Correcting–Double Symbol Detecting (SSC-DSD) Reed-Solomon error correction and detection codes. Simply put, SSC-DSD works by breaking down cache line accesses into "Code Words," which are composed of multi-bit tokens. The size of these tokens may vary depending on the processor architecture. Regardless of whether the token size is 4 bits or 32 bits, the encoding design allows a single token to correct for various combinations of bit errors. In many cases, depending on the SSC-DSD implementation, if all bits in a token are faulty, it can be corrected. SSC-DSD-based error correction codes can potentially improve fault correction and avoidance performance by up to 42 times compared to using SEC-DED ECC alone.

[0063] Taking a 64-byte (512-bit) cache line as an example, if the SSC-DSD algorithm, which uses 8 bits to form a "symbol," is used, then each cache line can be broken down into 64 such symbols. A symbol contains several cells, the exact number depending on the symbol's bit width. For example, an 8-bit symbol will contain 8 cells. Figure 3 This is a schematic diagram of the structure of an encoded word provided in an embodiment of this application, such as... Figure 3 As shown, the encoded word includes multiple 8-bit symbols, and each symbol includes multiple cell units. Figure 4 An example diagram illustrating an advanced ECC method for correcting multi-bit errors in a single token, as provided in this application embodiment, is shown below. Figure 4 As shown, using advanced ECC error correction mechanisms, multiple bit errors within a single token can generally be corrected. Figure 5 A schematic diagram illustrating how advanced ECC cannot correct errors in multiple notations, as provided in this application embodiment, is shown below. Figure 5 As shown, even with the advanced ECC error correction mechanism, errors in multiple tokens still cannot be effectively corrected.

[0064] In this application's embodiments, "currently uncorrectable error" refers to a multi-bit error occurring in memory that cannot be immediately corrected by a memory error handling mechanism (such as ECC). Such multi-bit errors typically lead to data loss or server system instability. The occurrence and development of memory errors are often not instantaneous, but rather involve a process from minor to severe. For example, an early correctable error (perhaps damage to a single storage unit) may gradually worsen if not corrected and handled in a timely manner, affecting more storage units in the same column or nearby, ultimately causing an initially correctable error to propagate into an uncorrectable error. Therefore, it can be understood that a currently uncorrectable error is derived from the propagation of a set of target historical correctable errors.

[0065] Memory failures are usually an evolutionary process. Multi-bit fault cells (UCEs) are not generated suddenly at the same time, but are derived from the evolution of historical CEs. Figure 6 An example diagram illustrating the evolution direction of a memory cell fault, provided in an embodiment of this application, is shown below. Figure 6 As shown, when a memory chip has a 1-bit error, Advanced ECC can correct the error; when a memory chip has a 2-bit error and the error is within the same mark, Advanced ECC can still correct the error; when a memory chip has a 3-bit error and the error is within different marks, Advanced ECC cannot correct the error.

[0066] To address the problem of inaccurate location and effective correction of multiple errors when uncorrectable memory errors (UCEs) occur, leading to data loss and decreased server system stability, this application embodiment utilizes the patterns of memory fault changes. When an uncorrectable memory error occurs, it attempts to use historical correctable error data, corrects the data, and then performs memory ECC again. The ECC result is then observed to see if the uncorrectable error can be corrected. If performing memory ECC again after correcting the data can correct the uncorrectable error, then the uncorrectable error can be corrected using this application embodiment.

[0067] The ECC (Error Checking and Correcting) mechanism is designed to not only detect errors but also, to some extent, pinpoint their location. However, there is a fundamental difference in ECC's ability to locate correctable errors (CE) and uncorrectable errors (UCE). For correctable errors (CE), the ECC algorithm can precisely determine the specific location of the error and attempt to correct it. For uncorrectable errors (UCE), UCE typically refers to the number of errors in the Code Word that exceeds the ECC's error correction capabilities, or the error pattern being outside the error correction range designed for ECC. In this case, ECC can detect the existence of errors but cannot determine the specific locations of all errors, and therefore cannot correct them all. ECC may indicate that there is an error in the entire Code Word but cannot identify which specific data bits need to be corrected. Therefore, in this embodiment, the memory address parameter of the current uncorrectable error refers to the highest logical level location information of the error that ECC can identify, mainly including DIMM, Rank, Device, and Bank, as well as the affected cache line and Code Word.

[0068] Memory errors that have occurred in memory are recorded and stored in a history error log file. This history error log file is a data storage structure used to record and store information related to correctable errors (CEs) that have previously occurred in memory, including but not limited to the error's location (DIMM, Rank, Device, Bank, Column information) and physical address. A target set of historical correctable errors in the history error log file is a set of historical records found in the history error log file that match the memory address parameters of the current uncorrectable error. A target set of historical correctable errors contains single-bit or multi-bit error information that previously occurred at the same memory location but has been successfully corrected.

[0069] When a memory error becomes currently uncorrectable, it may stem from a previously correctable error (CE) that was not properly handled and gradually worsened. Extracting a set of target historical correctable errors from the historical error log file that match the memory address parameters of the current uncorrectable error means finding the root cause of the precursor to the current uncorrectable error. Applying a correction algorithm to this set of target historical correctable errors is essentially an attempt to repair the initial point of corruption that led to the current uncorrectable error. If the set of target historical correctable errors is successfully corrected, it means the starting point of the corrupted chain has been restored, potentially eliminating or reversing the effects of error propagation and reverting the current uncorrectable error to a correctable state. In other words, after the set of target historical correctable errors is corrected, the current uncorrectable error is transformed into a derived correctable error.

[0070] Derived correctable errors refer to errors that were originally uncorrectable, but have since been successfully corrected. These errors transform from uncorrectable to correctable by the server system. Derived correctable errors indicate that the source or pattern of the currently uncorrectable error has changed, falling within the scope of ECC (Error Correction Control) mechanisms. The difference between derived correctable errors and currently uncorrectable errors is that derived correctable errors can be corrected by the server system. Currently uncorrectable errors are multi-bit errors that the server system cannot automatically correct through ECC, while derived correctable errors are transformed from currently uncorrectable errors after being repaired by a set of target historical correctable errors, and their error pattern returns to the CE (Error Correction) type within the scope of ECC. In short, derived correctable errors are the result of currently uncorrectable errors transforming into correctable errors under specific conditions. By correcting derived errors, the original currently uncorrectable error problem can be resolved, restoring data correctness.

[0071] Currently uncorrectable errors arise because the accumulation or mutation of Error Correction (CE) exceeds the error correction capabilities of Error Correction Capability (ECC). Once a set of target historical correctable errors, considered the cause of currently uncorrectable errors, is identified and corrected by the server system, this set of target historical correctable errors no longer serves as the basis for further error propagation. Therefore, currently uncorrectable errors directly or indirectly caused by a set of target historical correctable errors may transform into a less severe form of error—derived correctable errors. By correcting derived correctable errors, the server system is essentially repairing errors that are close to or just exceeding the ECC threshold, thereby bringing the error state back within the range that ECC can handle, effectively restoring data integrity, and avoiding the server-system-level impact of currently uncorrectable errors.

[0072] Optionally, Figure 7 A structural diagram of a server system provided in this application embodiment is shown below. Figure 7As shown, the server system includes memory 701, processor 702, baseboard controller (BMC) 703, baseboard input / output system (BIOS) 704, and operating system (OS) 705. The processor 702 is equipped with a memory controller (IMC). Figure 8 A flowchart of error correction for a server system provided in this application embodiment is shown below. Figure 8As shown, memory 701 is used to store data. When processor 702 reads data from memory 701, the IMC uses the ECC mechanism to verify the data. If the data verification fails (e.g., a CE is detected, or an error exceeding the ECC correction capability, i.e., a UCE), the IMC will record the error information (the specific location and physical address of the memory error) and update the relevant registers of the memory controller. When the error is a UCE, an uncorrectable error interrupt is generated and sent to the BIOS 704. The BIOS 704 reports the uncorrectable error to the OS 705. The OS 705 starts an exception handler. After the exception handler detects an uncorrectable error, it generates a software SMI (SwSMI) system interrupt, transferring control to the BIOS 704. That is, the BIOS 704 participates in the error correction algorithm, and in cooperation with the BIOS, it writes back the fault information to attempt to correct the uncorrectable error information. In the SMI processing procedure, the Baseboard Input / Output System (BIOS) 704 communicates with the Baseboard Controller (BMC) 703. The BIOS 704 sends a data acquisition command to the Baseboard Controller (BMC), retrieves a set of target historical correctable errors matching the current UCE memory address from the historical error log file maintained by the Baseboard Controller (BMC) 703, and performs a feedback-based attempt to correct the set of target historical correctable errors based on this set of errors. This includes attempting to modify and rewrite potential error bits. Then, the codeword is refreshed through the memory controller, ECC verification is performed again, and the correction result is fed back to the BIOS 704. If the feedback correction result indicates that the BIOS 704 has not successfully corrected the set of target historical correctable errors, the BIOS 704 continues to correct the data (i.e., continues to perform feedback-based attempts to correct the set of target historical correctable errors). If the feedback correction result indicates that the BIOS 704 has successfully corrected a set of target historical correctable errors, causing the current UCE to be transformed into a derived CE (i.e., an error type that ECC checks can handle), then the BIOS 704 will notify the operating system (OS) 705. The OS 705 will then attempt further correction of the derived CE. If successful, the affected memory region will be isolated to prevent future access to that region, thereby completely resolving the current UCE problem and preventing data corruption and system anomalies. If all correction attempts by the BIOS 704 fail to transform the UCE into a derived CE, the OS 705 will adopt the default error handling procedure, such as restarting the system and performing Soft PPR (Soft Processing Reset) to restore normal system operation.

[0073] In the embodiments of this application, when a current uncorrectable error occurs in memory, based on the evolution law of uncorrectable errors, a set of target historical correctable errors that match the memory address of the current uncorrectable error are extracted from the historical error record file. The set of target historical correctable errors is used as the starting point for repairing the current uncorrectable error, and an attempt is made to correct the set of target historical correctable errors. Once the set of target historical correctable errors is successfully processed, the current uncorrectable error has the opportunity to transform into a derived correctable error, so that the root cause or pattern of the current uncorrectable error changes, and the ECC mechanism can play a role again. Subsequently, the derived correctable errors are corrected to fundamentally resolve the current uncorrectable errors and restore the originally damaged data. Unlike related hard-handling methods for uncorrectable errors, such as system restart or hardware replacement, this application proposes a feedback process that attempts to correct the current uncorrectable error by using a set of target historical correctable error information that matches the memory address of the current uncorrectable error. This greatly reduces the possibility of data loss, ensures data integrity and server system stability, and demonstrates a new error recovery approach. That is, without changing the hardware configuration or disrupting the existing system operation, it dynamically repairs uncorrectable errors, improves the error tolerance and data recovery capability of the server system, significantly enhances the flexibility and efficiency of error recovery, and solves the problem in related technologies where multiple bit errors cannot be effectively corrected when uncorrectable errors occur in memory, leading to data loss and decreased server system stability.

[0074] In one exemplary embodiment, when a currently uncorrectable error occurs in memory, a set of target historical correctable errors matching the memory address parameters of the currently uncorrectable error is extracted from a historical error log file, including:

[0075] When an uncorrectable error occurs in memory, the physical address of the uncorrectable error is recorded, and the physical address of the uncorrectable error is translated into the memory address parameter of the uncorrectable error. The target historical correctable error is then searched in the historical error record file according to the memory address parameter of the uncorrectable error.

[0076] When the memory controller (IMC) detects an error beyond its error correction capabilities—a currently uncorrectable error—the physical address recorded by the IMC is the location identifier of the specific memory cell that caused the current uncorrectable error. The physical address of the current uncorrectable error contains complete information about its location, such as which DIMM module, rank, device, bank, and specific column and row it occurred in. In this embodiment, the physical address of the current uncorrectable error is used to accurately locate its occurrence. Subsequently, the BIOS performs address translation, converting it into higher-level memory address parameters for more in-depth error analysis and retrieval of historical error correction (CE) records.

[0077] The memory address parameter of the current uncorrectable error is an abstract description of the physical address, which includes information such as DIMM (Dual In-line Memory Module), Rank, Device, Bank, Column and Row, which together constitute the logical memory mapping.

[0078] Optionally, the Memory Controller (IMC) detects the current UCE in the processor and immediately records its physical address. This recorded physical address is then translated by the BIOS using an address mapping table, converting it into memory address parameters. The BIOS sends the translated memory address parameters to the BMC. The BMC then queries its maintained historical error log file to find a set of target historical correctable error records that match the current UCE address parameters. The historical error log file is a core function of the BMC, used to track and record detailed information about all historical CE events.

[0079] In this embodiment, the physical address of the current uncorrectable error is translated into a memory address parameter. This translation increases the accuracy of error location, enabling the server system to more accurately understand the root cause of the current uncorrectable error and take targeted corrective measures.

[0080] In one exemplary embodiment, the memory includes multiple cache lines; each cache line includes multiple storage units; the memory address parameter of the current uncorrectable error is used to indicate the target codeword where the current uncorrectable error is located; the target codeword refers to a portion of the storage unit of the target cache line where the current uncorrectable error is located in the multiple cache lines.

[0081] In this context, memory is the physical medium for storing data, while a cache line is the smallest unit for the CPU to read and write memory. It contains several memory cells and ECC bits used for error detection and correction. A memory cell is the basic physical unit in DRAM that stores data and occupies a specific position within the cache line. A memory cell is an individual unit capable of triggering Error Correction (CE) or Uncorrectable Error Correction (UCE), and its changes are crucial in triggering subsequent error correction processes.

[0082] A codeword is the basic unit in the ECC processing procedure, consisting of original data and a check bit, used to detect and correct errors. For example, Figure 9 An illustration of an encoded word provided in an embodiment of this application, such as... Figure 9 As shown, taking 10x4 memory as an example, the bit width is 4, the number of data granules is 0~7, the number of parity granules is 8~9, and each cache line contains 16 bursts, meaning 16 columns need to be burst-read. In this embodiment, the target codeword refers to the codeword where the current uncorrectable error is located. The target codeword contains multiple storage units (cells) and is the core data segment that attempts to correct the error using historical CE information.

[0083] In some embodiments, when a currently uncorrectable error occurs in memory, a set of target historical correctable errors matching the memory address parameters of the currently uncorrectable error is extracted from the historical error log file, including:

[0084] In the event of an uncorrectable error in memory, extract multiple correctable historical errors located in the target codeword from the historical error record file, and determine the extracted multiple correctable historical errors as a set of target historical correctable errors.

[0085] Optionally, the Memory Controller (IMC) detects the current UCE, immediately records the physical address of the fault, and triggers an error reporting mechanism. The physical address recorded by the IMC is translated into detailed memory address parameters by the BIOS, where the memory address parameters explicitly indicate which specific cache line the target codeword of the current UCE is located in. The BIOS then retrieves all target historical correctable errors from the historical error log file that correspond to the same location as the target codeword.

[0086] In this embodiment, based on the rule that UCEs are the accumulation or deterioration of previously incompletely corrected CEs, CEs that occurred in the same codeword in the past are extracted from the historical error log file, realizing the correlation between errors. Compared with the related UCE processing methods where errors are treated as isolated events, this embodiment can infer the possible origin of the current UCE through error correlation analysis, thereby formulating a more effective correction strategy.

[0087] In one exemplary embodiment, the memory includes multiple cache lines, and each cache line includes multiple storage units. The correction of a set of target historical correctable errors includes:

[0088] Identify a set of correction combinations corresponding to a set of target historical correctable errors; a set of correction combinations refers to a set of different correction methods that perform a reversal operation on the data bits of the storage unit where the target historical correctable error is located in the set of target historical correctable errors; a reversal operation refers to an operation that changes the binary state of the data bits of the storage unit where the target historical correctable error is located in the set of target historical correctable errors; correct the set of target historical correctable errors according to the correction combinations in the set of correction combinations.

[0089] In this embodiment, the process of correcting a set of target historical correctable errors according to a set of correction combinations essentially involves exploring multiple possibilities to find a method that can transform currently uncorrectable errors into derived correctable errors, thereby utilizing existing ECC mechanisms to complete the final data repair. The set of correction combinations used in the correction process refers to a collection of different correction strategies, each aimed at recovering erroneous data caused by a set of target historical correctable errors. This set of correction combinations, based on past CE data bit analysis and predictions of possible evolution paths for multi-bit errors, forms multiple possible correction methods to address the complexity of current UCE.

[0090] A correction combination is a method of performing a targeted bit reversal operation on the data bits of a single target historical correctable error within a set of target historical correctable errors. Each correction combination contains instructions to reverse the binary state of the data bits in a specific memory cell, with the aim of attempting to restore a multi-bit error that is currently uncorrectable to a correctable error state that can be corrected by the ECC mechanism.

[0091] Figure 10 This is a schematic diagram of a memory array provided in an embodiment of this application, as shown below. Figure 10 As shown, a word line represents a memory row, and a bit line represents a memory column. Therefore, a single encoded word contains multiple columns of information across multiple memory granules. A cell is the basic unit of memory storage, consisting of a transistor and a capacitor. Each cell can store one bit of data (0 or 1). The cell is the fundamental element constituting all the above levels and the ultimate target of all read and write operations.

[0092] A reversal operation refers to changing a data bit in a specific memory location from 0 to 1, or from 1 to 0, during the correction of a set of target historical correctable errors. This operation, based on the location and error pattern of the target historical correctable errors, attempts to eliminate or reduce the multi-bit errors that led to the current uncorrectable error, returning it to a correctable state.

[0093] Optionally, the BMC extracts a set of target historical correctable errors from the historical error log file based on the memory address parameters of the current uncorrectable error, and determines the memory cells involved in the set of target historical correctable errors. The BIOS generates multiple correction combinations based on the patterns of the set of target historical correctable errors. Each correction combination contains a different strategy for performing a reversal operation on specific data bits. Following the guidance in each correction combination, the BIOS modifies the binary state of the data bits in the memory cell, attempting to restore the UCE data format to a correctable error pattern. After applying each correction combination, the memory controller recalculates the ECC checksum to verify whether the data has been corrected. If the data can be recognized and corrected by the ECC, the current uncorrectable error is successfully transformed into a derived correctable error; otherwise, the next correction combination is tried until all attempts are completed.

[0094] Through this embodiment, the determined set of correction combinations includes multiple different strategies for reversing the data bits of the storage unit where each target historical correctable error is located. This shows that the server system does not use a single correction method, but has the ability to try multiple methods, which greatly increases the possibility of transforming the current uncorrectable error into a derived correctable error. Moreover, each correction combination is designed for a specific target historical correctable error pattern, reflecting accurate error correction after a deep understanding of multi-bit error patterns.

[0095] In one exemplary embodiment, determining a set of correction combinations corresponding to a set of target historical correctable errors includes:

[0096] A correction method that reverses the data bits of the memory cell containing one of the target historical correctable errors in a set of target historical correctable errors, while keeping the data bits of the memory cells containing the remaining target historical correctable errors in the set unchanged, is defined as a correction combination, thus obtaining a set of correction combinations.

[0097] In this embodiment, the number of correction combinations is determined with base 2 and exponentiated by the number of target historical correctable errors in a set of target historical correctable errors. For example, Figure 11This application provides a schematic diagram of a set of target historical correctable errors that match the memory address parameters of the current uncorrectable error in an embodiment of the present application. The diagram locates all target historical correctable errors in the target codeword that contain the memory address parameters of the current uncorrectable error. Figure 11 As shown, a set of target history correctable errors includes 5 target history correctable errors. Therefore, the number of correction combinations is 2 to the power of 5, that is, 32 correction combinations. Using these 32 correction combinations, we attempt to modify the possible error location data for fault re-verification processing.

[0098] Optionally, for each target historical correctable error, the BIOS or OS generates a corresponding data bit inversion instruction. This instruction ensures that, except for the data bit specified in the target historical correctable error, the state of other data bits in the memory cell remains unchanged, allowing for tentative correction on a per-CE basis. The BIOS or OS combines the inversion instructions for each CE into a correction combination, forming a set of correction combinations. Each combination represents a tentative correction strategy for a specific target historical correctable error, and this set of correction combinations covers all possible correction methods for all target historical correctable errors.

[0099] In this embodiment, for a set of target historical correctable errors, the inversion operation is performed only on the data bits of the storage unit where one target historical correctable error is located each time, instead of processing all target historical correctable errors at once. This allows for a detailed analysis of the impact range of each target historical correctable error and targeted attempts to correct it, avoiding the additional overhead and invalid attempts that may be caused by traditional full scans. Furthermore, when attempting to correct a target historical correctable error, the data bits of the storage units where other target historical correctable errors in the set are located remain unchanged. This means that when performing error correction operations, the impact on memory data can be precisely controlled, avoiding potential damage to other data in memory.

[0100] In one exemplary embodiment, correcting a set of target historical correctable errors according to a set of correction combinations includes:

[0101] A set of correction combinations is traversed sequentially, and the currently traversed correction combination is taken as the current correction combination. The current correction combination is used to indicate the reversal operation for the target historical correctable error specified in the set of target historical correctable errors. According to the current correction combination, the target historical correctable error specified in the set of target historical correctable errors is reversed, and after the reversal operation is performed, the data bits of the storage unit where the target historical correctable error is located are read again. If the data bits of the storage unit where the target historical correctable error is located are read correctly and the read data is valid, it is determined that the set of target historical correctable errors has been corrected.

[0102] Optionally, the BIOS processes a set of correction combinations sequentially, selecting each combination as the current correction combination. Each current correction combination explicitly specifies which specific target historical correctable errors (UCEs) should be reversed. Following the guidance of the current correction combination, the BIOS reverses the data bits of the specified target historical correctable errors within the set. After the operation, the memory controller verifies the reread data bits using the ECC mechanism to confirm whether the data has been read correctly and whether it is valid (i.e., whether it has been converted to CE or normal data). If the ECC verification result shows that the data is valid and there is no UCE, the BIOS determines that the set of target historical correctable errors has been corrected. Conversely, if data cannot be recovered after all correction combinations have been traversed, the BIOS will take other UCE handling measures, such as isolating the faulty memory or restarting.

[0103] In this embodiment, the current correction combination explicitly instructs a data bit reversal for a specified target historical correctable error. Unlike traditional large-area data bit scanning and repair, this embodiment specifically modifies the state of potentially faulty data bits, attempting to reverse the cause of the current uncorrectable error, while minimizing the impact on other data bits, ensuring data integrity and system stability. After performing the data bit reversal operation, the data bits of the storage unit where the target historical correctable error is located are reread, and the validity is verified through the ECC mechanism of the memory controller. It intelligently determines whether the reversal operation has successfully transformed the current uncorrectable error into a derived correctable error, thereby avoiding repeated attempts of invalid operations and improving the success rate of error correction.

[0104] In one exemplary embodiment, the above-described memory error correction method further includes:

[0105] If the data bits of the storage unit where a target historical correctable error is located are not read correctly or the read data is invalid, select a correction combination from the remaining correction combinations in the set of correction combinations other than the current correction combination as the new current correction combination. Based on the new current correction combination, return to the step of performing the reversal operation on the target historical correctable error specified in the set of target historical correctable errors according to the current correction combination and continue to execute until the set of target historical correctable errors is corrected, or until the set of correction combinations has been traversed.

[0106] In one exemplary embodiment, if a set of correction combinations has been traversed and a set of target historical correctable errors has not been corrected, the server system where the memory resides is restarted or the memory is repaired.

[0107] Optionally, when the operating system or BIOS attempts to read data bits from the memory cell containing a target historically correctable error, if the ECC mechanism detects a data read failure or invalid data (i.e., UCE still exists), the operating system or BIOS immediately determines that the current correction operation has failed. The BIOS will exclude the tested current combination from the set of correction combinations and select the next correction combination as the new current correction combination. Based on the new current correction combination, the BIOS will relocate and perform a data bit inversion operation, modifying the data bit state only for the target historically correctable errors specified in the new correction combination, while ensuring that the states of other data bits are unaffected. This process is repeated until a set of target historically correctable errors is successfully corrected (i.e., ECC verification passes, data read is valid), or until a set of correction combinations has been traversed without any combination correcting the current uncorrectable error. At this point, the operating system or BIOS will take default fault handling measures, such as isolating the faulty memory area or restarting the system.

[0108] This embodiment can intelligently judge the effect of each correction combination and decide whether to continue trying the next combination until an effective correction solution is found. If all correction combinations have been traversed and the current uncorrectable error is still not resolved, a decision will be made to restart or repair the memory. The error correction strategy can be dynamically adjusted according to the real-time correction results to maximize the possibility of software error correction.

[0109] In one exemplary embodiment, when a set of target historical correctable errors has been corrected, the derived correctable errors converted from the current uncorrectable errors are corrected to correct the current uncorrectable errors, including:

[0110] When a set of target historical correctable errors are corrected, the data bits of the memory cell containing the derived correctable error converted from the current uncorrectable error are reversed in order to correct the current uncorrectable error. The reversal operation refers to the operation of changing the binary state of the data bits of the memory cell containing the derived correctable error converted from the current uncorrectable error.

[0111] Specifically, when the server system successfully resolves a previously recorded set of target historical correctable errors through a feedback error correction mechanism, but the current uncorrectable error transforms into a new, derivative correctable error that can be identified and processed by the system, the server system will perform a targeted data bit reversal operation to correct this new CE (i.e., derivative correctable error), thereby indirectly repairing the current uncorrectable error. This data bit reversal operation refers to flipping specific data bits in the storage unit containing the derivative correctable error from 0 to 1, or from 1 to 0. By changing the binary state of these critical data bits, it attempts to reverse the multi-bit fault mode that caused the current uncorrectable error, restoring it to an error state that the ECC mechanism can correct.

[0112] Optionally, after attempting a feedback error correction mechanism, if a set of target historical correctable errors is corrected and the current uncorrectable error is transformed into a derived correctable error, the BIOS accurately locates the specific position of the derived correctable error, including its memory cell and data bits. The processor's integrated memory controller (IMC) is responsible for reading the data bits of the memory cell where the derived correctable error is located, obtaining its current binary state, and providing the basic data for the next inversion operation. Based on the read binary state, the BIOS performs a data bit inversion operation, that is, changing the data bits from 0 to 1 or from 1 to 0, in order to correct the derived correctable error transformed from the current uncorrectable error. After the data bit state of the memory cell where the derived correctable error is located is modified, the IMC performs ECC verification again to verify the validity of the data, ensuring that the inversion operation truly brings the derived correctable error to an error-free state.

[0113] In this embodiment, once a set of target historical correctable errors are successfully corrected, the current uncorrectable error may be transformed into a new CE mode. The BIOS can intelligently identify the transformation from UCE to CE, thus giving the originally uncorrectable error a chance to be included in the scope of correctable error processing, increasing the possibility of UCE being resolved. The BIOS can accurately locate the data bit where the derived correctable error is located and perform a data bit inversion operation. This operation specifically changes the binary state that caused the current uncorrectable error to be transformed, rather than blindly modifying the entire storage unit or cache line, ensuring data integrity and server system stability, while also significantly reducing resource consumption during the error correction process.

[0114] In one exemplary embodiment, the above-described memory error correction method further includes:

[0115] After the current uncorrectable error is corrected, the memory page containing the target codeword where the current uncorrectable error occurred is isolated.

[0116] In this context, a memory page is the basic unit of memory management in an operating system. After an uncorrectable error is corrected, to prevent future access to the same region from recurring the error, the operating system isolates the entire memory page, including the target codeword. This typically involves operating system-level access control and address space management, ensuring that the faulty region is no longer accessed by applications or system processes, thereby protecting data integrity and improving system stability.

[0117] Isolation is a measure taken by the operating system after detecting an uncorrectable error or a faulty memory region. In the embodiments of this application, isolation means that the operating system marks the faulty memory page as inaccessible, preventing subsequent read and write operations from triggering the error again. This mechanism helps with data protection and system recovery, maintaining the overall operational status of the system by limiting the impact of the faulty region.

[0118] Optionally, Figure 12 A flowchart of another memory error correction method provided in the embodiments of this application is shown below. Figure 12 As shown, when a memory error occurs, the error type is determined. If the memory error is uncorrectable, the BIOS translates the physical address of the current uncorrectable error into a memory address and locates the cache line containing that memory address. The BMC then queries the historical error log file based on the memory address of the current uncorrectable error to find a set of target historical correctable errors that match the memory address parameters of the current uncorrectable error. This set of target historical correctable errors is then fed back to the BIOS. The BIOS calls the memory controller to attempt feedback-based error correction on the set of target historical correctable errors. If the current uncorrectable error is successfully verified by ECC, the operating system verifies the validity of the data bits. After the data in the memory unit where the current uncorrectable error is located is successfully consumed, the address information is migrated and isolated to prevent the recurrence of uncorrectable memory errors. Conversely, if the verification fails, further measures will be taken according to preset policies, such as restarting the system or attempting other fault repair mechanisms.

[0119] In this embodiment, after successfully correcting the current uncorrectable error, the target codeword that caused the error is further located. The operating system will isolate the memory page where the target codeword is located. This means that the access permissions of the entire memory page are changed by the operating system, thereby preventing any application or system process from further reading or writing to the memory page. This avoids the risk of triggering UCE again when accessing the same area in the future. It can quickly and effectively protect data integrity and system stability without restarting the system.

[0120] In one exemplary embodiment, memory includes multiple cache lines; each cache line includes multiple storage units; isolating the memory page containing the target codeword where the current uncorrectable error resides includes:

[0121] The memory page containing the target codeword where the current uncorrectable error is located is marked as unavailable, thereby isolating the memory page containing the target codeword from available memory resources; the target codeword includes a portion of the storage unit of the target cache line in which the current uncorrectable error is located across multiple cache lines.

[0122] The unavailable flag is a special status indicator set on a memory page to indicate that the page has been deemed an inaccessible and unusable resource by the operating system due to containing past or current UCEs (User-Generated Contents). This flag ensures that the faulty area is not misread by system processes or applications, thereby maintaining the overall operating state of the system.

[0123] Optionally, if the currently uncorrectable error is successfully corrected, the operating system receives a notification from the BIOS and marks the memory page containing the target codeword as unavailable. The operating system updates the memory management table, removing the marked memory page from the list of available resources, thus achieving isolation. To avoid affecting the normal operation of the system, the operating system migrates the relevant processes or data to other available memory pages.

[0124] In this embodiment, after an uncorrectable error is identified and successfully corrected through a feedback error correction mechanism, the memory page containing the target codeword is further marked as unavailable, thus isolating it from available system resources. This effectively solves the potential data corruption and system instability problems caused by UCE in related technologies. By actively isolating faulty memory pages, UCE is prevented from recurring in subsequent accesses, ensuring data integrity and long-term system reliability.

[0125] In one exemplary embodiment, the above-described memory error correction method further includes:

[0126] When a correctable error occurs in memory, the data bits of the memory cell containing the correctable error are reversed to correct the error. The reversal operation refers to the operation of changing the binary state of the data bits of the memory cell containing the correctable error.

[0127] Optionally, if the memory controller detects a currently correctable error during data reading, it uses ECC verification information to locate the memory cell and specific data bit where the error occurred. The memory controller performs a binary state inversion on the located erroneous data bit, changing 0 to 1 or 1 to 0, to attempt to correct the error. After the inversion operation, the memory controller performs ECC verification again to confirm whether the error has been corrected. The memory controller feeds back the error correction result to the system. If the correction is successful, the memory cell is marked as repaired; if not, it is reported according to the UCE processing procedure.

[0128] In this embodiment, the state of the currently correctable error data bits is reversed, changing from 0 to 1 or from 1 to 0. This operation is performed directly at the software level without the need for physical access to or modification of memory hardware, which greatly reduces the complexity and time required for error correction. In addition, the data bit reversal operation is performed instantly, avoiding the possibility that CE will evolve into a more serious and uncorrectable UCE, significantly improving the reliability of the memory system and extending the server's fault-free uptime.

[0129] In one exemplary embodiment, the memory includes multiple cache lines, and each cache line includes multiple storage units; the set of target history correctable error types includes at least one of the following: cell error, column error; a cell error refers to an error occurring in one of the multiple storage units; a column error refers to an error occurring in a storage unit in the same column among the multiple storage units.

[0130] In this system, memory is organized into multiple cache lines, which are the basic units of memory access. Each cache line contains multiple contiguous data bits, typically related to the memory's burst length and bit width. When the processor needs to read or write data to memory, it usually operates in the form of cache lines, meaning that a single access processes the entire cache line of data, rather than a single data bit. This organization helps improve data access speed and efficiency because contiguous memory cells can be accessed through a single burst read or write operation, reducing memory access latency and frequency. In this application, the concept of multiple cache lines forms the basis for describing the memory organization structure and error detection and correction mechanisms.

[0131] A cell error (CE) refers to a correction error (CE) occurring in a specific memory cell, indicating that the bit state of that cell is incorrect and needs to be corrected. In this embodiment, cell errors are recorded in the historical correction routine and can be used for subsequent UCE correction attempts.

[0132] A column error refers to a situation where multiple memory cells located in the same column across multiple cache lines simultaneously experience a CE (Error Result). In this embodiment, column errors are also considered part of historical correctable errors, and their information is used to assist in UEC (User Estimation and Control) processing. Figure 11 As shown, a set of target history correctable errors includes 5 target history correctable errors, which are further divided into one unit error and one column error. The unit error and the column error overlap in the same codeword.

[0133] In some embodiments, the memory error correction method further includes the following steps:

[0134] 1. Record the error information of the currently correctable error in the historical error log file, and determine whether there are other historical correctable errors in the historical error log file that are in the same column as the storage unit where the currently correctable error is located.

[0135] 2. If there are no other historical correctable errors in the same column as the memory cell where the current correctable error is located, determine the error type of the current correctable error as a cell error.

[0136] 3. If there are other historical correctable errors in the same column as the memory cell where the current correctable error is located, mark multiple memory cells in the memory column where the current correctable error is located as having correctable errors, record the error information of the correctable errors that occurred in the memory cells in the memory column where the current correctable error is located in the historical error record file, and determine the error type of the correctable errors that occurred in the memory cells in the memory column where the current correctable error is located as a column error.

[0137] Among them, the error information of currently correctable errors refers to the detailed record of errors detected and successfully corrected by the memory controller during memory access. For example, the error information includes the precise location of the error, such as the specific memory cell in the memory device under test, the column it belongs to, and the physical address of the cache line it belongs to; the error type, i.e., this is a correctable error (CE) rather than an uncorrectable error (UCE); as well as the bit pattern of the error and possible correction methods, etc.

[0138] Other historical correctable errors refer to correctable errors (CEs) that the server system detected and logged in the historical error log file before the current correctable error. Other historical correctable errors also occur in memory storage units, but they may not occur at the same time as the current error, or they may not be in the same cache line.

[0139] If different Corrective Errors (CEs) occur repeatedly in the same memory column, it indicates a potential or persistent hardware failure in that column. In this case, multiple memory cells in the column containing the currently correctable error need to be marked. This means that by marking the entire column, even if some cells are currently functioning normally, the server system can take measures to protect the resources of that column, preventing data integrity and system stability from being affected as the faulty cells worsen. Furthermore, marking the entire column, rather than just the known faulty cells, simplifies the fault handling process. In server systems, handling a single faulty cell may require complex location and repair mechanisms, while marking the entire column as a potential fault area allows the system to employ simpler and more direct isolation or repair strategies, such as Soft PPR (Soft Repair Post-Patch).

[0140] Optionally, such as Figure 12 As shown, if the memory controller detects a correctable error during data reading, it records the error information, including DIMM, Rank, Device, Bank, Column, and Row information, as well as the physical address. This error information is transmitted to the BMC via the BIOS and stored in the historical error log file. The BMC searches the historical error log file for a historical CE record at the same memory column position as the correctable error. If no historical CE with the same column is found, the BMC marks the correctable error as a cell error. If a historical CE with the same column is found, the BMC marks the correctable error and its column as a column error. When the error type of the correctable error is determined to be a column error, the BMC updates the historical error log file, recording detailed column information. The BMC stores all recorded cell errors and column errors in the historical error log file, providing historical feedback data for correcting uncorrectable errors.

[0141] In this embodiment, if no other historical correctable errors exist in the same column as the memory cell where the current correctable error is located, the error type of the current correctable error is determined to be a cell error. If other historical correctable errors exist in the same column as the memory cell where the current correctable error is located, multiple memory cells in the memory column where the current correctable error is located are marked as having correctable errors, and the error type of the correctable errors in the multiple memory cells in the memory column where the current correctable error is located is determined to be a column error. By introducing an error type classification mechanism, the server system can respond to different types of errors in a targeted manner. Furthermore, by marking cell errors and column errors, in the subsequent process of correcting uncorrectable errors, historical column error correction and cell error correction can be attempted. This is equivalent to having more references and data support during the repair process, which improves the success rate of UCE correction, reduces the frequency of system reset or restart, and thus improves the server's operating efficiency and the continuity of data processing.

[0142] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0143] Embodiments of this application also provide a server system, including:

[0144] Memory is used to store data;

[0145] The memory controller is used to read data stored in memory and, in the event of a current uncorrectable error in memory, send an uncorrectable error interrupt to the basic input / output system.

[0146] The basic input / output system is used to report uncorrectable error interrupts to the operating system;

[0147] The operating system is used to start the exception handler. After the exception handler detects an uncorrectable error, it generates a system interrupt and feeds the system interrupt back to the basic input / output system.

[0148] The basic input / output system is also used to send data acquisition commands to the board management controller to obtain historical correctable errors stored in the historical error log file;

[0149] The baseboard management controller is used to respond to data acquisition commands and feed back a set of target historical correctable errors that match the memory address parameters of the current uncorrectable errors in the historical error log file to the basic input / output system.

[0150] The basic input / output system is also used to correct a set of target historical correctable errors; wherein, after a set of target historical correctable errors is corrected, the current uncorrectable error is converted into a derived correctable error; and when a set of target historical correctable errors is corrected, the derived correctable error converted from the current uncorrectable error is corrected in order to correct the current uncorrectable error.

[0151] Among them, memory is the hardware that stores data inside a computer. In this embodiment, it specifically refers to storage devices that are susceptible to software and hardware errors, such as DRAM (Dynamic Random Access Memory), which is the carrier of data reading and writing and the occurrence of errors.

[0152] The memory controller (IMC) is an internal module of the processor responsible for performing data read / write operations and error detection. When a Uncorrectable Error (UCE) is detected, it triggers an uncorrectable error interrupt to the BIOS. An uncorrectable error interrupt indicates a serious system error, requiring immediate action to prevent data loss or system crash. In this embodiment, the uncorrectable error interrupt is the trigger point for initiating a feedback error correction process.

[0153] The Basic Input / Output System (BIOS) is software that runs during hardware startup and is used to initialize the hardware and load the OS. In this embodiment, the BIOS receives a UCE interrupt, interacts with the BMC, and attempts to correct errors.

[0154] An operating system (OS) is software that manages computer resources. It initiates exception handlers, handles uncorrectable errors (UCEs), and generates system interrupts to feed back to the BIOS for error correction. Exception handlers are part of the operating system and are specifically designed to respond to and handle various abnormal events or error conditions, including UCEs in memory. In this application, the exception handler, upon detecting a UCE, generates a system interrupt and feeds it back to the BIOS to attempt to repair the error through software means, rather than simply restarting the system. A system interrupt is a control signal issued by the operating system to the processor when the hardware or software detects a situation requiring urgent attention. This signal requests the processor to suspend its current task and handle the emergency. In this embodiment, the operating system generates a system interrupt for the BIOS, prompting the BIOS to intervene in the error handling process and attempt to obtain a set of target historical correctable errors from the BMC to correct the currently uncorrectable error.

[0155] The Baseboard Management Controller (BMC) is a dedicated microcontroller that monitors server hardware. It responds to BIOS data fetch commands, providing a record of historical correctable errors to aid in error localization and correction. The BIOS data fetch command is a command sent to the BMC to retrieve a set of target historical correctable errors stored in the BMC that match the memory address of the current uncorrectable error. This set of target historical correctable errors contains details of past error corrections (CEs) occurring at the same or similar memory addresses, which can be used to assist in analysis and attempt to correct the current uncorrectable error (UCE).

[0156] For a description of the features in the embodiment corresponding to the server system, please refer to the relevant description of the embodiment corresponding to the memory error correction method, which will not be repeated here.

[0157] In one exemplary embodiment, the basic input / output system is further configured to perform multiple feedback attempts to correct a set of target historical correctable errors; the memory controller is further configured to refresh the codeword, re-perform error checking and correction verification, and feed back the correction result to the basic input / output system; the basic input / output system is further configured to continue to perform feedback attempts to correct a set of target historical correctable errors when the feedback correction result indicates that the basic input / output system has failed to correct a set of target historical correctable errors.

[0158] Among them, feedback-based attempted correction is a memory error correction strategy proposed in the embodiments of this application, specifically targeting UCEs (Uncorrectable Errors). The basic idea of ​​this strategy is that when the system encounters a UCE, it does not immediately take traditional restart or shutdown measures, but instead first attempts to analyze and correct the UCE using previously recorded CE (Correctable Error) information. For a detailed description of the feedback-based attempted correction process, please refer to the relevant descriptions of the embodiments corresponding to the memory error correction method, which will not be repeated here.

[0159] In one exemplary embodiment, the memory includes multiple cache lines; each cache line includes multiple storage units; the operating system is further configured to isolate the memory page containing the target codeword of the currently uncorrectable error, provided that the feedback correction result characterizes the basic input / output system as having successfully corrected a set of target historical correctable errors; the target codeword refers to a portion of the storage unit of the target cache line in which the currently uncorrectable error is located among the multiple cache lines.

[0160] For a description of the features in the embodiment corresponding to the server system, please refer to the relevant description of the embodiment corresponding to the memory error correction method, which will not be repeated here.

[0161] In one exemplary embodiment, the memory includes multiple cache lines; each cache line includes multiple storage units; the operating system is further configured to restart the server system where the memory resides or repair the memory if, after multiple feedback attempts to correct a set of target historical correctable errors by the basic input / output system, the correction fails.

[0162] For a description of the features in the embodiment corresponding to the server system, please refer to the relevant description of the embodiment corresponding to the memory error correction method, which will not be repeated here.

[0163] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above-described memory error correction method embodiments.

[0164] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described memory error correction method embodiments when run.

[0165] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0166] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described memory error correction method embodiments.

[0167] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described memory error correction method embodiments.

[0168] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0169] The foregoing has provided a detailed description of a memory error correction method, server system, electronic device, and storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A memory error correction method, characterized in that, include: In the event of a currently uncorrectable error in memory, extract a set of target historical correctable errors from the historical error record file that match the memory address parameters of the currently uncorrectable error; The current uncorrectable error is derived from the diffusion of the set of target historical correctable errors; The set of target historical correctable errors is corrected; wherein, after the set of target historical correctable errors is corrected, the current uncorrectable error is converted into a derived correctable error; If the set of target historical correctable errors is corrected, the derived correctable errors converted from the current uncorrectable errors are corrected in order to correct the current uncorrectable errors.

2. The method according to claim 1, characterized in that, In the event of a currently uncorrectable error in memory, the step of extracting a set of target historical correctable errors from the historical error record file that match the memory address parameters of the currently uncorrectable error includes: When the memory generates the current uncorrectable error, the physical address of the current uncorrectable error is recorded, and the physical address of the current uncorrectable error is translated into the memory address parameter of the current uncorrectable error. The memory address parameter of the current uncorrectable error is then used to search the historical error record file to obtain the set of target historical correctable errors.

3. The method according to claim 1, characterized in that, The memory includes multiple cache lines; each cache line includes multiple storage units; the memory address parameter of the current uncorrectable error is used to indicate the target encoding word where the current uncorrectable error is located; the target encoding word refers to a portion of the storage unit of the target cache line where the current uncorrectable error is located in the multiple cache lines. In the event of a currently uncorrectable error in memory, the step of extracting a set of target historical correctable errors from the historical error record file that match the memory address parameters of the currently uncorrectable error includes: When the memory generates the current uncorrectable error, multiple historical correctable errors in the target codeword are extracted from the historical error record file, and the extracted multiple historical correctable errors are determined as the set of target historical correctable errors.

4. The method according to claim 1, characterized in that, The memory includes multiple cache lines, and each cache line includes multiple storage units; the correction of the set of target historical correctable errors includes: A set of correction combinations is determined corresponding to the set of target historical correctable errors; the correction combination in the set of correction combinations refers to a set of different correction methods that perform a reversal operation on the data bits of the storage unit where the target historical correctable error is located in the set of target historical correctable errors; the reversal operation refers to the operation of changing the binary state of the data bits of the storage unit where the target historical correctable error is located in the set of target historical correctable errors. The set of target historical correctable errors are corrected according to the correction combination in the set of correction combinations.

5. The method according to claim 4, characterized in that, The determination of a set of correction combinations corresponding to the set of target historical correctable errors includes: A correction combination is determined by reversing the data bits of the storage unit containing one of the target historical correctable errors in the group of target historical correctable errors, while keeping the data bits of the remaining target historical correctable errors in the group unchanged.

6. The method according to claim 4, characterized in that, The step of correcting the set of target historical correctable errors according to the correction combination in the set of correction combinations includes: The set of correction combinations is traversed sequentially, and the currently traversed correction combination in the set of correction combinations is taken as the current correction combination; the current correction combination is used to indicate the reversal operation for the target historical correctable error specified in the set of target historical correctable errors. According to the current correction combination, a reversal operation is performed on the target historical correctable errors specified in the set of target historical correctable errors, and after the reversal operation is performed, the data bits of the storage unit where the set of target historical correctable errors is located are reread. If the data bits of the storage unit where the target historical correctable error is located are read correctly and the read data is valid, it is determined that the target historical correctable error has been corrected.

7. The method according to claim 6, characterized in that, The method further includes: If the data bit of the storage unit where the target historical correctable error is located is not read correctly or the read data is invalid, a correction combination is selected from the remaining correction combinations other than the current correction combination in the set of correction combinations as a new current correction combination. Based on the new current correction combination, the step of performing the reversal operation on the target historical correctable error specified in the set of target historical correctable errors according to the current correction combination is returned to continue execution until the set of target historical correctable errors is corrected, or until all the correction combinations in the set have been traversed.

8. The method according to claim 7, characterized in that, The method further includes: If all of the corrective combinations have been traversed and the set of target historical correctable errors have not been corrected, restart the server system where the memory resides or repair the memory.

9. The method according to claim 1, characterized in that, The step of correcting derived correctable errors converted from the current uncorrectable errors, when the set of target historical correctable errors has been corrected, to correct the current uncorrectable errors, includes: When the set of target historical correctable errors is corrected, the data bits of the storage cell where the current uncorrectable error is converted into a derived correctable error are located are reversed to correct the current uncorrectable error; the reversal operation refers to the operation of changing the binary state of the data bits of the storage cell where the current uncorrectable error is converted into a derived correctable error is located.

10. The method according to any one of claims 1 to 9, characterized in that, The method further includes: After the current uncorrectable error is corrected, the memory page containing the target codeword where the current uncorrectable error occurred is isolated.

11. The method according to claim 10, characterized in that, The memory includes multiple cache lines; each cache line includes multiple storage units; isolating the memory page containing the target encoded word where the current uncorrectable error is located includes: The memory page containing the target codeword where the current uncorrectable error is located is marked as unavailable, thereby isolating the memory page containing the target codeword from available memory resources; the target codeword includes a portion of the storage unit of the target cache line in which the current uncorrectable error is located in the plurality of cache lines.

12. The method according to any one of claims 1 to 9, characterized in that, The method further includes: When a correctable error occurs in the memory, the data bits of the storage cell containing the correctable error are reversed to correct the correctable error; the reversal operation refers to the operation of changing the binary state of the data bits of the storage cell containing the correctable error.

13. The method according to claim 12, characterized in that, The memory includes multiple cache lines, and each cache line includes multiple storage units; the set of target history correctable errors includes at least one of the following error types: cell error, column error; the cell error refers to an error that occurs in one of the multiple storage units; The column error refers to an error occurring in a storage cell that is in the same column among the plurality of storage cells; The method further includes: The error information of the currently correctable error is recorded in the historical error record file, and it is determined whether there are other historical correctable errors in the historical error record file that are in the same column as the storage unit where the currently correctable error is located; If there are no other historical correctable errors in the same column as the memory cell where the current correctable error is located, the error type of the current correctable error is determined to be the cell error; If there are other historical correctable errors in the same column as the memory cell where the current correctable error is located, mark that multiple memory cells in the memory column where the current correctable error is located have all experienced correctable errors, record the error information of the correctable errors that occurred in the multiple memory cells in the memory column where the current correctable error is located in the historical error record file, and determine the error type of the correctable errors that occurred in the multiple memory cells in the memory column where the current correctable error is located as the column error.

14. A server system, characterized in that, include: Memory is used to store data; The memory controller is used to read data stored in the memory and, in the event of a current uncorrectable error in the memory, send an uncorrectable error interrupt to the basic input / output system. The basic input / output system is used to report the uncorrectable error interrupt to the operating system; The operating system is used to start an exception handler, generate a system interrupt after the exception handler detects the current uncorrectable error, and feed the system interrupt back to the basic input / output system. The basic input / output system is also used to send data acquisition instructions to the baseboard management controller to obtain historical correctable errors stored in the historical error log file; The baseboard management controller is used to respond to the data acquisition command and feed back a set of target historical correctable errors that match the memory address parameters of the current uncorrectable error in the historical error record file to the basic input / output system; The basic input / output system is also used to correct the set of target historical correctable errors; wherein, after the set of target historical correctable errors is corrected, the current uncorrectable error is converted into a derived correctable error; and when the set of target historical correctable errors is corrected, the derived correctable error converted from the current uncorrectable error is corrected to correct the current uncorrectable error.

15. The server system according to claim 14, characterized in that, The basic input / output system is also used to perform multiple feedback attempts to correct the set of target historical correctable errors; The memory controller is also used to refresh the encoded word, re-perform error checking and correction verification, and feed back the correction results to the basic input / output system; The basic input / output system is further configured to continuously attempt to correct the set of target historical correctable errors in a feedback manner when the feedback correction result indicates that the basic input / output system has failed to successfully correct the set of target historical correctable errors.

16. The server system according to claim 15, wherein the memory includes multiple cache lines; each cache line includes multiple storage units; characterized in that, The operating system is also used to isolate the memory page where the target codeword of the current uncorrectable error is located, when the feedback correction result indicates that the basic input / output system has successfully corrected a set of target historical correctable errors; The target codeword refers to a portion of the storage unit of the target cache line in which the current uncorrectable error is located among the multiple cache lines.

17. The server system according to claim 15 or 16, characterized in that, The memory includes multiple cache lines; each cache line in the multiple cache lines includes multiple storage units; The operating system is also used to restart the server system where the memory resides or repair the memory if the basic input / output system fails to correct the set of target historical correctable errors after multiple feedback attempts.

18. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the memory error correction method as described in any one of claims 1 to 13 when executing the computer program.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the memory error correction method as described in any one of claims 1 to 13.

20. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the memory error correction method as described in any one of claims 1 to 13.

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