FPGA-based SATA bus system and implementation method thereof

Abstract

The invention discloses an SATA (Serial Advanced Technology Attachment) bus system based on an FPGA (Field Programmable Gate Array) and an implementation method thereof, and the SATA bus system comprises a hierarchical protocol processing unit which is used for realizing command analysis, data encapsulation, channel coding and signal conversion functions; the control module is used for receiving a read-write command and read-write parameters sent by the host, and then controlling the hierarchical protocol processing unit to read target data of the storage device according to the read-write command and the read-write parameters, or controlling the hierarchical protocol processing unit to write the target data into the storage device; the command and data processing module is used for caching read-write commands, read-write parameters and upper computer data in FIFO (First In First Out) in a layered manner; and the test data processing module is used for testing whether the storage equipment reads and writes the data normally to obtain a test result. According to the method, the interface design is simple and clear, the delay is low, the data reading and writing function of the storage medium can be tested without intervention of a host or a CPU, and the method can be widely applied to the technical field of serial advanced technology accessory interface control.

Description

Technical Field

[0001] The present invention relates to the field of serial advanced technology attachment interface control technology, in particular to a SATA bus system based on FPGA and an implementation method thereof. Background Art

[0002] The SATA (Serial Advanced Technology Attachment) bus is a high-speed serial data transmission bus, while the FPGA (Field Programmable Gate Array) is a programmable logic device with flexible and adaptable use. FPGA-based SATA bus implementation technology leverages the FPGA's flexibility and programmability to implement the SATA 3.0 bus protocol, meeting the high-speed data transmission requirements of mass storage devices and enabling rapid data writing and reading. However, existing FPGA-based SATA bus implementation technology has the following drawbacks:

[0003] 1. DDR (Double Data Rate Synchronous Dynamic RAM) is required as a cache. Data to be written must be cached in the DDR first, then read from the DDR and written to the storage medium via the SATA interface. Alternatively, data must be read from the SATA interface first, cached in the DDR, and finally read from the DDR and sent to the host or CPU (central processing unit). Using DDR requires access through an external interface, resulting in high latency and requiring additional hardware support, such as a DDR controller, which increases the complexity and cost of PCB design.

[0004] 2. The host or CPU needs to intervene to send data for testing to test whether the storage medium read and write access is normal. Without a host or CPU, the storage medium cannot be tested;

[0005] 3. The user end uses a wide variety of interfaces and the interface timing is complex. Summary of the Invention

[0006] To solve the above technical problems, the purpose of the present invention is to provide an FPGA-based SATA bus system and its implementation method with low latency, no need for host or CPU to test storage media, and simple port design.

[0007] To achieve the above objectives, one aspect of an embodiment of the present application provides an FPGA-based SATA bus system, comprising:

[0008] A layered protocol processing unit connected to the storage device for implementing command parsing, data encapsulation, channel coding, and signal conversion functions to enable end-to-end communication between the host and the storage device in accordance with the SATA protocol;

[0009] a control module connected to the layered protocol processing unit and configured to receive read and write commands and read and write parameters sent by the host, and then control the layered protocol processing unit to read target data from the storage device or control the layered protocol processing unit to write the target data to the storage device according to the read and write commands and the read and write parameters;

[0010] A command and data processing module, connected to the control module, for caching the read and write commands, the read and write parameters, and the host computer data in a hierarchical manner in a FIFO;

[0011] A test data processing module is connected to the control module and is used to test whether the storage device reads and writes data normally and obtain a test result.

[0012] In some embodiments, the layered protocol processing unit includes:

[0013] An application layer module, connected to the control module, for parsing the read and write commands and the read and write parameters to generate a FIS data structure that complies with the SATA protocol;

[0014] a transport layer module, connected to the application layer module, configured to frame the FIS data structure and send the framed FIS data structure to the link layer module, or parse the frame data sent by the link layer module and send the parsed frame data to the application layer module;

[0015] A link layer module, connected to the transport layer module, for performing data processing on the frame data;

[0016] A physical layer module, to which the link layer module and the storage device are both connected, is used to establish a physical link for data transmission between the host and the storage device, and to perform bidirectional conversion between serial data and parallel data.

[0017] In some embodiments, the transport layer module includes:

[0018] a first data sending module, to which both the application layer module and the link layer module are connected, configured to receive the FIS data structure sent by the application layer module, perform data framing on the FIS data structure to obtain the frame data, and then send the frame data to the link layer module;

[0019] The first data receiving module, the application layer module and the link layer module are both connected to the first data receiving module, and are used to receive the frame data sent by the link layer module, parse the frame data, and determine the FIS type of the frame data, and then send the parsing result to the application layer module according to the FIS type.

[0020] In some embodiments, the link layer module includes:

[0021] a second data sending module, wherein both the transport layer module and the physical layer module are connected to the second data sending module, and is configured to receive the first frame data sent by the transport layer module, perform CRC check and scrambling on the first frame data, and then send the first frame data after CRC check and scrambling to the physical layer module;

[0022] A second data receiving module, wherein the transport layer module and the physical layer module are both connected to the second data receiving module, and is used to receive the second frame data sent by the physical layer module, perform CRC check and descrambling on the second frame data, and then send the second frame data after CRC check and descrambling to the transport layer module.

[0023] In some embodiments, the physical layer module includes:

[0024] a high-speed serial transceiver, connected to the storage device and configured to perform bidirectional conversion between the serial data and the parallel data;

[0025] an initialization state machine, the initialization state machine being connected to the high-speed serial transceiver and being used to reset the high-speed serial transceiver;

[0026] A data transceiver control module, wherein the high-speed serial transceiver and the link layer module are both connected to the data transceiver control module, and are used to transmit the target data sent by the storage device to the link layer module, or transmit the target data sent by the link layer module to the storage device.

[0027] To achieve the above-mentioned purpose, another aspect of the present invention provides a method for implementing a SATA bus system based on an FPGA, comprising the following steps:

[0028] The layered protocol processing unit implements command parsing, data encapsulation, channel coding, and signal conversion functions to enable end-to-end communication between the host and storage device in accordance with the SATA protocol.

[0029] receiving, through the control module, a read / write command and a read / write parameter sent by the host, and then controlling the layered protocol processing unit to read target data from the storage device or to write the target data to the storage device according to the read / write command and the read / write parameter;

[0030] The read and write commands, the read and write parameters and the host computer data are hierarchically cached in a FIFO through a command and data processing module;

[0031] The test data processing module tests whether the storage device reads and writes data normally, and obtains a test result.

[0032] In some embodiments, the receiving, through the control module, read and write commands and read and write parameters sent by the host, and then controlling the layered protocol processing unit to read target data from the storage device or controlling the layered protocol processing unit to write the target data to the storage device according to the read and write commands and the read and write parameters, specifically includes:

[0033] receiving the read / write command and the read / write parameters sent by the host, wherein the read / write parameters include a sector start address and a sector quantity;

[0034] Parsing the read and write commands to obtain command types corresponding to the read and write commands;

[0035] When the command type is a write command, a write data parameter is issued, and the layered protocol processing unit is controlled to write the target data into the storage device through the read / write command and the write data parameter;

[0036] When the command type is a read command, a read data parameter is issued, and the layered protocol processing unit is controlled to read the target data of the storage device through the read and write command and the read data parameter.

[0037] In some embodiments, the FIFO includes a command parameter FIFO and a data FIFO, and the command and data processing module caches the read and write commands, the read and write parameters, and the host computer data in the FIFO in a hierarchical manner, specifically including:

[0038] Converting the read / write command and the read / write parameter into a command operator of a preset bit width, and storing the command operator in the command parameter FIFO;

[0039] Receive the host computer data sent by the host computer, and cache the host computer data in the data FIFO.

[0040] In some embodiments, the testing of whether the storage device reads and writes data normally by the test data processing module to obtain a test result specifically includes:

[0041] Generate test data, where the test data is accumulated data;

[0042] Setting a sector address to be tested, writing the test data into the storage device, and reading the test data in the sector address to be tested;

[0043] The test data and the data to be tested are verified to obtain the test result.

[0044] In some embodiments, verifying the test data and the data to be tested to obtain the test result specifically includes:

[0045] Comparing the test data with the data to be tested to see if they are consistent, and obtaining comparison data;

[0046] The error data in the comparison result are cumulatively counted to obtain the test result.

[0047] The beneficial effects of the present invention are as follows: the present invention provides an FPGA-based SATA bus system and implementation method thereof, comprising a layered protocol processing unit, a control module, a command and data processing module, and a test data processing module. On the one hand, the present invention utilizes the BRAM resources within the FPGA to construct a dual-FIFO architecture, directly caching command parameters and data through the FIFOs without requiring external interface access, resulting in lower latency and higher bandwidth. On the other hand, a test data processing module is added to test whether the storage device reads and writes data normally. This test can be performed directly through the FPGA without the intervention of a host or CPU, thus resolving the problem of being unable to test the storage device without a host or CPU. Furthermore, the present invention can implement read and write control of the storage device through the SATA interface through a simple port. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following introduction is made to the drawings required for use in the embodiments of the present invention. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative work.

[0049] Figure 1A block diagram of a SATA bus system based on FPGA provided by one embodiment of the present invention;

[0050] Figure 2 A structural block diagram of an application layer module provided in one embodiment of the present invention;

[0051] Figure 3 A flowchart of command parsing processing of an application layer module provided by one embodiment of the present invention;

[0052] Figure 4 A flowchart of a PIO DATA IN command process is provided for one embodiment of the present invention;

[0053] Figure 5 A flowchart of a PIO DATA OUT command process provided by an embodiment of the present invention;

[0054] Figure 6 A DMA IN command processing flow chart provided for an embodiment of the present invention;

[0055] Figure 7 A DMA OUT command processing flow chart provided for an embodiment of the present invention;

[0056] Figure 8 A structural block diagram of a transport layer module provided by an embodiment of the present invention;

[0057] Figure 9 A schematic diagram of a state machine jump of a TX_BUF module provided in one embodiment of the present invention;

[0058] Figure 10 A schematic diagram of a state machine jump of an RX_BUF module provided in one embodiment of the present invention;

[0059] Figure 11 A structural block diagram of a link layer module provided by an embodiment of the present invention;

[0060] Figure 12 A schematic diagram of a state machine jump of a TX control module provided by an embodiment of the present invention;

[0061] Figure 13 A schematic diagram of a state machine jump of an RX control module provided by an embodiment of the present invention;

[0062] Figure 14 A structural block diagram of a physical layer module provided in one embodiment of the present invention;

[0063] Figure 15 A schematic diagram of the initialization state machine jump provided by an embodiment of the present invention;

[0064] Figure 16A flowchart of a method for implementing an FPGA-based SATA bus system according to an embodiment of the present invention;

[0065] Figure 17 A processing flow chart of a control module provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are merely examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0067] It will be understood that the terms "first", "second", etc. used in this application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0068] The terms "at least one", "plurality", "each", "any", etc. used in this application include "at least one", "two" or more, "plurality" or "each", "any" or "any one", "each" or "any one" as used herein.

[0069] Before explaining the embodiments of the present application in detail, some of the nouns and terms involved in the embodiments of the present application are first explained. The nouns and terms involved in the embodiments of the present application are subject to the following explanations.

[0070] FPGA (Field Programmable Gate Array);

[0071] SATA (Serial Advanced Technology Attachment);

[0072] NCQ (Native Command Queuing).

[0073] The SATA bus is a high-speed serial bus data transmission bus, and FPGA is a programmable logic device with flexible and variable use. The technology of implementing SATA bus applications based on FPGA utilizes the flexibility and programmability of FPGA to implement the SATA 3.0 bus protocol, which can meet the high-speed data transmission requirements of large-capacity storage devices and realize the rapid writing and reading of data in large-capacity storage devices.

[0074] The SATA (Serial Advanced Technology Attachment) bus is a high-speed serial data transmission bus, while the FPGA (Field Programmable Gate Array) is a programmable logic device with flexible and adaptable use. FPGA-based SATA bus implementation technology leverages the FPGA's flexibility and programmability to implement the SATA 3.0 bus protocol, meeting the high-speed data transmission requirements of mass storage devices and enabling rapid data writing and reading. However, existing FPGA-based SATA bus implementation technology has the following drawbacks:

[0075] 1. DDR (Double Data Rate Synchronous Dynamic RAM) is required as a cache. Data to be written must be cached in the DDR first, then read from the DDR and written to the storage medium via the SATA interface. Alternatively, data must be read from the SATA interface first, cached in the DDR, and finally read from the DDR and sent to the host or CPU (central processing unit). Using DDR requires access through an external interface, resulting in high latency and requiring additional hardware support, such as a DDR controller, which increases the complexity and cost of PCB design.

[0076] 2. The host or CPU needs to intervene to send data for testing to test whether the storage device read and write access is normal. Without the host or CPU, the storage device cannot be tested;

[0077] 3. The user end uses a wide variety of interfaces and the interface timing is complex.

[0078] To this end, an embodiment of the present invention proposes an FPGA-based SATA bus system, comprising a layered protocol processing unit, a control module, a command and data processing module, and a test data processing module. On the one hand, the present invention uses the BRAM resources within the FPGA to construct a dual-FIFO architecture, directly caching command parameters and data through the FIFOs without requiring external interface access, resulting in lower latency and higher bandwidth. On the other hand, a test data processing module is added to test whether the storage device reads and writes data normally. This test can be performed directly through the FPGA without the intervention of a host or CPU, solving the problem of being unable to test storage devices without a host or CPU. Furthermore, the system can implement read and write control of storage devices through the SATA interface through a simple port.

[0079] Reference Figure 1 , Figure 1 This is a block diagram of a SATA bus system based on an FPGA according to an embodiment of the present invention. The present invention provides an FPGA-based SATA bus system, including:

[0080] A layered protocol processing unit is connected to the storage device and is used to implement command parsing, data encapsulation, channel coding, and signal conversion functions to enable end-to-end communication between the host and the storage device that complies with the SATA protocol;

[0081] A control module connected to the layered protocol processing unit, configured to receive read and write commands and read and write parameters sent by the host, and then control the layered protocol processing unit to read target data from the storage device or to write target data to the storage device according to the read and write commands and read and write parameters;

[0082] The command and data processing module is connected to the control module and is used to cache read and write commands, read and write parameters and host computer data in a hierarchical manner in the FIFO;

[0083] The test data processing module is connected to the control module and is used to test whether the storage device reads and writes data normally and obtain test results.

[0084] It should be noted that the user interface design of the SATA IP core in the embodiment of the present invention is relatively simple and clear. Through the control module, only command parameters, clocks, valid signals, and FIFO status signals are required to implement read and write control of the storage device through the SATA interface. This can effectively reduce the design risks caused by complex interfaces and also shorten the time it takes for users to become familiar with the technology.

[0085] The command and data processing module receives read and write commands and parameters from the CPU, converts them into 72-bit command operators, and caches them in the FIFO. The FIFO also caches data sent from the host computer. The state machine controls the SATA bus access to the storage device's sector address and data flow. The 72-bit read and write command operator format is: [31:0] indicates the number of read and write sectors, [63:32] indicates the read and write starting sector address, [65:64] indicates the read and write command, 2'b11 indicates write data, 2'b01 indicates read data, and [71:66] indicates reserved.

[0086] The test data processing module is used to generate test data to test and verify whether the SATA bus and storage device can read and write normally. The test data is accumulated data. First, the sector address to be tested is set, and then the data is written to the storage device. After writing, the data at the corresponding sector address is read out and verified. This module can directly test whether the SATA disk access is normal without the need for a host computer, solving the problem of being unable to test the storage device without a host or CPU.

[0087] In some optional embodiments, the SATA IP core design of the embodiments of the present invention follows the layered architecture of the SATA protocol specification, adopts a bottom-up modular design approach, is designed according to the model structure of the physical layer, link layer, transport layer and application layer, adopts a layer-by-layer progressive development path, and interacts between each layer through a standardized interface protocol, thereby ensuring complete compatibility with the SATA protocol and maintaining the independent scalability of each functional module.

[0088] Further as an optional implementation manner, the layered protocol processing unit includes:

[0089] The application layer module is connected to the control module and is used to parse read and write commands and parameters to generate a FIS data structure that complies with the SATA protocol;

[0090] A transport layer module, connected to the application layer module, configured to frame the FIS data structure and send the framed FIS data structure to the link layer module, or parse the frame data sent by the link layer module and send the parsed frame data to the application layer module;

[0091] The link layer module is connected to the transport layer module and is used to process the frame data;

[0092] The physical layer module, link layer module and storage device are all connected to the physical layer module, which is used to establish a physical link for data transmission between the host and the storage device and perform bidirectional conversion between serial data and parallel data.

[0093] Specifically, if Figure 2 The figure shows the structural block diagram of the application layer module, which includes the interface control module, APP control module and cache BUF module. Figure 3 The following figure shows the command parsing process flow of the application layer module. The application layer module parses the received commands and executes different command subsets in different processes. Read and write data operations include PIO and DMA methods.

[0094] Among them, the PIO DATA IN command processing flow is as follows Figure 4 As shown in the figure, the host first initializes the mapping register and sets BSY to 0. Then it writes a command to trigger the transmission, sets BSY to 1, and sends the FIS data structure to the storage device. The storage device parses the command, reads the data from the disk, and reports the data transmission ready status. The host confirms the direction through the HBA and stores the FIS content. Then the storage device sends the data to the host. The host starts to receive data and updates the mapping register. After the transmission is completed, the mapping register is updated to the end state and the end state is read. The entire PIO DATA IN command processing flow ends.

[0095] The PIO DATA OUT command processing flow is as follows: Figure 5 As shown in the figure, the host first initializes the mapping register, sets BSY to 0, then writes to the command register, sets BSY to 1, and sends the FIS data structure to the storage device; the storage device parses the command, then searches for the write location, and after being ready to receive data, sends the PIO Setup FIS to the host; after receiving the PIO Setup FIS, the host confirms the transmission direction and updates the mapping register with the content of the PIO Setup FIS, then obtains the data and sends it to the storage device; the storage device receives the data and writes it to the disk. When the transfer quantity is reached, the drive reports the write status to the host; finally, the host reads the completion status through the register FIS, and the entire PIO DATA OUT command processing flow ends.

[0096] DMA IN command processing flow is as follows Figure 6 As shown in the figure, the host first sends an H2D FIS to the storage device. After receiving the H2D FIS, the storage device updates its ATA register and prepares to read data from the disk. After the read operation is completed, the read data is encapsulated into a DATA FIS, and then the HBA transmits the data to the host. After the host receives the data, it writes it to the cache. Subsequently, the storage device sends a Register FIS to the host to report the command completion status. Finally, after the transfer is complete, the mapping register is updated to the end status and the read completion status, and the entire DMA IN command processing flow ends.

[0097] DMA OUT command processing flow is as follows Figure 7 As shown in the figure, the host first sends an H2D FIS to the storage device. After receiving the H2D FIS, the storage device updates its ATA register to notify the host that it is ready to receive data. The host obtains data from the cache through the HBA, encapsulates the data into a Data FIS, and sends it to the storage device. The storage device receives the data and writes it to the disk, reporting the command completion status. Finally, after the transfer is complete, the mapping register is updated to the end status and the completion status is read, and the entire DMAOUT command processing flow ends.

[0098] Reference Figure 8 , Figure 8 This is a structural block diagram of a transport layer module provided in one embodiment of the present invention. As an optional implementation, the transport layer module includes:

[0099] A first data sending module, to which both the application layer module and the link layer module are connected, is configured to receive the FIS data structure sent by the application layer module, perform data framing on the FIS data structure to obtain frame data, and then send the frame data to the link layer module;

[0100] The first data receiving module, the application layer module and the link layer module are all connected to the first data receiving module, and are used to receive the frame data sent by the link layer module, parse the frame data, and determine the FIS type of the frame data, and then send the parsing result to the application layer module according to the FIS type.

[0101] Specifically, the transport layer module is divided into two parts: sending and receiving, which are responsible for sending and receiving frame data respectively. Figure 8 The green part in the middle represents the sending part (ie, the first data sending module), and the blue part represents the receiving part (ie, the first data receiving module).

[0102] Among them, TX_BUF in the first data sending module is used to cache the data sent by the transport layer; the transport layer TX sending control module mainly implements the state machine of the transport layer sending control, and its state machine jumps as follows Figure 9 As shown, Figure 9 The status descriptions are as follows:

[0103] trn_tx_idle: initial state;

[0104] trn_tx_cmd_fis: send H2D register FIS;

[0105] trn_tx_cmd_status: waiting for sending to complete;

[0106] trn_tx_cmd_fis_done: sending process completed;

[0107] trn_tx_pio_data_fis_pre: PIO FIS send;

[0108] trn_tx_pio_data_fis: send data;

[0109] trn_tx_pio_data_fis_done: data sending completed;

[0110] trn_tx_dma_data_fis_pre: DMA data transmission;

[0111] trn_tx_dma_data_fis: send data conversion;

[0112] trn_tx_dma_data_fis_done: DMA data transmission completed.

[0113] The RX_BUF in the first data receiving module is used to cache the data received by the transport layer; the transport layer RX sending control module mainly implements the state machine of the transport layer receiving control, and its state machine jumps as follows Figure 10 As shown, Figure 10 The status descriptions are as follows:

[0114] trn_rx_idle: initial state;

[0115] trn_rx_chk_type: Detects whether the received data is a data FIS or a non-data FIS. If it is a data FIS, it jumps to the trn_rx_data_type state for processing; otherwise, it jumps to the trn_rx_nodata state for processing;

[0116] trn_rx_data_type: starts reading data from the link layer BUF;

[0117] trn_rx_data: reads data until the data length is reached and stops reading;

[0118] trn_rx_crc: checks the correctness of received data;

[0119] trn_rx_nodata: non-data FIS reception;

[0120] trn_rx_nodata_req: sends a non-data FIS request to the application layer;

[0121] trn_rx_nodata_ack: Receives the non-data FIS response from the application layer.

[0122] Reference Figure 11 , Figure 11 This is a structural block diagram of a link layer module provided in one embodiment of the present invention. As an optional implementation, the link layer module includes:

[0123] A second data sending module, the transport layer module and the physical layer module are both connected to the second data sending module, and is used to receive the first frame data sent by the transport layer module, perform CRC check and scrambling on the first frame data, and then send the first frame data after CRC check and scrambling to the physical layer module;

[0124] The second data receiving module, the transport layer module and the physical layer module are both connected to the second data receiving module, and are used to receive the second frame data sent by the physical layer module, perform CRC check and descrambling on the second frame data, and then send the second frame data after CRC check and descrambling to the transport layer module.

[0125] Specifically, the link layer module is divided into two parts: sending and receiving, which are responsible for sending and receiving frame data respectively. Figure 11 The green part in the middle represents the sending part (ie, the second data sending module), and the blue part represents the receiving part (ie, the second data receiving module).

[0126] The second data transmission module is mainly composed of TX_BUF, TX control module, CRC module and scrambling module. TX_BUF is used to buffer the data sent by the transport layer; the CRC module is used to implement the CRC check function, and its generating polynomial is: G(x) = x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x+1, CRC check calculates all data between SOF and EOF in each frame except the primitive, and puts the CRC value between the last data bit and EOF after check. Before each frame check starts, the CRC check value is initialized to 0x52325032; the scrambling module scrambles all data between SOF and EOF except the primitive, and its scrambler characteristic equation is: G(x)=x 16 +x 15 +x 13 +x 4 +1; TX control module mainly implements the state machine of link layer transmission control, and its state machine jumps as follows Figure 12 As shown, Figure 12 The status descriptions are as follows:

[0127] IDLE: initial state;

[0128] CMD: command parsing;

[0129] PRI_PROD: Generate primitives;

[0130] DATA_RX_TRN: receives data sent by the transport layer;

[0131] CRC: CRC calculation;

[0132] SCRAMBLE: data scrambling;

[0133] DATA_TX: data transmission;

[0134] DATA_TX_DONE: Data transmission is completed.

[0135] The second data receiving module is mainly composed of RX_BUF, RX control module, CRC module and descrambling module. The descrambling module is used to descramble all data except the primitive between SOF and EOF; the CRC module is used to implement the CRC check function; RX_BUF is used to cache the data sent to the transport layer; the RX control module mainly implements the state machine of the link layer receiving control, and its state machine jump is as follows Figure 13 As shown, Figure 13 The state design in is as follows:

[0136] IDLE: initial state;

[0137] RX_CHK: data frame transmission;

[0138] DESCRAMBLE: data frame sent;

[0139] DATA_RX: data frame sending ends;

[0140] CRC: CRC calculation;

[0141] CRC_CHK: CRC check;

[0142] RX_DONE: Data reception is completed.

[0143] Reference Figure 14 , Figure 14 This is a structural block diagram of a physical layer module provided in one embodiment of the present invention. As an optional implementation, the physical layer module includes:

[0144] A high-speed serial transceiver is connected to the storage device and is used for bidirectional conversion between serial data and parallel data;

[0145] An initialization state machine, the initialization state machine is connected to the high-speed serial transceiver and is used to reset the high-speed serial transceiver;

[0146] The data transceiver control module, the high-speed serial transceiver and the link layer module are all connected to the data transceiver control module, and are used to transmit the target data sent by the storage device to the link layer module, or transmit the target data sent by the link layer module to the storage device.

[0147] Specifically, the physical layer module is mainly composed of a high-speed serial transceiver, an initialization state machine, and a transceiver data control module. The high-speed serial transceiver mainly completes the conversion of parallel data to serial data, 8B / 10B encoding, and clock generation and recovery. The initialization state machine mainly completes the reset function and status output function of the high-speed serial transceiver. The transceiver data control mainly controls the reception of data to be sent from the link layer and the sending of the received data to the link layer. The initialization state machine jumps as follows Figure 15 As shown, Figure 15 The status descriptions are as follows:

[0148] gt_reset: reset the high-speed serial transceiver;

[0149] ssd_reset: reset SSD hardware;

[0150] phy_reset: physical layer reset;

[0151] phy_await_cominit: waits for receiving COMINIT signal;

[0152] phy_comwake: send COMWAKE signal;

[0153] phy_await_comwake: wait for receiving COMWAKE signal;

[0154] phy_await_active: activated;

[0155] phy_await_align: wait for device align primitive;

[0156] phy_send_align: send align primitive;

[0157] phy_wait_ready: issues a SYNC primitive and waits to receive a non-ALIGN primitive;

[0158] phy_get_ready: Link establishment is complete.

[0159] The above describes the structure and operating principle of the FPGA-based SATA bus system according to the embodiment of the present invention. It can be seen that compared with the existing FPGA-based technology for implementing SATA bus applications, the embodiment of the present invention has the following advantages:

[0160] 1. The user interface design of the present invention is concise and clear, and users can quickly become familiar with and call the IP;

[0161] Second, the present invention adds a test data processing module, through which the storage device is tested to see whether it reads and writes data normally, and the hardware environment can be tested without the intervention of the CPU;

[0162] 3. The present invention uses the internal FIFO of FPGA as data cache, avoiding the use of external DDR as cache, and is used for stacking command parameters and data, which can reduce hardware cost and PCB space.

[0163] Reference Figure 16 , Figure 16 This is a flowchart of a method for implementing a SATA bus system based on an FPGA according to an embodiment of the present invention. The embodiment of the present invention further provides a method for implementing a SATA bus system based on an FPGA, comprising the following steps S101 to S104:

[0164] S101, implementing command parsing, data encapsulation, channel coding, and signal conversion functions through a layered protocol processing unit to enable end-to-end communication between a host and a storage device that complies with the SATA protocol;

[0165] S102: receiving, through the control module, a read / write command and a read / write parameter sent by the host, and then controlling the layered protocol processing unit to read target data from the storage device or to write the target data to the storage device according to the read / write command and the read / write parameter;

[0166] S103, cache the read and write commands, read and write parameters and host computer data in FIFO by the command and data processing module;

[0167] S104: Test whether the storage device reads and writes data normally through the test data processing module to obtain a test result.

[0168] Reference Figure 17 , Figure 17 This is a processing flow chart of a control module provided in an embodiment of the present invention. As an optional implementation, step S102 can be further divided into the following steps S1021 to S1024:

[0169] S1021, receiving a read / write command and read / write parameters sent by the host, where the read / write parameters include a sector start address and a sector quantity;

[0170] S1022, parsing the read and write commands to obtain command types corresponding to the read and write commands;

[0171] S1023: When the command type is a write command, write data parameters are issued, and the layered protocol processing unit is controlled to write the target data into the storage device through the read / write command and the write data parameters;

[0172] S1024: When the command type is a read command, a read data parameter is issued, and the layered protocol processing unit is controlled to read the target data of the storage device through the read and write command and the read data parameter.

[0173] Specifically, when it is necessary to write target data to a storage device via a SATA interface, the user only needs to send a write command, write sector start address, and write sector quantity parameters according to timing requirements, and then write the data. The corresponding data can be processed according to the instructions of the write command and written to the storage device. When it is necessary to read target data from a storage device via a SATA interface, the user only needs to send a read command, read sector start address, and read sector quantity parameters according to timing requirements, and then wait for the target data to be returned. The user can then obtain the target data from the cache. The embodiment of the present invention can implement read and write control of a storage device via a SATA interface in a simple port manner, effectively reducing design risks caused by complex interfaces. It can also reduce the learning time of users using this technology, allowing users to quickly implement storage device read and write control without having to pay attention to the details of the underlying protocol, significantly shortening the product development cycle.

[0174] As an optional implementation, the FIFO includes a command parameter FIFO and a data FIFO, and step S103 can be further divided into the following steps S1031 and S1032:

[0175] S1031, converting the read / write command and the read / write parameter into a command operator of a preset bit width, and storing the command operator in a command parameter FIFO;

[0176] S1032: Receive the host computer data sent by the host computer, and cache the host computer data in the data FIFO.

[0177] Specifically, some existing technologies need to use DDR as a cache, first caching the data to be written in DDR, then reading it from DDR and writing it to the storage medium through the SATA interface, or first reading the data through the SATA interface, then caching it in DDR, and finally reading it from DDR and sending it to the host or CPU. The embodiment of the present invention uses the BRAM resources inside the FPGA to build a dual FIFO architecture, and generates the operation command parameter FIFO and data FIFO respectively through the vivado software to realize data and command layered caching. The data FIFO depth is 8192 and the bit width is 64 bits, and the command parameter FIFO depth is 1024 and the bit width is 72 bits, which are used to stack command parameters and data. The read and write commands and read and write parameters issued by the CPU are received through the command and data processing module, and the commands and parameters are converted into command operators with a bit width of 72 bits, which are cached in the command parameter FIFO. At the same time, the data FIFO is used to cache the data issued by the host computer, and the SATA bus is controlled by the state machine to access the sector address and data flow of the storage device. The advantages of using FIFO for data caching are low latency and high bandwidth. Because BRAM is internal to the FPGA, it has fast access speeds. Using DDR requires access through an external interface, resulting in higher latency and requiring additional hardware support, such as a DDR controller. This increases the complexity and cost of PCB design. This embodiment of the present invention uses the FPGA's internal FIFO as a data cache, eliminating the need for external DDR, reducing hardware costs and PCB space.

[0178] As an optional implementation, step S104 may be further divided into the following steps S1041 to S1043:

[0179] S1041. Generate test data, which is accumulated data;

[0180] S1042, setting the address of the sector to be tested, writing the test data into the storage device, and reading the test data in the address of the sector to be tested;

[0181] S1043. Verify the test data and the data to be tested to obtain the test results.

[0182] As an optional implementation, step S1043 may be further divided into the following steps S10431 and S10432:

[0183] S10431. Compare the test data and the data to be tested to see if they are consistent, and obtain comparison data;

[0184] S10432. Accumulate and count the error data in the comparison result to obtain the test result.

[0185] Specifically, the test data processing module generates test data, writes the test data to the storage medium through the SATA bus, and then reads the data from the storage medium to compare whether the read data and the written data are consistent, and performs a cumulative count of data errors. Furthermore, this function can be turned on or off through parameter configuration, and the storage medium can be partitioned or fully tested by setting parameters. This function can be used to directly use FPGA to test whether the hardware circuit is normal and whether the storage medium can be read and written normally. In the prior art, the host or CPU needs to intervene to send data for testing in order to test whether the storage medium can be read and written normally. The embodiment of the present invention does not require the intervention of the host or CPU, but can be tested directly through the FPGA, solving the problem that the storage medium cannot be tested in the absence of a host or CPU.

[0186] It should be appreciated that embodiments of the present invention can be implemented or practiced by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable memory. The above methods can be implemented in a computer program using standard programming techniques—including a non-transitory computer-readable storage medium configured with a computer program, wherein the storage medium so configured causes the computer to operate in a specific and predefined manner—according to the methods and figures described in the specific embodiments. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if desired, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. In addition, the program can be run on a programmed application-specific integrated circuit for this purpose.

[0187] Furthermore, the operations of the processes described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by the context. The processes described herein (or variations and / or combinations thereof) may be performed under the control of one or more computer systems configured with executable instructions and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that is executed collectively on one or more processors, by hardware, or a combination thereof. The computer programs described above include a plurality of instructions that may be executed by one or more processors.

[0188] Furthermore, the above methods can be implemented in any type of computing platform that is operably connected to a suitable computer, including but not limited to a personal computer, a minicomputer, a mainframe, a workstation, a network or distributed computing environment, a separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, etc. Various aspects of the present invention can be implemented as machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, an optical read and / or write storage medium, RAM, ROM, etc., so that it can be read by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the processes described herein. In addition, the machine-readable code, or portions thereof, can be transmitted over a wired or wireless network. When such media includes instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor, the invention described herein includes these and other different types of non-transitory computer-readable storage media. When programmed according to the methods and techniques described herein, the present invention also includes the computer itself.

[0189] The computer program can be applied to input data to perform the functions described herein, thereby converting the input data to generate output data that is stored in a non-volatile memory. The output information can also be applied to one or more output devices such as a display. In a preferred embodiment of the present invention, the converted data represents a physical and tangible object, including a specific visual depiction of the physical and tangible object produced on the display.

[0190] In the above description of this specification, reference to the terms "one embodiment / example," "another embodiment / example," or "certain embodiments / examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0191] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

[0192] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A SATA bus system based on FPGA, characterized in that: include: A layered protocol processing unit connected to the storage device for implementing command parsing, data encapsulation, channel coding, and signal conversion functions to enable end-to-end communication between the host and the storage device in accordance with the SATA protocol; a control module connected to the layered protocol processing unit and configured to receive read and write commands and read and write parameters sent by the host, and then control the layered protocol processing unit to read target data from the storage device or control the layered protocol processing unit to write the target data to the storage device according to the read and write commands and the read and write parameters; A command and data processing module, connected to the control module, for caching the read and write commands, the read and write parameters, and the host computer data in a hierarchical manner in a FIFO; A test data processing module is connected to the control module and is used to test whether the storage device reads and writes data normally and obtain a test result.

2. The FPGA-based SATA bus system according to claim 1, wherein: The layered protocol processing unit includes: An application layer module, connected to the control module, for parsing the read and write commands and the read and write parameters to generate a FIS data structure that complies with the SATA protocol; a transport layer module, connected to the application layer module, configured to frame the FIS data structure and send the framed FIS data structure to the link layer module, or parse the frame data sent by the link layer module and send the parsed frame data to the application layer module; A link layer module, connected to the transport layer module, for performing data processing on the frame data; A physical layer module, to which the link layer module and the storage device are both connected, is used to establish a physical link for data transmission between the host and the storage device, and to perform bidirectional conversion between serial data and parallel data.

3. The FPGA-based SATA bus system according to claim 2, wherein: The transport layer module includes: a first data sending module, to which both the application layer module and the link layer module are connected, configured to receive the FIS data structure sent by the application layer module, perform data framing on the FIS data structure to obtain the frame data, and then send the frame data to the link layer module; The first data receiving module, the application layer module and the link layer module are both connected to the first data receiving module, and are used to receive the frame data sent by the link layer module, parse the frame data, and determine the FIS type of the frame data, and then send the parsing result to the application layer module according to the FIS type.

4. The FPGA-based SATA bus system according to claim 2, wherein: The link layer module includes: a second data sending module, wherein both the transport layer module and the physical layer module are connected to the second data sending module, and is configured to receive the first frame data sent by the transport layer module, perform CRC check and scrambling on the first frame data, and then send the first frame data after CRC check and scrambling to the physical layer module; A second data receiving module, wherein the transport layer module and the physical layer module are both connected to the second data receiving module, and is used to receive the second frame data sent by the physical layer module, perform CRC check and descrambling on the second frame data, and then send the second frame data after CRC check and descrambling to the transport layer module.

5. The FPGA-based SATA bus system according to claim 2, wherein: The physical layer module includes: a high-speed serial transceiver, connected to the storage device and configured to perform bidirectional conversion between the serial data and the parallel data; an initialization state machine, the initialization state machine being connected to the high-speed serial transceiver and being used to reset the high-speed serial transceiver; A data transceiver control module, wherein the high-speed serial transceiver and the link layer module are both connected to the data transceiver control module, and are used to transmit the target data sent by the storage device to the link layer module, or transmit the target data sent by the link layer module to the storage device.

6. A method for implementing a SATA bus system based on FPGA, for implementing the SATA bus system based on FPGA according to any one of claims 1 to 5, characterized in that: The following steps are involved: The layered protocol processing unit implements command parsing, data encapsulation, channel coding, and signal conversion functions to enable end-to-end communication between the host and storage device in accordance with the SATA protocol. receiving, through the control module, a read / write command and a read / write parameter sent by the host, and then controlling the layered protocol processing unit to read target data from the storage device or to write the target data to the storage device according to the read / write command and the read / write parameter; The read and write commands, the read and write parameters and the host computer data are hierarchically cached in a FIFO through a command and data processing module; The test data processing module tests whether the storage device reads and writes data normally, and obtains a test result.

7. The implementation method according to claim 6, characterized in that: The receiving, through the control module, a read / write command and a read / write parameter sent by the host, and then controlling the layered protocol processing unit to read target data from the storage device or controlling the layered protocol processing unit to write the target data to the storage device according to the read / write command and the read / write parameter, specifically includes: receiving the read / write command and the read / write parameters sent by the host, wherein the read / write parameters include a sector start address and a sector quantity; Parsing the read and write commands to obtain command types corresponding to the read and write commands; When the command type is a write command, a write data parameter is issued, and the layered protocol processing unit is controlled to write the target data into the storage device through the read / write command and the write data parameter; When the command type is a read command, a read data parameter is issued, and the layered protocol processing unit is controlled to read the target data of the storage device through the read and write command and the read data parameter.

8. The implementation method according to claim 6, characterized in that: The FIFO includes a command parameter FIFO and a data FIFO, and the command and data processing module caches the read and write commands, the read and write parameters, and the host computer data in the FIFO in a hierarchical manner, specifically including: Converting the read / write command and the read / write parameter into a command operator of a preset bit width, and storing the command operator in the command parameter FIFO; Receive the host computer data sent by the host computer, and cache the host computer data in the data FIFO.

9. The implementation method according to claim 6, characterized in that: The step of testing whether the storage device reads and writes data normally by the test data processing module and obtaining a test result specifically includes: Generate test data, where the test data is accumulated data; Setting a sector address to be tested, writing the test data into the storage device, and reading the test data in the sector address to be tested; The test data and the data to be tested are verified to obtain the test result.

10. The implementation method according to claim 9, characterized in that: Verifying the test data and the data to be tested to obtain the test result specifically includes: Comparing the test data with the data to be tested to see if they are consistent, and obtaining comparison data; The error data in the comparison result are cumulatively counted to obtain the test result.

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