Defect detection method of super-large-scale integrated circuit, computer equipment and storage medium

Abstract

The embodiment of the invention provides a defect detection method for a super-large-scale integrated circuit, computer equipment and a storage medium. The method comprises the steps that a to-be-tested super-large-scale integrated circuit is divided into a plurality of basic function areas, and each basic function area is used for achieving a corresponding basic function; analyzing a logic tree of a test sample, and selecting at least one target basic function area associated with the logic tree of the test sample from the plurality of basic function areas; arranging and combining the selected target basic functional areas based on the logic tree of the test sample to obtain a to-be-tested functional area combination; and testing the functional region combination to be tested by using the test sample to determine the logic defects among the target basic functional regions in the functional region combination to be tested, and the method can be used for detecting the logic defects in the super-large-scale integrated circuit.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit defect detection, and in particular to a defect detection method, computer equipment, and storage medium for ultra-large-scale integrated circuits. Background Art

[0002] As the latest generation of very large-scale integrated circuits, graphics processing units (GPUs) and neural network processing units (NPUs) have a very large number of integrated circuit components per unit area (usually more than 100,000). As the requirements for the comprehensive performance of very large-scale integrated circuits continue to increase, they are iteratively developing towards larger and larger areas.

[0003] In practical applications, due to design or processing reasons, certain logical structure defects often exist in ultra-large-scale integrated circuits. The existence of these logical structure defects often affects normal operation, so defect detection is usually required. For example, patent CN202410188249.3 discloses a method for detecting integrated circuit defects. This method uses ultrasonic scanning to scan cracks in integrated circuits. However, for ultra-large-scale integrated circuits (such as GPUs), this method has poor detection accuracy and efficiency because the area and integration density of circuit components of ultra-large-scale integrated circuits are significantly greater than those of general integrated circuits. Patent CN202310765827.0 discloses a high-precision real-time detection method for wafer surface defects based on CUDA acceleration. This method uses an image acquisition platform to scan and collect surface images of the wafer to be detected multiple times, and then splices them to obtain a complete spliced ​​image of the wafer. The defect map of each local wafer surface image is drawn on the complete spliced ​​image of the wafer based on the defect information of each local wafer surface image, thereby obtaining the global position and defect information of all defects on the surface of the wafer to be detected. The method disclosed in this patent mainly detects hardware defects on the wafer surface, but cannot detect defects in the chip logic structure.

[0004] In particular, for ultra-large-scale integrated circuits such as GPUs and NPUs, due to the high integration density of circuit components and relatively large area, their logical structure is relatively complex, which also increases the difficulty of detecting logical structure defects. Therefore, it is necessary to provide defect detection solutions for ultra-large-scale integrated circuits. Summary of the Invention

[0005] The purpose of the embodiments of the present application is to propose a defect detection method for ultra-large-scale integrated circuits, a computer device, and a storage medium to solve the problems in the prior art.

[0006] In order to solve the above technical problems, the present invention provides a method for detecting defects in a very large scale integrated circuit, including:

[0007] Dividing the VLSI to be tested into a plurality of basic functional areas, wherein each basic functional area is used to implement a corresponding basic function;

[0008] By analyzing the logic tree of the test sample, selecting at least one target basic functional area associated with the logic tree of the test sample from the multiple basic functional areas;

[0009] Based on the logic tree of the test sample, the selected target basic functional areas are arranged and combined to obtain a functional area combination to be tested;

[0010] The test sample is used to test the functional area combination to determine the logic defects between the target basic functional areas in the functional area combination to be tested.

[0011] Preferably, the VLSI to be tested is divided into a plurality of basic functional areas, including:

[0012] Obtaining the design files and layout files of the VLSI to be tested;

[0013] Determining each actual basic unit included in the VLSI to be tested based on the design file and the layout file;

[0014] Each actual basic unit included in the VLSI to be tested is divided into a plurality of basic functional areas according to a division rule, wherein the division rule is used to define a mapping relationship between the basic functional areas and the basic units.

[0015] Preferably, the VLSI to be tested is divided into a plurality of basic functional areas, including:

[0016] The ultra-large-scale integrated circuit is divided into a core computing and logic processing functional area, a data storage and cache functional area, a signal interaction and interface functional area, a system management and support functional area, and an interconnection communication functional area.

[0017] Preferably, the logic tree includes logic nodes and logic edges, wherein the logic nodes represent atomic operations required to be performed by the test sample; the logic edges represent dependency relationships between logic nodes; and,

[0018] The step of analyzing the logic tree of the test sample and selecting at least one target basic functional area associated with the logic tree of the test sample from the multiple basic functional areas includes:

[0019] Identifying each logical node in the logic tree by analyzing the atomic operations of each logical node in the logic tree;

[0020] According to the identified logical nodes and the mapping relationship between the logical nodes and the basic functional areas, the corresponding basic functional areas are determined as target basic functional areas.

[0021] Preferably, based on the logic tree of the test sample, the selected target basic functional areas are arranged and combined to obtain a functional area combination to be tested, including:

[0022] Determine the dependency relationship of each selected target basic functional area according to each logical edge in the logic tree;

[0023] According to the dependency relationship of each target basic functional area, the target basic functional areas are arranged sequentially and / or in parallel to obtain the functional area combination to be tested.

[0024] Preferably, the step of testing the functional area combination to be tested using the test sample to determine the logic defects between the target basic functional areas in the functional area combination to be tested includes:

[0025] Inputting the test sample into the functional area combination to be tested;

[0026] Obtaining the actual output result of the functional area combination to be tested;

[0027] Comparing the actual output result with the expected output result of the test sample;

[0028] According to the comparison result, it is determined whether there is a logic defect between each target basic functional area in the functional area combination to be tested.

[0029] Preferably, the method further comprises:

[0030] When the actual output result is inconsistent with the expected output result, the type of the logic defect is determined.

[0031] Preferably, the logic tree of the test sample is constructed based on the functional requirements and / or design specifications of the VLSI.

[0032] In order to solve the above technical problems, the embodiment of the present application further provides a computer device, which adopts the following technical solution:

[0033] The method comprises a memory and a processor, wherein the memory stores computer-readable instructions, and the processor implements the steps of the above method when executing the computer-readable instructions.

[0034] In order to solve the above technical problems, the embodiment of the present application further provides a computer-readable storage medium, which adopts the following technical solution:

[0035] The computer-readable storage medium stores computer-readable instructions, which implement the steps of the above method when executed by a processor.

[0036] The present application provides a defect detection method for a very large scale integrated circuit, comprising dividing the very large scale integrated circuit to be tested into a plurality of basic functional areas, each of which is used to implement a corresponding basic function, and then analyzing the logic tree of the test sample to select at least one target basic functional area associated with the logic tree of the test sample from these basic functional areas, and then arranging and combining the selected target basic functional areas based on the logic tree of the test sample to obtain a combination of functional areas to be tested, and then using the test sample to test the combination of functional areas to be tested to determine the logic defects between the target basic functional areas in the combination of functional areas to be tested. Even when facing very large scale integrated circuits with high integration density and relatively large area of ​​circuit components such as GPUs and NPUs, this method divides them into a plurality of basic functional areas, and then combines the logic tree of the test sample to select at least one target basic functional area, and further arranges and combines to obtain the combination of functional areas to be tested, so that the test sample can be used to test the combination of functional areas to be tested to detect the logic defects in the combination of functional areas to be tested, and thus can also be used to detect logic defects in very large scale integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the solutions in this application, a brief introduction will be given below to the drawings required for use in the description of the embodiments of this application. Obviously, the drawings described below are some embodiments of this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0038] Figure 1 This is a flowchart of an implementation method for detecting defects in ultra-large-scale integrated circuits provided by an embodiment of the present application;

[0039] Figure 2 This is a schematic diagram of the specific structure of a defect detection device for a very large scale integrated circuit provided by an embodiment of the present application;

[0040] Figure 3 It is a structural diagram of an embodiment of a computer device according to the present application. DETAILED DESCRIPTION

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of the application are for the purpose of describing specific embodiments only and are not intended to limit this application. The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of this application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0042] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0043] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0044] As mentioned above, existing technologies mainly detect hardware defects in integrated circuits, but are unable to detect defects in the chip's logical structure. In particular, for very large-scale integrated circuits such as GPUs and NPUs, due to the high integration density of circuit components and their relatively large area, their logical structure is relatively complex, which also increases the difficulty of detecting logical structure defects. Therefore, it is necessary to provide a defect detection solution for very large-scale integrated circuits.

[0045] In view of this, the embodiments of the present application provide a method for detecting defects in a very large scale integrated circuit, a computer device, and a storage medium, which can be used to detect defects in the logic structure of a very large scale integrated circuit. Figure 1 FIG. 1 is a schematic diagram showing a specific flow chart of the VLSI defect detection method, which includes the following steps:

[0046] Step S11: Divide the VLSI to be tested into a plurality of basic functional areas.

[0047] Among them, the VLSI to be tested can be any large-scale integrated circuit, such as a GPU, NPU, etc. In this application, it is necessary to perform defect detection on the large-scale integrated circuit, so it is called a VLSI to be tested.

[0048] In step S11, each basic functional area is used to implement the corresponding basic function, which may specifically include core computing and logic processing, data storage and caching, signal interaction and interface, system management and support, and interconnection communication, and the corresponding basic functional areas are respectively the core computing and logic processing functional area (used to implement the basic function of core computing and logic processing), the data storage and caching functional area (used to implement the basic function of data storage and caching), the signal interaction and interface functional area (used to implement the basic function of signal interaction), the system management and support functional area (used to implement the basic function of system management and support), and the interconnection communication functional area (used to implement the basic function of interconnection communication).

[0049] That is to say, in the technical solution of the present application, the focus is not on the algorithm logic performed by the very large-scale integrated circuit to be tested itself, such as how the GPU processes graphics data and how it sends instructions to the CPU, but more on the nature of the functions and data interaction of the very large-scale integrated circuit to be tested itself. The functions of the very large-scale integrated circuit to be tested in the data processing process are divided into five basic functions: core computing and logic processing, data storage and caching, signal interaction and interface, system management and support, and interconnection and communication. The very large-scale integrated circuit to be tested is then divided into these five basic functional areas, namely, the core computing and logic processing functional area, the data storage and caching functional area, the signal interaction and interface functional area, the system management and support functional area, and the interconnection and communication functional area.

[0050] In actual applications, the ultra-large-scale integrated circuit itself has multiple basic units, including CPU / GPU / NPU computing units, combined and sequential logic units, SRAM units, Cache units, eDRAM units, ROM units, I / O units, analog mixed signal units (i.e. ADC / DAC), radio frequency units (i.e. RF), clock network units (i.e. PLL / CDN), power management units (i.e. PMU / LDO), reset / watchdog units, on-chip network units (NoC), bus bridge units, cross-module communication protocol stacks, etc. These basic units are the original structures of the ultra-large-scale integrated circuit itself. The basic functional areas in this application are formed based on the classification of the core logic of these basic units.

[0051] Therefore, the core logic of each basic unit in the VLSI can be classified in advance, that is, the basic units with similar core logic can be divided into one category, thereby generating a division rule that defines the mapping relationship between the basic functional area and the basic unit, such as Figure 1 The figure shows a division rule used in practical applications.

[0052] Table 1

[0053]

[0054] The division rules shown in Table 1 reveal the mapping relationship between the basic functional areas in the embodiment of the present application and the basic units in the ultra-large-scale integrated circuit. For example, the basic units corresponding to the core computing and logic processing functional area include operation units, combinational and sequential logic units; the basic units corresponding to the data storage and cache functional area include SRAM units, Cache units, eDRAM units, and ROM units; similarly, the division rules shown in Table 1 also reveal the basic units corresponding to the signal interaction and interface functional area, the system management and support functional area, and the interconnection communication functional area, respectively.

[0055] In actual applications, the VLSI to be tested may only have some of the above-mentioned basic units. Therefore, a specific implementation method of step S11 may be to obtain the design file and layout file of the VLSI to be tested. The design file includes a schematic diagram, a simulation model, etc., and is mainly used for circuit design and simulation verification. The layout file includes a GDS file, a LEF file, a CLF file, etc., and is mainly used to convert the design into an actual chip structure to ensure accurate replication in the manufacturing stage. Therefore, the design file and layout file include each actual basic unit in the VLSI to be tested; after obtaining the design file and layout file of the VLSI to be tested, the actual basic units included in the VLSI to be tested can be further determined based on the design file and layout file of the VLSI to be tested. Specifically, the design file and layout file can be analyzed to obtain the actual basic units included therein; and then the actual basic units included in the VLSI to be tested are further divided into multiple basic functional areas according to the division rules.

[0056] Step S12: Analyzing the logic tree of the test sample, selecting at least one target basic functional area associated with the logic tree of the test sample from the plurality of basic functional areas.

[0057] In step S12, the test sample serves as input data for subsequent defect detection, playing a key role in verifying whether the VLSI under test has any logic defects. In practical applications, the test sample is constructed based on the functional requirements and design specifications of the VLSI, and can be used to simulate the input signals of the VLSI in actual operating scenarios. By observing the VLSI's processed output of the test sample, it is determined whether it meets the design requirements.

[0058] For example, in a GPU, a test sample can be image data in a specific format, used to verify the GPU's image processing and recognition capabilities. In practical applications, multiple test samples can be pre-built based on the functional requirements and design specifications of the VLSI and stored in a sample library. In this way, in step S12, the required test samples can be directly obtained from the sample library.

[0059] Test samples can usually be generated in the following ways. Specifically, the functional requirements and design specifications of the very large-scale integrated circuit can be obtained, and then the various functional requirements of the very large-scale integrated circuit can be determined based on the functional requirements and design specifications, including the input and output characteristics of the function, processing logic and performance indicators, etc. For example, for a communication chip, it is necessary to clarify its supported communication protocols, data transmission rates, error checking mechanisms and other functional requirements; then, based on these functional requirements, specific test cases are designed, and the input parameters and expected output results of the test samples are determined. The test cases should cover all aspects of the functional requirements, including normal functions, exception handling and boundary conditions, etc. For example, when designing a test case for an adder, it is necessary to consider the addition of numbers of different sizes, the addition of positive and negative numbers, and overflow conditions, etc.; then, based on the generated test cases, test samples are generated. For example, multiple test cases can be combined into one test sample.

[0060] The logic tree of a test sample reflects the operational flow of a VLSI when executing the test sample. This logic tree is typically a tree-shaped directed acyclic graph (DAG). The logic tree of a test sample may include logic nodes and logic edges. The logic nodes in the logic tree represent the atomic operations required to execute the test sample. The logic edges in the logic tree represent the dependencies between logic nodes (such as data flow and control flow sequence), reflecting the interaction logic between basic functional areas. The atomic operation refers to the smallest operational unit that constitutes complex logic.

[0061] Therefore, in actual applications, after obtaining the test sample, the logic tree of the test sample can be generated in the following manner. Specifically, the actual atomic operations included in the test sample can be extracted from the algorithm description of the test sample, and then the logic nodes in the logic tree can be determined based on the actual atomic operations and the mapping relationship between the atomic operations and the node types (as shown in Table 2); then, based on the algorithm description of the test sample, the dependency relationship between the logic nodes is determined, and the logic edges in the logic tree are generated, so that the logic tree of the test sample can be finally generated. Therefore, in actual applications, the logic tree of the test sample can be generated in advance, so that after obtaining the test sample, the pre-generated logic tree can be directly obtained.

[0062] Table 2

[0063]

[0064] It should be noted that the logical nodes in this application mainly include data nodes, computing nodes, control nodes, storage nodes and transmission nodes, among which the atomic operations corresponding to each logical node (the atomic operations can be used to identify the corresponding logical nodes) are shown in Table 2.

[0065] In this way, for the specific implementation method of step S12, the logic tree of the test sample can be first obtained, and then the logic tree can be analyzed to identify the various logic nodes in the logic tree. For example, the atomic operations of each logic node in the logic tree can be identified, and then the corresponding logic nodes can be identified. Then, based on the identified logic nodes and the mapping relationship between the logic nodes and the basic functional areas, the corresponding basic functional areas are determined as the target basic functional areas.

[0066] The mapping relationship between the logical nodes and the basic functional areas is shown in Table 3. This mapping relationship reflects the corresponding relationship between the logical nodes and the basic functional areas. Therefore, it can be used to determine the target basic functional areas corresponding to each logical node in the logical tree.

[0067] Table 3

[0068]

[0069] Step S13: Based on the logic tree of the test sample, the selected target basic functional areas are arranged and combined to obtain a functional area combination to be tested.

[0070] After obtaining each target basic functional area through the above-mentioned step S12, in this step S13, the selected target basic functional areas are further arranged and combined based on the logic tree of the test sample to obtain the functional area combination to be tested. Among them, as for the specific implementation method of this step S13, it is mentioned in the above-mentioned step S12 that the logic tree includes logic nodes and logic edges, and the dependency relationship between the logic edges and logic nodes reflects the interactive logic between the basic functional areas. Therefore, this step S13 can be, according to each logic edge in the logic tree, to determine the dependency relationship between each selected target basic functional area, and then according to the dependency relationship between each target basic functional area, to arrange each target basic functional area sequentially and / or in parallel, so as to obtain the functional area combination to be tested. Among them, sequential arrangement means that the arrangement objects have a dependency relationship, so they are executed in series in sequence; parallel arrangement means that there is no dependency relationship between the arrangement objects, so they can be executed in parallel.

[0071] The dependencies between the selected target basic functional areas are determined according to the logical edges in the logic tree. This can be done by first extracting data dependency features, control dependency features, and resource dependency features from each logical edge, and then determining the dependencies between the selected target basic functional areas based on the data dependency features, control dependency features, and resource dependency features of each logical edge. The data dependency features reflect the data dependencies during execution and focus more on transmission protocols and bandwidth. For example, when the core computing area transmits a 1MB feature map to the data storage area, it must follow the AXI4 protocol and meet the 200ns latency requirement. The control dependency features focus on trigger conditions. For example, when the system management area switches power consumption modes, the clock gating of the computing unit must be completed within 100ns. The resource dependency features involve arbitration strategies, such as the priority polling allocation of the on-chip bus of the interconnected communication area.

[0072] Step S14: using the test sample to test the functional area combination to determine the logic defects between the target basic functional areas in the functional area combination to be tested.

[0073] It should be noted that the method of using the test sample to test the functional area combination to be tested in step S14 is to use the test sample as the input of the functional area combination to be tested, thereby obtaining the actual output result, and then locating the logical defect by comparing the deviation between the actual output result and the expected result. Its essence is to verify the correctness of the dependency relationship between the various target basic functional areas arranged in sequence and / or in parallel in the functional area combination to be tested. Therefore, the specific implementation method of step S14 can be to first input the test sample into the functional area combination to be tested, and then obtain the actual output result of the functional area combination to be tested, and then compare the actual output result with the expected output result of the test sample, and then determine whether there is a logical defect between the various target basic functional areas in the functional area combination to be tested based on the comparison result.

[0074] Of course, when the actual output result is consistent with the expected output result of the test sample, it means that there may be no logical defects between the target basic functional areas in the functional area combination to be tested (there may also be logical defects, which need to be continued by other test samples); conversely, when the actual output result is inconsistent with the expected output result of the test sample, the method can further include determining the type of logical defects.

[0075] For example, when the core computing and logic processing functional area transfers data to the data storage and cache functional area, if the actual storage address is offset by 32 bytes or more from the expected storage address, a logic defect is determined to exist, and the type of logic defect is an address mapping defect. Among them, the logic defects that may exist in the VLSI under test usually also include timing defects, data integrity defects, etc. Among them, if the timing of the actual output result does not match the timing of the expected result, such as the data transmission delay exceeds the design threshold of 200ns, it can be determined that there is a timing defect in the VLSI under test; for the test sample for testing data integrity, if the Hamming distance between the actual output result and the expected result (stored data) exceeds the preset distance (usually 1), it indicates that there is a data integrity defect in the VLSI under test.

[0076] The defect detection method for a very large scale integrated circuit provided by an embodiment of the present application includes dividing the very large scale integrated circuit to be tested into a plurality of basic functional areas, each of which is used to implement a corresponding basic function, and then analyzing the logic tree of the test sample to select at least one target basic functional area associated with the logic tree of the test sample from these basic functional areas, and then arranging and combining the selected target basic functional areas based on the logic tree of the test sample to obtain a combination of functional areas to be tested, and then using the test sample to test the combination of functional areas to be tested to determine the logic defects between the target basic functional areas in the combination of functional areas to be tested. Even when facing very large scale integrated circuits with high integration density and relatively large area of ​​circuit components such as GPUs and NPUs, this method divides them into a plurality of basic functional areas, and then combines the logic tree of the test sample to select at least one target basic functional area, and further arranges and combines to obtain the combination of functional areas to be tested, so that the combination of functional areas to be tested can be tested by the test sample to detect the logic defects in the combination of functional areas to be tested, and thus can also be used to detect logic defects in very large scale integrated circuits.

[0077] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing related hardware through computer-readable instructions. The computer-readable instructions can be stored in a computer-readable storage medium. When the program is executed, it can include the processes in the above-described method embodiments. The aforementioned storage medium can be a non-volatile storage medium such as a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0078] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0079] Based on the same inventive concept as the VLSI defect detection method provided in the embodiment of the present application, the embodiment of the present application also provides a VLSI defect detection device. If there is any unclear content in the embodiment of the device, please refer to the corresponding content in the method embodiment. Figure 2 FIG. 2 is a schematic diagram showing a specific structure of the apparatus 20 , which includes a division unit 201 , a selection unit 202 , an arrangement unit 203 , and a testing unit 204 , wherein:

[0080] A division unit 201 is configured to divide the VLSI under test into a plurality of basic functional areas, wherein each basic functional area is configured to implement a corresponding basic function;

[0081] A selection unit 202 is configured to select at least one target basic functional area associated with the logic tree of the test sample from the plurality of basic functional areas by analyzing the logic tree of the test sample;

[0082] The arrangement unit 203 is configured to arrange and combine the selected target basic functional areas based on the logic tree of the test sample to obtain a functional area combination to be tested;

[0083] The testing unit 204 is configured to test the functional area combination to be tested using the test sample to determine logic defects between target basic functional areas in the functional area combination to be tested.

[0084] Since the device 20 adopts the same inventive concept as the VLSI defect detection method provided in the embodiment of the present application, it can also solve the problems in the prior art, which will not be described in detail here.

[0085] The VLSI to be tested is divided into several basic functional areas, including:

[0086] Obtaining the design files and layout files of the VLSI to be tested;

[0087] Determining each actual basic unit included in the VLSI to be tested based on the design file and the layout file;

[0088] Each actual basic unit included in the VLSI to be tested is divided into a plurality of basic functional areas according to a division rule, wherein the division rule is used to define a mapping relationship between the basic functional areas and the basic units.

[0089] The VLSI to be tested is divided into several basic functional areas, including:

[0090] The ultra-large-scale integrated circuit is divided into a core computing and logic processing functional area, a data storage and cache functional area, a signal interaction and interface functional area, a system management and support functional area, and an interconnection communication functional area.

[0091] The logic tree includes logic nodes and logic edges, wherein the logic nodes represent atomic operations required to be performed by the test sample; the logic edges represent dependency relationships between logic nodes; and

[0092] The step of analyzing the logic tree of the test sample and selecting at least one target basic functional area associated with the logic tree of the test sample from the multiple basic functional areas includes:

[0093] Identifying each logical node in the logic tree by analyzing the atomic operations of each logical node in the logic tree;

[0094] According to the identified logical nodes and the mapping relationship between the logical nodes and the basic functional areas, the corresponding basic functional areas are determined as target basic functional areas.

[0095] The selected target basic functional areas are arranged and combined based on the logic tree of the test sample to obtain a functional area combination to be tested, including:

[0096] Determine the dependency relationship of each selected target basic functional area according to each logical edge in the logic tree;

[0097] According to the dependency relationship of each target basic functional area, the target basic functional areas are arranged sequentially and / or in parallel to obtain the functional area combination to be tested.

[0098] The step of testing the functional area combination to be tested using the test sample to determine the logic defects between the target basic functional areas in the functional area combination to be tested includes:

[0099] Inputting the test sample into the functional area combination to be tested;

[0100] Obtaining the actual output result of the functional area combination to be tested;

[0101] Comparing the actual output result with the expected output result of the test sample;

[0102] According to the comparison result, it is determined whether there is a logic defect between each target basic functional area in the functional area combination to be tested.

[0103] The device 20 may further include a defect type determination unit configured to determine the type of the logic defect when the actual output result is inconsistent with the expected output result.

[0104] The logic tree of the test sample is constructed based on the functional requirements and / or design specifications of the ultra-large-scale integrated circuit.

[0105] To solve the above technical problems, the present application also provides a computer device. Figure 3 , Figure 3 This is a basic structural block diagram of the computer device according to an embodiment of the present application.

[0106] The computer device 300 includes a memory 310, a processor 320, and a network interface 330 that are interconnected through a system bus. It should be noted that the figure only shows the computer device 300 having components 310-330, but it should be understood that it is not required to implement all the components shown, and more or fewer components can be implemented instead. Among them, those skilled in the art can understand that the computer device here is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessors, application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.

[0107] The computer device may be a desktop computer, notebook computer, PDA, cloud server, etc. The computer device may interact with the user via a keyboard, mouse, remote control, touchpad, or voice control device.

[0108] The memory 310 includes at least one type of readable storage medium, including flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 310 may be an internal storage unit of the computer device 300, such as the hard disk or memory of the computer device 300. In other embodiments, the memory 310 may also be an external storage device of the computer device 300, such as a plug-in hard disk equipped on the computer device 300, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash memory card, etc. Of course, the memory 310 may also include both the internal storage unit of the computer device 300 and its external storage device. In the embodiment of the present application, the memory 310 is generally used to store the operating system and various application software installed on the computer device 300, such as computer-readable instructions of the method. In addition, the memory 310 can also be used to temporarily store various data that has been output or is to be output.

[0109] In some embodiments, the processor 320 may be a central processing unit (CPU), a controller, a microcontroller, a microprocessor, or other data processing chip. The processor 320 is generally used to control the overall operation of the computer device 300. In the embodiment of the present application, the processor 320 is used to execute computer-readable instructions or process data stored in the memory 310, such as computer-readable instructions for executing the method provided in the embodiment of the present application.

[0110] The network interface 330 may include a wireless network interface or a wired network interface. The network interface 330 is generally used to establish a communication connection between the computer device 300 and other electronic devices.

[0111] The present application also provides another embodiment, namely, providing a computer-readable storage medium, wherein the computer-readable storage medium stores computer-readable instructions, and the computer-readable instructions can be executed by at least one processor to enable the at least one processor to perform the steps of the above method.

[0112] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0113] Obviously, the embodiments described above are only some of the embodiments of the present application, rather than all of the embodiments. The preferred embodiments of the present application are given in the accompanying drawings, but they do not limit the patent scope of the present application. The present application can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive. Although the present application has been described in detail with reference to the aforementioned embodiments, for those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned specific embodiments, or to make equivalent replacements for some of the technical features therein. Any equivalent structure made using the contents of the present application specification and the accompanying drawings, directly or indirectly used in other related technical fields, is also within the scope of patent protection of the present application.

Claims

1. A defect detection method for ultra-large-scale integrated circuits, characterized in that: include: Dividing the VLSI to be tested into a plurality of basic functional areas, wherein each basic functional area is used to implement a corresponding basic function; By analyzing the logic tree of the test sample, selecting at least one target basic functional area associated with the logic tree of the test sample from the multiple basic functional areas; Based on the logic tree of the test sample, the selected target basic functional areas are arranged and combined to obtain a functional area combination to be tested; The test sample is used to test the functional area combination to determine the logic defects between the target basic functional areas in the functional area combination to be tested.

2. The defect detection method according to claim 1, characterized in that: Divide the VLSI to be tested into several basic functional areas, including: Obtaining the design files and layout files of the VLSI to be tested; Determining each actual basic unit included in the VLSI to be tested based on the design file and the layout file; Each actual basic unit included in the VLSI to be tested is divided into a plurality of basic functional areas according to a division rule, wherein the division rule is used to define a mapping relationship between the basic functional areas and the basic units.

3. The defect detection method according to claim 1, wherein: Divide the VLSI to be tested into several basic functional areas, including: The ultra-large-scale integrated circuit is divided into a core computing and logic processing functional area, a data storage and cache functional area, a signal interaction and interface functional area, a system management and support functional area, and an interconnection communication functional area.

4. The defect detection method according to claim 1, wherein: The logic tree includes logic nodes and logic edges, wherein the logic nodes represent atomic operations required to be performed by the test sample; the logic edges represent dependency relationships between logic nodes; and, The step of analyzing the logic tree of the test sample and selecting at least one target basic functional area associated with the logic tree of the test sample from the multiple basic functional areas includes: Identifying each logical node in the logic tree by analyzing the atomic operations of each logical node in the logic tree; According to the identified logical nodes and the mapping relationship between the logical nodes and the basic functional areas, the corresponding basic functional areas are determined as target basic functional areas.

5. The defect detection method according to claim 4, characterized in that: Based on the logic tree of the test sample, the selected target basic functional areas are arranged and combined to obtain a functional area combination to be tested, including: Determine the dependency relationship of each selected target basic functional area according to each logical edge in the logic tree; According to the dependency relationship of each target basic functional area, the target basic functional areas are arranged sequentially and / or in parallel to obtain the functional area combination to be tested.

6. The defect detection method according to claim 1, characterized in that: The step of testing the functional area combination to be tested using the test sample to determine the logic defects between the target basic functional areas in the functional area combination to be tested includes: Inputting the test sample into the functional area combination to be tested; Obtaining the actual output result of the functional area combination to be tested; Comparing the actual output result with the expected output result of the test sample; According to the comparison result, it is determined whether there is a logic defect between each target basic functional area in the functional area combination to be tested.

7. The defect detection method according to claim 6, characterized in that: The method further comprises: When the actual output result is inconsistent with the expected output result, the type of the logic defect is determined.

8. The defect detection method according to claim 1, wherein: The logic tree of the test sample is constructed based on the functional requirements and / or design specifications of the ultra-large-scale integrated circuit.

9. A computer device comprising a memory and a processor, characterized in that: The memory stores computer-readable instructions, and when the processor executes the computer-readable instructions, the steps of the method according to any one of claims 1 to 8 are implemented.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-readable instructions, which, when executed by a processor, implement the steps of the method according to any one of claims 1 to 8.

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