Gate drive circuit and signal modulation method thereof

Abstract

The invention discloses a gate driving circuit which comprises a signal generating circuit, a pulse wave modulation control circuit and a control transistor. The signal generating circuit generates a global light-emitting signal and a reference light-emitting signal according to the blank time length. The pulse wave modulation control circuit receives the pulse width modulation data and the swing signal, and receives the global light-emitting signal from the signal generation circuit so as to provide a local light-emitting signal. The pulse width of the local light-emitting signal is less than or equal to the pulse width of the global light-emitting signal. The control transistor has a first terminal for receiving a reference light emitting signal, a control terminal for receiving a local light emitting signal, and a second terminal for providing an adjusted light emitting signal.

Description

Technical Field

[0001] The present disclosure relates to a gate driving circuit and a signal modulation method thereof, and more particularly to a gate driving circuit and a signal modulation method thereof for adjusting the frequency and pulse width of a light-emitting signal. Background Art

[0002] A display panel may be equipped with multiple gate-on-array (GOA) circuits to drive corresponding pixels. Conventionally, the display panel divides the GOA circuits into different groups corresponding to different blocks of pixels. Furthermore, the display panel may use complex decoder switching circuits to set different frequencies for the different GOA circuit groups, thereby enabling pixels in different blocks to be updated at different frequencies.

[0003] As display panel resolution increases, the area occupied by each component in the display panel must be increasingly reduced. However, the existing solution of using decoder switching circuits to set different frequencies for groups of GOA circuits inevitably increases circuit area. How to enable multiple GOA circuits to update frequencies arbitrarily while reducing circuit area is a major circuit design challenge for those skilled in the art. Summary of the Invention

[0004] This disclosure provides a gate drive circuit. The gate drive circuit includes a signal generating circuit, a pulse modulation control circuit, and a control transistor. The signal generating circuit generates a global light-emitting signal and a reference light-emitting signal based on the length of a blanking period. The pulse modulation control circuit receives pulse-width modulation data, an oscillation signal, and the global light-emitting signal from the signal generating circuit to provide a local light-emitting signal. The pulse width of the local light-emitting signal is less than or equal to the pulse width of the global light-emitting signal. The control transistor has a first terminal for receiving the reference light-emitting signal, a control terminal for receiving the local light-emitting signal, and a second terminal for providing an adjusted light-emitting signal.

[0005] This disclosure provides a signal modulation method applicable to a gate drive circuit, the gate drive circuit comprising a signal generating circuit, a pulse modulation control circuit, and a control transistor. The signal modulation method comprises: generating a global luminescence signal and a reference luminescence signal according to a blanking time length by the signal generating circuit; receiving pulse-width modulation data and an oscillating signal, and receiving the global luminescence signal from the signal generating circuit by the pulse modulation control circuit to provide a local luminescence signal; and receiving the reference luminescence signal and the local luminescence signal by the control transistor to provide an adjusted luminescence signal. The pulse width of the local luminescence signal is less than or equal to the pulse width of the global luminescence signal.

[0006] In summary, the gate drive circuit and signal modulation method disclosed herein can adjust the frequency of a light-emitting signal by adjusting the blanking time and pulse width duration, thereby adjusting the refresh frequency of corresponding pixel rows in a display device, thereby achieving the technical benefits of saving power and circuit area. Furthermore, multiple gate drive circuits provided in the display panel can each set multiple sets of light-emitting signal frequencies, enabling different pixel rows in the display device to have different refresh frequencies. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 1 is a block diagram of a gate driving circuit according to an embodiment of the present disclosure.

[0008] Figure 2 FIG. 1 is a waveform timing diagram of a plurality of light emitting signals and a plurality of oscillation signals according to an embodiment of the present disclosure.

[0009] Figure 3 FIG. 1 is a schematic diagram of component configuration of a pulse wave modulation control circuit according to an embodiment of the present disclosure.

[0010] Figure 4A Based on Figure 3 Driving waveform timing diagram of an embodiment of the present invention.

[0011] Figure 4B Based on Figure 3 Driving waveform timing diagram of an embodiment of the present invention.

[0012] Figure 4C Based on Figure 3 Driving waveform timing diagram of an embodiment of the present invention.

[0013] Figure 5 FIG. 1 is a schematic diagram of component configuration of a pulse wave modulation control circuit according to an embodiment of the present disclosure.

[0014] Figure 6A Based on Figure 5 Driving waveform timing diagram of an embodiment of the present invention.

[0015] Figure 6B Based on Figure 5 Driving waveform timing diagram of an embodiment of the present invention.

[0016] Figure 6C Based on Figure 5 Driving waveform timing diagram of an embodiment of the present invention.

[0017] Figure 7 FIG. 1 is a schematic diagram of component configuration of a pulse wave modulation control circuit according to an embodiment of the present disclosure.

[0018] Figure 8A Based on Figure 7 Driving waveform timing diagram of an embodiment of the present invention.

[0019] Figure 8B Based on Figure 7 Driving waveform timing diagram of an embodiment of the present invention.

[0020] Figure 9 FIG. 1 is a schematic diagram illustrating the configuration of control transistors and scan shift registers according to an embodiment of the present disclosure.

[0021] Figure 10 FIG. 1 is a schematic diagram illustrating the configuration of components in a gate driving circuit according to an embodiment of the present disclosure.

[0022] Figure 11 FIG. 1 is a flow chart of a signal modulation method according to an embodiment of the present disclosure.

[0023] Wherein, the reference numerals:

[0024] 100: Gate drive circuit

[0025] 110,110[1]-110[4]: Signal generation circuit

[0026] 120,120A,120B,120C,120[1]-120[4]: Pulse wave modulation control circuit

[0027] T11, T11[1]-T11[4]: control transistors

[0028] EM: Global luminescence signal

[0029] PWM_DAT: Pulse width modulation data

[0030] SWP, SWP1, SWP2, SWP3: Oscillation signal

[0031] PEM, PEM[1]-PEM[4]: Local luminous signal

[0032] EMQ,EMQ[1]-EMQ[4]: Reference luminescence signals

[0033] EMQ',EM_AA,EMQ'[1]-EMQ'[4]: adjusted luminous signals

[0034] EM1, EM2, EM3: Luminous signal

[0035] PW1, PW2, PW3: Pulse width

[0036] BKT240, BKT120, BKT80: Blank time length

[0037] TA1, TA2, TA3, TA4, TB1, TB2, TB3, TB4, TB5, TB6, TB7, TC1, TC2, TC3, TC4, TC5, TC6, TC7, TD1, TD2, TD3, TD4, TD5, TD6, TD7, TD8: transistor

[0038] CA1, CA2, CB1, CB2, CC1, CC2, CC3, CD1: capacitors

[0039] PEMH: High Voltage

[0040] PEML: Low Voltage

[0041] RST_PEM: reset signal

[0042] S1, S2: control signal

[0043] SE1, SE2, EE1, EE2, ESTR: Period

[0044] LV1: High voltage level

[0045] LV2: Low voltage level

[0046] TP1, TP2, TP3: time points

[0047] Vn: low voltage

[0048] P1, P2, P3: nodes

[0049] 110A: Scanning shift register

[0050] EM_PRE: Pre-stage full-range luminous signal

[0051] CLK1, CLK2, CLK3: clock signals

[0052] 1000: Gate drive circuit line

[0053] 1100: Signal Modulation Method

[0054] S110, S120, S130: Steps DETAILED DESCRIPTION

[0055] The following describes the embodiments of the present disclosure with reference to the accompanying drawings, wherein the same reference numerals represent the same or similar elements or method flows.

[0056] Please also refer to Figure 1 、 2 . Figure 1 FIG. 1 is a block diagram of a gate driving circuit 100 according to an embodiment of the present disclosure. Figure 21 is a waveform timing diagram of a plurality of light emitting signals EM1 , EM2 , EM3 and a plurality of swing signals SWP1 , SWP2 , SWP3 according to an embodiment of the present disclosure.

[0057] The gate driving circuit 100 may be a GOA circuit. Figure 1 The gate driver circuit 100 can be disposed in a display panel, and each of the plurality of gate driver circuits 100 can provide a corresponding light-emitting signal to control a pixel array of the display screen. The gate driver circuit 100 includes a signal generating circuit 110, a pulse modulation control circuit 120, and a control transistor T11.

[0058] The signal generating circuit 110 can generate the global luminous signal EM and the reference luminous signal EMQ according to the length of a blanking time. The blanking time length can be Figure 2 The blank time length in BKT120 and BKT80.

[0059] from Figure 2 It can be seen that the signal generating circuit 110 can use one of the plurality of light emitting signals EM1, EM2, EM3 with different frequencies as Figure 1 Global luminescence signal EM in .

[0060] In one embodiment, the frequency of the luminous signal EM1 may be 240 Hz, the frequency of the luminous signal EM2 may be 120 Hz, and the frequency of the luminous signal EM3 may be 80 Hz. The luminous signal EM1 has a blanking time length BKT240, the luminous signal EM2 has a blanking time length BKT120, and the luminous signal EM3 has a blanking time length BKT80. Furthermore, the luminous signals EM1, EM2, and EM3 all have the same pulse width PW1.

[0061] That is, the reason why the light emitting signals EM1 , EM2 , and EM3 have different frequencies is that the blank time lengths of the light emitting signals EM1 , EM2 , and EM3 are different.

[0062] In this embodiment, the gate driving circuit 100 can also set a plurality of oscillating signals SWP1, SWP2, SWP3 with different frequencies by using different blank time lengths, and use one of the oscillating signals SWP1, SWP2, SWP3 as Figure 1 The oscillating signal SWP in.

[0063] also, Figure 1 The reference light emitting signal EMQ and other operation signals (not shown) used by the gate driving circuit 100 Figure 1 ) can set the frequency by different blank time lengths, which will not be explained here.

[0064] It should be noted that the frequencies listed above are only used to help those skilled in the art to better understand the technology of this disclosure, and the actual application of this technology is not limited to the above frequencies.

[0065] The PWM control circuit 120 can receive the PWM data PWM_DAT and the swing signal SWP. The PWM control circuit 120 is coupled to the signal generating circuit 110 and receives the global luminous signal EM from the signal generating circuit 110 to provide the local luminous signal PEM.

[0066] In the embodiments of the present disclosure, the pulse width of the local emitting signal PEM is always less than or equal to the pulse width of the global emitting signal EM. The pulse width of the local emitting signal PEM is set based on the voltage level of the pulse-width modulation data PWM_DAT. Specifically, the higher the voltage level of the pulse-width modulation data PWM_DAT, the longer the pulse width of the local emitting signal PEM. Conversely, the lower the voltage level of the pulse-width modulation data PWM_DAT, the shorter the pulse width of the local emitting signal PEM.

[0067] A first terminal of the control transistor T11 can receive the reference luminous signal EMQ, a control terminal of the control transistor T11 can receive the local luminous signal PEM, and a second terminal of the control transistor T11 can provide an adjusted luminous signal EMQ'. The adjusted luminous signal EMQ' can be used to drive at least one pixel row of a pixel array of a display screen.

[0068] In summary, the multiple gate driver circuits 100 in the display panel described in this disclosure can each set the frequency of the light-emitting signal by adjusting the blanking time and pulse width, thereby adjusting the refresh frequency of corresponding pixel rows in the display device, thereby achieving the technical benefits of saving power and circuit area. Furthermore, the multiple gate driver circuits 100 can set multiple sets of light-emitting signal frequencies, allowing different pixel rows in the display device to have different refresh frequencies.

[0069] Please refer to Figure 3 , Figure 3 FIG. 1 is a schematic diagram illustrating the component configuration of a pulse wave modulation control circuit 120A according to an embodiment of the present disclosure. Figure 3 The pulse modulation control circuit 120A can be used to represent Figure 1 The internal circuit elements of the pulse wave modulation control circuit 120.

[0070] The pulse wave modulation control circuit 120A may include a transistor TA1, a transistor TA2, a transistor TA3, a transistor TA4, a capacitor CA1, and a capacitor CA2. The transistors TA1, TA2, TA3, and TA4 may be P-type transistors, but the present disclosure is not limited thereto.

[0071] Capacitor CA1 is coupled between the swing signal SWP and the first terminal of transistor TA1. The control terminal of transistor TA1 can receive the control signal S1, and the second terminal of transistor TA1 can receive the pulse width modulation data PWM_DAT. The first terminal of transistor TA2 can receive the high voltage PEMH, and the control terminal of transistor TA2 is coupled to the first terminal of transistor TA1. The first terminal of transistor TA3 is coupled to the second terminal of transistor TA2, the control terminal of transistor TA3 can receive the global luminescence signal EM, and the second terminal of transistor TA3 can provide the local luminescence signal PEM. The first terminal of transistor TA4 is coupled to the second terminal of transistor TA3, the control terminal of transistor TA4 can receive the reset signal RST_PEM, and the second terminal of transistor TA4 can receive the low voltage PEML. Capacitor CA2 is coupled between the second terminal of transistor TA3 and the low voltage PEML.

[0072] Please also refer to Figure 3 、 4A . Figure 4A Based on Figure 3 Driving waveform timing diagram of an embodiment of the present invention.

[0073] During the period SE1 when the control signal S1 is enabled, the transistor TA1 is turned on, and the pulse width modulation data PWM_DAT is transmitted to one end of the capacitor CA1 via the transistor TA1 ( Figure 3 The voltage difference across capacitor CA1 depends on the swing signal SWP and the pulse-width modulation data PWM_DAT. During period SE1, the voltage difference across capacitor CA1 is approximately equal to the voltage difference between the high voltage level LV1 and the pulse-width modulation data PWM_DAT.

[0074] Next, during the period EE2 when the reset signal RST_PEM is enabled, the transistor TA4 is turned on to pull the local light emitting signal PEM to a low voltage level (ie, the local light emitting signal PEM is enabled). At this time, the transistor TA1 is turned off.

[0075] During the period EE1 when the global emitting signal EM is enabled, transistor TA3 is turned on, and the voltage level of the swing signal SWP decreases from a high voltage level LV1 to a low voltage level LV2 over time, thereby decreasing the voltage level at the other end of capacitor CA1. During this process, the local emitting signal PEM is maintained at a low voltage PEML by capacitor CA2.

[0076] At time TP1, the voltage level of capacitor CA1 drops to the threshold voltage of transistor TA2 (i.e., the voltage at the control terminal of transistor TA2 reaches the turn-on threshold voltage), turning transistor TA2 on. When transistor TA2 is turned on, high voltage PEMH is transmitted through transistor TA2 to the second terminal of transistor TA3, thereby raising the voltage level of local emitting signal PEM.

[0077] For example, during period SE1, the swing signal SWP is at a high voltage level LV1 (7V), the voltage level at the control terminal of transistor TA2 is 5V, and the voltage difference across capacitor CA1 is approximately 2V. During period EE1, the swing signal SWP drops from 7V, and the voltage level across capacitor CA1 also drops accordingly. The voltage level at the other end of capacitor CA1 drops in proportion to the drop in the swing signal SWP. Assuming the threshold voltage of transistor TA2 is -0.2V, this means that when the swing signal SWP drops by [5-(PEMH-0.2)] volts (for example, if the voltage level of high voltage PEMH is 2V, the swing signal SWP drops by 3.2V), the voltage level at the other end of capacitor CA1 also drops by [5-(PEMH-0.2)] volts, bringing the voltage level at the other end of capacitor CA1 to (PEMH-0.2) volts (i.e., the sum of high voltage PEMH and the threshold voltage), turning on transistor TA2. (It should be noted that the voltage values ​​listed here are only used to enable those skilled in the art to more clearly understand the technology of this disclosure document, and the actual application of this technology is not limited to the above voltage values).

[0078] In this embodiment, the pulse width of the local emitting signal PEM is controlled by the global emitting signal EM enable period EE1, and is therefore at most equal to the pulse width of the global emitting signal EM. The pulse width of the local emitting signal PEM is set based on the voltage level of the pulse-width modulation data PWM_DAT. The higher the voltage level of the pulse-width modulation data PWM_DAT (the closer it is to the high voltage level LV1), the longer the pulse width of the local emitting signal PEM. Conversely, the lower the voltage level of the pulse-width modulation data PWM_DAT, the shorter the pulse width of the local emitting signal PEM.

[0079] Please also refer to Figure 3 、 4A , 4B. Figure 4B Based on Figure 2 Driving waveform timing diagram of an embodiment of the present invention. Figure 4B and Figure 4A The difference is that in Figure 4A The embodiment is suitable for the case where the voltage level of the pulse width modulation data PWM_DAT is higher. Figure 4B The embodiment is applicable to the case where the voltage level of the pulse width modulation data PWM_DAT is relatively low (eg, lower than the threshold voltage of the transistor TA2).

[0080] exist Figure 4B In the embodiment, during the period SE1 when the control signal S1 is enabled, the swing signal SWP is at the low voltage level LV2, and the voltage difference across the capacitor CB1 is approximately equal to the voltage difference between the low voltage level LV2 and the pulse width modulation data PWM_DAT.

[0081] During period SE1, the voltage level of the swing signal SWP is at a low voltage level LV2. At the beginning of period EE1, the voltage level of the swing signal SWP rises to a high voltage level LV1, causing the voltage level at the other end of capacitor CA1 to rise accordingly. Subsequently, the voltage level of the swing signal SWP decreases from the high voltage level LV1 to the low voltage level LV2 over time, further decreasing the voltage level at the other end of capacitor CA1.

[0082] When the voltage level of the capacitor CA1 drops to the threshold voltage of the transistor TA2 , the transistor TA2 is turned on, so that the high voltage PEMH is transmitted to the second terminal of the transistor TA3 via the transistor TA2 , thereby raising the voltage level of the local emitting signal PEM.

[0083] For example, in Figure 4B During period SE1, the swing signal SWP is at a low voltage level LV2 (0V), the control terminal of transistor TA2 is at -1V, and the voltage difference across capacitor CA1 is approximately -1V. At the beginning of period EE1, the swing signal SWP first rises to a high voltage level LV1 (7V), causing the voltage level at the other end of capacitor CA1 to rise to 6V. Then, the swing signal SWP falls from the high voltage level LV1, and the voltage level at the other end of capacitor CA1 also falls. Assuming the threshold voltage of transistor TA2 is also -0.2 volts, this means that when the swing signal SWP drops by [6-(PEMH-0.2)] volts (for example, if the voltage level of high voltage PEMH is 2V, the swing signal SWP drops by 4.2V), the voltage level at the other end of capacitor CA1 will also drop by [6-(PEMH-0.2)] volts, causing the voltage level at the other end of capacitor CA1 to reach (PEMH-0.2) volts (i.e., the sum of high voltage PEMH and the threshold voltage), turning on transistor TA2. (Note that the voltage values ​​listed here are merely intended to help those skilled in the art better understand the technology of this disclosure; the actual application of this technology is not limited to these voltage values.)

[0084] Through the above Figure 4A and Figure 4B In the embodiment of the present invention, a person skilled in the art should be able to clearly understand how the technology of this disclosure corresponds to the pulse width modulation data PWM_DAT of different voltage levels by changing the waveform of the swing signal SWP.

[0085] Please also refer to Figure 4B 、 4C . Figure 4C Based on Figure 3 Driving waveform timing diagram of an embodiment of the present invention. Figure 4C and Figure 4B The difference is that Figure 4C The swing signal SWP is in the form of a staircase wave, decreasing from a high voltage level LV1 to a low voltage level LV2 over time. The staircase wave form allows the pulse modulation control circuit 120A to accurately provide the local light emitting signal PEM.

[0086] Please refer to Figure 5 , Figure 5 FIG. 1 is a schematic diagram illustrating the component configuration of a pulse wave modulation control circuit 120B according to an embodiment of the present disclosure. Figure 5 The pulse modulation control circuit 120B can be used to represent Figure 1 The internal circuit elements of the pulse wave modulation control circuit 120.

[0087] The pulse modulation control circuit 120B may include transistors TB1, TB2, TB3, TB4, TB5, TB6, TB7, capacitors CB1, and CB2. Transistors TB1, TB2, TB3, TB4, TB5, TB6, and TB7 may be P-type transistors, but the present disclosure is not limited thereto.

[0088] Capacitor CB1 is coupled between the swing signal SWP and the first terminal of transistor TB1. The control terminal of transistor TB1 can receive the control signal S1, and the second terminal of transistor TB1 can receive the low voltage Vn. The first terminal of transistor TB2 can receive the pulse width modulation data PWM_DAT, and the control terminal of transistor TB2 can receive the control signal S2. The first terminal of transistor TB3 is coupled to the first terminal of transistor TB1, and the control terminal of transistor TB3 can receive the control signal S2. The first terminal of transistor TB4 is coupled to the second terminal of transistor TB2, the control terminal of transistor TB4 is coupled to the first terminal of transistor TB1, and the second terminal of transistor TB4 is coupled to the second terminal of transistor TB3. The first terminal of transistor TB5 can receive the high voltage PEMH, the control terminal of transistor TB5 can receive the global emission signal EM, and the second terminal of transistor TB5 is coupled to the first terminal of transistor TB4. The first terminal of transistor TB6 is coupled to the second terminal of transistor TB3, the control terminal of transistor TB6 receives the global emission signal EM, and the second terminal of transistor TB6 is used to provide the local emission signal PEM. The first terminal of transistor TB7 is coupled to the second terminal of transistor TB6 , the control terminal of transistor TB7 can receive the reset signal RST_PEM, and the second terminal of transistor TB7 can receive the first low voltage PEML. Capacitor CB2 is coupled between the second terminal of transistor TB6 and the low voltage PEML.

[0089] It is worth mentioning that the transistor TB3 is a compensation transistor for compensating the threshold voltage of the transistor TB4. Figure 3In the embodiment, the low voltage Vn may be different from the low voltage PEML. The voltage level of the low voltage Vn should be lower than the minimum voltage value of the pulse width modulation data PWM_DAT, so that any voltage value of the pulse width modulation data PWM_DAT can flow through the transistor TB4 when the transistor TB4 is turned on.

[0090] Please also refer to Figure 5 、 6A . Figure 6A Based on Figure 5 Driving waveform timing diagram of an embodiment of the present invention.

[0091] During the period SE1 when the control signal S1 is enabled, the transistor TB1 is turned on, and the low voltage Vn is transmitted to one end of the capacitor CB1 and the control end of the transistor TB4 , so that the transistor TB4 is turned on.

[0092] Then, during the period SE2 when the control signal S2 is enabled, the transistors TB2 and TB3 are turned on, and the pulse width modulation data PWM_DAT is transmitted to one of the terminals of the capacitor CB1 via the transistors TB2, TB3, and TB4 ( Figure 3 The voltage difference across capacitor CB1 depends on the swing signal SWP, the pulse width modulation data PWM_DAT, and the threshold voltage of transistor TB3. At this time, transistor TB4 is turned off due to the increase in the voltage at the control terminal.

[0093] Next, during the period EE2 when the reset signal RST_PEM is enabled, the transistor TB7 is turned on to pull the local light-emitting signal PEM to a low voltage level (ie, the local light-emitting signal PEM is enabled).

[0094] During the period EE1 when the global emitting signal EM is enabled, transistors TB5 and TB6 are turned on, and the voltage level of the swing signal SWP decreases from the high voltage level LV1 to the low voltage level LV2 over time. During this process, the local emitting signal PEM is maintained at a low voltage by the capacitor CB2.

[0095] At time TP2 , the voltage at the control terminal of transistor TB4 reaches the threshold voltage for conduction, and transistor TB4 is turned on, so that the high voltage PEMH is transmitted to the second terminal of transistor TB6 via transistor TB5 , thereby raising the voltage level of the local light emitting signal PEM.

[0096] In this embodiment, controlled by the period EE1 during which the global emitting signal EM is enabled, the pulse width of the local emitting signal PEM is at most equal to the pulse width of the global emitting signal EM. The higher the voltage level of the pulse-width modulation data PWM_DAT, the longer the pulse width of the local emitting signal PEM. Conversely, the lower the voltage level of the pulse-width modulation data PWM_DAT, the shorter the pulse width of the local emitting signal PEM.

[0097] Please also refer to Figure 5 、 6B . Figure 6B Based on Figure 5 The driving waveform timing diagram of the embodiment of the present invention. Figure 6A The embodiment is suitable for the case where the voltage level of the pulse width modulation data PWM_DAT is higher. Figure 6B The embodiment is applicable to the case where the voltage level of the pulse width modulation data PWM_DAT is relatively low (eg, lower than the threshold voltage of the transistor TA2).

[0098] exist Figure 6B In the embodiment, during periods SE1 and SE2, the swing signal SWP is at a low voltage level LV2. During period SE2 when the control signal S2 is enabled, the voltage across the capacitor CB1 is equal to the voltage difference between the low voltage level LV2 of the swing signal SWP and the pulse width modulation data PWM_DAT minus the threshold voltage of the transistor TB4. Figure 6A and Figure 6B A person skilled in the art should be able to clearly understand how the technology of this disclosure corresponds to the pulse width modulation data PWM_DAT of different voltage levels through the waveform change of the oscillating signal SWP.

[0099] Please also refer to Figure 6B 、 6C . Figure 6C Based on Figure 5 Driving waveform timing diagram of an embodiment of the present invention. Figure 6C and Figure 6B The difference is that Figure 6C The swing signal SWP is in the form of a staircase wave, decreasing from a high voltage level LV1 to a low voltage level LV2 over time. The staircase wave form allows the pulse modulation control circuit 120B to accurately provide the local light emitting signal PEM.

[0100] Please refer to Figure 7 , Figure 7 FIG. 1 is a schematic diagram illustrating the component configuration of a pulse wave modulation control circuit 120C according to an embodiment of the present disclosure. Figure 7 The pulse modulation control circuit 120C can be used to represent Figure 1 The internal circuit elements of the pulse wave modulation control circuit 120.

[0101] The pulse modulation control circuit 120C may include transistors TC1, TC2, TC3, TC4, TC5, TC6, TC7, capacitors CC1, CC2, and CC3. Transistors TC1, TC2, TC3, TC5, and TC6 may be P-type transistors, while transistors TC4 and TC7 may be N-type transistors, but this disclosure is not limited thereto.

[0102] A first terminal of transistor TC1 can receive a low voltage Vn, a control terminal of transistor TC1 can receive a control signal S1, and a second terminal of transistor TC1 can be coupled to node P1. A first terminal of transistor TC2 can be coupled to node P1, a control terminal of transistor TC2 can receive a control signal S2, and a second terminal of transistor TC2 can receive pulse-width modulation data PWM_DAT. A first terminal of transistor TC3 can receive a high voltage PEMH, a control terminal of transistor TC3 can be coupled to node P2, and a second terminal of transistor TC3 can be coupled to node P3. A first terminal of transistor TC4 can be coupled to node P3, a control terminal of transistor TC4 can be coupled to node P2, and a second terminal of transistor TC4 can receive a low voltage PEML. A first terminal of transistor TC5 can be coupled to node P2, a control terminal of transistor TC5 can receive a control signal S1, and a second terminal of transistor TC5 can be coupled to node P3. A first terminal of transistor TC6 can be coupled to node P3, a control terminal of transistor TC6 can receive a global emission signal EM, and a second terminal of transistor TC6 can provide a local emission signal PEM. A first terminal of the transistor TC7 is coupled to the second terminal of the transistor TC6 . A control terminal of the transistor TC7 can receive the global emitting signal EM. A second terminal of the transistor TC7 can receive the high voltage PEMH.

[0103] The capacitor CC1 is coupled between the swing signal SWP and the node P1. The capacitor CC2 is coupled between the capacitor CC1 and the node P2. The capacitor CC3 is coupled between the second terminal of the transistor TC6 and the high voltage PEMH.

[0104] It is worth mentioning that the voltage level of the low voltage Vn should be lower than the minimum voltage value of the pulse width modulation data PWM_DAT, so that the node P1 can be completely reset (completely discharged) in the transistor TC1.

[0105] Please also refer to Figure 7 、 8A . Figure 8A Based on Figure 7 Driving waveform timing diagram of an embodiment of the present invention.

[0106] During the period SE1 when the control signal S1 is enabled, the transistor TC1 is turned on, and the low voltage Vn is transmitted to the node P1 to reset the node P1. At the same time, the transistor TC5 is turned on, and the voltage level of the node P2 is the same as the voltage level of the node P3.

[0107] Next, during period SE2 when control signal S2 is enabled, transistor TC2 transmits the pulse-width modulation data PWM_DAT to node P1 via transistor TC2. Capacitor CC2 acts as a coupling capacitor, ensuring that the voltage level at node P2 depends on the swing signal SWP and the pulse-width modulation data PWM_DAT. During this period, the global-emission signal EM remains high, turning on transistor TC7 and maintaining the local-emission signal PEM at a high voltage PEMH.

[0108] Then, during period ESTR, transistor TC6 is turned on and transistor TC7 is turned off. After period ESTR, the swing signal SWP momentarily rises from the low voltage level LV2 to the high voltage level LV1, turning on transistor TC4. This causes the low voltage PEML to be transmitted to the second terminal of transistor TC6 via transistor TC3, thereby lowering the voltage level of the local light emitting signal PEM.

[0109] Then, the swing signal SWP decreases from the high voltage level LV1 to the low voltage level LV2 over time, and the voltage level of the node P2 also continues to decrease.

[0110] At time TP3 , the voltage at the control terminal of transistor TC3 (same as node P2 ) reaches the threshold voltage for conduction, and transistor TC3 is turned on, so that the high voltage PEMH is transmitted to the second terminal of transistor TC6 via transistor TC3 to raise the voltage level of the local light emitting signal PEM.

[0111] In this embodiment, controlled by the period EE1 during which the global emitting signal EM is enabled, the pulse width of the local emitting signal PEM is at most equal to the pulse width of the global emitting signal EM. The higher the voltage level of the pulse-width modulation data PWM_DAT, the longer the pulse width of the local emitting signal PEM. Conversely, the lower the voltage level of the pulse-width modulation data PWM_DAT, the shorter the pulse width of the local emitting signal PEM.

[0112] Please also refer to Figure 8A 、 8B . Figure 8B Based on Figure 7 Driving waveform timing diagram of an embodiment of the present invention. Figure 8B and Figure 8A The difference is that Figure 8B The swing signal SWP is in the form of a staircase wave, decreasing from a high voltage level LV1 to a low voltage level LV2 over time. The staircase wave form allows the pulse modulation control circuit 120C to accurately provide the local light emitting signal PEM.

[0113] Please also refer to Figure 1 、 9 , Figure 9FIG. 1 is a schematic diagram illustrating the configuration of the control transistor T11 and the scan shift register 110A according to an embodiment of the present disclosure. Figure 9 The scan shift register 110A can be represented by Figure 1 The internal circuit elements of the signal generating circuit 110.

[0114] The scan shift register 110A of this embodiment is an 8T1C circuit. The scan shift register 110A may include transistors TD1, TD2, TD3, TD4, TD5, TD6, TD7, TD8, and capacitor CD1. Transistors TD1, TD2, TD3, TD4, TD5, TD6, TD7, and TD8 may be P-type transistors, but the present invention is not limited thereto.

[0115] A first terminal and a control terminal of transistor TD1 can receive a previous global-emission signal EM_PRE. A second terminal of transistor TD1 is coupled to one terminal of capacitor CD1, and the other terminal of capacitor CD1 is coupled to a node outputting the global-emission signal EM. In this embodiment, the global-emission signal EM can be used to drive a pixel row in a pixel array of a display screen, and the previous global-emission signal EM_PRE can be used to drive the row immediately preceding the pixel row.

[0116] The first terminals of transistors TD2, TD5, and TD7 can receive the clock signal CLK1, or the clock signals CLK2 and CLK3. The clock signals CLK1, CLK2, and CLK3 can correspond to different frequencies of the previous global luminous signal EM_PRE and the global luminous signal EM.

[0117] In this embodiment, a first terminal of the control transistor T11 is coupled to the control terminal of the transistor TD5 and the second terminal of the transistor TD1 to receive the reference light emitting signal EMQ. A second terminal of the control transistor T11 is coupled to the control terminal of the transistor TD7 and provides the adjusted light emitting signal EMQ' to the control terminal of the transistor TD7, thereby causing the scan shift register 110A to provide the adjusted light emitting signal EM_AA to the pixel row (not shown) connected thereto.

[0118] Please also refer to Figure 1 、 10 , Figure 10 FIG. 1 is a schematic diagram showing the configuration of components of a gate driver circuit 1000 according to an embodiment of the present disclosure. Figure 10In the embodiment of the present invention, the gate drive circuit row 1000 can be arranged in the display panel. The gate drive circuit row 1000 at least has a pulse modulation control circuit 120[1]-120[4], a signal generating circuit 110[1]-110[4] and a control transistor T11[1]-T11[4]. The present disclosure does not limit the number of components of the gate drive circuit row 1000. Figure 10 Just a simple example.

[0119] The gate driving circuit row 1000 can at least control a plurality of pixel rows of a pixel array of a display screen through the adjusted light emitting signals EMQ'[1]-EMQ'[4], and the plurality of pixel rows can have different update frequencies.

[0120] Please also refer to Figure 1 、 11 . Figure 11 1 is a flow chart of a signal modulation method 1100 according to an embodiment of the present disclosure. The signal modulation method 1100 is applicable to Figure 1 The gate driving circuit 100 is provided.

[0121] In step S110 , the gate driving circuit 100 may generate a global luminous signal EM and a reference luminous signal EMQ according to the blank time through the signal generating circuit 110 .

[0122] In step S120 , the gate driving circuit 100 may receive the pulse width modulation data PWM_DAT and the swing signal SWP through the pulse modulation control circuit 120 , and receive the global luminous signal EM from the signal generating circuit 110 to provide the local luminous signal PEM.

[0123] In step S130 , the gate driving circuit 100 may receive the reference luminous signal EMQ and the local luminous signal PEM by controlling the transistor T11 , and provide an adjusted luminous signal EMQ′.

[0124] In summary, the multiple gate driver circuits 100 and their signal modulation method 1100 in the display panel of this disclosure can set the frequency of the light-emitting signal by adjusting the duration of the blank time and pulse width, thereby adjusting the refresh frequency of corresponding pixel rows of the display device, thereby achieving the technical benefits of saving power and circuit area. Furthermore, the multiple gate driver circuits 100 can set multiple sets of light-emitting signal frequencies, so that different pixel rows of the display device have different refresh frequencies.

[0125] The above are merely preferred embodiments of the present disclosure. Various modifications and equivalents may be made to the present disclosure without departing from the scope or spirit of the present disclosure. In summary, all modifications and equivalents of the present disclosure within the scope of the following claims are intended to be covered by the present disclosure.

Claims

1. A gate drive circuit, characterized in that: Include: a signal generating circuit for generating a global luminous signal and a reference luminous signal according to a blank time length; a pulse modulation control circuit receiving a pulse width modulation data, a swing signal, and the global lighting signal from the signal generating circuit to provide a local lighting signal, wherein the pulse width of the local lighting signal is less than or equal to the pulse width of the global lighting signal; and A control transistor has a first terminal receiving the reference light emitting signal, a control terminal receiving the local light emitting signal, and a second terminal providing an adjusted light emitting signal.

2. The gate drive circuit according to claim 1, wherein: The signal generating circuit is further configured to set the global light emitting signal using a plurality of light emitting signals with different frequencies, wherein each of the light emitting signals has the same pulse width.

3. The gate drive circuit according to claim 1, wherein: The pulse width of the local light emitting signal is set according to the voltage level of the pulse width modulation data.

4. The gate drive circuit according to claim 1, wherein: The pulse wave modulation control circuit comprises: a first transistor having a first terminal, a control terminal receiving a first control signal, and a second terminal receiving the pulse width modulation data; a first capacitor coupled between the swing signal and the first terminal of the first transistor; a second transistor having a first terminal receiving a first high voltage, a control terminal coupled to the first terminal of the first transistor, and a second terminal; a third transistor having a first terminal coupled to the second terminal of the second transistor, a control terminal receiving the global light emitting signal, and a second terminal providing the local light emitting signal; a second capacitor coupled between the second terminal of the third transistor and a first low voltage; and A fourth transistor has a first end coupled to the second end of the third transistor, a control end receiving a reset signal, and a second end receiving the first low voltage.

5. The gate driving circuit according to claim 1, wherein: The pulse wave modulation control circuit comprises: a first transistor having a first terminal, a control terminal receiving a first control signal, and a second terminal receiving a second low voltage; a first capacitor coupled between the swing signal and the first terminal of the first transistor; a second transistor having a first terminal for receiving the pulse width modulation data, a control terminal for receiving a second control signal, and a second terminal; a third transistor having a first terminal coupled to the first terminal of the first transistor, a control terminal receiving the second control signal, and a second terminal; a fourth transistor having a first end coupled to the second end of the second transistor, a control end coupled to the first end of the first transistor, and a second end coupled to the second end of the third transistor; a fifth transistor having a first terminal receiving a first high voltage, a control terminal receiving the global light emitting signal, and a second terminal coupled to the first terminal of the fourth transistor; a sixth transistor having a first terminal coupled to the second terminal of the third transistor, a control terminal receiving the global light emitting signal, and a second terminal providing the local light emitting signal; a second capacitor coupled between the second terminal of the sixth transistor and a first low voltage; and A seventh transistor has a first end coupled to the second end of the sixth transistor, a control end receiving a reset signal, and a second end receiving the first low voltage.

6. The gate driving circuit according to claim 1, wherein: The pulse wave modulation control circuit comprises: a first transistor having a first terminal receiving a second low voltage, a control terminal receiving a first control signal, and a second terminal; a first capacitor coupled between the swing signal and the second terminal of the first transistor; a second transistor having a first end coupled to the second end of the first transistor, a control end receiving a second control signal, and a second end receiving the PWM data; a third transistor having a first terminal receiving a first high voltage, a control terminal, and a second terminal; a second capacitor coupled between the first capacitor and the control terminal of the third transistor; a fourth transistor having a first terminal coupled to the second terminal of the third transistor, a control terminal coupled to the control terminal of the third transistor, and a second terminal receiving a first low voltage; a fifth transistor having a first end coupled to the control end of the third transistor, a control end receiving the first control signal, and a second end coupled to the first end of the fourth transistor; a sixth transistor having a first terminal coupled to the second terminal of the third transistor, a control terminal receiving the global light emitting signal, and a second terminal providing the local light emitting signal; a third capacitor coupled between the second terminal of the sixth transistor and the first high voltage; and A seventh transistor has a first end coupled to the second end of the sixth transistor, a control end receiving the global light emitting signal, and a second end receiving the first high voltage.

7. The gate driving circuit according to claim 1, wherein: The oscillating signal is a step wave.

8. A signal modulation method, characterized in that: Applicable to a gate drive circuit, wherein the gate drive circuit includes a signal generating circuit, a pulse modulation control circuit and a control transistor, the signal modulation method includes: The signal generating circuit generates a global luminous signal and a reference luminous signal according to a blank time length; receiving a pulse width modulation data and an oscillation signal through the pulse modulation control circuit, and receiving the global light emitting signal from the signal generating circuit to provide a local light emitting signal, wherein the pulse width of the local light emitting signal is less than or equal to the pulse width of the global light emitting signal; and The reference light emitting signal and the local light emitting signal are received through a control transistor, and an adjusted light emitting signal is provided.

9. The signal modulation method according to claim 8, wherein: The method further includes setting the global light emitting signal by using a plurality of light emitting signals with different frequencies, wherein each of the light emitting signals has the same pulse width.

10. The signal modulation method according to claim 8, wherein: The pulse width of the local light emitting signal is set according to the voltage level of the pulse width modulation data.

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