Memory and control method thereof

Abstract

The invention provides a memory, which at least comprises a phase inverter, an input end of which is used for receiving a first control signal, a power supply end of which is used for receiving a second control signal, an output end of which is used for outputting a third control signal and is connected with a first end of a word line through a word line selection switch, and a second end of the word line is connected with a sleep voltage through a bleeder switch, a grid electrode of the word line selection switch is used for receiving a word line selection signal, and a grid electrode of the discharge switch is used for receiving a discharge signal.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a memory and a control method thereof. Background Art

[0002] In a dynamic random access memory (DRAM), the data of the memory cells to be output is determined based on the selected word lines and bit lines. Specifically, the target row address is obtained by row address decoding, and the word line corresponding to the target row address is activated, that is, the potential of the word line is pulled from a low level to a high level to turn on the access transistors in the memory cells. The word line corresponding to the target row address can be called the target word line. After the access transistors of all memory cells connected to the target word line are turned on, the column select transistors corresponding to the target column address are turned on to output the data in some memory cells. Summary of the Invention

[0003] The embodiments of the present disclosure provide a memory that at least helps to improve the timing freedom of the memory.

[0004] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a memory, which may at least include: an inverter, an input end for receiving a first control signal, a power supply end for receiving a second control signal, an output end for outputting a third control signal, the output end being connected to a first end of a word line through a word line selection switch, the second end of the word line being connected to a sleep voltage through a discharge switch, the gate of the word line selection switch being used to receive a word line selection signal, and the gate of the discharge switch being used to receive a discharge signal.

[0005] In some embodiments, the second control signal is an inverted signal of the first control signal.

[0006] In some embodiments, the memory further includes: a NAND circuit, wherein the first input terminal of the NAND circuit is used to receive the first row address decoding signal, the second input terminal is used to receive the second control signal, and the output terminal is used to output the first control signal.

[0007] In some embodiments, the memory further includes: a plurality of layers of memory arrays stacked in a vertical direction, each layer of the memory array comprising a plurality of word lines arranged along a first horizontal direction, the word lines extending along a second horizontal direction; a plurality of word line selection control lines for transmitting the word line selection signals, each layer of the memory array having a corresponding word line selection control line, and the word line selection switches corresponding to all the word lines of the memory array in the same layer being connected to the same word line selection control line; a plurality of discharge control lines for transmitting the discharge signals, each layer of the memory array having a corresponding discharge control line, and the discharge switches corresponding to all the word lines of the memory array in the same layer being connected to the same discharge control line; the word line selection control line and the discharge control line both extending along the first horizontal direction, and the word line selection control line and the discharge control line being located on opposite sides of the word line along the second horizontal direction.

[0008] In some embodiments, the memory further includes: a drive control line for transmitting the third control signal, the drive control line extending along the vertical direction, different word line selection switches stacked along the vertical direction are connected to the same drive control line, and different word line selection switches arranged along the first horizontal direction are connected to different drive control lines; a sleep control line for transmitting the sleep voltage, the sleep control line extending along the vertical direction, different discharge switches stacked along the vertical direction are connected to the same sleep control line, and different discharge switches arranged along the first horizontal direction are connected to different sleep control lines.

[0009] In some embodiments, the memory further includes: a multi-layer memory array stacked along a vertical direction, each layer of the memory array comprising a plurality of word lines arranged along a first horizontal direction, the word lines extending along a second horizontal direction; a plurality of drive control lines for transmitting the third control signal, each layer of the memory array having a corresponding drive control line, the word line selection switches corresponding to all the word lines of the memory array in the same layer being connected to the same drive control line; a sleep voltage transmission structure for transmitting the sleep voltage, the discharge switches corresponding to all the word lines of the memory array in the same layer being connected to the same sleep voltage transmission structure; the drive control line extending along the first horizontal direction, the sleep voltage transmission structure extending at least along the first horizontal direction, and the drive control line and the sleep voltage transmission structure being located on opposite sides of the word line along the second horizontal direction.

[0010] In some embodiments, the memory further includes: a word line selection control line for transmitting the word line selection signal, the word line selection control line extending along the vertical direction, different word line selection switches stacked along the vertical direction are connected to the same word line selection control line, and different word line selection switches arranged along the first horizontal direction are connected to different word line selection control lines; a discharge control line for transmitting the discharge signal, the discharge control line extending along the vertical direction, different discharge switches stacked along the vertical direction are connected to the same discharge control line, and different discharge switches arranged along the first horizontal direction are connected to different discharge control lines.

[0011] In some embodiments, the sleep voltage transmission structure extends along the first horizontal direction and the vertical direction, and the discharge switches corresponding to the word lines of the memory arrays at different layers are all connected to the same sleep voltage transmission structure.

[0012] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a memory control method, which may at least include: when the word line selection switch is turned on, first controlling the second control signal to enter a disabled state, and then controlling the discharge signal to be in an enabled state; after controlling the discharge signal to be in the enabled state, controlling the first control signal to be in an enabled state.

[0013] In some embodiments, the memory control method further includes: turning on the word line selection switch before turning off the bleeder switch.

[0014] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0015] In the embodiment of the present disclosure, by setting the word line selection switch WlselT, the output end of the inverter InV and the first end of the word line WL can be isolated, so that the first control signal Ctr1 and the second control signal Ctr2 have more timing freedom, for example, a high level can be output before the word line WL is activated, and a high level can continue to be output after the word line WL is turned off; in addition, since a discharge transistor Pd and a sleep voltage Vdis are provided, the word line WL can be turned off, so an additional pull-down transistor is no longer required between the inverter InV and the word line selection switch WlselT, which is beneficial to saving devices and reducing the device's occupied area. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more embodiments are exemplarily described by the pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0017] Figure 1 A circuit diagram of a memory provided by an embodiment of the present disclosure;

[0018] Figure 2 Another circuit diagram of a memory provided by an embodiment of the present disclosure;

[0019] Figure 3 A side view of a memory provided for an embodiment of the present disclosure;

[0020] Figure 4 A main view of a memory provided by an embodiment of the present disclosure;

[0021] Figure 5 A side view of a memory provided according to another embodiment of the present disclosure;

[0022] Figure 6 A front view of a memory provided in accordance with another embodiment of the present disclosure;

[0023] Figure 7 A timing diagram of a memory control method provided in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0025] Figure 1 A circuit diagram of a memory provided in an embodiment of the present disclosure.

[0026] refer to Figure 1 The memory includes: an inverter InV, an input end for receiving a first control signal Ctr1, a power supply end for receiving a second control signal Ctr2, an output end connected to a first end of a word line WL through a word line selection switch WlselT, a second end of the word line WL connected to a sleep voltage Vdis through a discharge switch PdT, a gate of the word line selection switch WlselT for receiving a word line selection signal Wlsel, and a gate of the discharge switch PdT for receiving a discharge signal Pd.

[0027] In the embodiment of the present disclosure, by setting the word line selection switch WlselT, the output end of the inverter InV and the first end of the word line WL can be isolated, so that the first control signal Ctr1 and the second control signal Ctr2 have more timing freedom, for example, a high level can be output before the word line WL is activated, and a high level can continue to be output after the word line WL is turned off; in addition, since a discharge transistor Pd and a sleep voltage Vdis are provided, the word line WL can be turned off, so an additional pull-down transistor is no longer required between the inverter InV and the word line selection switch WlselT, which is beneficial to saving devices and reducing the device's occupied area.

[0028] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0029] In the embodiment of the present disclosure, the inverter InV plays a driving role, and is therefore often referred to as a word line driver. In other words, in the embodiment of the present disclosure, the word line driver is composed of only two transistors in the inverter InV, and has a relatively simple structure. Specifically, the inverter InV includes a pull-up transistor P1 for pulling up, and the pull-up transistor can be a Pmos tube, and includes a pull-down transistor N1 for pulling down, and the pull-down transistor can be an Nmos tube. Among them, the gates of the pull-up transistor P1 and the pull-down transistor N1 are connected as the input end of the inverter InV, the drain end of the pull-up transistor P1 and the drain end of the pull-down transistor N1 are connected as the output end of the inverter InV, and the source end of the pull-down transistor N1 is used to receive a low-level signal.

[0030] Furthermore, the word line selection switch WlselT and the discharge switch PdT can be set as a PMOS tube or an NMOS tube as needed. Figure 3-Figure 7 In the embodiment of FIG. 5 , the word line selection switch WlselT and the discharge switch PdT are both NMOS transistors as an example.

[0031] In the disclosed embodiment, the same word line WL is connected to multiple memory cell cells, different memory cell cells are connected to different bit lines BL, and different word lines WL may share the same bit line BL or correspond to different bit lines BL.

[0032] In some embodiments, the second control signal Ctr2 is an inverted signal of the first control signal Ctr1. In this embodiment, the different first control signals Ctr1 received by different inverters InV are relatively independent. That is, the voltages output by different inverters InV in the same memory block are completely determined by the first control signal Ctr1. It can be understood that when the word line selection switches WlselT corresponding to all inverters InV are turned on, in order to ensure that only one word line WL is activated at the same time, the first control signal Ctr1 corresponding to only one inverter InV should be a low-level signal. In addition, by setting the second control signal Ctr2 to the inverted signal of the first control signal Ctr1, it is helpful to reduce the number of decoding circuits, so that only the first control signal Ctr1 needs to be generated based on the row address decoding, and there is no need to decode and generate the relatively independent first control signal Ctr1 and second control signal Ctr2 based on the row address. At the same time, it is also helpful to avoid the first control signal Ctr1 and the second control signal Ctr2 being simultaneously low.

[0033] A memory block typically refers to a multi-layer memory array stacked vertically. In some embodiments, a single memory block is configured to receive m first control signals Ctr1, where m is a positive integer less than or equal to 128, such as 16, 24, 32, 64, 96, or 128. It will be appreciated that when m is greater than 128, since each control signal Ctr1 is generated by a relatively independent device, the device used to generate the m first control signals Ctr1 may occupy a relatively large area.

[0034] In another embodiment of the present disclosure, the memory further includes: a NAND circuit, wherein the first input terminal of the NAND circuit is used to receive the first row address decoding signal, the second input terminal is used to receive the second control signal, and the output terminal is used to output the first control signal. It should be noted that the NAND circuit may include multiple NAND sub-circuits, and different NAND sub-circuits receive different first row address decoding signals and / or different second control signals. Among the multiple first row address decoding signals and multiple second control signals received by the multiple NAND sub-circuits, only one row address decoding signal and one second control signal are at a high level. The second control signal Ctr2 can also be obtained based on the row address decoding. Generating the first control signal Ctr1 by the NAND circuit and the second control signal is conducive to avoiding the first control signal Ctr1 and the second control signal Ctr2 being at a low level at the same time, while ensuring that only one of the multiple first control signals Ctr1 generated is in a low level state, thereby enabling only a single inverter InV to output the high level voltage received by the power supply end.

[0035] In a specific embodiment, the same memory block receives voltage signals output by 64 different inverters Inv, and the 64 different inverters InV are controlled by a 6-bit row address. Figure 2 The first decoder Dec1 decodes the 3-bit row address RA<2:0> and outputs eight first row address decoding signals A<7:0>. The second decoder Dec2 decodes another 3-bit row address RA<5:3> and outputs eight second control signals Ctr2<7:0>. The NAND circuit NAND<63:0> generates 64 first control signals Ctr1<63:0> based on the eight first row address decoding signals A<7:0> and the eight second control signals Ctr2<7:0>. The NAND circuit NAND<63:0> may include 64 NAND sub-circuits, each of which is used to generate a first control signal Ctr1. It is understood that the number and location of row addresses received by the first and second decoders Dec1 and Dec2 can vary; it is sufficient to ensure that the first and second decoders Dec1 and Dec2 decode based on six different row addresses.

[0036] In some embodiments, the memory includes: a plurality of layers of memory arrays stacked in a vertical direction, each layer of memory array including a plurality of word lines arranged along a first horizontal direction, and the word lines extending along a second horizontal direction; a plurality of word line selection control lines for transmitting word line selection signals, each layer of memory array having a corresponding word line selection control line, and word line selection switches corresponding to all word lines of the same layer of memory array being connected to the same word line selection control line; a plurality of discharge control lines for transmitting discharge signals, each layer of memory array having a corresponding discharge control line, and discharge switches corresponding to all word lines of the same layer of memory array being connected to the same discharge control line; the word line selection control line and the discharge control line both extend along the first horizontal direction, and the word line selection control line and the discharge control line are located on opposite sides of the word line along the second horizontal direction.

[0037] In some embodiments, a memory device includes stacked memory chips and peripheral circuit chips, which can be electrically connected via hybrid bonding or other methods. The memory chip can include multiple memory structures stacked vertically, each memory structure including multiple memory arrays arranged in an array along a first horizontal direction and a second horizontal direction. The multiple memory arrays stacked vertically constitute the aforementioned memory block. The first horizontal direction, the second horizontal direction, and the vertical direction are perpendicular to each other.

[0038] refer to Figure 3 and Figure 4 , Figure 3 A side view of a memory provided by an embodiment of the present disclosure, further comprising: Figure 3 A side view of a memory chip that may be provided in an embodiment of the present disclosure; Figure 4A main view of the memory provided by the embodiment of the present disclosure, further, Figure 4 This may be a front view of the memory chip provided by an embodiment of the present disclosure.

[0039] refer to Figure 3 and Figure 4 The memory includes: a multi-layer memory array Array stacked along a vertical direction Z, each layer of the memory array Array including a plurality of word lines WL arranged along a first horizontal direction X, the word lines WL extending along a second horizontal direction Y; a plurality of word line selection control lines CL1 for transmitting a word line selection signal Wlsel, each layer of the memory array Array having a corresponding word line selection control line CL1, and gates of word line selection switches WlselT corresponding to all word lines WL in the same layer of the memory array Array being connected to the same word line selection control line CL1; a plurality of discharge control lines CL2 for transmitting a discharge signal Pd, each layer of the memory array Array having a corresponding discharge control line CL2, and discharge switches PdT corresponding to all word lines WL in the same layer of the memory array Array being connected to the same discharge control line CL2; the word line selection control line CL1 and the discharge control line CL2 both extending along the first horizontal direction X, and the word line selection control line CL1 and the discharge control line CL2 being located on opposite sides of the word line WL in the second horizontal direction.

[0040] To make it clearer, Figure 3 Each word line selection control line CL1 is marked with a purple line. The multiple word line selection control lines CL1 are the first word line selection control line CL11 to the fifth word line selection control line CL15. This clearly illustrates that different word line selection control lines CL1 receive different word line selection signals Wlsel. The multiple word line selection signals Wlsel are the first word line selection signal Wlsel1 to the fifth word line selection signal Wlsel5. Furthermore, the potentials of different word line selection control lines CL1 in a specific scenario are also marked. Specifically, only the second word line selection control line CL12 is at a high potential H, while the remaining word line selection control lines CL1 are at a low potential L. To more clearly distinguish the word line selection control lines CL1 at different potentials, the word line selection control lines CL1 at a high potential H are drawn with a solid purple line, and the word line selection control lines CL1 at a low potential are drawn with a dashed purple line.

[0041] also, Figure 3 Each drive control line CL3 is marked with a red line. The drive control line CL3 is used to transmit the third control signal Ctr3. The potential of different drive control lines CL3 in a specific scenario is also marked. The drive control line CL3 at a high level H is drawn with a red solid line, and the drive control line CL3 at a low level L is drawn with a red dotted line.

[0042] Figure 4 In addition to the purple and red lines, multiple discharge control lines CL2 are also marked with green lines. The multiple discharge control lines CL2 are respectively the first discharge control line CL21 to the fifth discharge control line CL25. The discharge control lines CL2 and the word line selection control line CL1 both extend along the first horizontal direction X. Figure 4 All the discharge control lines CL2 are marked with green solid lines, without marking the potential and without using solid lines and dashed lines to distinguish different discharge control lines CL2. It can be understood that this does not mean that the potentials of all discharge control lines CL2 are the same.

[0043] It should be noted that Figure 3 and Figure 4 A five-layer storage array is used as an example. Figure 3 Only two word line selection switches WlselT arranged along the first horizontal direction X are shown. Figure 4 In the figure, only one word line selection switch WlselT and one bleeder switch PdT are shown in the first horizontal direction X. However, in an actual memory or memory block structure, there is no limit on the number of stacked layers of the memory array Array in the vertical direction Z, nor on the number of word line selection switches WlselT and bleeder switches PdT arranged in the first horizontal direction X. The number of word line selection switches WlselT, the number of word lines WL, and the number of bleeder switches PdT arranged in the first horizontal direction X are generally equal.

[0044] Further references Figure 3 and Figure 4 The memory further includes: a driving control line CL3 for transmitting a third control signal Ctr3, the driving control line CL3 extending along a vertical direction Z, different word line selection switches WlselT stacked along the vertical direction Z connected to the same driving control line CL3, and different word line selection switches WlselT arranged along the first horizontal direction X connected to different driving control lines CL3; a sleep control line CL4 for transmitting a sleep voltage Vdis, the sleep control line Vdis extending along the vertical direction Z, different discharge switches PdT stacked along the vertical direction Z connected to the same sleep control line CL4, and different discharge switches PdT arranged along the first horizontal direction X connected to different sleep control lines CL4.

[0045] It can be understood that if a memory block includes m word lines arranged along a first horizontal direction X and n word lines WL arranged along a vertical direction Z, the memory block correspondingly includes m drive control lines CL3 and m sleep control lines CL4 arranged along the first horizontal direction X and extending along the vertical direction Z. Both m and n are positive integers greater than 1.

[0046] exist Figure 4 In the illustrated embodiment, the drive control line CL3 and the sleep control line CL4 are located on the same side of the corresponding word line WL in the first horizontal direction X, and different drive control lines CL3 and different sleep control lines CL4 are located on the same side of the corresponding word line WL in the first horizontal direction X; in other embodiments, the drive control line CL3 and the sleep control line CL4 may be located on different sides of the corresponding word line WL in the first horizontal direction X. In this case, different drive control lines CL3 corresponding to adjacent word lines WL may be located on the same side or different sides of the corresponding word line WL in the first horizontal direction X, and accordingly, different sleep control lines corresponding to adjacent word lines WL may be located on the same side or different sides of the corresponding word line WL in the first horizontal direction X.

[0047] In yet other embodiments, the sleep control line CL4 may be located on one side of the word line WL in the second horizontal direction Y. That is, the word line selection control line CL1 and the sleep control line CL4 are located on opposite sides of the word line WL in the second horizontal direction Y, and the discharge control line CL2 may be located between the sleep control line CL4 and the word line WL. Furthermore, different sleep control lines CL4 arranged along the first horizontal direction X may be electrically connected to each other, or even form a wall-like structure, which can be used to simultaneously provide the sleep voltage Vdis to all discharge switches PdT.

[0048] The following will be based on Figure 3 The potentials of the control signals received by different word line select switches WlselT (first word line select switch T1 to fourth word line select switch T4) affect the operating states of the corresponding word lines WL and the bleeder switch PdT. The first word line select switch T1 and the second word line select switch T2 are located in different layers of the memory array Array and are connected to the same drive control line CL3; the third word line select switch T3 and the fourth word line select switch T4 are located in different layers of the memory array Array and are connected to the same drive control line CL3; the first word line select switch T1 and the third word line select switch T3 are located in the same layer of the memory array Array and are connected to different drive control lines CL3; and the second word line select switch T2 and the fourth word line select switch T4 are located in the same layer of the memory array Array and are connected to different drive control lines CL3.

[0049] For the first word line selection switch T1, the drain terminal receives the high-level third control signal Ctr3, and the gate terminal receives the high-level word line selection signal Wlsel (i.e., the second word line selection signal Wlsel2). The first word line selection switch T1 is turned on. At this time, the potential of the corresponding word line WL is pulled high, and the corresponding discharge switch PdT should be turned off, that is, the discharge signal Pd is at a low level.

[0050] For the second word line selection switch T2, the drain terminal receives the high-level third control signal Ctr3, and the gate receives the low-level word line selection signal Wlsel (i.e., the fifth word line selection signal Wlsel5). The second word line selection switch T2 is turned off. At this time, the corresponding discharge switch PdT should be turned on to pull the voltage of the corresponding word line WL down to a low level through the sleep voltage Vdis. It should be noted that Figure 3 and Figure 4 The illustrated embodiment is described by taking as an example that only one word line WL can be activated at the same time in the same memory block; in other embodiments, multiple word lines WL can be activated at the same time in the same memory block, and the multiple activated word lines are in the same layer of the memory array Array or in different layers of the memory array Array. It is only necessary to ensure that the different word lines WL activated at the same time do not share the bit line BL.

[0051] In some embodiments, the bit lines include local bit lines and common bit lines. The local bit lines are electrically connected to memory cells. Multiple local bit lines are electrically connected to the same common bit line via local bit line select switches. To avoid data conflicts, only one local bit line select switch can be enabled at a time. In this embodiment, the phrase "different word lines WL do not share a common bit line BL" means that different word lines WL that are activated simultaneously have different local bit lines and different common bit lines corresponding to them.

[0052] For the third word line select switch T3, the drain terminal receives a low-level third control signal Ctr3, and the gate terminal receives a high-level word line select signal Wlsel (i.e., the second word line select signal Wlsel2). When the third word line select switch T3 is turned on, the third control signal Ctr3 pulls the voltage of the word line WL down to a low level. Furthermore, the corresponding bleeder switch PdT is also turned on, simultaneously pulling the voltage of the word line WL down to a low level via the sleep voltage Vdis. When the word line WL is at a low level, the access transistor in the memory cell is turned off, and charge sharing does not occur between the storage capacitor and the bit line BL.

[0053] For the fourth word line selection switch T4, the drain terminal receives the low-level third control signal Ctr3, and the gate terminal receives the low-level word line selection signal Wlsel (i.e., the fifth word line selection signal Wlsel5). The fourth word line selection switch T4 is disconnected. At this time, the corresponding discharge switch PdT should be turned on to pull the voltage of the corresponding word line WL down to a low level through the sleep voltage Vdis.

[0054] refer to Figure 5 and Figure 6 , Figure 5 A side view of a memory provided in another embodiment of the present disclosure, further comprising: Figure 5 A side view of a memory chip that may be provided in accordance with another embodiment of the present disclosure; Figure 6 This is a main view of a memory provided by another embodiment of the present disclosure, further, Figure 6 This is a front view of a memory chip provided by another embodiment of the present disclosure.

[0055] refer to Figure 5 and Figure 6 The memory includes: a multi-layer memory array Array stacked along a vertical direction Z, each layer of the memory array Array including a plurality of word lines WL arranged along a first horizontal direction X, the word lines WL extending along a second horizontal direction Y; a plurality of drive control lines CL3 for transmitting a third control signal Ctr3, each layer of the memory array Array having a corresponding drive control line CL3, word line selection switches WlselT corresponding to all word lines WL in the same layer of the memory array Array being connected to the same drive control line CL3; a sleep voltage transmission structure SS for transmitting a sleep voltage Vdis, discharge switches PdT corresponding to all word lines WL in the same layer of the memory array Array being connected to the same sleep voltage transmission structure SS; the drive control line CL3 extending along the first horizontal direction X, the sleep voltage transmission structure SS extending at least along the first horizontal direction X, and the drive control line CL3 and the sleep voltage transmission structure SS being located on opposite sides of the word line WL in the second horizontal direction Y.

[0056] It is understandable that Figure 5 and Figure 6 The embodiment shown is relative to Figure 3 and Figure 4 The illustrated embodiments share a common feature of using five stacked memory array layers as an example. In each embodiment, only one or two word line selection switches WlselT are shown in the first horizontal direction X. In each embodiment, one discharge switch PdT is shown in the first horizontal direction X. The word line selection switches WlselT are electrically connected to the discharge switch PdT via a word line WL extending along a second horizontal direction Y. Different word line selection switches WlselT in the same memory array layer receive the same control signal, and different discharge switches PdT in the same memory array layer receive the same voltage signal.

[0057] The difference is that in Figure 3 and Figure 4 In the embodiment shown, different word line selection switches WlselT in the same layer of the memory array Array receive the same control signal, which is the word line selection signal Wlsel. The word line selection control line CL1 extends along the first horizontal direction X, and the drive control line CL3 extends along the vertical direction Z. Correspondingly, different discharge switches PdT in the same layer of the memory array Array all receive the same discharge signal Pd. The discharge control line CL2 extends along the first horizontal direction X, and the sleep control line CL4 extends along the vertical direction Z. However, in Figure 5and Figure 6 In the illustrated embodiment, different word line selection switches WlselT in the same layer of the memory array Array receive the same control signal, namely, the third control signal Ctr3. The word line selection control line CL1 extends along the vertical direction Z, and the drive control line CL3 extends along the first horizontal direction X. Correspondingly, different discharge switches PdT in the same layer of the memory array Array all receive the sleep voltage Vdis. The discharge control line CL2 extends along the vertical direction Z, and the sleep voltage transmission structure SS extends at least along the first horizontal direction X.

[0058] It is understood that in some embodiments, the same memory block may correspond to multiple sleep voltage transmission structures SS, with each layer of the memory array having a corresponding sleep voltage transmission structure SS. The different sleep voltage transmission structures SS are independent of each other and are all used to receive and transmit the sleep voltage Vdis. In other embodiments, the same memory block corresponds to only one sleep voltage transmission structure, and memory arrays at different layers correspond to the same sleep voltage transmission structure. The sleep voltage transmission structure may be a wall-shaped structure, which may be composed of multiple sleep voltage transmission substructures electrically connected to each other via a connection structure. The wall-shaped sleep voltage transmission structure may contain a cavity surrounded by the sleep voltage transmission substructures and the connection structure. Each sleep voltage transmission substructure corresponds to a different layer of the memory array.

[0059] Further, in Figure 5 and Figure 6 In the illustrated embodiment, the memory further includes: a word line selection control line CL1, for transmitting a word line selection signal Wlsel, the word line selection control line CL1 extending along a vertical direction Z, different word line selection switches WlselT stacked along the vertical direction Z are connected to the same word line selection control line CL1, and different word line selection switches WlselT arranged along a first horizontal direction X are connected to different word line selection control lines CL1; and a discharge control line CL2, for transmitting a discharge signal Pd, the discharge control line CL2 extending along the vertical direction Z, different discharge switches PdT stacked along the vertical direction Z are connected to the same discharge control line CL2, and different discharge switches PdT arranged along the first horizontal direction X are connected to different discharge control lines CL2.

[0060] exist Figure 5 and Figure 6In the illustrated embodiment, the first word line selection switch T1 is turned on based on a high-level word line selection signal Wlsel, and the word line WL is activated based on a high-level third control signal Ctr3, at which point the corresponding bleeder switch PdT is turned off; the second word line selection switch T2 is turned on based on a high-level word line selection signal Wlsel, and the word line WL is pulled down to a low level based on a low-level third control signal Ctr3, at which point the corresponding bleeder switch PdT can be turned on or off; the third word line selection switch T3 is turned off based on a low-level word line selection signal Wlsel, at which point the corresponding bleeder switch PdT should be turned on to lower the voltage of the word line WL via the sleep voltage Vdis, thereby preventing the word line from being in a floating state; the fourth word line selection switch T4 is turned off based on a low-level word line selection signal Wlsel, at which point the corresponding bleeder switch PdT should be turned on to lower the voltage of the word line WL via the sleep voltage Vdis, thereby preventing the word line from being in a floating state.

[0061] It should be noted that in Figures 3 to 6 In the embodiment, the word line selection control line CL1, the discharge control line CL2, the drive control line CL3 and the sleep control line CL4 (or the sleep voltage transmission structure SS) are all part of the memory block; the control lines extending along the first horizontal direction X, for example Figure 3-4 The word line selection control line CL1 and the drain control line CL2 shown in FIG. Figure 5-6 The driving control lines CL3 shown in FIG. 1 are all part of the memory array of the corresponding layer.

[0062] In the embodiment of the present disclosure, by setting the word line selection switch WlselT, the output end of the inverter InV and the first end of the word line WL can be isolated, so that the first control signal Ctr1 and the second control signal Ctr2 have more timing freedom, for example, they can output a high level before the word line WL is activated, and continue to output a high level after the word line WL is turned off; in addition, since the discharge transistor Pd and the sleep voltage Vdis are provided, the word line WL can be turned off, so there is no need to set an additional pull-down transistor between the inverter InV and the word line selection switch WlselT, which is beneficial to saving devices.

[0063] Figure 7 A timing diagram of a memory control method provided in another embodiment of the present disclosure. Figure 7 The timing diagram of the memory control method shown in FIG. 1 can be used in any of the above embodiments. Figure 7 , the memory control method includes:

[0064] When the word line selection switch is turned on, the second control signal Ctr2 is first controlled to enter the disabled state, and then the discharge signal Pd is controlled to be enabled. After the discharge signal Pd is controlled to be enabled, the first control signal Ctr1 is controlled to be enabled.

[0065] In the embodiment of the present disclosure, when the word line selection switch is turned on, the second control signal Ctr2 is first controlled to enter a disabled state, which is conducive to enabling the word line WL to be discharged for the first time through the power supply terminal of the inverter; then the discharge signal Pd is controlled to be in an enabled state, which is conducive to enabling the word line WL to be discharged for the second time based on the sleep voltage; finally, the first control signal Ctr1 is controlled to be in an enabled state, and the third discharge is performed through the pull-down transistor in the inverter. This is conducive to making the source-drain voltage difference of the pull-down transistor in the inverter smaller during the third discharge, thereby effectively avoiding the hot carrier injection effect (HCI) in the pull-down transistor; at the same time, the time for the word line to be pulled down to a low level is extended, which is conducive to allowing the charge that enters the substrate for various reasons during the data reading and writing process to enter the storage capacitor.

[0066] In some embodiments, the memory control method further includes: turning on the word line selection switch WlselT before turning off the discharge switch PdT, so as to prevent the word line WL from being in a floating state.

[0067] The following will be combined Figure 7 The memory control method is further described. Figure 7 In the embodiment shown, the low level includes the first voltage V1 and the second voltage V2. Unless otherwise specified, the signal entering or being in a disabled state refers to the signal entering or being in a low level. Correspondingly, the high level includes the third voltage V3 and the second voltage V4. Unless otherwise specified, the signal entering or being in an enabled state refers to the signal entering or being in a high level. Figure 7 In the illustrated embodiment, word line WL has a first voltage when inactive and a third voltage when active. The word line select signal Wlsel is enabled at a fourth voltage, effectively pulling word line WL up to a third voltage V3. The discharge signal Pd is enabled at a fourth voltage, enabling rapid discharge of the voltage on word line WL. The enabled voltages of all other signals are the third voltage, and the disabled voltages of all signals except word line WL are the second voltage. The second voltage V2 can be 0V, and the first voltage V1 can be a negative voltage.

[0068] exist Figure 1 and Figure 7In the illustrated embodiment, the timing diagram includes at least two phases: word line activation (WL on) and word line deactivation (WL off). During the phase between word line activation and word line deactivation, when the word line remains activated, the potentials of various signals remain unchanged, or in other words, the on / off states of various switches / transistors remain unchanged. During the word line activation phase, the word line select signal Wlsel first enters the enabled state to turn on the word line select switch WlselT, and then turns off the bleeder switch PdT to prevent word line WL from floating. After turning off the bleeder switch PdT, the first control signal Ctr1 is first controlled to enter the disabled state to connect the power supply terminal and the output terminal of the inverter InV. This prevents leakage and increased power consumption of the pull-up transistor P1 caused by the second control signal Ctr2 being in the enabled state while the pull-up transistor P1 is turned off. It can be seen that after the second control signal Ctr2 enters the enabled state, the voltage of the word line WL is gradually pulled up.

[0069] It can be understood that turning on the word line selection switch WlselT before the first control signal Ctr1 enters the disabled state is beneficial to avoiding the situation where the gate voltage of the word line selection switch WlselT is low and the drain voltage is high, thereby reducing the gate induced leakage current and enhancing the device reliability of the word line selection switch WlselT.

[0070] At the same time, when the word line is turned off, the second control signal Ctr2 first enters the disabled state, then the discharge signal Pd enters the disabled state, and then the first control signal Ctr1 enters the enabled state. After three discharges, the word line selection signal Wlsel is controlled to enter the disabled state, turning off the word line selection switch WlselT, and maintaining the word line WL in the off state only by relying on the sleep voltage. In addition, through three different discharges, not only can the HCI effect of the pull-down transistor in the inverter InV be weakened, but it is also helpful to slow down the potential pull-down state of the word line WL (the voltage pull-down speed of the word line is less than the voltage pull-up speed, or in other words, the word line voltage pull-down time is 2-6 times the word line voltage pull-up time, for example, 2, 3, 4, 5 or 6 times), so that the charge entering the substrate due to various reasons during the data reading and writing process can enter the storage capacitor.

[0071] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present disclosure. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope defined in the claims.

Claims

1. A memory, characterized in that: include: An inverter, wherein the input end is used to receive a first control signal, the power supply end is used to receive a second control signal, the output end is used to output a third control signal, the output end is connected to a first end of a word line through a word line selection switch, the second end of the word line is connected to a sleep voltage through a discharge switch, the gate of the word line selection switch is used to receive a word line selection signal, and the gate of the discharge switch is used to receive a discharge signal.

2. The memory according to claim 1, wherein The second control signal is an inverted signal of the first control signal.

3. The memory according to claim 1, wherein: It also includes: a NAND circuit, wherein the first input end of the NAND circuit is used to receive the first row address decoding signal, the second input end is used to receive the second control signal, and the output end is used to output the first control signal.

4. The memory according to claim 1, wherein: include: A multi-layer memory array stacked in a vertical direction, each layer of the memory array comprising a plurality of word lines arranged along a first horizontal direction, the word lines extending along a second horizontal direction; a plurality of word line selection control lines for transmitting the word line selection signal, each layer of the memory array having a corresponding word line selection control line, and the word line selection switches corresponding to all the word lines of the memory array in the same layer are connected to the same word line selection control line; a plurality of discharge control lines for transmitting the discharge signal, wherein each layer of the memory array has a corresponding discharge control line, and the discharge switches corresponding to all the word lines of the memory array in the same layer are connected to the same discharge control line; The word line selection control line and the drain control line both extend along the first horizontal direction, and the word line selection control line and the drain control line are located on two opposite sides of the word line along the second horizontal direction.

5. The memory according to claim 4, wherein: include: a drive control line, configured to transmit the third control signal, the drive control line extending along the vertical direction, different word line selection switches stacked along the vertical direction connected to the same drive control line, and different word line selection switches arranged along the first horizontal direction connected to different drive control lines; A sleep control line is used to transmit the sleep voltage, the sleep control line extends along the vertical direction, different discharge switches stacked along the vertical direction are connected to the same sleep control line, and different discharge switches arranged along the first horizontal direction are connected to different sleep control lines. The memory according to claim 1 , wherein: include: A multi-layer memory array stacked in a vertical direction, each layer of the memory array comprising a plurality of word lines arranged along a first horizontal direction, the word lines extending along a second horizontal direction; a plurality of drive control lines for transmitting the third control signal, each layer of the memory array having a corresponding drive control line, and the word line selection switches corresponding to all the word lines of the memory array in the same layer being connected to the same drive control line; A sleep voltage transmission structure, configured to transmit the sleep voltage, wherein the discharge switches corresponding to all the word lines of the memory array at the same layer are connected to the same sleep voltage transmission structure; The driving control line extends along the first horizontal direction, the sleep voltage transmission structure extends at least along the first horizontal direction, and the driving control line and the sleep voltage transmission structure are located on opposite sides of the word line along the second horizontal direction.

7. The memory according to claim 6, wherein: include: a word line selection control line, configured to transmit the word line selection signal, the word line selection control line extending along the vertical direction, different word line selection switches stacked along the vertical direction being connected to the same word line selection control line, and different word line selection switches arranged along the first horizontal direction being connected to different word line selection control lines; A discharge control line is used to transmit the discharge signal, the discharge control line extending along the vertical direction, different discharge switches stacked along the vertical direction are connected to the same discharge control line, and different discharge switches arranged along the first horizontal direction are connected to different discharge control lines.

8. The memory according to claim 6, wherein: The sleep voltage transmission structure extends along the first horizontal direction and the vertical direction, and the discharge switches corresponding to the word lines of the memory arrays at different layers are all connected to the same sleep voltage transmission structure.

9. A memory control method, applied to the memory according to any one of claims 1 to 8, characterized in that: include: When the word line selection switch is turned on, first controlling the second control signal to enter a disabled state, and then controlling the discharge signal to be in an enabled state; After controlling the discharge signal to be in the enabled state, controlling the first control signal to be in the enabled state.

10. The memory control method according to claim 9, comprising: The word line selection switch is turned on before the bleeder switch is turned off.

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