Semiconductor structure and manufacturing method thereof

Abstract

A semiconductor structure includes a silicon carbide substrate and an epitaxial layer. The top surface of the silicon carbide substrate is provided with a plurality of concave parts, the bottommost part of each concave part is provided with a first inclined surface and a second inclined surface which are connected with each other, and the included angle between the first inclined surface and the second inclined surface is 88-92 degrees. The epitaxial layer is disposed on a top surface of the silicon carbide substrate. Before silicon carbide epitaxy is carried out, the silicon carbide substrate is pretreated to form the plurality of concave parts on the top surface of the silicon carbide substrate, so that the surface property of the silicon carbide substrate is further changed, the conversion efficiency of converting BPD into TED can be improved, and the epitaxy quality is further improved.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Art

[0002] Silicon carbide (SiC) is a special semiconductor material with characteristics such as wide bandwidth, high critical breakdown electric field, high thermal conductivity, and high carrier saturation drift velocity. It is suitable for the manufacture of high-temperature, high-voltage, high-power, and radiation-resistant semiconductor devices. Although SiC materials have many advantages, there are often a large number of defects in SiC materials, such as basal plane dislocations (BPDs). These defects will further extend from the substrate to the epitaxial layer, causing the reverse leakage current of the semiconductor device to increase or the breakdown voltage to decrease, resulting in reduced reliability of the semiconductor device. Compared with BPDs, threading edge dislocations (TEDs) have less impact on the performance of semiconductor devices. Therefore, how to increase the ratio of BPDs converted to TEDs during SiC epitaxial growth and prevent BPDs in the substrate from extending into the epitaxial layer is very important for improving the performance of semiconductor devices. Summary of the Invention

[0003] According to one or more embodiments of the present disclosure, a semiconductor structure includes a silicon carbide substrate and an epitaxial layer. The top surface of the silicon carbide substrate has multiple recesses, each of which has a first inclined surface and a second inclined surface connected at the bottom thereof, with the angle between the first inclined surface and the second inclined surface being 88 to 92 degrees. The epitaxial layer is disposed on the top surface of the silicon carbide substrate.

[0004] In one or more embodiments of the present disclosure, an average value of the maximum width of the recesses is 5 μm to 35 μm.

[0005] According to one or more embodiments of the present disclosure, a method for manufacturing a semiconductor structure includes: performing an etching process on the top surface of a silicon carbide substrate using an alkaline etching solution, wherein the alkaline etching solution contains at least one alkaline substance having hydroxyl groups; after the etching process, performing a polishing process on the top surface of the silicon carbide substrate using a polishing solution, wherein the polishing solution includes hydrogen peroxide and a plurality of silicon dioxide particles; and performing an epitaxial process on the top surface of the silicon carbide substrate to form an epitaxial layer.

[0006] In one or more embodiments of the present disclosure, the alkaline substance is potassium hydroxide, sodium hydroxide, tetramethylammonium hydroxide, or a combination thereof.

[0007] In one or more embodiments of the present disclosure, the weight of the alkaline substance is 80 wt % to 90 wt % based on the total weight of the alkaline etching solution.

[0008] In one or more embodiments of the present disclosure, the average particle size of the silicon dioxide particles is 70 nm to 80 nm.

[0009] In one or more embodiments of the present disclosure, the weight of the silicon dioxide particles is 5 wt % to 25 wt % based on the total weight of the polishing liquid.

[0010] In one or more embodiments of the present disclosure, the grinding depth of the top surface of the silicon carbide substrate is 0.10 μm to 0.20 μm.

[0011] According to one or more embodiments of the present disclosure, a method for manufacturing a semiconductor structure includes: performing an etching process on a top surface of a silicon carbide substrate to form a plurality of etch pits on the top surface, wherein the average maximum width of the etch pits is 30 to 50 microns; after the etching process, performing a grinding process on the top surface of the silicon carbide substrate to reduce the average maximum width of the etch pits to 5 to 35 microns; and performing an epitaxial process on the top surface of the silicon carbide substrate to form an epitaxial layer.

[0012] In one or more embodiments of the present disclosure, during the epitaxial process, the conversion rate of basal plane dislocations to threading edge dislocations in the epitaxial layer is greater than 99.98%.

[0013] According to the above-mentioned embodiment of the present disclosure, by pre-treating the silicon carbide substrate before performing silicon carbide epitaxy to form multiple recesses on the top surface of the silicon carbide substrate, thereby changing the surface properties of the silicon carbide substrate, the conversion efficiency of BPD to TED can be improved, thereby improving the epitaxial quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] To make the above and other objects, features, advantages and embodiments of the present disclosure more apparent and understandable, the accompanying drawings are described as follows:

[0015] Figure 1 is a schematic side view of a semiconductor structure according to some embodiments of the present disclosure;

[0016] Figure 2 is a schematic side view of a semiconductor structure of a comparative example; and

[0017] Figure 3 The present invention is a flowchart of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] The following drawings illustrate various embodiments of the present disclosure. For clarity, many practical details will be included in the following description. However, it should be understood that these practical details should not be construed as limiting the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not essential and therefore should not be construed as limiting the present disclosure. Furthermore, to simplify the drawings, some conventional structures and components are depicted in simplified schematic form. Furthermore, for ease of viewing, the dimensions of the components in the drawings are not drawn to scale.

[0019] It should be understood that although the terms "first," "second," and "third," etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, the "first element," "component," "region," "layer," or "portion" described below may also be referred to as a second element, component, region, layer, or portion without departing from the teachings of this document.

[0020] On the other hand, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element, as shown in the accompanying drawings. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the drawings. For example, if the device in a drawing is turned over, the element described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. Thus, the exemplary term "lower" can include both "lower" and "upper" orientations, depending on the particular orientation of the drawing. Similarly, if the device in a drawing is turned over, the element described as being "lower" or "below" other elements will be oriented as being "above" the other elements. Thus, the exemplary terms "lower" or "below" can include both "lower" and "upper" orientations.

[0021] This disclosure relates to a method for improving the reliability of semiconductor structures. Specifically, this method pre-treats the silicon carbide substrate prior to epitaxial deposition, modifying the surface properties of the silicon carbide substrate. This improves the conversion efficiency of BPDs to TEDs, thereby reducing the probability of killer defects and improving epitaxial quality. Consequently, the disclosed semiconductor structure can meet the performance and reliability requirements of high-voltage and high-current electronic devices.

[0022] See also Figure 1, which is a schematic side view of a semiconductor structure 100 according to some embodiments of the present disclosure. Specifically, the semiconductor structure 100 of the present disclosure includes a silicon carbide substrate 110 and an epitaxial layer 120, with the epitaxial layer 120 disposed on the top surface 111 of the silicon carbide substrate 110, wherein the top surface 111 of the silicon carbide substrate 110 serves as the crystal growth surface. It should be understood that the silicon carbide substrate 110 of the present disclosure has a 4H-SiC crystal structure, and the present disclosure contemplates the use of 4H-SiC homoepitaxial growth.

[0023] See Figure 1 In the locally enlarged area R in FIG, the top surface 111 of the silicon carbide substrate 110 has a plurality of recesses C. The bottom of the recess C has a first inclined surface S1 and a second inclined surface S2 connected to each other, that is, the lowest point P of the recess C is any point in the intersection of the first inclined surface S1 and the second inclined surface S2. In addition, the angle θ1 between the first inclined surface S1 and the second inclined surface S2 is 88 to 92 degrees. For example, the angle θ1 may be 88 degrees, 89 degrees, 90 degrees, 91 degrees or 92 degrees. With such a design, when the epitaxial layer 120 is subsequently formed by epitaxially growing upward from the silicon carbide substrate 110, the conversion efficiency of BPD to TED can be improved, thereby improving the quality of epitaxial growth. In a preferred embodiment, the angle θ1 may be 90 degrees. The following will be Figure 1 and Figure 2 The reason for this is explained by comparing them. It should be understood that the Burgers vector direction of the BPD (denoted by "BPD" in the figure) and the Burgers vector direction of the TED (denoted by "TED" in the figure) are perpendicular to each other.

[0024] Please see first Figure 2 , which is a side view of a semiconductor structure 200 of a comparative example. When a silicon carbide substrate 210 without any recess C is used, the angle θ2 between the top surface 211 of the silicon carbide substrate 210 and the direction of the BPD's Burkina Fatale vector is 4 degrees, and the direction D of epitaxial growth is perpendicular to the top surface 211 of the silicon carbide substrate 210. In this case, according to the following formula (1) and formula (2), since the elastic energy per unit length of the BPD dislocation line E BPD is approximately equal to the elastic energy per unit length of the TED dislocation line, so the elastic energy per unit growth length of the BPD is W BPD The elastic energy W per unit length of TED will be greater than TED Therefore, most of the BPDs will be converted into TEDs during the epitaxial growth process.

[0025] Formula (1): W BPD=E BPD / cos 86°

[0026] Formula (2): W TED =E TED / cos 4°

[0027] →W BPD >W TED (E BPD ≒E TED )

[0028] Please return Figure 1 Since the top surface 111 of the silicon carbide substrate 110 disclosed in this case has a plurality of concave portions C, wherein the bottom of the concave portion C has an angle θ1 of 88 to 92 degrees, the direction D of epitaxial growth is perpendicular to the first inclined surface S1 of the silicon carbide substrate 110. In this case, according to the following formula (3) and formula (4), the elastic energy W per unit growth length of the BPD is BPD Elastic energy W per unit length of TED TED The difference becomes larger (compared to Figure 2 Therefore, more BPDs can be converted into TEDs during the epitaxial growth process. Equations (3) and (4) are calculated based on an angle θ1 of 90 degrees.

[0029] Formula (3): W BPD =E BPD / cos 90°

[0030] Formula (4): W TED =E TED / cos 0°

[0031] →W BPD >>W TED (E BPD ≒E TED )

[0032] In some embodiments, the first inclined surface S1 and the second inclined surface S2 each extend straight to the top surface 111, and the angle θ3 between the top surface 111 and the first inclined surface S1 is between 174 and 178 degrees. For example, the angle θ3 can be 175, 176, or 177 degrees. With this design, the entire first inclined surface S1 can achieve high BPD conversion efficiency, thereby improving epitaxial quality. In a preferred embodiment, the angle θ3 can be 176 degrees.

[0033] In some embodiments, the average maximum width L of the recess C may be between 5 and 35 microns. For example, the average maximum width L of the recess C may be 10, 15, 20, 25, or 30 microns. Because the average maximum width L of the recess C is small, the recess C does not affect the overall flatness of the top surface 111 of the silicon carbide substrate 110 from the perspective of crystal growth, thereby reducing the probability of large defects (e.g., triangle defects and carrot defects) caused by surface unevenness. Furthermore, although the recess C is small, it still has a certain size. This design facilitates the construction of a suitable angle θ1, thereby improving the BPD conversion efficiency. It should be understood that the "maximum width L of the recess C" herein refers to the "maximum length of the recess C measured along a direction parallel to the top surface 111," and the "average maximum width L of the recess C" is the value obtained by averaging the maximum widths L of 15,000 recesses C.

[0034] The following will be Figure 1 and Figure 3 The manufacturing method of the semiconductor structure 100 disclosed in the present invention is described, wherein Figure 3 FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure 100 according to some embodiments of the present disclosure. The method for manufacturing the semiconductor structure 100 includes steps S10 to S30, and steps S10 to S30 are performed sequentially.

[0035] In step S10, an alkaline etching solution is used to perform an etching process on the top surface 111 of the silicon carbide substrate 110, wherein the alkaline etching solution contains at least one alkaline substance, and the alkaline substance has a hydroxyl group. By performing an etching process with a strong base having a hydroxyl group, a plurality of etching pits (not shown) with a suitable size can be etched out on the top surface 111 of the silicon carbide substrate 110. In detail, the average value of the maximum width of the plurality of etching pits formed by the etching process is 30 microns to 50 microns (for example, 35 microns, 40 microns or 45 microns), wherein the etching pits with smaller sizes can be directly retained and become recesses C, while the etching pits with larger sizes can be smoothed to a certain extent during the subsequent grinding process and thus have a reduced size and become recesses C. On the other hand, by performing an etching process with a strong base having a hydroxyl group, the etching pits can also have the aforementioned suitable angle θ1, thereby making the recess C formed finally have a suitable angle θ1. It should be understood that the "maximum width of the etching pit" in this article refers to the "maximum length of the etching pit measured along the direction parallel to the top surface 111", and the "average length of the long axis of the etching pit" is the value obtained by averaging the maximum widths of 15,000 etching pits.

[0036] In some embodiments, the alkaline substance in the alkaline etching solution may be potassium hydroxide, sodium hydroxide, tetramethylammonium hydroxide, or a combination thereof. In a preferred embodiment, the alkaline substance may be potassium hydroxide to better control the size and angle θ1 of the etching pit formed. In some embodiments, the alkaline etching solution may be an aqueous solution containing an alkaline substance, for example, an aqueous solution containing potassium hydroxide. In some embodiments, the weight of the alkaline substance may be 80 wt % to 90 wt % based on the total weight of the alkaline etching solution. This concentration range helps to control the size and angle θ1 of the etching pit. In other embodiments, the alkaline etching solution may be molten potassium hydroxide. The use of molten potassium hydroxide has a better etching effect for the silicon carbide substrate 110 with a higher BPD density.

[0037] In some embodiments, the etching process may be performed for 2 to 20 minutes, and the etching process temperature may be 300 to 600 degrees Celsius (e.g., 350, 400, 450, 500, or 550 degrees Celsius). By controlling the etching process time to less than 20 minutes, it is helpful to avoid the formation of oversized etch pits, thereby reducing the time of the subsequent grinding process and the amount of grinding fluid used, thereby improving the efficiency of the overall process. In addition, by controlling the temperature within the range of 300 to 600 degrees Celsius, the alkaline substance in the alkaline etching solution can be made to have appropriate reactivity with the silicon carbide substrate 110, which helps to control the size and angle θ1 of the etch pits.

[0038] After the etching process, in step S20, the top surface 111 of the silicon carbide substrate 100 is polished using a polishing slurry comprising hydrogen peroxide and a plurality of silicon dioxide particles. Specifically, the hydrogen peroxide rapidly heats and oxidizes the top surface 111 of the silicon carbide substrate 100, forming a soft oxide. The silicon dioxide particles then polish away the soft oxide, thereby smoothing out any unintended surface roughness caused by the etching process. This reduces the probability of large defects during subsequent epitaxial deposition caused by uneven top surface 111 of the silicon carbide substrate 100. Overall, the polishing process can reduce the average maximum width of the etched pits to 5 microns to 35 microns (e.g., 10 microns, 15 microns, 20 microns, 25 microns, 30 microns).

[0039] In some embodiments, the average particle size of the silica particles is 70 nanometers (nm) to 80 nanometers (nm) (e.g., 71 nm, 72 nm, 73 nm, 74 nm, 75 nm, 76 nm, 77 nm, 78 nm, 79 nm). The design of the silica particle size helps to improve the dispersibility of the silica particles and prevent the silica particles from agglomerating and forming scratches on the top surface 111 of the silicon carbide substrate 110. In addition, carbon dioxide particles with a suitable size can avoid discarding the special angle θ1 in the etch pit to ensure that the BPD conversion efficiency can be improved. In some embodiments, the weight of the silica particles can be 5 wt% to 25 wt% based on the total weight of the polishing liquid. This concentration range can improve the dispersibility of the silica particles, prevent the silica particles from agglomerating, and allow the silica particles and hydrogen peroxide to be appropriately matched with each other, thereby improving the polishing rate and achieving a higher polishing quality.

[0040] In some embodiments, an etch pit (recess C) of suitable size can be obtained by controlling the grinding depth of the top surface 111 of the silicon carbide substrate 100 to reduce the probability of large defects. In detail, the grinding depth of the grinding liquid on the top surface 111 of the silicon carbide substrate 110 can be 0.1 micron to 0.2 micron. For example, the grinding depth can be 0.11 micron, 0.12 micron, 0.13 micron, 0.14 micron, 0.15 micron, 0.16 micron, 0.17 micron, 0.18 micron, 0.19 micron. If the grinding depth is too large, most of the etch pits may be removed, and the recess C cannot be left on the top surface 111 of the silicon carbide substrate 100; if the grinding depth is too small, the surface roughness of the top surface 111 of the silicon carbide substrate 100 may not be removed, increasing the probability of large defects during subsequent epitaxy.

[0041] In general, after the polishing process, the remaining etch pit on the top surface 111 of the silicon carbide substrate 100 can form the recess C disclosed herein, wherein the bottom of the recess C has a first inclined surface S1 and a second inclined surface S2 connected to each other, and the angle θ1 between the first inclined surface S1 and the second inclined surface S2 is 88 degrees to 92 degrees.

[0042] Subsequently, in step S30, an epitaxial growth process is performed on the top surface 111 of the silicon carbide substrate 110 to form an epitaxial layer 120. Specifically, a growth source (e.g., a carbon source and a silicon source) and a dopant source (e.g., a nitrogen source) may be continuously introduced at an epitaxial temperature to epitaxially grow the epitaxial layer 120 on the silicon carbide substrate 100 having the recess C. In some embodiments, the epitaxial temperature may be between 1550°C and 1650°C, the carbon to silicon molar ratio (C / Si Ratio) in the growth source may be between 0.9 and 1.3, and the dopant source may be supplied at a concentration of 1E15 atoms / cm3 to 5E16 atoms / cm3. The carbon source may include methane, propane, ethylene, acetylene, or a combination thereof; the silicon source may include chlorosilane, dichlorosilane, trichlorosilane, tetrachlorosilane, or a combination thereof; and the nitrogen source may include nitrogen, ammonia, or a combination thereof.

[0043] like Figure 1 As shown, since the epitaxial growth of silicon carbide begins in the recess C, and the direction D of epitaxial growth is perpendicular to the first inclined surface S1 of the silicon carbide substrate 210, a portion of the epitaxial layer 120 is located in the recess C and fills the recess C. In other words, the epitaxial layer 120 and the silicon carbide substrate 110 are closely arranged with no other layers or gaps between them. In other words, the bottom surface 121 of the epitaxial layer 120 conforms to the top surface 111, the first inclined surface S1, and the second inclined surface S2 of the silicon carbide substrate 110 (i.e., the bottom surface 121 of the epitaxial layer 120 undulates along the contours of the top surface 111, the first inclined surface S1, and the second inclined surface S2 of the silicon carbide substrate 110), and the epitaxial layer 120 and the silicon carbide substrate 110 are in close contact with each other.

[0044] On the other hand, by forming a plurality of recesses C with a suitable angle θ1 on the top surface 111 of the silicon carbide substrate 110, the probability of BPDs in the silicon carbide substrate 110 being epitaxially transferred to the epitaxial layer 120 can be reduced, and the conversion efficiency of BPDs to TEDs can be improved. Specifically, in some embodiments, during the epitaxial process, the conversion rate of basal plane dislocations (BPDs) to threading edge dislocations (TEDs) in the epitaxial layer 120 is greater than 99.98%. Furthermore, in some embodiments, after the epitaxial process, the basal plane dislocation (BPD) density of the silicon carbide substrate 110 is 5,000 to 30,000 times that of the epitaxial layer 120.

[0045] Although the present disclosure has been disclosed above in the form of embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

[0046]

Explanation of symbols

[0047] 100,200:Semiconductor structure

[0048] 110,210:Silicon carbide substrate

[0049] 111,211: Top

[0050] 120: epitaxial layer

[0051] 121: Bottom

[0052] S1: First slope

[0053] S2: Second slope

[0054] P: Lowest point

[0055] C: concave part

[0056] R: Local magnified area

[0057] L: Maximum width

[0058] θ1~θ3: Angle

[0059] D: Direction

[0060] BPD:BPD's cloth vector direction

[0061] TED: TED's cloth vector direction

[0062] S10~S30: steps.

Claims

1. A semiconductor structure, characterized in that include: A silicon carbide substrate, wherein a top surface of the silicon carbide substrate has a plurality of recesses, the bottom of each of the plurality of recesses has a first inclined surface and a second inclined surface connected to each other, and the angle between the first inclined surface and the second inclined surface is 88 degrees to 92 degrees; and An epitaxial layer is disposed on the top surface of the silicon carbide substrate. 2 . The semiconductor structure according to claim 1 , wherein an average value of the maximum widths of the plurality of recesses is 5 μm to 35 μm.

3. A method for manufacturing a semiconductor structure, characterized in that: include: Performing an etching process on the top surface of the silicon carbide substrate using an alkaline etching solution, wherein the alkaline etching solution contains at least one alkaline substance, and the alkaline substance has a hydroxyl group; After the etching process, the top surface of the silicon carbide substrate is polished using a polishing liquid, wherein the polishing liquid comprises hydrogen peroxide and a plurality of silicon dioxide particles; as well as An epitaxial process is performed on the top surface of the silicon carbide substrate to form an epitaxial layer. 4 . The method for manufacturing a semiconductor structure according to claim 3 , wherein the alkaline substance is potassium hydroxide, sodium hydroxide, tetramethylammonium hydroxide or a combination thereof. 5 . The method for manufacturing a semiconductor structure according to claim 3 , wherein the weight of the alkaline substance is 80 wt % to 90 wt % based on the total weight of the alkaline etching solution. The method for manufacturing a semiconductor structure according to claim 3 , wherein an average particle size of the plurality of silicon dioxide particles is 70 nm to 80 nm. 7 . The method for manufacturing a semiconductor structure according to claim 3 , wherein the weight of the plurality of silicon dioxide particles is 5 wt % to 25 wt % based on the total weight of the polishing liquid. 8 . The method for manufacturing a semiconductor structure according to claim 3 , wherein a grinding depth of the grinding process performed on the top surface of the silicon carbide substrate is 0.10 μm to 0.20 μm.

9. A method for manufacturing a semiconductor structure, characterized in that: include: Performing an etching process on a top surface of the silicon carbide substrate so that a plurality of etch pits are formed on the top surface, wherein an average value of a maximum width of the plurality of etch pits is 30 micrometers to 50 micrometers; After performing the etching process, performing a grinding process on the top surface of the silicon carbide substrate so that an average value of the maximum width of the plurality of etching pits is reduced to 5 microns to 35 microns; An epitaxial process is performed on the top surface of the silicon carbide substrate to form an epitaxial layer. 10 . The method for manufacturing a semiconductor structure according to claim 9 , wherein during the epitaxial process, a conversion rate of basal plane dislocations to threading edge dislocations in the epitaxial layer is greater than 99.98%.

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