Display substrate, display substrate preparation method and display device

Abstract

The embodiment of the invention provides a display substrate, a display substrate preparation method and a display device. The display substrate comprises a substrate, an anti-reflection layer and a gate metal layer, the anti-reflection layer is arranged on the substrate, and the gate metal layer is arranged on one side, far away from the substrate, of the anti-reflection layer; wherein the anti-reflection layer is an indium tin oxide layer. According to the array substrate, the anti-reflection layer (for reducing the reflectivity) is arranged between the gate metal layer and the substrate, and the anti-reflection layer is made of indium tin oxide (ITO), so that the reflectivity of the gate metal layer to ambient light is reduced when the array substrate faces the display side, and the overall display effect of a display product is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate, a method for preparing a display substrate, and a display device. Background Art

[0002] In the current development of display products, borderless display is one of the important development directions. In order to achieve borderless display, COF (Chip On Flex, or Chip On Film) needs to be hidden behind the display panel. In the related technology, the display panel is inverted, that is, the array substrate faces the display side and the color filter substrate faces the non-display side, and the COF is folded toward the color filter side, and the binding area is used to cover the COF. Figure 18 However, when the array substrate faces the display side, the gate layer (gate metal layer) has a dense metal layout and high reflectivity due to the wiring of the GOA (Gate On Array, gate drive circuit), Clock (clock signal), and Lead area (lead area) around the array substrate. Simultaneously, the reflectivity of the display area is also higher than that of the color filter substrate, affecting the display effect of the display product.

[0003] Therefore, how to reduce the reflectivity of the gate metal layer to ambient light when the array substrate faces the display side becomes an urgent problem to be solved. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a display substrate, a method for manufacturing a display substrate, and a display device to reduce the reflectivity of the gate metal layer to ambient light. The specific technical solution is as follows:

[0005] In a first aspect, an embodiment of the present application provides a display substrate, comprising:

[0006] Substrate, anti-reflection layer and gate metal layer;

[0007] The anti-reflection layer is arranged on the substrate, and the gate metal layer is arranged on a side of the anti-reflection layer away from the substrate; wherein the anti-reflection layer is an indium tin oxide layer.

[0008] In a possible embodiment, the gate metal layer includes: a first metal layer and a second metal layer; the first metal layer is disposed on a side of the anti-reflection layer away from the substrate, and the second metal layer is disposed on a side of the first metal layer away from the substrate;

[0009] The first metal layer is molybdenum metal or titanium metal, and the second metal layer is copper metal or aluminum metal; or the first metal layer is an alloy metal with molybdenum metal / titanium metal as the base material, and the second metal layer is an alloy metal with copper metal / aluminum metal as the base material.

[0010] In one possible implementation,

[0011] The thickness of the anti-reflection layer ranges from 1 nanometer to 100 nanometers, the thickness of the first metal layer ranges from 1 nanometer to 200 nanometers, and the thickness of the second metal layer ranges from 100 nanometers to 1000 nanometers.

[0012] In a possible implementation manner, the first projection of the gate metal layer on the substrate is included in the second projection of the anti-reflection layer on the substrate;

[0013] In which, in the row direction of the first projection and the second projection, the distance between adjacent first projection edges and second projection edges ranges from 0.05 microns to 0.3 microns; in the column direction of the first projection and the second projection, the distance between adjacent first projection edges and second projection edges ranges from 0.05 microns to 0.3 microns.

[0014] In a possible implementation, the display substrate further includes: a first insulating layer, a first active layer, a first electrode layer, a first source-drain electrode layer, a second insulating layer, and a second electrode layer;

[0015] The first insulating layer is arranged on a side of the second metal layer away from the substrate, the first active layer is arranged on a side of the first insulating layer away from the substrate, the first electrode layer is arranged on a side of the first active layer away from the substrate, the first source-drain electrode layer is arranged on a side of the first electrode layer away from the substrate, the second insulating layer is arranged on a side of the first source-drain electrode layer away from the substrate, and the second electrode layer is arranged on a side of the second insulating layer away from the substrate.

[0016] In a possible implementation, the display substrate further includes: a third insulating layer, a second active layer, a second source-drain electrode layer, a first buffer layer, a first organic layer, a third electrode layer, a fourth insulating layer, and a fourth electrode layer;

[0017] The third insulating layer is arranged on a side of the second metal layer away from the substrate, the second active layer is arranged on a side of the third insulating layer away from the substrate, the second source-drain electrode layer is arranged on a side of the second active layer away from the substrate, the first buffer layer is arranged on a side of the second source-drain electrode layer away from the substrate, the first organic layer is arranged on a side of the first buffer layer away from the substrate, the third electrode layer is arranged on a side of the first organic layer away from the substrate, the fourth insulating layer is arranged on a side of the third electrode layer away from the substrate, and the fourth electrode layer is arranged on a side of the fourth insulating layer away from the substrate.

[0018] In a possible implementation, the display substrate further includes: a fifth insulating layer, a third active layer, a third source-drain electrode layer, a second buffer layer, a color filter layer, a second organic layer, and a fifth electrode layer;

[0019] The fifth insulating layer is arranged on a side of the second metal layer away from the substrate, the third active layer is arranged on a side of the fifth insulating layer away from the substrate, the third source-drain electrode layer is arranged on a side of the third active layer away from the substrate, the second buffer layer is arranged on a side of the third source-drain electrode layer away from the substrate, the color filter layer is arranged on a side of the second buffer layer away from the substrate, the second organic layer is arranged on a side of the color filter layer away from the substrate, and the fifth electrode layer is arranged on a side of the second organic layer away from the substrate.

[0020] In a possible implementation, the reflectivity of the gate metal layer to light ranges from 17% to 30%.

[0021] In a second aspect, an embodiment of the present application provides a method for preparing a display substrate, the method comprising:

[0022] Obtaining a substrate of the display substrate;

[0023] An anti-reflection layer and a gate metal layer are prepared on the substrate; wherein the anti-reflection layer is provided on the substrate and is an indium tin oxide layer, and the gate metal layer is provided on a side of the anti-reflection layer away from the substrate;

[0024] Perform subsequent preparation processes for the display substrate.

[0025] In a possible implementation, the step of preparing an anti-reflection layer and a gate metal layer on the substrate includes:

[0026] Depositing an anti-reflection structure on the substrate; wherein the anti-reflection structure comprises an initial anti-reflection layer and an initial gate metal layer, the initial anti-reflection layer being disposed on the substrate, and the initial gate metal layer being disposed on a side of the initial anti-reflection layer away from the substrate;

[0027] coating a photoresist on a side of the anti-reflection structure away from the substrate;

[0028] performing an exposure operation on the photoresist through a prefabricated mask, so that the photoresist is divided into an exposed portion and an unexposed portion;

[0029] Using a developer to remove unexposed portions of the photoresist, so that a photoresist pattern identical to the prefabricated mask pattern is formed on a side of the anti-reflection structure away from the substrate;

[0030] determining a non-overlapping portion of a projection of the anti-reflection structure on the substrate and a projection of the photoresist pattern on the substrate;

[0031] The non-overlapping portion of the anti-reflection structure is removed by etching to obtain an anti-reflection layer and a gate metal layer.

[0032] In a possible implementation, after removing the non-overlapping portion of the anti-reflection structure by etching to obtain the anti-reflection layer and the gate metal layer, the method further includes:

[0033] The photoresist remaining on the side of the gate metal layer away from the substrate is stripped.

[0034] In a possible implementation, removing the non-overlapping portion of the anti-reflection structure by etching to obtain the anti-reflection layer and the gate metal layer includes:

[0035] The non-overlapping portion of the anti-reflection structure is removed by using a first etching solution to obtain an anti-reflection layer and a gate metal layer.

[0036] In a possible implementation, removing the non-overlapping portion of the anti-reflection structure by etching to obtain the anti-reflection layer and the gate metal layer includes:

[0037] Using a second etching solution to remove the non-overlapping portion of the initial gate metal layer of the anti-reflective structure to obtain a gate metal layer;

[0038] The non-overlapping portion of the initial anti-reflection layer of the anti-reflection structure is removed by using a third etching solution to obtain an anti-reflection layer.

[0039] In a possible implementation manner, depositing an anti-reflection structure on the substrate includes:

[0040] Depositing an initial anti-reflection layer on the substrate by magnetron sputtering deposition;

[0041] An initial gate metal layer is deposited on a side of the initial anti-reflection layer away from the substrate by magnetron sputtering deposition.

[0042] In a possible implementation manner, after preparing the anti-reflection layer and the gate metal layer on the substrate, the method further includes:

[0043] forming a first insulating layer on a side of the gate metal layer away from the substrate;

[0044] forming a first active layer on a side of the first insulating layer away from the substrate;

[0045] forming a first electrode layer on a side of the first active layer away from the substrate;

[0046] forming a first source-drain electrode layer on a side of the first electrode layer away from the substrate;

[0047] forming a second insulating layer on a side of the first source-drain electrode layer away from the substrate;

[0048] A second electrode layer is formed on a side of the second insulating layer away from the substrate.

[0049] In a possible implementation manner, after preparing the anti-reflection layer and the gate metal layer on the substrate, the method further includes:

[0050] forming a third insulating layer on a side of the gate metal layer away from the substrate;

[0051] preparing a second active layer on a side of the third insulating layer away from the substrate;

[0052] forming a second source-drain electrode layer on a side of the second active layer away from the substrate;

[0053] forming a first buffer layer on a side of the second source-drain electrode layer away from the substrate;

[0054] forming a first organic layer on a side of the first buffer layer away from the substrate;

[0055] forming a third electrode layer on a side of the first organic layer away from the substrate;

[0056] forming a fourth insulating layer on a side of the third electrode layer away from the substrate;

[0057] A fourth electrode layer is formed on a side of the fourth insulating layer away from the substrate.

[0058] In a possible implementation manner, after preparing the anti-reflection layer and the gate metal layer on the substrate, the method further includes:

[0059] forming a fifth insulating layer on a side of the gate metal layer away from the substrate;

[0060] preparing a third active layer on a side of the fifth insulating layer away from the substrate;

[0061] forming a third source-drain electrode layer on a side of the third active layer away from the substrate;

[0062] forming a second buffer layer on a side of the third source-drain electrode layer away from the substrate;

[0063] forming a color filter layer on a side of the second buffer layer away from the substrate;

[0064] preparing a second organic layer on a side of the color filter layer away from the substrate;

[0065] A fifth electrode layer is formed on a side of the second organic layer away from the substrate.

[0066] In a third aspect, an embodiment of the present application provides a display device, comprising the display substrate described in any one of the first aspects above.

[0067] Beneficial effects of the embodiments of the present application:

[0068] Embodiments of the present application provide a display substrate, a method for manufacturing a display substrate, and a display device. The display substrate includes: a substrate, an anti-reflection layer, and a gate metal layer. The anti-reflection layer is disposed on the substrate, and the gate metal layer is disposed on a side of the anti-reflection layer away from the substrate. The anti-reflection layer is an indium tin oxide layer. By disposing the anti-reflection layer (reducing reflectivity) between the gate metal layer and the substrate, the anti-reflection layer is made of indium tin oxide (ITO). This reduces the reflectivity of the gate metal layer to ambient light when the array substrate faces the display side, thereby improving the overall display quality of the display product.

[0069] Of course, it is not necessary to achieve all the advantages described above at the same time when implementing any product or method of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0071] Figure 1 A schematic diagram of the first structure of a display substrate provided in an embodiment of the present application;

[0072] Figure 2 A schematic diagram of a second structure of a display substrate provided in an embodiment of the present application;

[0073] Figure 3a A schematic diagram of a first structure of a gate metal layer and an anti-reflection layer of a display substrate provided in an embodiment of the present application;

[0074] Figure 3b A schematic diagram of a second structure of a gate metal layer and an anti-reflection layer of a display substrate provided in an embodiment of the present application;

[0075] Figure 4aThis is a SEM (Scanning Electron Microscope) photo of the etching process of the gate metal layer and the anti-reflective layer using the first-step etching solution;

[0076] Figure 4b This is a SEM image of the etching process of the gate metal layer and the anti-reflection layer using the second one-step etching solution;

[0077] Figure 5 A third structural schematic diagram of a display substrate provided in an embodiment of the present application;

[0078] Figure 6 A fourth structural schematic diagram of a display substrate provided in an embodiment of the present application;

[0079] Figure 7 A fifth structural schematic diagram of a display substrate provided in an embodiment of the present application;

[0080] Figure 8 A schematic diagram of a first process of a method for preparing a display substrate provided in an embodiment of the present application;

[0081] Figure 9 A second schematic flow chart of the method for preparing a display substrate provided in an embodiment of the present application;

[0082] Figure 10 A third schematic flow chart of the method for preparing a display substrate provided in an embodiment of the present application;

[0083] Figure 11 A fourth flow chart of the method for preparing a display substrate provided in an embodiment of the present application;

[0084] Figure 12 A fifth flow chart of the method for preparing a display substrate provided in an embodiment of the present application;

[0085] Figure 13 A sixth flow chart of the method for preparing a display substrate provided in an embodiment of the present application;

[0086] Figure 14 A seventh flow chart of the method for preparing a display substrate provided in an embodiment of the present application;

[0087] Figure 15 This is a schematic diagram of an eighth process of the method for preparing a display substrate provided in an embodiment of the present application;

[0088] Figure 16 A ninth flow chart of the method for preparing a display substrate provided in an embodiment of the present application;

[0089] Figure 17 A schematic structural diagram of a display device provided in an embodiment of the present application;

[0090] Figure 18 This is a structural diagram of an inverted display panel in the related art. DETAILED DESCRIPTION

[0091] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field based on this application are within the scope of protection of this application.

[0092] First, a brief introduction to the four-sided borderless display products in the relevant technology is given. In the current development of display products, four-sided borderless is one of the important development directions of display products. In the traditional design, the color film substrate is usually set on the array substrate (the array substrate faces the non-display side, and the color film substrate faces the display side), and the two are combined into a box and finally form the corresponding display panel structure. However, if you want to achieve the four-sided borderless display product to the greatest extent, you need to break the box structure in the traditional design, and instead set the larger array substrate on the color film substrate (the array substrate faces the display side, and the color film substrate faces the non-display side), thereby realizing a four-sided borderless full screen, as described below:

[0093] In order to achieve a borderless display product on all four sides, the COF (Chip On Flex, or Chip On Film) needs to be hidden behind the display panel. In related technologies, the display panel is inverted, that is, the array substrate faces the display side and the color filter substrate faces the non-display side, and the COF is folded toward the color filter side, and the COF is shielded by the binding area, such as Figure 18 shown.

[0094] However, when the array substrate faces the display side, the densely packed gate layer (gate metal layer) has a high reflectivity (up to approximately 40%) due to the wiring of the GOA (Gate On Array), clock signal, and lead areas surrounding the array substrate. Furthermore, the reflectivity of the display area is higher than that of the color filter substrate, affecting the display quality of the product. Therefore, reducing the reflectivity of the gate metal layer to ambient light when the array substrate faces the display side has become an urgent issue.

[0095] In order to reduce the reflectivity of the gate metal layer to ambient light when the array substrate faces the display side, related technologies propose to reduce the reflectivity of the gate metal layer to ambient light by providing a silicon nitride anti-reflection layer under the gate metal layer. However, the silicon nitride anti-reflection layer is deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition), while the gate metal layer is deposited by magnetron sputtering. The silicon nitride anti-reflection layer and the gate metal layer cannot be deposited in one step using the same process equipment. Therefore, the use of a silicon nitride anti-reflection layer will add additional deposition process steps compared to the original process, affecting production efficiency.

[0096] The following is a brief introduction to PECVD deposition and magnetron sputtering deposition:

[0097] PECVD technology is a method for preparing semiconductor thin films and other thin films by chemically depositing them on a substrate after ionization via glow discharge in a deposition chamber. Plasma activation enhances the activity of chemical vapor phase reactants, increases surface reaction rates, and significantly reduces film deposition temperatures through high-energy ions. Under the action of the plasma, the gas is dissociated in the chamber, forming a highly reactive species containing gas molecules, high-energy ions, electrons, and active free radicals. The deposition surface undergoes not only conventional thermochemical reactions but also complex plasma chemical reactions. The deposited film grows under the combined action of these two chemical reactions.

[0098] Magnetron sputtering is a type of physical vapor deposition (PVD). Magnetron sputtering involves the collision of incident particles with a target. Within the target, the particles undergo a complex scattering process, colliding with target atoms and transferring some of their momentum to them. These target atoms then collide with other target atoms, forming a cascade process. During this cascade, some target atoms near the surface gain sufficient momentum to move outward, leaving the target and being sputtered. Magnetron sputtering introduces a magnetic field on the target cathode surface, using the magnetic field to confine charged particles, thereby increasing the plasma density and the sputtering rate.

[0099] In order to solve at least one of the above problems, embodiments of the present application provide a display substrate, a method for preparing a display substrate, and a display device.

[0100] Next, a display substrate 1 provided in an embodiment of the present application is described in detail. Figure 1 , the display substrate 1 includes:

[0101] Substrate 11, anti-reflection layer 12 and gate metal layer 13;

[0102] The anti-reflection layer 12 is disposed on the substrate 11 , and the gate metal layer 13 is disposed on a side of the anti-reflection layer 12 away from the substrate 11 ; wherein the anti-reflection layer 12 is an indium tin oxide layer.

[0103] The gate metal layer is deposited by magnetron sputtering deposition, and the indium tin oxide (ITO) anti-reflection layer is also deposited by magnetron sputtering deposition. The indium tin oxide anti-reflection layer and the gate metal layer can be deposited in one step using the same process equipment. Specifically, by adding sputtering chamber units, magnetron sputtering target units corresponding to the thin film to be deposited can be added to achieve one-step deposition of different types of thin films. Therefore, by using indium tin oxide as the material for the anti-reflection layer, the anti-reflection layer and the gate metal layer can be deposited in one step. Compared with the related art that uses silicon nitride as the material for the anti-reflection layer, no additional deposition process steps are added, and the impact on production efficiency is relatively small.

[0104] In the embodiments of the present application, an anti-reflection layer 12 (reducing reflectivity) is provided between the gate metal layer 13 and the substrate 11. Anti-reflection layer 12 is made of indium tin oxide. This reduces the reflectivity of the gate metal layer 13 to ambient light when the array substrate faces the display side, thereby improving the overall display quality of the display product. Compared to the related art using silicon nitride as the anti-reflection layer, no additional deposition process steps are added, resulting in a minimal impact on production efficiency.

[0105] In one possible implementation, see Figure 2 The gate metal layer 13 includes: a first metal layer 131 and a second metal layer 132; the first metal layer 131 is arranged on a side of the anti-reflection layer 12 away from the substrate 11, and the second metal layer 132 is arranged on a side of the first metal layer 131 away from the substrate 11;

[0106] In which, the first metal layer 131 is molybdenum metal (Mo) or titanium metal (Ti), and the second metal layer 132 is copper metal (Cu) or aluminum metal (Al); or, the first metal layer 131 is an alloy metal with molybdenum metal / titanium metal as the base material, and the second metal layer 132 is an alloy metal with copper metal / aluminum metal as the base material.

[0107] The structure and material description of the gate metal layer can be found in the prior art and will not be elaborated in this application.

[0108] In one possible implementation,

[0109] The thickness of the anti-reflection layer 12 ranges from 1 nm to 100 nm, the thickness of the first metal layer 131 ranges from 1 nm to 200 nm, and the thickness of the second metal layer 132 ranges from 100 nm to 1000 nm.

[0110] In one example, the thickness of the anti-reflection layer 12 can be 20 nm. In one example, the thickness of the first metal layer 131 can be 30 nm. In one example, the thickness of the second metal layer 132 can be 200 nm.

[0111] In one possible implementation, see Figure 3a , a first projection of the gate metal layer 13 on the substrate 11 is included in a second projection of the anti-reflection layer 12 on the substrate 11;

[0112] In which, in the row direction of the first projection and the second projection, the distance d between adjacent first projection edges and second projection edges ranges from 0.05 micrometers (μm) to 0.3 micrometers; in the column direction of the first projection and the second projection, the distance d between adjacent first projection edges and second projection edges ranges from 0.05 micrometers to 0.3 micrometers.

[0113] The size of the anti-reflection layer 12 is larger than that of the gate metal layer 13, and the first projection of the gate metal layer 13 on the substrate 11 is included in the second projection of the anti-reflection layer 12 on the substrate 11, corresponding to Figure 3a The cross-sectional structure diagram of the gate metal layer 13 disposed on the anti-reflection layer 12 is shown in FIG. Figure 3b This design can avoid the problem of corrosion caused by residual etching solution in the retracted gap when the edges of the anti-reflection layer are retracted from the edges of the gate metal layer.

[0114] In an example, in the row direction of the first projection and the second projection, the distance d between adjacent first projection edges and second projection edges can be 0.15 microns, and in the column direction of the first projection and the second projection, the distance d between adjacent first projection edges and second projection edges can be 0.15 microns.

[0115] It should be noted that the aforementioned distance d is for the distance between the gate metal layer 13 and the anti-reflection layer 12 using a one-step etching process. Distance d can be adjusted by adjusting the composition and ratio of the one-step etching solution, and can even be adjusted to a reduced state (as mentioned above, reduction is detrimental to yield).

[0116] Figure 4aThis is a physical SEM (Scanning Electron Microscope) image of the etching process of the gate metal layer and the anti-reflective layer using the first-step etching solution in the related technology. The distance d using the first-step etching solution ranges from 1.0 microns to 1.5 microns. However, if the distance d is too large, the overlapping capacitance between the gate metal layer and the SD (source-drain electrode), Com (common electrode), Pixel (pixel electrode), etc. will increase. Therefore, when the distance d is in the range of 1.0 microns to 1.5 microns, the charging rate of the display product will be reduced by about 1-2%.

[0117] Figure 4b In this application, the SEM physical image of the etching process of the gate metal layer and the anti-reflection layer using the second one-step etching solution is shown. The distance d using the second one-step etching solution ranges from 0.05 microns to 0.3 microns. Compared with the use of the first one-step etching solution, the distance d is reduced, thereby improving the charging rate of the display product.

[0118] The related process flow of etching the gate metal layer 13 and the anti-reflection layer 12 in a one-step process will be described in detail later.

[0119] The range of the distance d corresponding to the step-by-step etching process between the gate metal layer 13 and the anti-reflection layer 12 can be found in the prior art and will not be further described in this application. Compared to a one-step etching process, a step-by-step etching process adds an additional etching step. Therefore, the etching process of the gate metal layer 13 and the anti-reflection layer 12 can be performed using a second one-step etching solution, without adding an additional etching step, which has a minimal impact on production efficiency.

[0120] In an embodiment of the present application, the etching process of the gate metal layer 13 and the anti-reflection layer 12 is carried out by using the second one-step etching solution. Compared with the step-by-step etching process, no additional etching process steps are added, and the impact on production efficiency is small. Compared with the use of the first one-step etching solution, the distance d is reduced, thereby improving the charging rate of the display product.

[0121] In one possible implementation, see Figure 5 Taking the display substrate of HADS (High Aperture Advanced Super Dimensional Switching) display mode as an example, based on Figure 2 The display substrate 1 may further include: a first insulating layer 14, a first active layer 15, a first electrode layer 16, a first source-drain electrode layer 17, a second insulating layer 18 and a second electrode layer 19;

[0122] The first insulating layer 14 is arranged on the side of the second metal layer 132 away from the substrate 11, the first active layer 15 is arranged on the side of the first insulating layer 14 away from the substrate 11, the first electrode layer 16 is arranged on the side of the first active layer 15 away from the substrate 11, the first source-drain electrode layer 17 is arranged on the side of the first electrode layer 16 away from the substrate 11, the second insulating layer 18 is arranged on the side of the first source-drain electrode layer 17 away from the substrate 11, and the second electrode layer 19 is arranged on the side of the second insulating layer 18 away from the substrate 11.

[0123] In one possible implementation, see Figure 6 Taking the display substrate of HADS display mode with organic film layer as an example, based on Figure 2 The display substrate 1 may further include: a third insulating layer 21, a second active layer 22, a second source-drain electrode layer 23, a first buffer layer 24, a first organic layer 25, a third electrode layer 26, a fourth insulating layer 27 and a fourth electrode layer 28;

[0124] The third insulating layer 21 is arranged on the side of the second metal layer 132 away from the substrate 11, the second active layer 22 is arranged on the side of the third insulating layer 21 away from the substrate 11, the second source-drain electrode layer 23 is arranged on the side of the second active layer 22 away from the substrate 11, the first buffer layer 24 is arranged on the side of the second source-drain electrode layer 23 away from the substrate 11, the first organic layer 25 is arranged on the side of the first buffer layer 24 away from the substrate 11, the third electrode layer 26 is arranged on the side of the first organic layer 25 away from the substrate 11, the fourth insulating layer 27 is arranged on the side of the third electrode layer 26 away from the substrate 11, and the fourth electrode layer 28 is arranged on the side of the fourth insulating layer 27 away from the substrate 11.

[0125] In one possible implementation, see Figure 7 Taking the display substrate of VA (Vertical Alignment) or IPS (In-Plane Switching) display mode as an example, based on Figure 2 The display substrate 1 may further include: a fifth insulating layer 31, a third active layer 32, a third source-drain electrode layer 33, a second buffer layer 34, a color filter layer 35, a second organic layer 36, and a fifth electrode layer 37;

[0126] The fifth insulating layer 31 is arranged on the side of the second metal layer 132 away from the substrate 11, the third active layer 32 is arranged on the side of the fifth insulating layer 31 away from the substrate 11, the third source-drain electrode layer 33 is arranged on the side of the third active layer 32 away from the substrate 11, the second buffer layer 34 is arranged on the side of the third source-drain electrode layer 33 away from the substrate 11, the color filter layer 35 is arranged on the side of the second buffer layer 34 away from the substrate 11, the second organic layer 36 is arranged on the side of the color filter layer 35 away from the substrate 11, and the fifth electrode layer 37 is arranged on the side of the second organic layer 36 away from the substrate 11.

[0127] In a possible implementation, the reflectivity of the gate metal layer 13 to light ranges from 17% to 30%.

[0128] In one example, by providing the anti-reflection layer 12 made of indium tin oxide, the reflectivity of the gate metal layer 13 to light can be reduced to 22%.

[0129] In the embodiment of the present application, compared to when the array substrate faces the display side and no measures are taken to reduce the reflectivity, the reflectivity of the gate metal layer to light (about 40%) is greatly reduced by providing an anti-reflection layer 12 made of indium tin oxide. The reflectivity range can be reduced to 17% to 30%.

[0130] The present application also provides a method for preparing a display substrate. Figure 8 , including the following steps:

[0131] Step S801 , obtaining the substrate 11 of the display substrate.

[0132] In step S802 , an anti-reflection layer 12 and a gate metal layer 13 are prepared on the substrate 11 . The anti-reflection layer 12 is provided on the substrate 11 and is an indium tin oxide layer. The gate metal layer 13 is provided on a side of the anti-reflection layer 12 away from the substrate 11 .

[0133] The anti-reflection layer 12 is made of indium tin oxide, and the detailed analysis is the same as above, which will not be repeated here.

[0134] Step S803 , performing subsequent preparation processes of the display substrate 1 .

[0135] In the embodiments of the present application, an anti-reflection layer 12, made of indium tin oxide, is provided between the gate metal layer 13 and the substrate 11. This layer reduces the reflectivity of the gate metal layer 13 to ambient light when the array substrate faces the display side, thereby improving the overall display quality of the display product. Compared to the related art using silicon nitride as the anti-reflection layer, no additional deposition process steps are required, resulting in a minimal impact on production efficiency.

[0136] In one possible implementation, see Figure 9 , which is a second flow chart of the method for preparing a display substrate provided in an embodiment of the present application, based on Figure 8 Step S802 in the embodiment is refined and includes the following steps:

[0137] In step S901, an anti-reflection structure is deposited on the substrate 11; wherein the anti-reflection structure includes an initial anti-reflection layer and an initial gate metal layer, the initial anti-reflection layer is arranged on the substrate, and the initial gate metal layer is arranged on a side of the initial anti-reflection layer away from the substrate.

[0138] It is understandable that the definition of the initial anti-reflection layer and the initial gate metal layer is to distinguish them from the anti-reflection layer 12 and the gate metal layer 13 prepared after the etching process.

[0139] The initial anti-reflection layer and the initial gate metal layer can be deposited in one step or in multiple steps.

[0140] In step S902 , photoresist is coated on a side of the anti-reflection structure away from the substrate 11 .

[0141] Photoresist (PR) is a photosensitive material that can undergo chemical changes under the irradiation of light to form the desired pattern.

[0142] Step S903 , performing an exposure operation on the photoresist through a prefabricated mask, so that the photoresist is divided into an exposed portion and an unexposed portion.

[0143] Mask, also known as mask, is an indispensable component of the photolithography process. The mask carries the design pattern, and light passes through it, projecting the design pattern onto the photoresist.

[0144] During the exposure process, the photosensitive molecules in the photoresist change due to the irradiation of light or electron beam.

[0145] Step S904 : removing the unexposed portion of the photoresist with a developer, so that a photoresist pattern identical to the prefabricated mask pattern is formed on the side of the anti-reflection structure away from the substrate.

[0146] After exposure, a developer is used to remove the unchanged portion of the photoresist. After development, a photoresist pattern that matches the mask pattern is formed on the anti-reflective structure.

[0147] Step S905 : determining a non-overlapping portion between a projection of the anti-reflection structure on the substrate and a projection of the photoresist pattern on the substrate.

[0148] Step S906 , removing the non-overlapping portion of the anti-reflection structure by etching to obtain the anti-reflection layer 12 and the gate metal layer 13 .

[0149] The portion of the anti-reflection structure not covered by the photoresist is removed by an etching process, thereby forming an anti-reflection layer 12 and a gate metal layer 13 that conform to the mask pattern.

[0150] The metal and tin oxide are usually etched by wet etching. The anti-reflection layer 12 and the gate metal layer 13 can be obtained by a one-step etching process or a step-by-step etching process.

[0151] In the embodiment of the present application, the anti-reflection layer 12 and the gate metal layer 13 are prepared through relevant process flows.

[0152] In one possible implementation, see Figure 10 , is a third flow chart of the method for preparing a display substrate provided in an embodiment of the present application, based on Figure 9 , further comprising the following steps:

[0153] Step S1001 : stripping the photoresist remaining on the side of the gate metal layer 13 away from the substrate 11 .

[0154] After obtaining the anti-reflection layer 12 and the gate metal layer 13, the remaining photoresist is stripped. The remaining photoresist can be stripped using a relevant solvent or by laser stripping. This application does not make any specific restrictions on this.

[0155] In the embodiment of the present application, the anti-reflection layer 12 and the gate metal layer 13 are exposed by stripping off the photoresist remaining on the side of the gate metal layer 13 away from the substrate 11 .

[0156] In one possible implementation, see Figure 11 , which is a fourth flow chart of the method for preparing a display substrate provided in an embodiment of the present application, based on Figure 9 Step S906 is refined to include the following steps:

[0157] In step S1101 , a first etching solution is used to remove non-overlapping portions of the anti-reflection structure to obtain an anti-reflection layer 12 and a gate metal layer 13 .

[0158] The first etching solution is a one-step etching solution for metal and indium tin oxide.

[0159] In the embodiment of the present application, the initial anti-reflection layer and the initial gate metal layer can be etched with a first etching solution to obtain the anti-reflection layer 12 and the gate metal layer 13 in one step.

[0160] In one possible implementation, see Figure 12 , which is a fifth flow chart of the method for preparing a display substrate provided in an embodiment of the present application, based on Figure 9 Step S906 is refined to include the following steps:

[0161] Step S1201 : using a second etching solution to remove the non-overlapping portion of the initial gate metal layer of the anti-reflective structure to obtain a gate metal layer 13 .

[0162] The second etching solution is a metal etching solution.

[0163] Step S1202 : using a third etching solution to remove the non-overlapping portion of the initial anti-reflection layer of the anti-reflection structure to obtain an anti-reflection layer 12 .

[0164] The third etching solution is indium tin oxide etching solution.

[0165] In an embodiment of the present application, the second etching solution can be used to etch the initial gate metal layer to obtain the gate metal layer 13, and then the third etching solution can be used to etch the initial anti-reflection layer to obtain the anti-reflection layer 12, and the anti-reflection layer 12 and the gate metal layer 13 can be obtained by etching in steps.

[0166] Compared with the step-by-step etching process, the one-step etching process does not add any additional etching process steps and has less impact on production efficiency.

[0167] In one possible implementation, see Figure 13 , which is a sixth flow chart of the method for preparing a display substrate provided in an embodiment of the present application, based on Figure 9 Step S901 is refined to include the following steps:

[0168] Step S1301 : depositing an initial anti-reflection layer on the substrate 11 by magnetron sputtering deposition.

[0169] In step S1302 , an initial gate metal layer is deposited on a side of the initial anti-reflection layer away from the substrate 11 by magnetron sputtering deposition.

[0170] The specific analysis is the same as above and will not be repeated here.

[0171] In an embodiment of the present application, the initial anti-reflection layer and the initial gate metal layer can be deposited in one step by magnetron sputtering deposition. Compared with the related art of using silicon nitride as the material for the anti-reflection layer, no additional deposition process steps are added, and the impact on production efficiency is relatively small.

[0172] In the present application, the anti-reflection layer 12 and the gate metal layer 13 can be prepared by using a one-step deposition process and a one-step etching process simultaneously. No additional process steps are added to the entire process flow, and the impact on production efficiency is relatively small.

[0173] The mask process in the embodiment of the present application adopts Full Tone Mask (full tone mask), that is, the display substrate provided in the embodiment of the present application is based on the Full Tone Mask process (applicable to the Full Tone Mask process).

[0174] In one possible implementation, see Figure 14 , which is a seventh flow chart of the method for preparing a display substrate provided in an embodiment of the present application, taking a display substrate of a HADS display mode as an example, based on Figure 8 After step S802, the following steps are also included:

[0175] In step S1401 , a first insulating layer 14 is formed on a side of the gate metal layer 13 away from the substrate 11 .

[0176] Step S1402 : forming a first active layer 15 on a side of the first insulating layer 14 away from the substrate 11 .

[0177] Step S1403 : forming a first electrode layer 16 on a side of the first active layer 15 away from the substrate 11 .

[0178] Step S1404 : forming a first source-drain electrode layer 17 on a side of the first electrode layer 16 away from the substrate 11 .

[0179] Step S1405 : forming a second insulating layer 18 on a side of the first source / drain electrode layer 17 away from the substrate 11 .

[0180] Step S1406 , forming a second electrode layer 19 on a side of the second insulating layer 18 away from the substrate 11 .

[0181] In one possible implementation, see Figure 15 , which is a schematic diagram of the eighth process of the method for preparing a display substrate provided in an embodiment of the present application, taking a display substrate of a HADS display mode with an organic film layer as an example, based on Figure 8 After step S802, the following steps are also included:

[0182] In step S1501 , a third insulating layer 21 is formed on a side of the gate metal layer 13 away from the substrate 11 .

[0183] Step S1502 : forming a second active layer 22 on a side of the third insulating layer 21 away from the substrate 11 .

[0184] Step S1503 : forming a second source-drain electrode layer 23 on a side of the second active layer 22 away from the substrate 11 .

[0185] Step S1504 : forming a first buffer layer 24 on a side of the second source-drain electrode layer 23 away from the substrate 11 .

[0186] Step S1505 : forming a first organic layer 25 on a side of the first buffer layer 24 away from the substrate 11 .

[0187] Step S1506 : forming a third electrode layer 26 on a side of the first organic layer 25 away from the substrate 11 .

[0188] Step S1507 : forming a fourth insulating layer 27 on a side of the third electrode layer 26 away from the substrate 11 .

[0189] Step S1508 : forming a fourth electrode layer 28 on a side of the fourth insulating layer 27 away from the substrate 11 .

[0190] In one possible implementation, see Figure 16 , which is a ninth flow chart of the method for preparing a display substrate provided in an embodiment of the present application, taking a display substrate of a VA or IPS display mode as an example, based on Figure 8 After step S802, the following steps are also included:

[0191] Step S1601 : forming a fifth insulating layer 31 on a side of the gate metal layer 13 away from the substrate 11 .

[0192] Step S1602 : forming a third active layer 32 on a side of the fifth insulating layer 31 away from the substrate 11 .

[0193] In step S1603 , a third source-drain electrode layer 33 is formed on a side of the third active layer 32 away from the substrate 11 .

[0194] In step S1604 , a second buffer layer 34 is formed on a side of the third source / drain electrode layer 33 away from the substrate 11 .

[0195] Step S1605 : forming a color filter layer 35 on a side of the second buffer layer 34 away from the substrate 11 .

[0196] Step S1606 : forming a second organic layer 36 on a side of the color filter layer 35 away from the substrate 11 .

[0197] Step S1607 : forming a fifth electrode layer 37 on a side of the second organic layer 36 away from the substrate 11 .

[0198] It can be understood that, in addition to the display substrates corresponding to the above three display modes, the anti-reflection layer 12 provided in the present application can also be applied to display substrates corresponding to other display modes.

[0199] The present application also provides a display device 4, see Figure 17 , the display device 4 includes the display substrate 1 described in any one of the above embodiments.

[0200] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0201] Each embodiment in this specification is described in a related manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiment is generally similar to the method embodiment, so the description is relatively simple. For related parts, refer to the description of the method embodiment.

[0202] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application are included in the scope of protection of the present application.

Claims

1. A display substrate, characterized in that: The display substrate comprises: Substrate, anti-reflection layer and gate metal layer; The anti-reflection layer is arranged on the substrate, and the gate metal layer is arranged on a side of the anti-reflection layer away from the substrate; wherein the anti-reflection layer is an indium tin oxide layer.

2. The display substrate according to claim 1, wherein: The gate metal layer includes: a first metal layer and a second metal layer; the first metal layer is arranged on a side of the anti-reflection layer away from the substrate, and the second metal layer is arranged on a side of the first metal layer away from the substrate; The first metal layer is molybdenum metal or titanium metal, and the second metal layer is copper metal or aluminum metal; or the first metal layer is an alloy metal with molybdenum metal / titanium metal as the base material, and the second metal layer is an alloy metal with copper metal / aluminum metal as the base material.

3. The display substrate according to claim 2, wherein: The thickness of the anti-reflection layer ranges from 1 nanometer to 100 nanometers, the thickness of the first metal layer ranges from 1 nanometer to 200 nanometers, and the thickness of the second metal layer ranges from 100 nanometers to 1000 nanometers.

4. The display substrate according to claim 1, wherein: A first projection of the gate metal layer on the substrate is included in a second projection of the anti-reflection layer on the substrate; In which, in the row direction of the first projection and the second projection, the distance between adjacent first projection edges and second projection edges ranges from 0.05 microns to 0.3 microns; in the column direction of the first projection and the second projection, the distance between adjacent first projection edges and second projection edges ranges from 0.05 microns to 0.3 microns.

5. The display substrate according to claim 2, wherein: The display substrate further comprises: a first insulating layer, a first active layer, a first electrode layer, a first source-drain electrode layer, a second insulating layer and a second electrode layer; The first insulating layer is arranged on a side of the second metal layer away from the substrate, the first active layer is arranged on a side of the first insulating layer away from the substrate, the first electrode layer is arranged on a side of the first active layer away from the substrate, the first source-drain electrode layer is arranged on a side of the first electrode layer away from the substrate, the second insulating layer is arranged on a side of the first source-drain electrode layer away from the substrate, and the second electrode layer is arranged on a side of the second insulating layer away from the substrate.

6. The display substrate according to claim 2, wherein: The display substrate further includes: a third insulating layer, a second active layer, a second source-drain electrode layer, a first buffer layer, a first organic layer, a third electrode layer, a fourth insulating layer and a fourth electrode layer; The third insulating layer is arranged on a side of the second metal layer away from the substrate, the second active layer is arranged on a side of the third insulating layer away from the substrate, the second source-drain electrode layer is arranged on a side of the second active layer away from the substrate, the first buffer layer is arranged on a side of the second source-drain electrode layer away from the substrate, the first organic layer is arranged on a side of the first buffer layer away from the substrate, the third electrode layer is arranged on a side of the first organic layer away from the substrate, the fourth insulating layer is arranged on a side of the third electrode layer away from the substrate, and the fourth electrode layer is arranged on a side of the fourth insulating layer away from the substrate.

7. The display substrate according to claim 2, wherein: The display substrate further includes: a fifth insulating layer, a third active layer, a third source-drain electrode layer, a second buffer layer, a color filter layer, a second organic layer, and a fifth electrode layer; The fifth insulating layer is arranged on a side of the second metal layer away from the substrate, the third active layer is arranged on a side of the fifth insulating layer away from the substrate, the third source-drain electrode layer is arranged on a side of the third active layer away from the substrate, the second buffer layer is arranged on a side of the third source-drain electrode layer away from the substrate, the color filter layer is arranged on a side of the second buffer layer away from the substrate, the second organic layer is arranged on a side of the color filter layer away from the substrate, and the fifth electrode layer is arranged on a side of the second organic layer away from the substrate.

8. The display substrate according to claim 1, wherein: The reflectivity of the gate metal layer to light ranges from 17% to 30%.

9. A method for preparing a display substrate, characterized in that: The method comprises: Obtaining a substrate of the display substrate; An anti-reflection layer and a gate metal layer are prepared on the substrate; wherein the anti-reflection layer is provided on the substrate and is an indium tin oxide layer, and the gate metal layer is provided on a side of the anti-reflection layer away from the substrate; Perform subsequent preparation processes for the display substrate.

10. The method according to claim 9, characterized in that The step of preparing an anti-reflection layer and a gate metal layer on the substrate comprises: Depositing an anti-reflection structure on the substrate; wherein the anti-reflection structure comprises an initial anti-reflection layer and an initial gate metal layer, the initial anti-reflection layer being disposed on the substrate, and the initial gate metal layer being disposed on a side of the initial anti-reflection layer away from the substrate; coating a photoresist on a side of the anti-reflection structure away from the substrate; performing an exposure operation on the photoresist through a prefabricated mask, so that the photoresist is divided into an exposed portion and an unexposed portion; Using a developer to remove unexposed portions of the photoresist, so that a photoresist pattern identical to the prefabricated mask pattern is formed on a side of the anti-reflection structure away from the substrate; determining a non-overlapping portion of a projection of the anti-reflection structure on the substrate and a projection of the photoresist pattern on the substrate; The non-overlapping portion of the anti-reflection structure is removed by etching to obtain an anti-reflection layer and a gate metal layer.

11. The method according to claim 10, characterized in that After removing the non-overlapping portion of the anti-reflection structure by etching to obtain the anti-reflection layer and the gate metal layer, the method further includes: The photoresist remaining on the side of the gate metal layer away from the substrate is stripped.

12. The method according to claim 10, characterized in that The non-overlapping portion of the anti-reflection structure is removed by etching to obtain an anti-reflection layer and a gate metal layer, comprising: The non-overlapping portion of the anti-reflection structure is removed by using a first etching solution to obtain an anti-reflection layer and a gate metal layer.

13. The method according to claim 10, characterized in that The non-overlapping portion of the anti-reflection structure is removed by etching to obtain an anti-reflection layer and a gate metal layer, comprising: Using a second etching solution to remove the non-overlapping portion of the initial gate metal layer of the anti-reflective structure to obtain a gate metal layer; The non-overlapping portion of the initial anti-reflection layer of the anti-reflection structure is removed by using a third etching solution to obtain an anti-reflection layer.

14. The method according to claim 10, characterized in that Depositing an anti-reflection structure on the substrate comprises: Depositing an initial anti-reflection layer on the substrate by magnetron sputtering deposition; An initial gate metal layer is deposited on a side of the initial anti-reflection layer away from the substrate by magnetron sputtering deposition.

15. The method according to claim 9, characterized in that After the anti-reflection layer and the gate metal layer are prepared on the substrate, the method further comprises: forming a first insulating layer on a side of the gate metal layer away from the substrate; forming a first active layer on a side of the first insulating layer away from the substrate; forming a first electrode layer on a side of the first active layer away from the substrate; forming a first source-drain electrode layer on a side of the first electrode layer away from the substrate; forming a second insulating layer on a side of the first source-drain electrode layer away from the substrate; A second electrode layer is formed on a side of the second insulating layer away from the substrate.

16. The method according to claim 9, characterized in that After the anti-reflection layer and the gate metal layer are prepared on the substrate, the method further comprises: forming a third insulating layer on a side of the gate metal layer away from the substrate; preparing a second active layer on a side of the third insulating layer away from the substrate; forming a second source-drain electrode layer on a side of the second active layer away from the substrate; forming a first buffer layer on a side of the second source-drain electrode layer away from the substrate; forming a first organic layer on a side of the first buffer layer away from the substrate; forming a third electrode layer on a side of the first organic layer away from the substrate; forming a fourth insulating layer on a side of the third electrode layer away from the substrate; A fourth electrode layer is formed on a side of the fourth insulating layer away from the substrate.

17. The method according to claim 9, characterized in that After the anti-reflection layer and the gate metal layer are prepared on the substrate, the method further comprises: forming a fifth insulating layer on a side of the gate metal layer away from the substrate; preparing a third active layer on a side of the fifth insulating layer away from the substrate; forming a third source-drain electrode layer on a side of the third active layer away from the substrate; forming a second buffer layer on a side of the third source-drain electrode layer away from the substrate; forming a color filter layer on a side of the second buffer layer away from the substrate; preparing a second organic layer on a side of the color filter layer away from the substrate; A fifth electrode layer is formed on a side of the second organic layer away from the substrate.

18. A display device, characterized in that: The display device comprises the display substrate according to any one of claims 1 to 8.

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