Solder mask fault optical fiber sensor

Abstract

Aspects of the present disclosure configure a processor to detect faults in a printed circuit board (PCB) solder resist using an optical waveguide. The processor directs a light beam to an input of one or more optical waveguides embedded in a protective coating of a PCB adjacent to one or more traces of the PCB. The processor measures a beam characteristic of the light beam output by the one or more optical waveguides. The processor detects an interruption of the light beam output by the one or more optical waveguides based on the light beam characteristics. The processor detects a fault in the protective coating of the PCB based on detecting the interruption of the light beam output by the one or more optical waveguides.

Description

[0001] Priority application

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 446,204, filed February 16, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to detecting physical faults, such as cracks, in a printed circuit board (PCB) implementing the memory subsystem. Background Art

[0004] A memory subsystem can be a storage system, such as a solid-state drive (SSD), and can include one or more memory components that store data. For example, the memory components can be non-volatile memory components and volatile memory components. Generally speaking, a host system can use the memory subsystem to store data on and retrieve data from the memory components. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments of the present disclosure.

[0006] Figure 1 is a block diagram illustrating an example computing environment including a memory subsystem according to some embodiments of the present disclosure.

[0007] Figure 2 is a diagram of an example physical assembly of a memory subsystem with an optical waveguide, according to some embodiments of the present disclosure.

[0008] Figure 3A is a block diagram of an example physical assembly of a system for detecting physical faults in a PCB using an optical waveguide, according to some embodiments of the present disclosure.

[0009] Figure 3B is a block diagram of an example physical assembly of a system for detecting physical faults in a PCB using an optical waveguide, according to some embodiments of the present disclosure.

[0010] Figure 4A is a flow chart of an example method for detecting physical faults in a PCB using an optical waveguide, according to some embodiments of the present disclosure.

[0011] Figure 4B is a flow chart of an example method of manufacturing a PCB having an optical waveguide according to some embodiments of the present disclosure.

[0012] Figure 5is a block diagram illustrating a pictorial representation of a machine in the form of a computer system within which a set of instructions may be executed, causing the machine to perform any one or more of the methodologies discussed herein, according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] Aspects of the present disclosure configure system components, such as a processor, to detect physical faults in a PCB using an optical waveguide or multiple optical waveguides. The PCB may include multiple layers, including a layer with traces (e.g., conductive metal interconnects), a layer with a protective coating embedded with the optical waveguides, and a layer with various physical components (e.g., memory subsystem components and / or processing device components). A laser may generate a light beam that propagates through the optical waveguide. The processor may measure or detect interruptions in the light beam, for example, based on differences in beam characteristics (e.g., frequency, attenuation, and / or intensity) between light entering the optical waveguide and light exiting the optical waveguide. In response to and based on these differences in beam characteristics, the processor may identify the presence and / or physical location of physical faults (e.g., cracks) in the protective coating and / or traces. These physical faults can then be corrected during manufacturing and / or operation, for example, to prevent damage to PCB components or data transmission failures between connected components on the PCB. This improves the overall efficiency of operating and implementing the memory subsystem.

[0014] The memory subsystem may be a memory device, a memory module, or a mixture of a memory device and a memory module. Examples of memory devices and memory modules are described below in conjunction with Figure 1 Description. In general, a host system may utilize a memory subsystem that includes one or more memory components, such as memory devices (e.g., memory dies) that store data. The host system may send access requests (e.g., write commands, read commands) to the memory subsystem to store data in the memory subsystem and to read data from the memory subsystem. Data (or data sets) specified by the host are hereinafter referred to as "host data," "application data," or "user data."

[0015] The memory subsystem can initiate media management operations, such as write operations, on host data stored on the memory device. For example, as part of a garbage collection management operation, the memory subsystem's firmware can overwrite previously written host data from a location on the memory device to a new location. Data overwritten, such as by firmware, is referred to hereinafter as "garbage collection data." "User data" may include host data and garbage collection data. Hereinafter, "system data" refers to data created and / or maintained by the memory subsystem to perform operations in response to host requests and for media management. Examples of system data include, but are not limited to, system tables (e.g., logical-to-physical address mapping tables), log data, scratch pad data, and the like.

[0016] Many different media management operations can be performed on a memory device. For example, media management operations may include different scan rates, different scan frequencies, different wear leveling, different read disturb management, different near miss error correction (ECC), and / or different dynamic data refreshes. Wear leveling ensures that all blocks in a memory component approach their defined erase cycle budget at the same time, rather than some blocks approaching it earlier than others. Read disturb management counts all read operations on the memory component. If a specific threshold is reached, the surrounding area is refreshed. Near miss ECC refreshes all data read by an application that exceeds a configured error threshold. Dynamic data refresh scans all data as a background operation and identifies error conditions for all blocks. If a specific per-block or per-ECC cell error threshold is exceeded in this scan read, a refresh operation is triggered.

[0017] The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies or other physical components. Each die may be composed of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. For some memory devices, a block is the smallest area that can be erased. Each block is composed of a set of pages. Each page is composed of a set of memory cells that store data bits. The memory device may be a raw memory device (e.g., NAND), which is managed externally, for example, by an external controller. The memory device may be a managed memory device (e.g., managed NAND), which is a combination of a raw memory device and a local embedded controller for memory management within the same memory device package.

[0018] If physical faults occur on the PCB implementing the memory device and / or memory controller, effectively managing or executing media management operations on a typical memory device can be challenging. Specifically, a typical memory subsystem is typically implemented on a PCB, with components distributed across the PCB. The various components on the PCB are interconnected via physical wires or conductive traces. These wires and traces may be exposed to various environmental conditions and, in some cases, may become damaged. To reduce damage to the traces, a protective coating in the form of solder mask (which can comprise various resins) may be placed on top of and / or underneath the wires and traces. While this coating helps alleviate some of the physical stresses encountered by the PCB in the environment and reduce damage to the wires and traces, in many cases, physical cracks can still form in the protective coating. These cracks can ultimately damage or corrode the physical wires and traces, leading to improper operation and additional errors in the memory device. Detecting the presence of such cracks or other physical faults during manufacturing is extremely difficult, and even more so during PCB operation. Typically, when such cracks cause damage, the PCB is discarded, wasting resources.

[0019] Aspects of the present disclosure address the above and other deficiencies by providing an optical waveguide or waveguides embedded within a protective coating on a PCB. The present disclosure can generate a laser or other light beam that is transmitted through the waveguide. A processor can measure or detect interruptions in the light beam, for example, based on differences in beam characteristics (e.g., frequency, attenuation, and / or intensity) between light entering the waveguide and light exiting the waveguide. In response to and based on these differences in beam characteristics, the processor can identify the presence and / or physical location of physical faults (e.g., cracks) in the protective coating and / or traces. These physical faults can then be corrected during manufacturing and / or operation, for example, to prevent damage to PCB components or data transmission failures between connected components on the PCB. This improves the efficiency of operating a memory system, reduces the amount of physical resources consumed by the memory subsystem, and avoids waste. Specifically, by using an optical waveguide to detect cracks in a protective coating on a PCB, the protective coating can be repaired or replaced without damaging the traces or conductors, thereby avoiding the need to discard the PCB due to such cracks.

[0020] In some examples, a system is provided that includes a PCB having multiple layers. The system includes multiple traces, including a first layer of the multiple layers. The multiple traces can couple one or more physical components, including a set of memory components of a memory subsystem, to a processing device. The system includes a protective coating, including a second layer of the multiple layers. The protective coating can be adjacent to (above and / or below) the multiple traces. One or more optical waveguides can be embedded in the protective coating. The one or more optical waveguides can be configured to detect a fault associated with the protective coating based on an interruption of a light beam passing through the one or more optical waveguides.

[0021] In some examples, the one or more physical components and the processing device are on a third layer of the plurality of layers. The third layer may be adjacent to the protective coating. In some examples, the one or more physical components and the processing device are arranged in a stack. In some examples, the fault comprises a crack in the protective coating. In some examples, the fault comprises a crack in the plurality of traces. In some examples, the protective coating comprises a solder mask.

[0022] In some examples, the system includes an additional set of optical waveguides embedded in an additional protective coating, the additional protective coating comprising a third layer of the plurality of layers. In some examples, the plurality of traces are physically located between the second layer and the third layer.

[0023] In some examples, the system includes a laser for generating the light beam. The system includes a first lens for receiving the light beam from the laser and passing the light beam to a polarizer. The system includes a second lens for receiving the light beam passed through the polarizer and directing the light beam to the one or more optical waveguides. In some examples, the system includes: a third lens for receiving the light beam output from the one or more optical waveguides; and a sensor for receiving the light beam passed through the third lens. The sensor can be configured to detect the interruption of the light beam relative to the light beam generated by the laser.

[0024] In some examples, the sensor is configured to perform operations including measuring a time of flight of the light beam and determining a physical location of the fault based on the time of flight of the light beam. In some examples, the one or more optical waveguides include a plurality of optical waveguides. The sensor can be configured to perform operations including measuring a frequency or attenuation of the light beam received from each of the plurality of optical waveguides. The operations can include determining that the frequency or attenuation of the light beam output by a particular optical waveguide of the plurality of optical waveguides is different from the frequency or attenuation of the light beam output by the remaining optical waveguides of the plurality of optical waveguides. The operations can include physically locating the particular optical waveguide based on determining that the frequency or intensity of the light beam output by the particular optical waveguide is different from the frequency or intensity of the light beam output by the remaining optical waveguides, thereby identifying the physical location of the fault.

[0025] In some examples, the one or more optical waveguides include a grid of optical waveguides. The sensor can be configured to perform operations including measuring a frequency or attenuation of the optical beam received from each of the grid of optical waveguides and determining that the frequency or attenuation of the optical beam output by a pair of individual optical waveguides in the plurality of optical waveguides is different from the frequency or attenuation of the optical beam output by the remaining optical waveguides in the plurality of optical waveguides. The operations can include identifying a physical location of the fault based on a physical location of an intersection between the pair of optical waveguides.

[0026] In some examples, the one or more optical waveguides are placed in areas of the PCB associated with a greater likelihood of failure, such as critical areas including edges or corners of the PCB. In some examples, the one or more optical waveguides include one or more glass fibers or optical fiber cables.

[0027] In some examples, the disclosed technology directs a light beam to the input of one or more optical waveguides embedded in a protective coating of a PCB. The protective coating may be adjacent to one or more traces of the PCB. The disclosed technology measures beam characteristics of the light beam output by the one or more optical waveguides and, based on the beam characteristics, detects an interruption in the light beam output by the one or more optical waveguides. The disclosed technology detects a fault in the protective coating of the PCB based on detecting the interruption in the light beam output by the one or more optical waveguides.

[0028] In some examples, the disclosed technology generates the light beam using a laser and passes the light beam through a first lens and then through a polarizer. The disclosed technology passes the light beam output by the polarizer through a second lens to direct the light beam to the input of the one or more optical waveguides.

[0029] In some examples, the technology described herein relates to a method for manufacturing a PCB containing a memory system. The disclosed technology places a plurality of traces comprising a first layer of a plurality of layers on the PCB. The plurality of traces couples one or more physical components comprising a set of memory components of a memory subsystem to a processing device. The disclosed technology deposits a protective coating comprising a second layer of the plurality of layers. The protective coating may be adjacent to the plurality of traces. The disclosed technology embeds one or more optical waveguides in the protective coating. The one or more optical waveguides may be configured to detect a fault associated with the protective coating based on an interruption of a light beam passing through the one or more optical waveguides.

[0030] Although various embodiments are described herein as being implemented with respect to a memory subsystem (eg, a controller of a memory subsystem), some or all portions of the embodiments may be implemented with respect to a host system (eg, a software application or operating system of a host system).

[0031] Figure 1 An example computing environment 100 including a memory subsystem 110 according to some examples of the present disclosure is shown. Memory subsystem 110 may include media, such as memory components 112A through 112N (hereinafter also referred to as "memory devices"). Memory components 112A through 112N may be volatile memory devices, non-volatile memory devices, or a combination thereof. Memory components 112A through 112N may be implemented by individual dies, such that first memory component 112A may be implemented by a first memory die (or a first set of memory dies), and second memory component 112N may be implemented by a second memory die (or a second set of memory dies). These individual dies may be coupled to each other on an integrated circuit and placed on a PCB as individual or combined components.

[0032] In some embodiments, the memory subsystem 110 is a storage system. The memory subsystem 110 can be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual inline memory modules (NVDIMMs).

[0033] The computing environment 100 may include a host system 120 coupled to a memory system. The memory system may include one or more of the memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 One example of a host system 120 is shown coupled to an instance of a memory subsystem 110. The host system 120 uses the memory subsystem 110, for example, to write data to and read data from the memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., with no intervening components), whether wired or wireless, including connections such as electrical connections (conductive traces), optical connections, magnetic connections, and the like.

[0034] Host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or a computing device including memory and processing devices. Host system 120 may include or be coupled to memory subsystem 110, such that host system 120 can read data from or write data to memory subsystem 110. Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel interface, a Serial Attached SCSI (SAS) interface, an M.2 SSD interface, and the like. The physical host interface may be used to transfer data between host system 120 and memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface and / or an M.2 SSD interface, the host system 120 may further access the memory components 112A to 112N using an NVM Express (NVMe) interface. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. The memory subsystem 110 may be implemented on a PCB that is coupled to the host system 120 via a designated interface, such as an M.2 SSD interface.

[0035] Memory components 112A through 112N may include any combination of different types of nonvolatile memory components and / or volatile memory components. Examples of nonvolatile memory components include NAND-type flash memory. Each of memory components 112A through 112N may include one or more memory cell arrays, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., TLC or QLC). In some embodiments, a particular memory component 112 may include both an SLC portion and an MLC portion of memory cells. Each of the memory cells may store one or more data bits (e.g., a block) for use by the host system 120. Although nonvolatile memory components such as NAND-type flash memory are described, memory components 112A through 112N may be based on any other type of memory, such as volatile memory. In some embodiments, the memory components 112A to 112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), NOR (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point array of nonvolatile memory cells.

[0036] A cross-point array of nonvolatile memory cells can be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. Furthermore, in contrast to many flash-based memories, cross-point nonvolatile memory can perform write-in-place operations, where nonvolatile memory cells can be programmed without prior erasure. Furthermore, the memory cells of memory components 112A through 112N can be grouped into memory pages or blocks, which can refer to the cells of memory component 112 used to store data.

[0037] The memory subsystem controller 115 may communicate with the memory components 112A through 112N to perform memory operations, such as reading data, writing data, or erasing data, among other such operations, at the memory components 112A through 112N. The memory subsystem controller 115 may communicate with the memory components 112A through 112N to perform various memory management operations, such as different scan rates, different scan frequencies, different wear leveling, different read disturb management, different near miss ECC operations, and / or different dynamic data refreshes.

[0038] The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, a physical fault detection unit 122, an optical waveguide 130, a buffer memory, and / or a combination thereof. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor. The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 includes embedded memory that is configured to store instructions to perform various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120. In some embodiments, the local memory 119 may include memory registers that store memory pointers, retrieved data, and the like. The local memory 119 may also include a read-only memory (ROM) for storing microcode having instructions for execution by the memory subsystem controller 115, such as firmware. Although Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or provided by a processor 117 or a controller separate from the memory subsystem 110).

[0039] Generally speaking, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A to 112N. The memory subsystem controller 115 can be responsible for other memory management operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, memory component 112A to 112N initialization and / or address translation. The memory subsystem controller 115 can further include host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can convert commands received from the host system 120 into command instructions for accessing the memory components 112A to 112N, and convert responses associated with the memory components 112A to 112N into information for the host system 120. The memory subsystem controller 115 can include a memory interface for communicating with the memory components 112A to 112N. Any component included as part of the memory subsystem controller 115 may be included in the memory interface, and vice versa.

[0040] The memory subsystem 110 may also include additional circuitry or components not shown, such as capacitors, resistors, transistors, and various other active or passive devices. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., a DRAM or other temporary storage location or device) and address circuitry (e.g., a row decoder and a column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory components 112A to 112N.

[0041] The memory device may be a raw memory device (e.g., NAND) that is managed externally, for example, by an external controller (e.g., memory subsystem controller 115). The memory device may be a managed memory device (e.g., managed NAND), which is a raw memory device combined with a local embedded controller (e.g., a local media controller) for memory management within the same memory device package. Any of the memory components 112A to 112N may include a media controller (e.g., media controller 113A and media controller 113N) for managing the memory cells of the memory component (e.g., to perform one or more memory management operations), communicating with the memory subsystem controller 115, and executing memory requests (e.g., reads or writes) received from the memory subsystem controller 115.

[0042] The memory subsystem controller 115 may include a physical fault detection unit 122 coupled to an optical waveguide 130. In some cases, the physical fault detection unit 122 may be a separate physical component from the components of the memory subsystem controller 115 and / or may include some components implemented as part of the memory subsystem controller 115 and some components implemented external to the memory subsystem 110. In some cases, the physical fault detection unit 122 and the components of the memory subsystem controller 115 are implemented by the same physical device or integrated circuit. The optical waveguide 130 is a separate physical device from the physical fault detection unit 122 and / or the memory subsystem controller 115. The optical waveguide 130 is embedded in a protective coating that is deposited on top of and / or below the conductive traces (in the conductive trace layer) of the PCB.

[0043] In one example, optical waveguide 130 can be implemented using one or more fiber optic cables / conductors, such as glass fibers. Optical waveguide 130 comprises a specified refractive index that allows a light beam to enter, pass through, and exit optical waveguide 130 with little or no loss of intensity (e.g., with little attenuation) and / or without changing the frequency of the light beam. Optical waveguide 130 can comprise a braid or mesh of multiple such fiber optic cables or conductors, or any other suitable arrangement of fiber optic cables or conductors. In some cases, optical waveguide 130 comprises a single fiber optic cable or conductor.

[0044] The physical fault detection unit 122 can generate or activate a laser to generate a light beam and pass the light beam through a series of lenses and one or more polarizers before entering each of the one or more fiber optic cables / conductors of the optical waveguide 130. The physical fault detection unit 122 can communicate with a sensor at the output of the optical waveguide 130 to determine whether the light beam at the output of the optical waveguide 130 has undergone any attenuation and / or frequency change relative to the light beam at the input of the optical waveguide 130. In response to determining that the sensor detects a change and that the change exceeds a specified threshold, the physical fault detection unit 122 can determine that a physical fault exists in the protective coating embedded in the optical waveguide 130. For example, if a crack exists in the protective coating, the crack can interfere with the light beam, causing it to attenuate and / or change in frequency. Based on time-of-flight information or measurements associated with the light beam, the physical fault detection unit 122 can determine and identify the physical location of the physical fault and trigger or generate a warning to an operator. In this way, the physical fault can be corrected with minimal cost and before damage occurs to the conductive trace layer connecting the various physical components of the memory subsystem 110 and the host system 120.

[0045] In some examples, in addition to or in lieu of using time-of-flight information or measurements, the physical fault detection unit 122 can communicate with a sensor to identify which of a plurality of fiber optic cables or conductors has a change in beam attenuation or frequency relative to the rest of the plurality of fiber optic cables. For example, if there are 100 fiber optic cables in the optical waveguide 130 and a change in attenuation or frequency is detected in a subset of cables (e.g., 2 of the 100), the physical fault detection unit 122 can determine the physical location of the subset of cables. The physical fault detection unit 122 can estimate the physical location of the physical fault as a path along the subset of cables. In some cases, the plurality of fiber optic cables are arranged in a braid or grid. In such cases, the physical fault detection unit 122 can determine an intersection between two or more of the plurality of fiber optic cables. The intersection can indicate the physical location of the physical fault.

[0046] Depending on the embodiment, the physical fault detection unit 122 may include logic (e.g., a set of transient or non-transient machine instructions, such as firmware) or one or more components that enable the physical fault detection unit 122 to perform the operations described herein. The physical fault detection unit 122 may include tangible or non-tangible units capable of performing the operations described herein.

[0047] For example, a PCB on which the host system 120 and / or the memory subsystem 110 is implemented may include multiple layers. A plurality of traces comprising a first layer of the plurality of layers couples one or more physical components comprising a set of memory components (e.g., memory components 112A to 112N) of the memory subsystem 110 to a processing device, such as the processor 117. A protective coating comprising a second layer of the plurality of layers may be adjacent to the plurality of traces, and one or more optical waveguides, such as the optical waveguide 130, may be embedded in the protective coating. The one or more optical waveguides may be configured to detect a physical fault associated with the protective coating based on an interruption of a light beam passing through the one or more optical waveguides.

[0048] The one or more physical components and processing devices on the PCB can be on a third layer of the multiple layers adjacent to the protective coating. In some embodiments, the one or more physical components and processing devices can be arranged in a stack. The protective coating can include a solder mask layer, which can include a polymer material or other non-conductive material deposited on top of or below the conductive traces.

[0049] The PCB may include an additional set of optical waveguides embedded in an additional protective coating, which comprises a third layer of the plurality of layers. For example, a first protective coating may be deposited beneath a conductive trace on the PCB, and a second protective coating may be deposited on top of the conductive trace. In this way, the conductive trace is sandwiched between the two protective coatings. Each of the first and second protective coatings may include a respective set of optical waveguides 130. By passing a light beam through the optical waveguides 130 in the first and second protective coatings, physical faults in the protective coatings and / or the conductive traces can be detected and identified for correction.

[0050] In some examples, a laser is provided external to or internal to the memory subsystem 110 for generating a light beam. A first lens may be positioned to receive the light beam from the laser and pass the light beam to a polarizer. A second lens may be positioned to receive the light beam passed through the polarizer and direct the light beam to the input of the optical waveguide 130. A third lens may be positioned to receive the light beam output from the optical waveguide 130, and a sensor may be positioned to receive the light beam passed through the third lens. The sensor may be configured to detect an interruption in the light beam relative to the light beam generated by the laser (e.g., a change in attenuation or a change in frequency).

[0051] The sensor can be configured to measure the time of flight of the light beam and determine the physical location of the fault based on the time of flight of the light beam. The optical waveguide 130 may include a plurality of optical waveguides, and the sensor can measure the frequency or attenuation of the light beam received from each of the plurality of optical waveguides. The sensor can determine that the frequency or attenuation of the light beam output by an individual optical waveguide of the plurality of optical waveguides is different from the frequency or attenuation of the light beam output by the remaining optical waveguides of the plurality of optical waveguides to identify the physical location of the fault. In some cases, the optical waveguide 130 includes a grid of optical waveguides, and the sensor can measure the frequency or attenuation of the light beam received from each of the optical waveguide grids and determine that the frequency or attenuation of the light beam output by a pair of individual optical waveguides of the plurality of optical waveguides is different from the frequency or attenuation of the light beam output by the remaining optical waveguides of the plurality of optical waveguides. This enables the sensor to identify the physical location of the fault based on the physical location of the intersection between the pair of optical waveguides.

[0052] In some examples, physical fault detection unit 122 directs a light beam to the input of an optical waveguide 130 embedded in a protective coating of a PCB. Physical fault detection unit 122 measures beam characteristics (e.g., attenuation or frequency variation) of the light beam output by the one or more optical waveguides. Physical fault detection unit 122 detects an interruption in the light beam output by the one or more optical waveguides based on the beam characteristics, and detects a physical fault in the protective coating of the PCB based on the detection of the interruption in the light beam output by optical waveguide 130.

[0053] In some examples, a PCB including the memory subsystem 110 is fabricated by placing a plurality of traces comprising a first layer of a plurality of layers on the PCB, the plurality of traces coupling one or more physical components of a set of memory components comprising the memory subsystem to a processing device. A protective coating comprising a second layer of the plurality of layers is deposited adjacent to the plurality of traces. One or more optical waveguides are embedded in the protective coating, the one or more optical waveguides being configured to detect a fault associated with the protective coating based on an interruption of a light beam passing through the one or more optical waveguides.

[0054] Figure 2 FIG2 is a diagram of an example physical assembly or PCB 200 on which the memory subsystem 110 and the optical waveguide 130 are implemented, according to some embodiments of the present disclosure. The PCB 200 includes one or more physical memory components 214 that can implement the memory subsystem 110 and / or the memory components 112A through 112N. The PCB 200 may include one or more physical controller components 212 that implement the memory subsystem controller 115 and / or the host system 120. The one or more physical memory components 214 and the one or more physical controller components 212 are implemented in a stacked arrangement and are coupled to each other via various methods, such as conductive traces and vias in the first layer 210 of the PCB 200.

[0055] PCB 200 includes a second layer 230 that includes one or more conductive traces 232. The one or more conductive traces 232 include various wires and / or vias that interconnect the one or more physical memory components 214 and / or the one or more physical controller components 212 to each other and to various external components of PCB 200. In some cases, the one or more conductive traces 232 are implemented using solder balls and can be coupled to physical interface 220, such as external pins or solder balls of PCB 200. The one or more conductive traces 232 receive signals from devices external to PCB 200 via interface 220.

[0056] In some examples, a first protective coating 250 is deposited or placed atop the interface 220. The first protective coating 250 can include a first set of optical waveguides 252 embedded in the optical waveguides 130 within the first protective coating 250. After depositing the first protective coating 250 atop the interface 220, a second layer 230 including the one or more conductive traces 232 is formed or deposited atop the first protective coating 250. After forming or depositing the second layer 230, a second protective coating 240 is deposited or placed atop the second layer 230. The second protective coating 240 can include a second set of optical waveguides 242 embedded in the optical waveguides 130 within the first protective coating 250.

[0057] The second set of optical waveguides 242 and the first set of optical waveguides 252 can be implemented using the same type and form of optical fibers as each other, or they can be different. For example, optical waveguides 242 can be implemented using a grid arrangement of optical fibers, while optical waveguides 252 can be implemented using only horizontal and / or only vertical optical fibers. The number of optical fibers included in optical waveguides 242 can be different from the number of optical fibers included in optical waveguides 252. Optical waveguides 252 can be used to detect interruptions in a light beam passing through optical waveguides 252 to identify and / or locate a physical fault in the bottom portion of the first protective coating 250 and / or the second layer 230. Optical waveguides 242 can be used to detect interruptions in a light beam passing through optical waveguides 242 to identify and / or locate a physical fault in the top portion of the second protective coating 240 and / or the second layer 230.

[0058] Figure 3A According to some embodiments of the present disclosure, Figure 2 A block diagram of an example physical assembly 300 of a PCB 200 for an optical waveguide is shown. Figure 3A 2 shows a top view or perspective view of PCB 200. Figure 3A As shown, laser 310 is positioned to generate one or more light beams having a specific frequency and / or intensity. The light beam from laser 310 passes through first lens 320 and is directed to polarizer 330. Polarizer 330 polarizes the light beam and passes the polarized light beam to second lens 340. Second lens 340 can be an active lens or a static lens and is used to direct the polarized light beam to each fiber optic cable or wire contained in optical waveguide 130.

[0059] For example, light output by the second lens 340 is directed to the optical waveguide 242, which includes one or more fiber optic cables 352. In some cases, the one or more fiber optic cables 352 are placed on a layer above or below the one or more conductive traces 350. The configuration, orientation, and positioning of the one or more fiber optic cables 352 can correspond to, mirror, or be similar to the orientation and configuration of the one or more conductive traces 350. That is, the path of the one or more conductive traces 350 can mirror the path of the one or more fiber optic cables 352. This enables the identification and detection of cracks in critical areas of the PCB 200 (or substrate) where the one or more conductive traces 350 and the one or more fiber optic cables 352 are implemented.

[0060] Specifically, light is output by the one or more fiber optic cables 352 and received by a third lens 360. The third lens 360, which can also be an active or static lens, is positioned to receive a light beam from each of the one or more fiber optic cables 352 and direct such light beam to a polarizer 370. The output of the polarizer 370 passes through a fourth lens 380 and is directed to a detector 390. The detector 390 is configured to measure one or more characteristics of the light beam exiting the optical waveguide 130 and compare the characteristics of the light beam to the light beam entering the optical waveguide 130. The detector 390 can identify one or more fiber optic cables in which the one or more characteristics (e.g., attenuation and / or frequency) of the light beam change by more than a threshold value (e.g., the characteristic change exceeds the threshold value). In some cases, the detector 390 can identify which fiber optic cable contains the change in light beam characteristics relative to the other fiber optic cables in the optical waveguide 130. The detector 390 can then identify the physical location of the physical fault that caused the change in light beam characteristics, for example, using time-of-flight measurements.

[0061] In some cases, the optical waveguides 130 embedded in the protective layer comprise a grid of optical fiber cables or other geometric patterns. Figure 3B As shown in FIG301 , the one or more fiber optic cables 352 are implemented as a grid of fiber optic cables 355. Detector 390 can identify a pair of fiber optic cables that contain similar variations in beam characteristics relative to the other fiber optic cables of optical waveguide 130, for example, in different planes or axes. That is, detector 390 can determine that a first fiber optic cable running along the horizontal axis of optical waveguide 130 contains a variation in beam characteristics that exceeds a threshold. Additionally, detector 390 can determine that a second fiber optic cable running along the vertical axis of optical waveguide 130 contains a similar or related variation in beam characteristics that exceeds a threshold. Detector 390 can identify an intersection 357 of the first and second fiber optic cables. Detector 390 can determine that a physical fault in the protective coating exists in the region corresponding to intersection 357.

[0062] Figure 4A is a flow chart of an example method 400 for detecting physical faults in a PCB using an optical waveguide according to some embodiments of the present disclosure. The method 400 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1The physical fault detection unit 122 of the embodiment of the present invention is executed. Although the processes are shown in a specific order or sequence, unless otherwise specified, the process order may be modified. Therefore, the illustrated embodiment should be understood as merely an example, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, in various embodiments, one or more processes may be omitted. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0063] Now refer to Figure 4A The method (or process) 400 begins at operation 405, where the physical fault detection unit 122 of a memory subsystem (e.g., memory subsystem 110) directs a light beam to the input of one or more optical waveguides embedded in a protective coating of a printed circuit board (PCB), the protective coating being adjacent to one or more traces of the PCB. Next, at operation 410, the physical fault detection unit 122 measures beam characteristics of the light beams output by the one or more optical waveguides. At operation 415, the physical fault detection unit 122 detects an interruption in the light beams output by the one or more optical waveguides based on the beam characteristics. At operation 420, the physical fault detection unit 122 detects a fault in the protective coating of the PCB based on the detection of the interruption in the light beams output by the one or more optical waveguides.

[0064] Figure 4B is a flow chart of an example method for manufacturing a PCB with an optical waveguide according to some embodiments of the present disclosure. Method 401 can be performed by processing logic, which can include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, device hardware, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. Although the processes are shown in a particular order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, in various embodiments, one or more processes can be omitted. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0065] Now refer to Figure 4B, method (or process) 401 begins at operation 411, where a plurality of traces comprising a first layer of a plurality of layers are placed on a PCB. The plurality of traces couple one or more physical components comprising a set of memory components of the memory subsystem 110 to a processing device. Next, at operation 416, a protective coating comprising a second layer of the plurality of layers is deposited. The protective coating may be adjacent to the plurality of traces, and at operation 421, one or more optical waveguides are embedded in the protective coating. The one or more optical waveguides may be configured to detect a fault associated with the protective coating based on an interruption of a light beam passing through the one or more optical waveguides.

[0066] According to the above disclosure, various examples are described below. It should be noted that one or more features of the examples, whether considered alone or in combination, should be considered to be within the scope of the disclosure of this application.

[0067] Example 1. A system comprising: a printed circuit board (PCB) comprising a plurality of layers; a plurality of traces comprising a first layer of the plurality of layers, the plurality of traces coupling one or more physical components comprising a set of memory components of a memory subsystem to a processing device; a protective coating comprising a second layer of the plurality of layers, the protective coating being adjacent to the plurality of traces; and one or more optical waveguides embedded in the protective coating, the one or more optical waveguides being configured to detect a fault associated with the protective coating based on an interruption of a light beam transmitted through the one or more optical waveguides.

[0068] Example 2. The system of example 1, wherein the one or more physical components and the processing device are on a third layer of the plurality of layers, the third layer being adjacent to the protective coating.

[0069] Example 3. The system of Example 2, wherein the one or more physical components and the processing device are arranged in a stack.

[0070] Example 4. The system of any of Examples 1 to 3, wherein the fault comprises a crack in the protective coating.

[0071] Example 5. The system of any of Examples 1 to 4, wherein the fault comprises a crack in the plurality of traces.

[0072] Example 6. The system of any of Examples 1 to 5, wherein the protective coating comprises a solder mask.

[0073] Example 7. The system of any of Examples 1 to 6, comprising: an additional set of optical waveguides embedded in an additional protective coating, the additional protective coating comprising a third layer of the plurality of layers.

[0074] Example 8. The system of Example 7, wherein the plurality of traces are physically located between the second layer and the third layer.

[0075] Example 9. The system of any one of Examples 1 to 8, comprising: a laser for generating the light beam; a first lens for receiving the light beam from the laser and passing the light beam to a polarizer; and a second lens for receiving the light beam passed through the polarizer to direct the light beam to an input of the one or more optical waveguides.

[0076] Example 10. The system of Example 9, comprising: a third lens for receiving the light beam output from the one or more optical waveguides; and a sensor for receiving the light beam passed through the third lens, the sensor being configured to detect the interruption of the light beam relative to the light beam generated by the laser.

[0077] Example 11. The system of Example 10, wherein the sensor is configured to perform operations comprising: measuring a time of flight of the light beam; and determining a physical location of the fault based on the time of flight of the light beam.

[0078] Example 12. A system according to any of Examples 10 to 11, wherein the one or more optical waveguides include a plurality of optical waveguides, and wherein the sensor is configured to perform operations including: measuring a frequency or attenuation of the light beam received from each of the plurality of optical waveguides; determining that the frequency or attenuation of the light beam output by an individual one of the plurality of optical waveguides is different from the frequency or attenuation of the light beam output by the remaining optical waveguides; and physically locating the individual optical waveguide based on determining that the frequency or intensity of the light beam output by the individual optical waveguide is different from the frequency or intensity of the light beam output by the remaining optical waveguides, thereby identifying the physical location of the fault.

[0079] Example 13. The system of any of Examples 10 to 13, wherein the one or more optical waveguides comprise a grid of optical waveguides, and wherein the sensor is configured to perform operations comprising: measuring a frequency or attenuation of the optical beam received from each of the grid of optical waveguides; determining that the frequency or attenuation of the optical beam output by a pair of individual optical waveguides of the plurality of optical waveguides is different from the frequency or attenuation of the optical beam output by the remaining optical waveguides of the plurality of optical waveguides; and identifying a physical location of the fault based on a physical location of an intersection between the pair of optical waveguides.

[0080] Example 14. The system of any of Examples 1 to 13, wherein the one or more optical waveguides are placed in an area of ​​the PCB associated with a greater likelihood of failure.

[0081] Example 15. The system of any of Examples 1 to 14, wherein the one or more optical waveguides comprise one or more glass fibers.

[0082] Example 16. A method comprising: directing an optical beam to the input of one or more optical waveguides embedded in a protective coating of a printed circuit board (PCB), the protective coating being adjacent to one or more traces of the PCB; measuring beam characteristics of the optical beam output by the one or more optical waveguides; detecting an interruption of the optical beam output by the one or more optical waveguides based on the beam characteristics; and detecting a fault in the protective coating of the PCB based on detecting the interruption of the optical beam output by the one or more optical waveguides.

[0083] Example 17. The method of Example 16, wherein the fault comprises a crack in the protective coating.

[0084] Example 18. The method of any of Examples 16 to 17, wherein the protective coating comprises a solder mask.

[0085] Example 19. The method of any one of Examples 16 to 18, comprising: generating the light beam by a laser; passing the light beam through a first lens and then through a polarizer; and passing the light beam output by the polarizer through a second lens to direct the light beam to the input of the one or more optical waveguides.

[0086] Example 20. A method of manufacturing a printed circuit board (PCB) including a memory system, the method comprising: placing a plurality of traces including a first layer of a plurality of layers on the PCB, the plurality of traces coupling one or more physical components of a set of memory components including a memory subsystem to a processing device; depositing a protective coating including a second layer of the plurality of layers, the protective coating adjacent to the plurality of traces; and embedding one or more optical waveguides in the protective coating, the one or more optical waveguides being configured to detect a fault associated with the protective coating based on an interruption of a light beam transmitted through the one or more optical waveguides.

[0087] Methods and computer-readable storage media having instructions for performing any of the above examples.

[0088] Figure 5An example machine is shown in the form of a computer system 500 within which a set of instructions may be executed to cause the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 500 may correspond to a host system (e.g., Figure 1 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110), or can be used to perform operations of the controller (for example, to execute an operating system to perform operations related to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client user machine in server-client network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0089] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a network switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be performed by the machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0090] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0091] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, and the like. More specifically, processing device 502 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, and the like. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 that communicates via a network 520.

[0092] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methodologies or functions described herein. The instructions 526 may also reside completely or partially within the main memory 504 and / or within the processing device 502 during execution by the computer system 500, the main memory 504, and the processing device 502, which also constitute the machine-readable storage medium. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0093] In one embodiment, instructions 526 implement the instructions corresponding to Figure 1 The functionality of the physical fault detection unit 122 is provided. Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0094] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. An operation is one requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0095] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities within the computer system's registers and memories and transforms it into other data represented in a similar manner as physical quantities within the computer system's memories or registers or other such information storage systems.

[0096] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), each coupled to a computer system bus; read-only memory (ROM); random access memory (RAM); erasable programmable read-only memory (EPROM); EEPROM; magnetic or optical cards; or any type of medium suitable for storing electronic instructions.

[0097] The algorithms and displays presented herein are not inherently related to any specific computer or other device. Various general-purpose systems can be used together with the programs according to the teachings herein, or it can be demonstrated that it is convenient to construct a more specialized device for performing the method. The structure of various these systems will be presented as described above. In addition, the present disclosure is not described with reference to any specific programming language. It should be understood that various programming languages ​​can be used to implement the teachings of the present disclosure as described herein.

[0098] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being useful for programming a computer system (or other electronic device) to perform a method according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., computer-readable) storage medium, such as a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0099] In the foregoing description, the embodiments of the present disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. The description and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: a printed circuit board (PCB), which includes multiple layers; a plurality of traces comprising a first layer of the plurality of layers, the plurality of traces coupling one or more physical components comprising a set of memory components of a memory subsystem to a processing device; a protective coating comprising a second layer of the plurality of layers, the protective coating being adjacent to the plurality of traces; as well as One or more optical waveguides are embedded in the protective coating, the one or more optical waveguides configured to detect a fault associated with the protective coating based on an interruption of a light beam passing through the one or more optical waveguides. 2 . The system of claim 1 , wherein the one or more physical components and the processing device are on a third layer of the plurality of layers, the third layer being adjacent to the protective coating.

3. The system of claim 2, wherein the one or more physical components and the processing device are arranged in a stack.

4. The system of claim 1, wherein the fault comprises a crack in the protective coating. The system of claim 1 , wherein the fault comprises a crack in the plurality of traces. The system of claim 1 , wherein the protective coating comprises a solder mask.

7. The system according to claim 1, comprising: An additional set of optical waveguides is embedded in an additional protective coating, the additional protective coating comprising a third layer of the plurality of layers.

8. The system of claim 7, wherein the plurality of traces are physically located between the second layer and the third layer.

9. The system according to claim 1, comprising: a laser for generating the light beam; a first lens for receiving the light beam from the laser and passing the light beam to a polarizer; as well as A second lens is configured to receive an input of the light beam passed through the polarizer to direct the light beam to the one or more optical waveguides.

10. The system according to claim 9, comprising: a third lens for receiving the light beam output from the one or more light waveguides; as well as A sensor is provided for receiving the light beam transmitted through the third lens, the sensor being configured to detect the interruption of the light beam relative to the light beam generated by the laser.

11. The system of claim 10, wherein the sensor is configured to perform operations comprising: measuring a time of flight of the light beam; as well as Based on the time of flight of the light beam, a physical location of the fault is determined.

12. The system of claim 10, wherein the one or more optical waveguides comprises a plurality of optical waveguides, and wherein the sensor is configured to perform operations comprising: measuring a frequency or attenuation of the light beam received from each of the plurality of optical waveguides; determining that the frequency or attenuation of the optical beam output by an individual optical waveguide of the plurality of optical waveguides is different from the frequency or attenuation of the optical beam output by the remaining optical waveguides of the plurality of optical waveguides; as well as Based on determining that the frequency or intensity of the light beam output by the individual optical waveguide is different from the frequency or intensity of the light beam output by the remaining optical waveguides, the individual optical waveguide is physically located, thereby identifying the physical location of the fault.

13. The system of claim 10, wherein the one or more optical waveguides comprise a grid of optical waveguides, and wherein the sensor is configured to perform operations comprising: measuring the frequency or attenuation of the light beam received from each of the optical waveguide grids; determining that the frequency or attenuation of the optical beam output by a pair of individual ones of the plurality of optical waveguides is different from the frequency or attenuation of the optical beam output by the remaining ones of the plurality of optical waveguides; as well as Based on the physical location of the intersection between the pair of optical waveguides, the physical location of the fault is identified.

14. The system of claim 1, wherein the one or more optical waveguides are placed in an area of ​​the PCB associated with a greater likelihood of failure.

15. The system of claim 1, wherein the one or more optical waveguides comprise one or more glass fibers.

16. A method comprising: directing an optical beam to an input of one or more optical waveguides embedded in a protective coating of a printed circuit board (PCB), the protective coating being adjacent to one or more traces of the PCB; measuring beam characteristics of the light beam output by the one or more optical waveguides; detecting an interruption of the light beam output by the one or more optical waveguides based on the light beam characteristics; as well as A fault in the protective coating of the PCB is detected based on detecting the interruption of the light beam output by the one or more optical waveguides.

17. The method of claim 16, wherein the fault comprises a crack in the protective coating. The method of claim 16 , wherein the protective coating comprises a solder resist layer.

19. The method according to claim 16, comprising: generating the light beam by a laser; passing the light beam through a first lens and then through a polarizer; as well as The light beam output by the polarizer is passed through a second lens to direct the light beam to the input of the one or more optical waveguides.

20. A method of manufacturing a printed circuit board (PCB) including a memory system, the method comprising: placing a plurality of traces comprising a first layer of the plurality of layers on the PCB, the plurality of traces coupling one or more physical components comprising a set of memory components of a memory subsystem to a processing device; depositing a protective coating comprising a second layer of the plurality of layers, the protective coating adjacent to the plurality of traces; as well as One or more optical waveguides are embedded in the protective coating, the one or more optical waveguides configured to detect a fault associated with the protective coating based on an interruption of a light beam passing through the one or more optical waveguides.

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