Voltage detection circuit

Abstract

A voltage detection circuit is provided with: an AD converter (50); an input chopper circuit (40) that switches the connection state between each input terminal of the AD converter and the first and second input wires at a first frequency (fc1); an output chopper circuit (60) that alternately performs an inversion operation and a non-inversion operation with respect to the output value of the AD converter at the first frequency (fc1); a digital low-pass filter (70) operating at an output frequency fd and removing a high-frequency component from an output value of the output chopper circuit; and a current chopper circuit (34) that switches the connection state of the first current source, the first input wiring, the second current source, and the second input wiring at a second frequency fc2. When m and n are integers greater than or equal to 0, fc1 = fd2m, fc2 = fd2n, and n > = m are satisfied.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a voltage detection circuit. Background Art

[0002] Patent Document 1 discloses a technique for detecting disconnection on the analog circuit side of an AD converter (analog-to-digital converter) that converts an input voltage into a digital value. This technique detects disconnection based on the output value of the AD converter at the time of increasing or decreasing the potential at the AD converter's input terminal.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: U.S. Patent No. 11353517 Summary of the Invention

[0006] In the AD converter of Patent Document 1, the input voltage of the AD converter changes during disconnection detection, so the target voltage detection operation must be suspended during disconnection detection. This specification proposes a technology that can detect disconnection during target voltage detection and accurately detect the target voltage.

[0007] According to one technical solution of the present disclosure, a voltage detection circuit includes: an AD converter that converts a voltage applied between a first input terminal and a second input terminal into a digital value; a first input wiring; a second input wiring; an input chopper circuit that switches the connection state at a first frequency fc1 between a first connection state in which the first input wiring is connected to the first input terminal and the second input wiring is connected to the second input terminal, and a second connection state in which the first input wiring is connected to the second input terminal and the second input wiring is connected to the first input terminal; and an output chopper circuit that alternately performs the AD conversion at the first frequency fc1. An inverting operation for inverting and outputting the output value of the converter and a non-inverting operation for outputting the output value of the AD converter without inverting; a digital low-pass filter operating at an output frequency fd and removing high-frequency components from the output value of the output chopper circuit; a first current source; a second current source; and a current chopper circuit switching the connection state at a second frequency fc2 between a third connection state in which the first current source is connected to the first input wiring and the second current source is connected to the second input wiring, and a fourth connection state in which the first current source is connected to the second input wiring and the second current source is connected to the first input wiring. When m and n are integers greater than 0, fc1 = fd·2 m 、fc2=fd·2 n , n≥m.

[0008] In this voltage detection circuit, a first input wiring and a second input wiring are connected to a device to be detected. The voltage between the first and second input wirings is converted by an input chopper circuit into a voltage that fluctuates at a first frequency fc1 and is then input into an A / D converter. The A / D converter outputs the input voltage (i.e., the voltage that fluctuates at the first frequency fc1) as a digital value. The output chopper circuit inverts the output value of the A / D converter (i.e., the voltage that fluctuates at the first frequency fc1) at predetermined intervals at the first frequency fc1, thereby restoring the waveform corresponding to the original voltage (i.e., the voltage between the first and second input wirings). A digital low-pass filter removes high-frequency components from the output value of the output chopper circuit. With this configuration, low-frequency noise generated by the A / D converter is modulated to a high frequency by the output chopper circuit, and this high-frequency voltage is removed by the digital low-pass filter, thereby suppressing errors caused by the low-frequency noise. Furthermore, in this voltage detection circuit, current is supplied to the first and second input wirings from a first current source and a second current source. Through the action of the current chopping circuit, the supply current of the first current source and the supply current of the second current source flow alternately in the first input wiring and the second input wiring. When no disconnection occurs in the first input wiring and the second input wiring, an offset voltage is generated between the first input wiring and the second input wiring due to the error between the current supplied from the first current source and the current supplied from the second current source. Since the current chopping circuit switches the connection state at the second frequency fc2, the offset voltage becomes a voltage that varies at the second frequency fc2. The offset voltage is input to the digital low-pass filter via the input chopping circuit, the AD converter, and the output chopping circuit. The offset voltage that varies at a high frequency is removed by the digital low-pass filter. Therefore, the voltage of the detection object can be correctly detected while suppressing the influence of the offset voltage. In particular, by satisfying fc1=fd·2 m , fc2=fd·2 n , n≥m, the voltage having the first frequency fc1 and the voltage having the second frequency fc2 can be appropriately removed by the digital low-pass filter. Therefore, according to this voltage detection circuit, the voltage of the detection object can be detected more accurately. In addition, if a disconnection occurs in the first input wiring, the current supplied from the current chopping circuit to the first input wiring no longer flows to the voltage detection object device side, so the potential of the first input wiring rises. If a disconnection occurs in the second input wiring, the current supplied from the current chopping circuit to the second input wiring no longer flows to the voltage detection object device, so the potential of the second input wiring rises. Therefore, the disconnection can be detected based on the potential of the first input wiring and the potential of the second input wiring. As described above, according to this voltage detection circuit, the disconnection detection action can be performed in parallel with the detection action of the target voltage, and the target voltage can be accurately detected. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 1 is a circuit diagram of a voltage detection circuit according to Example 1.

[0010] Figure 2 This is a diagram showing various voltages during the operation of the voltage detection circuit of Example 1.

[0011] Figure 3 This is a circuit diagram of a voltage detection circuit of Example 2.

[0012] Figure 4 This is a diagram showing various voltages during the operation of the voltage detection circuit of the second embodiment. DETAILED DESCRIPTION

[0013] [Example 1]

[0014] Figure 1 The voltage detection circuit 10 of the first embodiment shown includes a shunt resistor 12. The shunt resistor 12 is connected to an external circuit (not shown). A current Is supplied from the external circuit flows through the shunt resistor 12. The voltage detection circuit 10 detects the current Is by detecting a voltage Vs across the ends of the shunt resistor 12.

[0015] The voltage detection circuit 10 has a first input wiring 20a, a second input wiring 20b and an antialiasing filter 24 (hereinafter referred to as AAF24). The first input wiring 20a and the second input wiring 20b are connected to the shunt resistor 12 via the AAF24. The AAF24 has a first resistor 24a, a second resistor 24b and a capacitor 24c. The first input wiring 20a is connected to the terminal 12a on one side of the shunt resistor 12 (more specifically, the terminal on the high potential side) via the first resistor 24a. The second input wiring 20b is connected to the terminal 12b on the other side of the shunt resistor 12 (more specifically, the terminal on the low potential side) via the second resistor 24b. Therefore, the shunt resistor 12 is connected between the first input wiring 20a and the second input wiring 20b via the first resistor 24a and the second resistor 24b. The resistance of the first resistor 24a is equal to the resistance of the second resistor 24b. The capacitor 24c is connected between the first input wiring 20a and the second input wiring 20b.

[0016] The voltage detection circuit 10 includes a frequency signal generating circuit 80. The frequency signal generating circuit 80 has a duty ratio of 50% and outputs a pulse signal 90 oscillating at a frequency fc. The pulse signal 90 is input to each chopper circuit described later.

[0017] The voltage detection circuit 10 includes a first current source 30a, a second current source 30b, and a current chopper circuit 34. The first current source 30a generates a constant DC current Iwod1. The second current source 30b generates a constant DC current Iwod2. The output terminals of the first current source 30a and the second current source 30b are connected to the current chopper circuit 34.

[0018] The current chopping circuit 34 changes the connection state between the first current source 30a, the second current source 30b, the first input wiring 20a, and the second input wiring 20b. The current chopping circuit 34 alternately switches the connection state between connection state A and connection state B. In connection state A, the output terminal of the first current source 30a is connected to the first input wiring 20a, and the output terminal of the second current source 30b is connected to the second input wiring 20b. Therefore, in connection state A, current Iwod1 flows through the first input wiring 20a, and current Iwod2 flows through the second input wiring 20b. In connection state B, the output terminal of the first current source 30a is connected to the second input wiring 20b, and the output terminal of the second current source 30b is connected to the first input wiring 20a. Therefore, in connection state B, current Iwod1 flows through the second input wiring 20b, and current Iwod2 flows through the first input wiring 20a. Pulse signal 90 output by frequency signal generation circuit 80 is input to current chopping circuit 34. Current chopping circuit 34 alternately switches the connection state between connection state A and connection state B in synchronization with pulse signal 90. Therefore, current chopping circuit 34 alternately switches the connection state between connection state A and connection state B at a frequency fc. Furthermore, because the duty cycle of pulse signal 90 is 50%, the length of the period in connection state A and the length of the period in connection state B in each cycle are equal.

[0019] like Figure 1As shown, the current I1 (i.e., current Iwod1 or current Iwod2) supplied from the current chopping circuit 34 to the first input wiring 20a flows to the external circuit via the first resistor 24a and the shunt resistor 12. In addition, the current I2 (i.e., current Iwod1 or current Iwod2) supplied from the current chopping circuit 34 to the second input wiring 20b flows to the external circuit via the second resistor 24b. As described above, the resistances of the first resistor 24a and the second resistor 24b are equal to each other. Hereinafter, the resistances of the first resistor 24a and the second resistor 24b are represented as resistance R. The resistance of the shunt resistor 12 is much smaller than the resistance R of the first resistor 24a and the second resistor 24b. Since the current I1 flows into the first resistor 24a, the potential of the first input wiring 20a becomes higher by the voltage Va (=R·I1) than the potential of the terminal 12a of the shunt resistor 12. Furthermore, because current I2 flows through second resistor 24b, the potential of second input wiring 20b increases by voltage Vb (=R·I2) compared to the potential of terminal 12b of shunt resistor 12. Therefore, a voltage V1 is applied between first input wiring 20a and second input wiring 20b, where V1 = Vs + ΔV (ΔV = Va - Vb). If Iwod1 = Iwod2, then I1 = I2, and therefore ΔV = 0. However, an error actually occurs between currents Iwod1 and Iwod2, so a voltage ΔV resulting from the difference between currents Iwod1 and Iwod2 is applied between first input wiring 20a and second input wiring 20b. Thus, a voltage that deviates by a voltage ΔV from the voltage Vs being detected is applied between first input wiring 20a and second input wiring 20b. Hereinafter, voltage ΔV is referred to as offset voltage ΔV. Since the current chopping circuit 34 allows current to flow through the first input wiring 20 a and the second input wiring 20 b while switching between the current Iwod1 and the current Iwod2 , the direction of the offset voltage ΔV generated in the connection state A is opposite to the direction of the offset voltage ΔV generated in the connection state B. Therefore, the offset voltage ΔV alternately changes between positive and negative.

[0020] The voltage detection circuit 10 includes an input chopper circuit 40, an analog-to-digital converter 50 (hereinafter referred to as ADC 50), an output chopper circuit 60, and a digital low-pass filter 70 (hereinafter referred to as DLPF 70). The first input wiring 20a and the second input wiring 20b are connected to the input chopper circuit 40. The ADC 50 includes a first input terminal 50a and a second input terminal 50b. The first input terminal 50a and the second input terminal 50b are connected to the input chopper circuit 40. The input chopper circuit 40 changes the mutual connection state between the first input wiring 20a, the second input wiring 20b, the first input terminal 50a, and the second input terminal 50b. The input chopper circuit 40 alternately switches the connection state between connection state C and connection state D. In connection state C, the first input wiring 20a is connected to the first input terminal 50a, and the second input wiring 20b is connected to the second input terminal 50b. In connection state D, the first input wiring 20a is connected to the second input terminal 50b, and the second input wiring 20b is connected to the first input terminal 50a. Therefore, in connection state C, the voltage V2 applied between the first input terminal 50a and the second input terminal 50b matches the voltage V1 between the first input wiring 20a and the second input wiring 20b. Furthermore, in connection state D, the voltage V2 applied between the first input terminal 50a and the second input terminal 50b matches the voltage V1 between the first input wiring 20a and the second input wiring 20b, which is a positive-negative inversion of the voltage V1 between the first input wiring 20a and the second input wiring 20b. The input chopper circuit 40 alternately switches the connection state between connection state C and connection state D in synchronization with the pulse signal 90 input from the frequency signal generating circuit 80. Therefore, the input chopper circuit 40 alternately switches the connection state between connection state C and connection state D at a frequency fc. Furthermore, since the duty ratio of the pulse signal 90 is 50%, the length of the period of the connection state C and the length of the period of the connection state D in each cycle are equal.

[0021] ADC50 outputs a signal obtained by converting the voltage V2 applied between the first input terminal 50a and the second input terminal 50b into a digital value. Hereinafter, the voltage represented by the digital signal output by ADC50 is referred to as voltage V3. Voltage V3 includes voltage V2 and an error component generated by ADC50.

[0022] The output chopper circuit 60 processes the voltage V3, which is the digital value output by the ADC 50. The output chopper circuit 60 alternately performs a non-inverting operation, outputting the voltage V3 as is, and an inverting operation, outputting a voltage with the sign of the voltage V3 reversed. The output chopper circuit 60 alternately performs the non-inverting and inverting operations in synchronization with the pulse signal 90 input from the frequency signal generating circuit 80. Therefore, the output chopper circuit 60 alternately performs the non-inverting and inverting operations at a frequency fc. Furthermore, since the duty cycle of the pulse signal 90 is 50%, the length of the non-inverting period and the length of the inverting period in each cycle are equal. Hereinafter, the voltage represented by the digital signal output by the output chopper circuit 60 will be referred to as voltage V4.

[0023] The DLPF 70 removes the high-frequency component from the voltage V4 output by the output chopper circuit 60. Specifically, the DLPF 70 calculates the average value of the voltage V4 during one cycle of the output frequency fd and outputs this average value as the voltage V5. Therefore, the DLPF 70 repeatedly outputs the voltage V5 at the output frequency fd. In this way, the DLPF 70 repeatedly calculates the average value of the voltage V4 and outputs the voltage V5 after removing the high-frequency component from the voltage V4. The output frequency fd is the value obtained by dividing the sampling frequency fs of the ADC 50 by the specified decimation ratio. In other words, the output frequency fd is lower than the sampling frequency fs. Furthermore, the frequency fc is lower than the sampling frequency fs and is greater than the output frequency fd. In the first embodiment, fc = fd.

[0024] Figure 2 The figure shows the changes of voltages V1 to V5 when the voltage detection circuit 10 is operating normally. In addition, since the change rate of voltage Vs is much lower than the change rate of voltages V1 to V4, Figure 2 The voltage Vs is represented as a fixed value. Figure 2 In the equation, the period Td represents the period of one cycle of the frequency fd. That is, Td = 1 / fd. Figure 2 Period T1 is the first half of period Td, and period T2 is the second half of period Td. Periods T1 and T2 are equal in length. As described above, voltage V1 applied between input wirings 20a and 20b is V1 = Vs + ΔV. Furthermore, as described above, current chopper circuit 34 switches the current path at frequency fc, so offset voltage ΔV alternates between positive and negative at frequency fc. Consequently, voltage V1 fluctuates at frequency fc around voltage Vs.

[0025] As described above, the input chopper circuit 40 switches the connection state between connection state C and connection state D at frequency fc. During period T1, the connection state is connection state C, and during period T2, the connection state is connection state D. As described above, in connection state C (i.e., period T1), voltage V2 matches voltage V1. Furthermore, in connection state D (i.e., period T2), voltage V2 matches voltage V1 with its sign reversed.

[0026] As described above, ADC50 outputs a signal obtained by converting voltage V2 into a digital value. However, a certain error voltage Verr is generated in the output value of ADC50. Error voltage Verr is a substantially DC component. Therefore, voltage V3 represented by the output value of ADC50 is a voltage obtained by varying voltage V2 by error voltage Verr (i.e., V3 = V2 + Verr).

[0027] As described above, the output chopper circuit 60 performs the non-inverting operation and the inverting operation alternately at the frequency fc. The output chopper circuit 60 performs the non-inverting operation during the period T1 and performs the inverting operation during the period T2. During the non-inverting operation (i.e., during the period T1), the voltage V4 is consistent with the voltage V3. In addition, during the inverting operation (i.e., during the period T2), the voltage V4 is consistent with the voltage obtained by inverting the positive and negative of the voltage V3. In addition, during Figure 2 In FIG, the voltage V1c and the error voltage Verrc that constitute the voltage V4 are shown. That is, V4 = V1c + Verrc. The voltage V1c is a component equivalent to the voltage V1, and the error voltage Verrc is a voltage equivalent to the error voltage Verr. Figure 2 As shown, the DC error voltage Verr is converted by output chopper circuit 60 into a high-frequency error voltage Verrc that fluctuates at a frequency fc. Furthermore, output chopper circuit 60 performs non-inverting and inverting operations in synchronization with pulse signal 90, thereby restoring voltage V1c equivalent to voltage V1. Voltage V1c fluctuates around voltage Vs by an offset voltage ΔV and is substantially consistent with voltage V1.

[0028] DLPF 70 outputs voltage V5 as the average value of voltage V4 within period Td. That is, DLPF 70 repeatedly outputs voltage V5 for each period Td. By repeatedly calculating voltage V5 in this manner, voltage V5 is obtained by removing the high-frequency component from voltage V4. Error voltage Verrc in voltage V4 is a high-frequency component and is therefore removed by DLPF 70. Furthermore, voltage V1c in voltage V4 is identical to voltage V1 (V1 = Vs + ΔV). The offset voltage ΔV that constitutes voltage V1c is a high-frequency component and is therefore removed by DLPF 70. Voltage Vs that constitutes voltage V1c is a DC component and is therefore not removed by DLPF 70. Therefore, voltage V5 output by DLPF 70 is identical to voltage Vs.

[0029] As described above, the voltage detection circuit 10 can output a voltage V5 that matches the voltage Vs. In particular, the error voltage Verr can be eliminated by the output chopper circuit 60 and the DLPF 70. Furthermore, since the offset voltage ΔV is modulated into a high-frequency component by the operation of the current chopper circuit 34, the offset voltage ΔV can be eliminated by the DLPF 70. Furthermore, since the frequency fc of the offset voltage ΔV and the frequency fc of the error voltage Verrc are both equal to the output frequency fd of the DLPF 70, no error due to frequency deviation occurs in the DLPF 70. Therefore, the voltage detection circuit 10 can accurately detect the voltage Vs.

[0030] Furthermore, in the first embodiment, since the current chopper circuit 34 is operated at the same frequency fc as the input chopper circuit 40 and the output chopper circuit 60, a common pulse signal 90 can be input to these chopper circuits. Since the frequency signal generating circuit 80 can be shared by each chopper circuit, the voltage detection circuit 10 can be miniaturized.

[0031] Next, the disconnection detection by the voltage detection circuit 10 will be described. Figure 1If a disconnect occurs at point X, the first input wiring 20a is disconnected from terminal 12a, and current I1 no longer flows from the first input wiring 20a to terminal 12a. Consequently, the first input wiring 20a is charged by current I1, and the potential of the first input wiring 20a rises rapidly. For example, capacitor 24c is charged by current I1, and the potential of the first input wiring 20a rises rapidly. For example, voltage V1 rises to an excessively high positive voltage. Furthermore, although not shown, if the second input wiring 20b is disconnected from terminal 12b, current I2 no longer flows from the second input wiring 20b to terminal 12b, and voltage V1 drops rapidly. For example, voltage V1 drops to an excessively large negative voltage. Therefore, disconnection can be detected based on the absolute value or rate of change of voltage V1. For example, disconnection can be detected based on the absolute value or rate of change of voltage V5, which changes in response to voltage V1. In this way, voltage detection circuit 10 can perform disconnection detection in parallel with voltage Vs detection. This can prevent erroneous detection of voltage Vs when disconnection occurs.

[0032] As described above, according to the voltage detection circuit 10 of the first embodiment, the voltage Vs can be accurately detected, and disconnection can be detected during the detection operation of the voltage Vs.

[0033] [Example 2]

[0034] Figure 3 The voltage detection circuit 100 of the second embodiment shown has two frequency signal generating circuits 81 and 82. The frequency signal generating circuit 81 outputs a pulse signal 91 oscillating at a frequency fc1. The frequency fc1 is equal to the output frequency fd of the DLPF 70. The duty cycle of the pulse signal 91 is 50%. The frequency signal generating circuit 82 outputs a pulse signal 92 oscillating at a frequency fc2. The frequency fc2 is four times the output frequency fd of the DLPF 70 (i.e., 2 2 times). The duty cycle of pulse signal 92 is 50%. Pulse signal 91 is input to input chopper circuit 40 and output chopper circuit 60. Input chopper circuit 40 and output chopper circuit 60 operate in synchronization with pulse signal 91. Pulse signal 92 is input to current chopper circuit 34. Current chopper circuit 34 operates in synchronization with pulse signal 92. The remaining structure of voltage detection circuit 100 of Example 2 is the same as that of Example 1.

[0035] Figure 4Figure 2 shows the changes in voltages V1 to V5 during normal operation of the voltage detection circuit 100 of Example 2. In Example 2, the current chopper circuit 34 switches its connection state at a frequency fc2 that is four times the output frequency fd. Therefore, the offset voltage ΔV oscillates four times during period Td. Furthermore, since the operating frequency fc1 of the input chopper circuit 40 is equal to the output frequency fd of the DLPF, the input chopper circuit 40 operates in the same manner as in Example 1. Therefore, voltage V2 is equal to voltage V1 during period T1 and becomes the inverted version of voltage V1 during period T2. Similarly to Example 1, the ADC 50 converts voltage V2 into a digital value, resulting in voltage V3 being the voltage V2 plus the error voltage Verr. Since the operating frequency fc1 of the output chopper circuit 60 is equal to the output frequency fd of the DLPF, the output chopper circuit 60 operates in the same manner as in Example 1. Therefore, the voltage V4 output by the output chopper circuit 60 includes a voltage V1c, which is the result of restoring the voltage V1, and an error voltage Verrc, which is the result of modulating the error voltage Verr to a high frequency. As in Example 1, the DLPF 70 operates at the output frequency fd to remove the high-frequency component from the voltage V4. The error voltage Verrc is removed by the DLPF 70. Furthermore, the high-frequency component (i.e., the offset voltage ΔV) included in the voltage V1c is also removed by the DLPF 70. As a result, the output voltage V5 is a voltage that is substantially identical to the voltage Vs.

[0036] As described above, the voltage detection circuit 100 of Example 2, like Example 1, can output a voltage V5 that matches the voltage Vs. Furthermore, in Example 2, since the offset voltage ΔV is modulated at a higher frequency fc2 than in Example 1, the DLPF 70 can more appropriately remove the offset voltage ΔV, thereby reducing noise. Furthermore, like Example 1, Example 2 can detect disconnection during the voltage Vs detection operation. Thus, the voltage detection circuit 100 of Example 2 can accurately detect the voltage Vs and detect disconnection during the voltage Vs detection operation.

[0037] When m and n are integers greater than or equal to 0, the voltage Vs can be accurately detected as long as the frequencies fd, fc1, and fc2 satisfy the following relationship: fc1 = fd·2 m , fc2=fd·2 n, n≥m. In addition, Example 1 is an example in the case of m=0, n=0, and Example 2 is an example in the case of m=0, n=2. In addition, in Examples 1 and 2, m is 0, but m can also be an integer greater than 1. In this way, if the frequencies fc1 and fc2 are greater than the frequency fd, the offset voltage ΔV and the error voltage Verr can be modulated to a high frequency band that can be removed by the DLPF 70. Therefore, the offset voltage ΔV and the error voltage Verr can be appropriately removed. In addition, if the frequencies fc1 and fc2 are twice the frequency fd, m times or 2 n times, it is possible to prevent the DLPF 70 from misaligning the processing of the offset voltage ΔV and the error voltage Verr, and to suppress the occurrence of errors in the DLPF 70. Therefore, as long as the above relationship is satisfied, the voltage Vs can be accurately detected.

[0038] Connection state A is an example of the third connection state. Connection state B is an example of the fourth connection state. Connection state C is an example of the first connection state. Connection state D is an example of the second connection state.

[0039] The above describes the implementation methods in detail, but these are merely examples and are not intended to limit the scope of the present disclosure. The technology described in the claims of the present disclosure includes various forms of deformation and modification of the specific examples exemplified above. The technical elements described in this specification or the drawings exert technical usefulness individually or through various combinations, and are not limited to the combinations described in the present disclosure at the time of application. In addition, the technology exemplified in this specification or the drawings is used to achieve multiple purposes at the same time, and achieving one of the purposes itself has technical usefulness.

Claims

1. A voltage detection circuit, characterized in that: have: an AD converter that converts the voltage applied between the first input terminal and the second input terminal into a digital value; 1st input wiring; 2nd input wiring; an input chopper circuit configured to switch a connection state at a first frequency fc1 between a first connection state in which the first input wiring is connected to the first input terminal and the second input wiring is connected to the second input terminal, and a second connection state in which the first input wiring is connected to the second input terminal and the second input wiring is connected to the first input terminal; an output chopper circuit that alternately performs an inverting operation of inverting and outputting an output value of the AD converter and a non-inverting operation of outputting the output value of the AD converter without inverting at the first frequency fc1; A digital low-pass filter operates at an output frequency fd to remove high-frequency components from the output value of the output chopper circuit; 1st current source; a second current source; as well as a current chopping circuit configured to switch a connection state at a second frequency fc2 between a third connection state in which the first current source is connected to the first input wiring and the second current source is connected to the second input wiring, and a fourth connection state in which the first current source is connected to the second input wiring and the second current source is connected to the first input wiring; When m and n are integers greater than 0, fc1=fd·2 m fc2=fd·2 n n≥m.

2. The voltage detection circuit according to claim 1, wherein: n=m.

3. The voltage detection circuit according to claim 1, wherein: n>m.

4. The voltage detection circuit according to any one of claims 1 to 3, wherein: The first input wiring is connected to the voltage detection target device via a first resistor; The second input wiring is connected to the voltage detection target device via a second resistor.

5. The voltage detection circuit according to any one of claims 1 to 3, wherein: A shunt resistor is connected between the first input wiring and the second input wiring.

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