Power supply control method and circuit, electronic equipment and readable storage medium

Abstract

The invention discloses a power supply control method and circuit, electronic equipment and a readable storage medium, and belongs to the technical field of power management. The method comprises the following steps: acquiring an expected power value of each load unit, and if a first load unit with the expected power value greater than or equal to a power upper limit value exists in the plurality of load units, acquiring a working power value of each power supply chip in the plurality of power supply chips, and updating the power upper limit value of each power supply chip according to the working power values of all the power supply chips, the expected power values of all the first load units and the total power upper limit value of the system on chip.

Description

Technical Field

[0001] The present application belongs to the field of power management technology, and specifically relates to a power supply control method, circuit, electronic device and readable storage medium. Background Art

[0002] Currently, the power supply architecture of smart terminals mostly uses multiple chips to power the load unit. When a load unit in a smart terminal experiences an abnormality, that is, the load unit's required supply voltage or current increases, the corresponding power chip needs to adjust the power supply.

[0003] In related technologies, the power supply chip that supplies power to the load unit will activate a protection mechanism, that is, automatically reduce the output voltage or limit the current to prevent damage to the load unit and the chip itself due to overcurrent.

[0004] However, the solutions proposed in the related art will reduce the probability of the load unit working, thereby resulting in poor system scheduling performance. Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide a power supply control method, circuit, electronic device and readable storage medium, which can solve the relevant technical solutions, reduce the probability of the load unit working, and thus cause the problem of poor system scheduling performance.

[0006] In a first aspect, an embodiment of the present application provides a power supply control method, which is applied to a system on chip, wherein the system on chip includes: a plurality of power chips and a plurality of load units; the load units correspond one-to-one to the power chips; the method includes:

[0007] Obtaining an expected power value of each of the load units; the expected power value is the power value required for the load unit to operate normally;

[0008] If, among the multiple load units, there is a first load unit whose expected power value is greater than or equal to the upper power limit value, then obtaining the operating power value of each of the multiple power chips; the upper power limit value is used to represent the power upper limit of the power chip corresponding to the load unit; and the operating power value is the power value of the power chip when it is actually working;

[0009] The power upper limit value of each power chip is updated according to the operating power values ​​of all the power chips, the expected power values ​​of all the first load units and the total power upper limit value of the on-chip system; the updated power upper limit value is used for subsequent comparison with the expected power value of the load unit.

[0010] In a second aspect, an embodiment of the present application provides a power supply control circuit, the circuit comprising:

[0011] A battery and a system on chip; the system on chip includes: a plurality of power chips and a plurality of load units; the load units correspond to the power chips one by one; the battery is connected to the system on chip;

[0012] The on-chip system is used to obtain the expected power value of each of the load units; the expected power value is the power value required for the normal operation of the load unit; among the multiple load units, if there is a first load unit whose expected power value is greater than or equal to the power upper limit value, then the working power value of each of the multiple power chips is obtained; the power upper limit value is used to characterize the power upper limit of the power chip corresponding to the load unit; the working power value is the power value of the power chip when it is actually working; according to the working power values ​​of all the power chips, the expected power values ​​of all the first load units and the total power upper limit value of the on-chip system, the power upper limit value of each of the power chips is updated; the updated power upper limit value is used for subsequent comparison with the expected power value of the load unit.

[0013] In a third aspect, an embodiment of the present application provides an electronic device comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the method described in the first aspect are implemented.

[0014] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the method described in the first aspect are implemented.

[0015] In a fifth aspect, an embodiment of the present application provides a chip, which includes a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the method described in the first aspect.

[0016] In a sixth aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the method described in the first aspect.

[0017] In an embodiment of the present application, among multiple load units, if there is a first load unit whose expected power value is greater than or equal to the power upper limit value, then the updated power upper limit value corresponding to each power chip is determined according to the respective working power values ​​of all power chips in the on-chip system, the expected power values ​​of all first load units, and the total power upper limit value of the on-chip system, so as to dynamically adjust the original power upper limit value corresponding to each power chip, so that the working power value of the power chip is within the range of the updated power upper limit value, the system maintains normal operation, and the probability of the first load unit continuing to work is increased when the power chip supplying power to the first load unit does not activate the protection mechanism, thereby improving the scheduling performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a flowchart of a power supply control method provided by an embodiment of the present application;

[0019] Figure 2 This is a flowchart of another power supply control method provided by an embodiment of the present application;

[0020] Figure 3 This is a schematic diagram of communication between a master and a slave device provided in an embodiment of the present application;

[0021] Figure 4 This is a simplified framework diagram of the master-slave system power supply proposed in the related technology;

[0022] Figure 5 This is a simplified framework diagram of the power supply from the system provided in the embodiment of the present application.

[0023] Figure 6 This is a power control flow chart when an abnormality occurs in a load unit provided by an embodiment of the present application;

[0024] Figure 7 This is a flowchart of the power detection steps provided by an embodiment of the present application;

[0025] Figure 8 This is a schematic structural diagram of a power supply control device provided in an embodiment of the present application;

[0026] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0027] Figure 10 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0029] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0030] Figure 1 This is a flowchart of a power supply control method provided by an embodiment of the present application. The method may include the following steps:

[0031] Step 101 : Obtain an expected power value of each load unit; the expected power value is the power value required for the load unit to operate normally.

[0032] For example, a system-on-chip (SoC) is a very large-scale integrated circuit (VLSI) that integrates multiple functions on a single chip. It can implement complex system functions and is widely used in various electronic devices, such as smartphones, tablets, and smartwatches. Load cells are functional modules within a SoC that consume power to perform specific functions, such as the central processing unit (CPU), graphics processing unit (GPU), memory, and various sensors. Different load cells have different power requirements under different operating conditions. The expected power value is the amount of power required by the load cell in its current operating state to meet its performance requirements and operate normally. This value varies depending on factors such as the load cell's operating mode and task complexity.

[0033] Step 102: If there is a first load unit among multiple load units whose expected power value is greater than or equal to the power upper limit value, the operating power value of each power chip among the multiple power chips is obtained; the power upper limit value is used to characterize the power upper limit of the first power chip corresponding to the first load unit; the operating power value is the power value when the power chip is actually working.

[0034] For example, if the expected power value is greater than or equal to the upper power limit value set for the power chip that supplies power to the load unit, it can be understood that an abnormality has occurred in the load unit.

[0035] For example, a power cap is a power limit set for a power chip, representing the maximum power that the power chip can safely and stably output. Exceeding the power cap may cause the power chip to overheat, become damaged, or become otherwise unstable. For example, the load unit may be a graphics processor. The power cap for the power chip powering the graphics processor can be set to 1 watt. When the expected power value is greater than or equal to 1 watt, the operating power of each power chip powering each load unit in the system-on-chip is obtained.

[0036] For example, the operating power value refers to the power consumed or output by the power chip that supplies power to each load unit in the system-on-chip during actual operation. It reflects the actual power usage of the power chip at the current moment. The current and voltage of the load units in the system-on-chip can be obtained, and the operating power of the power chip that supplies power to the load units can be calculated based on the current and voltage.

[0037] Step 103, updating the power upper limit value of each power chip according to the working power values ​​of all power chips, the expected power values ​​of all first load units and the total power upper limit value of the on-chip system; the updated power upper limit value is used for subsequent comparison with the expected power value of the load unit.

[0038] For example, the total power cap of a system on a chip (SoC) is the maximum power a battery can supply to the circuits. It represents the maximum power limit the entire SoC can withstand. Exceeding this limit can cause system overheating, instability, or even damage. The updated power cap is a new power cap for each power chip based on the operating power values ​​of all power chips, the expected power values ​​of all primary load units, and the total power cap of the SoC. This is an optimized value set to ensure reasonable power distribution and stable system operation, taking into account the overall system power situation.

[0039] For example, under normal operating conditions, the total power limit of the eight load units within the SoC is 10 watts. Assume that each load unit operates at 1 watt during normal operation. An unexpected event causes the multimedia subunit's desired power to reach 5 watts, exceeding the preset limit. To meet the multimedia subunit's normal operating requirements, the power limit of the power supply chip can be dynamically adjusted based on the 1 watt operating power of each load unit, the multimedia subunit's desired power value of 5 watts, and the total power limit of 10 watts. This helps to rationally allocate system resources. This ensures that each load unit receives sufficient power without overloading a power supply chip and leaving other chips idle, thereby improving resource utilization efficiency across the SoC.

[0040] The power cap is the power limit used by the power chip during initial setup or during previous operating phases. This value is typically set based on the chip's default configuration, early system requirements, or preliminary power planning, but may no longer be applicable as system operating conditions change. Updating the power cap of the power chip replaces the original power cap used by the power chip with the newly calculated power cap, allowing the chip to operate within the new power limit. Updating the power cap of the power chip allows the chip's power output to precisely match the system's current needs. When the system-on-chip's workload changes, such as in different application scenarios or during task switching, the power requirements of the load unit also change accordingly. By promptly updating the power cap of the power chip, the system can quickly adapt to these changes, maintain stable operation, and meet power requirements under varying operating conditions.

[0041] In an embodiment of the present application, if a first load unit among multiple load units has an expected power value greater than or equal to the power cap, an updated power cap is determined for each power chip based on the operating power values ​​of all power chips in the system-on-chip, the expected power values ​​of all first load units, and the total power cap of the system-on-chip. This allows dynamic adjustment of the original power cap for each power chip, ensuring that the operating power value of the power chip falls within the updated power cap range and that the system maintains normal operation. This increases the probability of the first load unit continuing to operate even if the power chip supplying power does not activate its protection mechanism, thereby improving system scheduling performance.

[0042] Figure 2 This is a flowchart of another power supply control method provided by an embodiment of the present application. The method may include the following steps:

[0043] Step 201 : Obtain an expected power value of each load unit; the expected power value is the power value required for the load unit to operate normally.

[0044] This step may be specifically referred to the above step 101 and will not be described in detail here.

[0045] Step 202: If there is a first load unit among multiple load units whose expected power value is greater than or equal to the power upper limit value, obtain the first working power value of the first power supply chip corresponding to the first load unit; the power upper limit value is used to characterize the power upper limit of the first power supply chip; the first working power value is the power value of the first power supply chip when it is actually working.

[0046] This step may be specifically referred to the above step 102 and will not be described in detail here.

[0047] Step 203 : When the first operating power value is less than the upper power limit of the first power chip, calculate a first difference between the upper power limit of the first power chip and the first operating power value.

[0048] For example, taking a first operating power value of 0.99 watts as an example, by calculating the first difference between the power upper limit of 1 watt and the first operating power value of 0.99 watt, the current power headroom of the first power chip can be determined, that is, the amount of additional power that the chip can provide without exceeding the power upper limit. This helps the system determine whether there is sufficient power headroom to cope with possible load changes or sudden power demands.

[0049] Step 204 : When the first difference is greater than a preset difference, a trigger signal is received; the trigger signal is a signal sent by the first power chip through the system power management interface.

[0050] For example, the trigger signal is an electrical signal sent by the first power chip through the system power management interface (SPMI) when the first difference is greater than a preset threshold. It is used to notify the system on chip or other power chips that the power state of the first power chip has changed and the system needs to perform corresponding processing or response. The system power management interface is a hardware interface in the system on chip used to realize communication and interaction between the power chip and other modules. It provides a standardized way for the power chip to transmit its own status information to the system, and also allows the system to control and manage the power chip.

[0051] See also Figure 3 The related technology is to extend the protocol content of the existing system power management interface of the slave to other slave protocols. The command comes from the system power management interface, and the system power management interface converts the write instructions of a slave into write instructions of other slaves and executes them. However, the system power management interface of this solution does not introduce a new protocol. The focus is on increasing the existing communication between devices based on the existing system power management interface protocol. While synchronizing to the power chips of the same level, it will also feedback to the main control, and make a summary judgment based on the total power consumption of the system and the power status of each power chip, dynamically adjust the working power of each channel, and limit or relax the output power of the system.

[0052] When the first difference is greater than the preset threshold, receiving the trigger signal allows the system to promptly understand that the first operating power value of the first power supply chip is very close to the power upper limit value, so that the system can respond quickly and take corresponding measures according to the specific situation, such as adjusting load distribution, optimizing power management strategies, etc., to fully utilize the power in the circuit and improve the overall performance and efficiency of the system.

[0053] For example, the trigger signal is a high-level signal or a binary signal; the binary signal is a signal generated after converting the first operating power value into a binary number.

[0054] For example, in digital circuits, a high level is a signal level that indicates a specific state and is used to transmit and represent information. For example, if the preset threshold is 1%, when the first difference exceeds 1%, the first power chip transmits a high-level signal to other power chips and the system-on-chip (SoC) via the system power management interface. This enables communication between power chips, saves the SoC from issuing commands and tasks, improves efficiency, and shortens the response time of the entire system.

[0055] A binary signal is a signal that represents information in the form of binary numbers. In computer systems and digital circuits, information is typically stored, transmitted, and processed in binary form. Taking a preset threshold of 1% as an example, when the first difference is greater than 1%, the first operating power value is converted into a string of binary numbers. The first power chip transmits the binary number to other power chips and the system on chip through the system power management interface, enabling communication between power chips, saving the system on chip from issuing commands and tasks, improving efficiency, and shortening the response time of the entire system. Furthermore, binary numbers can more accurately represent the numerical information of the first operating power value and facilitate processing, analysis, and comparison by the digital system.

[0056] Step 205, in response to the trigger signal, obtain the second working power value of the second power chip; the second working power value is sent by the second power chip through the system power management interface; the second power chip is a power chip among multiple power chips, excluding the first power chip.

[0057] By obtaining the second operating power value of the second power chip, the system can gain a more comprehensive understanding of the power usage of the entire system-on-chip. After the power state of the first power chip changes and sends a trigger signal, timely obtaining the operating power of other power chips helps the system comprehensively evaluate whether the power distribution of each component is reasonable and whether adjustments are needed.

[0058] Figure 4 This is a simplified master-slave system power supply framework diagram proposed in related technologies. It consists of a power supply system and a system-on-chip (SoC) load unit. System power is managed by a power management unit (PMU), which in turn is powered by a battery. After a power tree design, various power outputs are generated. Assuming the power tree consists of eight power chips, the SoC, as the system's most important load, contains multiple sub-load modules. These sub-modules handle different SoC functions and consume varying amounts of power. The accelerator processing unit (CPU), graphics processing unit (GPU), and central processing unit (CPU) process more information and consume relatively high power.

[0059] See also Figure 4Traditional system power management interfaces rely on "master-slave" communication. A "master-slave" relationship involves a single master controller and multiple devices. Information originates from the master controller, who initiates, controls, and makes decisions. The devices receive, are controlled, and execute. Each control signal network in a "master-slave" relationship operates bidirectionally. The master controller determines which device to communicate with by reading the chip identity of each device. However, devices cannot communicate with each other.

[0060] This application proposes a detection mechanism in which power chips can monitor and communicate with each other, and can analyze load overvoltage and overcurrent. The power chips used can quickly reflect the information to the system on chip through the system power management interface, and the system on chip can make adjustments and adapt. This application introduces "slave-slave" communication between power chips, so that the information of power control detection can be shared in the power network, and the overall system on chip is provided with the best power supply solution, improving system performance, optimizing system scheduling and reducing power consumption. The "slave-slave" relationship re-establishes new communication and connection between device ends, and information and control commands can be exchanged. Figure 5 As shown, different from Figure 4 The system power management interface uses a solid line, indicating that devices can also communicate with each other.

[0061] Step 206 : updating the power upper limit value of each power chip according to the operating power values ​​of all power chips, the expected power values ​​of all first load units, and the total power upper limit value of the system on chip.

[0062] This step may be specifically referred to the above step 103 and will not be described in detail here.

[0063] Optionally, step 206 may specifically include:

[0064] Sub-step 2061: determining the expected power value of the first load unit as the updated upper power limit value of the first power chip; the updated upper power limit value of the first power chip is greater than the original upper power limit value of the first power chip;

[0065] Sub-step 2062: Determine updated power upper limits for at least some of the second power supply chips based on the updated power upper limits of all first power supply chips, the corresponding operating power values ​​of the second power supply chips, and the total power upper limit of the system on chip; the updated power upper limits of at least some of the second power supply chips are smaller than their corresponding original power upper limits.

[0066] Regarding sub-steps 2061 and 2062, for example, under normal operating conditions, the total power limit of the power supply to the eight load units within the system-on-chip is 10 watts. Assuming that each load unit operates at a power of 1 watt during normal operation, and an unexpected event causes the operating power of the multimedia sub-unit to reach 5 watts, exceeding the preset limit, to meet the normal operation requirements of the multimedia sub-unit, the updated power limit value of the first power chip supplying power to the multimedia sub-unit is determined to be the expected power value, i.e., 5 watts. Alternatively, the updated power limit value of the first power chip may be determined to be a value greater than the expected power value, i.e., 6 watts.

[0067] Taking into account the impact of the increased total power consumption of the updated power cap of the first power chip and the limitations of the system's total power cap, to balance power distribution, the updated power caps of the second power chips corresponding to at least some of the second load units are adjusted to be lower than their respective original power caps. This adjustment ensures that the multimedia subunits receive sufficient power to process high-definition video, ensuring image quality. Furthermore, the updated power caps of at least some of the second power chips balance power distribution across the entire system-on-chip, ensuring stable system operation within the total power cap.

[0068] Optionally, sub-step 2062 may specifically include:

[0069] Sub-step 20621: if the operating power value corresponding to the second power chip is less than a preset power threshold, determine the second power chip as a target power chip;

[0070] Sub-step 20622: Obtain the original power upper limit values ​​corresponding to each of the second power chips, and calculate a second difference between the total power upper limit value and the original power upper limit value corresponding to the third power chip; the third power chip is the power chip among the second power chips excluding the target power chip;

[0071] Sub-step 20623, calculating a third difference between the second difference and the updated upper power limit of the first power chip, and determining the third difference as the allocable power value;

[0072] Sub-step 20624 , allocating the corresponding updated power upper limit value to the target power chip using the allocable power value.

[0073] For sub-steps 20621-20624, for specific application scenarios, modules that are strongly related to sub-modules such as the image processing unit, data processing unit, core unit, etc. maintain preset power values, and other sub-modules such as the static storage unit, modulation and demodulation unit, etc. can moderately control the output power to optimize the overall system power consumption.

[0074] For example, taking the multimedia sub-unit as an example, the load units in the system on chip are divided into units that are strongly related to the multimedia sub-unit and units that are weakly related to the multimedia sub-unit. The units that are strongly related to the multimedia sub-unit may specifically be image processing units, data processing units, and core units. The units that are weakly related to the multimedia sub-unit may specifically be storage units, modulation units, and the like. The power chip that supplies power to the units that are weakly related to the multimedia sub-unit may be referred to as a target power chip. The sum of the power upper limit values ​​corresponding to the power chips other than the target power chip is calculated to be 3 watts. The second difference between the total power upper limit value of 10 watts and 3 watts is calculated to be 7 watts, and the third difference between the second difference of 7 watts and the updated power upper limit value of 5 watts corresponding to the first power chip is calculated to be 2 watts, and the third difference of 2 watts is determined as the allocable power value.

[0075] Optionally, sub-step 20624 may specifically include:

[0076] Sub-step 206241, calculating the ratio of the allocable power value to the number of target power chips to obtain an average value;

[0077] Sub-step 206242: determining the average value as the updated power upper limit value corresponding to the target power chip.

[0078] For sub-steps 206241 and 206242, assuming the number of target power chips is 4 and the allocable power value is 2 watts, the updated power limit is determined as 0.5 watts, the ratio of 2 watts to 4. By calculating the average of the ratio of the allocable power value to the number of target power chips and determining this as the updated power limit, relatively balanced power distribution can be achieved across the target power chips. Other allocation schemes are also possible and are not limited here.

[0079] Optionally, sub-step 2062 may specifically include:

[0080] Sub-step 20625, calculating a fourth difference between the total power upper limit value and the updated power upper limits of all first power chips;

[0081] Sub-step 20626, determining the updated power upper limit value corresponding to each second power chip based on the operating power value corresponding to each second power chip and the fourth difference; the updated power upper limit value corresponding to the second power chip is smaller than the original power upper limit value corresponding to each second power chip.

[0082] In sub-steps 20625 and 20626, the fourth difference between the total power limit of 10 watts and the updated power limit of 5 watts corresponding to the first power chip is calculated to be 5 watts. In this case, 5 watts is the allocable power value. Based on the corresponding operating power of each second power chip, 1 watt, and the fourth difference of 5 watts, the updated power limit corresponding to each second power chip is determined. Based on the total power limit and the operating power of each power chip, the power limits of the second power chips are redistributed. For example, the power limits of all second power chips may be reduced to appropriately reserve power. Specifically, each load unit is designed with a power table containing the relationship between voltage and frequency. The operating voltage and frequency of the load unit strictly follow this voltage-frequency relationship. This table is configured via software registers. When operating conditions meet certain conditions, the table is reconfigured. Similarly, to reduce the power consumption of the load unit, the system-on-chip actively modifies the operating conditions. If the power of a module is high, the voltage-frequency parameters of the remaining load units are adjusted to maintain the total power consumption, while increasing the power headroom of one load unit.

[0083] Optionally, after step 206, the method further includes:

[0084] Step 207 , when the expected power value of the first load unit is greater than or equal to the updated upper power limit value of the first power chip, proceed to the step of obtaining the operating power value of each power chip among the multiple power chips;

[0085] Step 208 : When the expected power value of the first load unit is less than the updated upper power limit value of the first power chip, control the power chips to operate according to their respective updated upper power limits.

[0086] In steps 207 and 208, when the expected power value is greater than or equal to the power limit set for the power chip, the system proceeds to the step of obtaining the operating power of each power chip, allowing the system to promptly understand the actual operating status of each power chip. When the expected power value is less than the power limit set for the power chip, the power chips are controlled to operate according to their respective updated power limits, ensuring that the power chips operate within a reasonable power range, further ensuring system stability.

[0087] Optionally, the method further includes:

[0088] Step 210: Calculate the total power and count the number of times the total power exceeds the upper limit of the total power of the system on chip; the total power is the sum of the operating power values ​​of all power chips;

[0089] Step 211: If the number of times exceeds a preset number, an early warning is issued.

[0090] In steps 210 and 211, the SoC reads the operating power of each power chip through the system power management interface and performs a sum calculation to obtain the total power. Theoretically, this total power cannot be too high; it must be within the battery output power to ensure that the system does not power down. If the continuously monitored total power shows an upward trend and repeatedly touches the SoC's total power limit, an alert is issued.

[0091] For example, when the first power chip triggers the protection mechanism, the SoC will invite all power chips to perform spot checks and provide feedback, ultimately outputting a general command to determine whether the terminal's battery needs to be cut off for protection or instantly powered off and restarted. If the calculated total power exceeds the total power limit of the SoC for a number of consecutive times exceeding the preset number, there is a risk of damaging the battery and shortening its lifespan, and the battery power supply needs to be cut off. Otherwise, continuous monitoring and power supply are maintained. This protects the SoC from excessive damage while also protecting the battery from over-discharge.

[0092] In an embodiment of the present application, among multiple load units, if there is a first load unit whose expected power value is greater than or equal to the power upper limit value, then the updated power upper limit value corresponding to each power chip is determined according to the respective working power values ​​of all power chips in the on-chip system, the expected power values ​​of all first load units, and the total power upper limit value of the on-chip system, so as to dynamically adjust the original power upper limit value corresponding to each power chip, so that the working power value of the power chip is within the range of the updated power upper limit value, the system maintains normal operation, and the probability of the first load unit continuing to work is increased when the power chip supplying power to the first load unit does not activate the protection mechanism, thereby improving the scheduling performance of the system.

[0093] Figure 6 It is a power control flow chart provided by an embodiment of the present application when an abnormality occurs in a load unit. Specifically, when the system is working normally, it is determined whether the power consumption of the load unit suddenly changes. If the power consumption suddenly changes, that is, the current expected power value of the load unit is greater than or equal to the power upper limit value set by the first power chip that supplies power to the load unit, then the first power chip starts overcurrent or overvoltage protection. The modules inside the on-chip main control collect data and analyze the specific abnormal module. If it can be repaired, the system works normally, otherwise it reports an error for maintenance. If the power supply chip can be informed through the system power management interface, the power supply chip is notified to perform total power detection and start the power detection mechanism. Determine whether the total power supply power is normal. If it is normal, the system works normally, otherwise continue to start the power detection mechanism. If the power supply chip cannot be informed through the system power management interface, an error is reported for maintenance.

[0094] Figure 7 This is a flow chart of the power detection steps provided by the embodiment of the present application, see Figure 7, which includes:

[0095] Step M1: Start the power detection mechanism.

[0096] Step M2 , detecting the total power supplied by the power supply, that is, detecting the operating power of each power chip and calculating the total power of the operating power of each power chip.

[0097] Step M3, determines whether the total power exceeds the standard, that is, determines whether the total power is greater than the upper limit of the total power. If it is greater than the upper limit of the total power, enters step M4, otherwise enters step M2.

[0098] Step M4: detecting the operating power of each power chip and feeding back the result.

[0099] Step M5, detecting whether the power of the single power supply exceeds the standard, that is, determining whether the first operating power of the first power chip is greater than or equal to the power upper limit value. If it is greater than or equal to the power upper limit value, proceed to step M6, otherwise proceed to step M3.

[0100] In step M6, the power upper limit of each power chip is reallocated, and the process proceeds to step M2.

[0101] The power supply control method provided in the embodiment of the present application can be executed by a power supply control device. In the embodiment of the present application, the power supply control device provided in the embodiment of the present application is described by taking the power supply control method executed by the power supply control device as an example.

[0102] Figure 8 This is a structural diagram of a power supply control device 300 provided in an embodiment of the present application, referring to Figure 10 , the apparatus 300 may include:

[0103] The first acquisition module 301 is configured to acquire an expected power value of each load unit; the expected power value is the power value required for the load unit to work normally;

[0104] A second acquisition module 302 is configured to acquire, if among the plurality of load units, a first load unit having an expected power value greater than or equal to an upper power limit value, an operating power value of each of the plurality of power chips; the upper power limit value is used to represent the upper power limit of the power chip corresponding to the load unit; and the operating power value is the actual operating power value of the power chip;

[0105] Determination module 303 updates the power upper limit value of each power chip according to the working power values ​​of all the power chips, the expected power values ​​of all the first load units and the total power upper limit value of the system on chip; the updated power upper limit value is used for subsequent comparison with the expected power value of the load unit.

[0106] Optionally, the multiple power chips include: a first power chip, and a second power chip other than the first power chip; the first power chip is the power chip corresponding to the first load unit; the operating power value of each of the multiple power chips includes: a first operating power value of the first power chip, and a second operating power value of each of the second power chips;

[0107] The second acquisition module includes:

[0108] a first acquisition submodule, configured to acquire the first operating power value, and, if the first operating power value is less than the upper power limit of the first power chip, calculate a first difference between the upper power limit of the first power chip and the first operating power value;

[0109] a receiving submodule, configured to receive a trigger signal when the first difference is greater than a preset difference; the trigger signal is a signal sent by the first power chip through the system power management interface;

[0110] The second acquisition submodule is configured to acquire the second operating power value in response to the trigger signal; the second operating power value is sent by the second power chip through the system power management interface.

[0111] Optionally, the trigger signal is a high-level signal or a binary signal; the binary signal is a signal generated after converting the first operating power value into a binary number.

[0112] Optionally, the multiple load units further include: a second load unit other than the first load unit; the multiple power supply chips include: the first power supply chip corresponding to the first load unit, and the second power supply chip corresponding to the second load unit; the operating power values ​​include: the operating power values ​​corresponding to each of the second power supply chips;

[0113] The determining module includes:

[0114] a first determining submodule, configured to determine the expected power value of the first load unit as the updated power upper limit value of the first power chip; the updated power upper limit value of the first power chip being greater than the original power upper limit value of the first power chip;

[0115] The second determination submodule is used to determine the updated power upper limit value for at least some of the second power supply chips based on the updated power upper limit values ​​of all the first power supply chips, the corresponding working power values ​​of each of the second power supply chips, and the total power upper limit value of the on-chip system; the updated power upper limit value of at least some of the second power supply chips is less than the corresponding original power upper limit value.

[0116] Optionally, the second determining submodule includes:

[0117] a first determining unit, configured to determine one of the second power chips as a target power chip when an operating power value corresponding to the second power chip is less than a preset power threshold;

[0118] a first calculation unit, configured to obtain an original power upper limit value corresponding to each of the second power chips, and calculate a second difference between the total power upper limit value and the original power upper limit value corresponding to a third power chip; the third power chip being a power chip among the second power chips excluding the target power chip;

[0119] a second calculating unit, configured to calculate a third difference between the second difference and the updated upper power limit of the first power chip, and determine the third difference as an allocable power value;

[0120] An allocating unit is configured to allocate the corresponding updated power upper limit value to the target power chip according to the allocable power value.

[0121] Optionally, the allocation unit includes:

[0122] a calculation subunit, configured to calculate a ratio of the allocable power value to the number of target power chips to obtain an average value;

[0123] The determining subunit is configured to determine the average value as the updated power upper limit value corresponding to the target power chip.

[0124] Optionally, the second determining submodule includes:

[0125] a third calculating unit, configured to calculate a fourth difference between the total power upper limit value and the updated power upper limits of all the first power chips;

[0126] The second determination unit is used to determine the updated power upper limit value corresponding to each second power supply chip based on the working power value corresponding to each second power supply chip and the fourth difference; the updated power upper limit value corresponding to the second power supply chip is less than the original power upper limit value corresponding to each.

[0127] Optionally, the device further includes:

[0128] a first determining module configured to, when the expected power value of the first load unit is greater than or equal to the updated upper power limit value of the first power chip, proceed to a step of obtaining an operating power value of each of the plurality of power chips; the first power chip being the power chip corresponding to the first load unit;

[0129] The second judgment module is configured to control the power supply chips to operate according to their respective updated power upper limits when the expected power value of the first load unit is less than the updated power upper limit of the first power supply chip.

[0130] Optionally, the device further includes:

[0131] a calculation module, configured to calculate a total power and count the number of times the total power is greater than an upper limit of the total power of the system on chip; the total power is the sum of the respective operating power values ​​of all the power chips;

[0132] The early warning module is used to issue an early warning when the number of times exceeds a preset number.

[0133] In an embodiment of the present application, if a first load unit among multiple load units has an expected power value greater than or equal to the power cap, an updated power cap is determined for each power chip based on the operating power values ​​of all power chips in the system-on-chip, the expected power values ​​of all first load units, and the total power cap of the system-on-chip. This allows dynamic adjustment of the original power cap for each power chip, ensuring that the operating power value of the power chip falls within the updated power cap range and that the system maintains normal operation. This increases the probability of the first load unit continuing to operate even if the power chip supplying power does not activate its protection mechanism, thereby improving system scheduling performance.

[0134] The power supply control device in the embodiment of the present application can be an electronic device or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or a device other than a terminal. For example, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc. It can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., and the embodiment of the present application does not make specific limitations.

[0135] The power supply control device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0136] Alternatively, as Figure 9 As shown, an embodiment of the present application also provides an electronic device 400, including a processor 401 and a memory 402, wherein the memory 402 stores a program or instruction that can be run on the processor 401. When the program or instruction is executed by the processor 401, the various steps of the above-mentioned power supply control method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0137] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0138] Figure 10 This is a schematic diagram of the hardware structure of an electronic device implementing an embodiment of the present application. The electronic device 500 includes, but is not limited to, components such as a radio frequency unit 501, a network module 502, an audio output unit 503, an input unit 504, a sensor 505, a display unit 506, a user input unit 507, an interface unit 508, a memory 509, and a processor 510.

[0139] Those skilled in the art will understand that the electronic device 500 may also include a power source (such as a battery) to power each component, and the power source may be logically connected to the processor 510 through a power management system, thereby implementing functions such as charging, discharging, and power consumption management through the power management system. Figure 10 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be repeated here.

[0140] It should be understood that in an embodiment of the present application, the input unit 504 may include a graphics processing unit (GPU) 5041 and a microphone 5042, and the graphics processor 5041 processes the image data of a static picture or video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 506 may include a display panel 5061, and the display panel 5061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 507 includes a touch panel 5071 and at least one of other input devices 5072. The touch panel 5071 is also called a touch screen. The touch panel 5071 may include two parts: a touch detection device and a touch controller. Other input devices 5072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and an operating stick, which will not be repeated here.

[0141] The memory 509 can be used to store software programs and various data. The memory 509 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, applications or instructions required for at least one function (such as a sound playback function, an image playback function, etc.). In addition, the memory 509 may include a volatile memory or a non-volatile memory, or the memory 509 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM), and a direct memory bus random access memory (DRRAM). The memory 509 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0142] Processor 510 may include one or more processing units. Optionally, processor 510 integrates an application processor and a modem processor. The application processor primarily handles operations related to the operating system, user interface, and application programs, while the modem processor primarily processes wireless communication signals, such as a baseband processor. It is understood that the modem processor may not be integrated into processor 510.

[0143] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned power supply control method embodiment are implemented and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0144] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0145] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned Huam content display method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0146] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0147] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the power supply control method embodiment described above, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0148] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0149] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0150] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A power supply control method, characterized in that: Applied to a system on chip, the system on chip includes: a plurality of power chips and a plurality of load units; the load units correspond one to one with the power chips; the method includes: Obtaining an expected power value of each of the load units; the expected power value is the power value required for the load unit to operate normally; If, among the multiple load units, there is a first load unit whose expected power value is greater than or equal to the upper power limit value, then obtaining the operating power value of each of the multiple power chips; the upper power limit value is used to represent the power upper limit of the power chip corresponding to the load unit; and the operating power value is the power value of the power chip when it is actually working; The power upper limit value of each power chip is updated according to the operating power values ​​of all the power chips, the expected power values ​​of all the first load units and the total power upper limit value of the on-chip system; the updated power upper limit value is used for subsequent comparison with the expected power value of the load unit.

2. The method according to claim 1, characterized in that The multiple power chips include: a first power chip, and a second power chip other than the first power chip; the first power chip is the power chip corresponding to the first load unit; the operating power value of each of the multiple power chips includes: a first operating power value of the first power chip, and a second operating power value of each of the second power chips; If, among the plurality of load units, there is a first load unit whose expected power value is greater than or equal to the upper power limit value, obtaining the operating power value of each of the plurality of power chips includes: Obtaining the first operating power value, and if the first operating power value is less than the upper power limit of the first power chip, calculating a first difference between the upper power limit of the first power chip and the first operating power value; When the first difference is greater than a preset difference, a trigger signal is received; the trigger signal is a signal sent by the first power chip through the system power management interface; In response to the trigger signal, the second operating power value is acquired; the second operating power value is sent by the second power chip through the system power management interface.

3. The method according to claim 2, characterized in that The trigger signal is a high-level signal or a binary signal; the binary signal is a signal generated by converting the first operating power value into a binary number.

4. The method according to claim 1, wherein The multiple load units further include: a second load unit other than the first load unit; the multiple power supply chips include: the first power supply chip corresponding to the first load unit, and the second power supply chip corresponding to the second load unit; the operating power value includes: the operating power value corresponding to each of the second power supply chips; Updating the power upper limit value of each power chip according to the operating power values ​​of all the power chips, the expected power values ​​of all the first load units, and the total power upper limit value of the system on chip includes: determining the expected power value of the first load unit as the updated power upper limit value of the first power chip; wherein the updated power upper limit value of the first power chip is greater than the original power upper limit value of the first power chip; Based on the updated power upper limit values ​​of all the first power supply chips, the corresponding working power values ​​of each of the second power supply chips, and the total power upper limit value of the on-chip system, the updated power upper limit values ​​are determined for at least some of the second power supply chips; the updated power upper limit values ​​of at least some of the second power supply chips are less than their corresponding original power upper limit values.

5. The method according to claim 4, characterized in that The step of determining the updated power upper limit value for at least some of the second power supply chips based on the updated power upper limit values ​​of all the first power supply chips, the operating power values ​​corresponding to the respective second power supply chips, and the total power upper limit value of the system on chip includes: When the operating power value corresponding to the second power chip is less than a preset power threshold, determining the second power chip as a target power chip; Obtaining the original power upper limit value corresponding to each of the second power chips, and calculating a second difference between the total power upper limit value and the original power upper limit value corresponding to a third power chip; the third power chip is a power chip among the second power chips excluding the target power chip; Calculating a third difference between the second difference and the updated power upper limit value of the first power chip, and determining the third difference as the allocable power value; The updated power upper limit value is allocated to the target power chip according to the allocable power value.

6. The method according to claim 5, characterized in that Allocating the corresponding updated power upper limit value to the target power chip using the allocable power value includes: Calculating a ratio of the allocable power value to the number of target power chips to obtain an average value; The average value is determined as the updated power upper limit value corresponding to the target power chip.

7. The method according to claim 4, characterized in that The step of determining the updated power upper limit value for at least some of the second power supply chips based on the updated power upper limit values ​​of all the first power supply chips, the operating power values ​​corresponding to the respective second power supply chips, and the total power upper limit value of the system on chip includes: Calculating a fourth difference between the total power upper limit value and the updated power upper limits of all the first power chips; According to the working power value corresponding to each of the second power supply chips and the fourth difference, the updated power upper limit value corresponding to each of the second power supply chips is determined; the updated power upper limit value corresponding to the second power supply chip is less than the original power upper limit value corresponding to each of them.

8. The method according to claim 1, characterized in that After updating the power upper limit value of each power chip according to the operating power values ​​of all the power chips, the expected power values ​​of all the first load units, and the total power upper limit value of the system on chip, the method further includes: When the expected power value of the first load unit is greater than or equal to the updated power upper limit value of the first power chip, the step of obtaining the operating power value of each of the multiple power chips is performed; the first power chip is the power chip corresponding to the first load unit; When the expected power value of the first load unit is less than the updated upper power limit of the first power chip, the power chips are controlled to operate according to their respective updated upper power limits.

9. The method according to claim 1, characterized in that The method further comprises: Calculating a total power and counting the number of times the total power is greater than the upper limit of the total power of the system on chip; the total power is the sum of the operating power values ​​of all the power chips; When the number of times exceeds the preset number, an early warning is issued.

10. A power supply control circuit, characterized in that: The circuit comprises: A battery and a system on chip; the system on chip includes: a plurality of power chips and a plurality of load units; the load units correspond to the power chips one by one; the battery is connected to the system on chip; The on-chip system is used to obtain the expected power value of each of the load units; the expected power value is the power value required for the normal operation of the load unit; among the multiple load units, if there is a first load unit whose expected power value is greater than or equal to the power upper limit value, then the working power value of each of the multiple power chips is obtained; the power upper limit value is used to characterize the power upper limit of the power chip corresponding to the load unit; the working power value is the power value of the power chip when it is actually working; according to the working power values ​​of all the power chips, the expected power values ​​of all the first load units and the total power upper limit value of the on-chip system, the power upper limit value of each of the power chips is updated; the updated power upper limit value is used for subsequent comparison with the expected power value of the load unit.

11. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the power supply control method according to any one of claims 1 to 9 are implemented.

12. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by the processor, the steps of the power supply control method according to any one of claims 1 to 9 are implemented.

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