Method and device for updating host-flash memory comparison table, and storage medium

Abstract

The invention relates to a method for updating a host-flash memory comparison table, a computer readable storage medium and a device. The method is executed by a processing unit and comprises the following steps of: configuring a flash-host comparison temporary storage area in a random access memory to store a flash-host comparison table corresponding to a current block; setting the refresh number according to the information whether the useful space in the flash memory module is sufficient or the information whether the garbage collection program is executed during the period of writing the mission data into the flash memory module; and after the user data is written into the physical address of the current block corresponding to the check point, updating mapping information in a plurality of host-flash memory contrast sub-tables according to the recorded mapping information of the refresh number in the flash memory-host contrast temporary storage area, and writing the updated host-flash memory contrast sub-table into a specified physical address in the flash memory module.

Description

Technical Field

[0001] The present invention relates to a storage device, and in particular to a method for updating a host-flash memory comparison table running in a flash memory device, a computer-readable storage medium and a device. Background Art

[0002] Flash memory is generally categorized as NOR flash and NAND flash. NOR flash is a random access device. The central processing unit (CPU) can provide any address to access the NOR flash on the address pins and promptly retrieve the data stored at that address from the NOR flash's data pins. In contrast, NAND flash is not random access, but serial access. Unlike NOR flash, NAND flash cannot access any random address. Instead, the CPU must write serial byte values ​​to the NAND flash to define the type of command requested (e.g., read, write, erase, etc.) and the address used for that command. The address can point to a page (the smallest data block in flash memory for write operations) or a block (the smallest data block in flash memory for erase operations). Efficient execution of host write commands has always been a key issue for NAND flash devices. Summary of the Invention

[0003] In view of this, how to alleviate or eliminate the defects in the above-mentioned related fields is indeed a problem to be solved.

[0004] The present invention relates to a method for updating a host-flash memory comparison table, which is executed by a processing unit and comprises: configuring a flash memory-host comparison temporary storage area in a random access memory to store the flash memory-host comparison table corresponding to a current block; setting a refresh number based on information about whether there is sufficient useful space in the flash memory module, or based on information about whether a garbage collection program is also to be executed during the writing of messenger data to the flash memory module; and after the user data is written to the physical address of the current block corresponding to a checkpoint, updating mapping information in a plurality of host-flash memory comparison sub-tables based on mapping information recorded in the flash memory-host comparison temporary storage area for the refresh number, and writing the updated host-flash memory comparison sub-tables into a designated physical address in the flash memory module.

[0005] The present invention also relates to a computer-readable storage medium for storing program code that can be loaded and executed by a processing unit, and wherein the program code implements the above-mentioned method for updating the host-flash memory comparison table when executed by the processing unit.

[0006] The present invention also relates to a device for updating a host-flash memory comparison table, comprising: a random access memory; a flash memory interface coupled to a flash memory module; and a processing unit coupled to the random access memory and the flash memory interface. The processing unit is configured to configure a flash memory-host comparison temporary storage area to store the flash memory-host comparison table corresponding to the current block. The processing unit is configured to set a refresh number based on information about whether there is sufficient usable space in the flash memory module or whether a garbage collection process is also performed during the writing of messenger data to the flash memory module. After the user data is written to the physical address of the current block corresponding to the checkpoint, the processing unit is configured to update mapping information in a plurality of host-flash memory comparison sub-tables based on mapping information recorded in the flash memory-host comparison temporary storage area according to the refresh number, and drive the flash memory interface to write the updated host-flash memory comparison sub-table to a designated physical address in the flash memory module.

[0007] The flash memory-host mapping table includes a plurality of records for storing information on which logical address the user data stored at each physical address in the current block is mapped to according to the order of the physical addresses.

[0008] One of the advantages of the above embodiment is that by controlling the refresh number of records in the flash memory-host mapping table as described above, the execution frequency of the flash memory-host mapping table refresh procedure can be adjusted according to the actual storage status of the flash memory module.

[0009] Other advantages of the present invention will be explained in more detail with reference to the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application.

[0011] Figure 1 FIG. 4 is a system architecture diagram of an electronic device according to an embodiment of the present invention.

[0012] Figure 2 FIG. 1 is a schematic diagram of a flash memory module according to an embodiment of the present invention.

[0013] Figure 3 FIG. 4 is a partial hardware architecture diagram of a NAND flash memory unit according to an embodiment of the present invention.

[0014] Figure 4 FIG. 4 is a schematic diagram illustrating the association between a high-level lookup table and a host-flash memory lookup sub-table according to an embodiment of the present invention.

[0015] Figure 5 FIG. 1 is a schematic diagram illustrating the association between a host-flash memory reference subtable and a physical page according to an embodiment of the present invention.

[0016] Figure 6 Schematic diagram of refreshing the host-flash memory mapping sub-table based on mapping information in the flash memory-host mapping table according to an embodiment of the present invention.

[0017] Figure 7 Flowchart of a method for updating a host-flash memory reference table according to an embodiment of the present invention.

[0018] Figures 8A to 8H Schematic diagram of updating the host-flash memory comparison sub-table based on mapping information of the flash memory-host comparison temporary area according to an embodiment of the present invention.

[0019] Description of reference numerals:

[0020] 10 Electronic devices

[0021] 110 Host side

[0022] 130 Flash Memory Controller

[0023] 131 Host Interface

[0024] 132 bus architecture

[0025] 134 processing units

[0026] 136 Random Access Memory

[0027] 139 Flash memory interface

[0028] 150 Flash Memory Module

[0029] 151 Interface

[0030] 153#0~153#15 NAND flash memory unit

[0031] CH#0~CH#3 channels

[0032] CE#0~CE#3 start signal

[0033] 300 storage blocks

[0034] 310 floating-gate transistor

[0035] BL1~BL3 bit lines

[0036] WL0~WL5 word lines

[0037] 410 Advanced Comparison Table

[0038] 430#0~430#15 Host-Flash Comparison Subtable

[0039] 500#1 Super Block

[0040] 510 physical pages

[0041] 530 Physical address information

[0042] 530-0 Superblock number

[0043] 530-1 Physical page number and segment number

[0044] Part 610 Flash-Host Comparison Table

[0045] S710~S780 Method Step 810 Current Block

[0046] Physical addresses of checkpoints 812, 814, and 816

[0047] 830 Flash Memory - Host Comparison Buffer

[0048] 832, 834, 836 refresh addresses

[0049] A-1, B-1, B-2, B-3, C-1, D-1, D-2, E-1, F-1, G-1, H-1, H-2

[0050] Label DETAILED DESCRIPTION

[0051] The embodiments of the present invention will be described below with reference to the accompanying drawings. In these drawings, the same reference numerals represent the same or similar components or method flows.

[0052] The following provides various aspects and embodiments of the present invention. Some embodiments can be implemented independently, while others can be combined and implemented as readily apparent to one skilled in the art. The following description is for illustrative purposes only, with specific details provided to provide a complete understanding of the various aspects of the present invention. However, it will be apparent that these embodiments do not necessarily require such exhaustive implementation. The drawings and description are not intended to limit the present invention.

[0053] The following descriptions are merely examples of various aspects and are not intended to limit the scope, applicability, or configuration of this specification. Instead, the various examples are intended to provide a description that one of ordinary skill in the art can implement. It should be understood that the functions and arrangements of the components herein may be modified without violating the scope and spirit of the claims.

[0054] refer to Figure 1. The electronic device 10 includes a host side (Host Side) 110, a flash memory controller 130 and a flash memory module 150, and the flash memory controller 130 and the flash memory module 150 can be collectively referred to as the device side (Device Side). The electronic device 10 can be implemented in electronic products such as peripheral storage devices, personal computers, laptop computers (Laptop PCs), tablet computers, mobile phones, digital cameras, digital video cameras, smart TVs, smart refrigerators, and automotive electronic systems. The host side 110 and the host interface (Host Interface) 131 of the flash memory controller 130 can communicate with each other using communication protocols such as Universal Serial Bus (USB), Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCI-E), Universal Flash Storage (UFS), and Embedded Multi-Media Card (eMMC). The flash memory interface 139 of the flash memory controller 130 and the flash memory module 150 can communicate with each other using a double data rate (DDR) communication protocol, such as the OpenNAND Flash Interface (ONFI), a double data rate switch (DDR Toggle), or other communication protocols. The flash memory controller 130 includes a processing unit 134, which can be implemented in a variety of ways, such as using general-purpose hardware (e.g., a single processor, a microcontroller unit, a multi-processor with parallel processing capabilities, a graphics processor, or other processor with computing capabilities), and provides the functions described below when executing software and / or firmware instructions. The processing unit 134 receives host commands, such as write commands and read commands, through the host interface 131, and schedules and executes these commands.Flash controller 130 also includes random access memory (RAM) 136, which can be implemented as dynamic random access memory (DRAM), static random access memory (SRAM), or a combination of the two. This RAM 136 is used to configure space as a data buffer for storing user data (also referred to as host data) read from host 110 and to be written to flash memory module 150, as well as user data read from flash memory module 150 and to be output to host 110. RAM 136 can also store data required during execution, such as variables, data tables, data structures, host-to-flash (H2FTable) tables, and flash-to-host (F2H) tables. The flash memory interface 139 includes a NAND Flash Controller (NFC) that provides functions required for accessing the flash memory module 150 , such as a command serializer (CSerializer) and a low-density parity check (LDPC).

[0055] Flash memory controller 130 may be configured with a bus architecture 132 for coupling components to each other for transmitting data, addresses, and control signals. These components include, but are not limited to, host interface 131, processing unit 134, RAM 136, and flash memory interface 139. Direct memory access (DMA) circuits within these components can transfer data between components via bus architecture 132 based on instructions or control signals. For example, a DMA circuit within host interface 131 or flash memory interface 139 can move data from a specific data buffer therein to a specific address within RAM 136, or vice versa.

[0056] Flash memory module 150 provides a large amount of storage space, typically hundreds of gigabytes (GB) or even multiple terabytes (TB), for storing large amounts of user data, such as high-resolution images and videos. Flash memory module 150 includes control circuitry and a memory array. The memory cells in the memory array can be configured as single-level cells (SLCs), multiple-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs), or any combination thereof. Processing unit 134 writes user data to a specified address (destination address) in flash memory module 150 and reads user data from a specified address (source address) in flash memory module 150 via flash memory interface 139. Flash memory interface 139 coordinates the transfer of data and commands between flash memory controller 130 and flash memory module 150 using multiple electronic signals, including data lines, clock signals, and control signals. The data lines can be used to transmit commands, addresses, read and write data; the control signal lines can be used to transmit control signals such as chip enable (CE), address latch enable (ALE), command latch enable (CLE), and write enable (WE).

[0057] refer to Figure 2 The interface 151 in the flash memory module 150 may include four input / output channels (I / O channels, hereinafter referred to as channels) CH#0 to CH#3, each of which connects to four NAND flash memory cells. For example, channel CH#0 connects to NAND flash memory cells 153#0, 153#4, 153#8, and 153#12. Each NAND flash memory cell may be packaged as an independent chip (die). The flash memory interface 139 may activate NAND flash memory cells 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11, or 153#12 to 153#15 by issuing one of the activation signals CE#0 to CE#3 via the interface 151, and then read user data from or write user data to the activated NAND flash memory cells in parallel.

[0058] refer to Figure 3The local hardware architecture of a NAND flash memory cell. Each NAND flash memory cell may include a memory block 300, which includes multiple memory cells, such as floating gate transistors 310 or other charge trap devices. The structure of the memory block 300 includes multiple bit lines and multiple word lines. For simplicity, Figure 3 Only bit lines BL1 to BL3 and word lines WL0 to WL5 are shown. For example, floating gate transistors on word lines WL0 to WL2 and WL3 to WL5 form different pages for storing data.

[0059] Each NAND flash memory cell can contain multiple data planes, and each data plane can contain multiple physical blocks. In order to improve the efficiency of data writing and reading, the physical pages in multiple data planes of multiple NAND flash memory cells can be organized into a super page (SP). For example, Figure 2In the example setting shown, each flash memory cell contains four data planes, and each data plane contains a 4-kilobyte (KB) physical page. A super page can store 256KB of user data (= 4 channels × 4 CEs × 4 data planes × 4KB). Multiple super pages can form a super block (SB). In some embodiments, any super block can be configured as a single-level cell super block (SLC SB), and each super page in the SLC SB is an SLCSP. In other embodiments, any super block can be configured as a multi-level cell super block (MLCSB), and each super page in the MLC SB can be a most significant bit super page (MSB SP) or a least significant bit super page (LSB SP). In other embodiments, any super-block can be configured as a triple-level cell super-block (TLC SB), and each super-page in the TLC SB can be an MSB SP, a center significant bit super-page (CSB SP), or an LSB SP. In other embodiments, any super-block can be configured as a quad-level cell super-block (QLC SB), and each super-page in the QLC SB can be a top significant bit super-page (TSB Page), an MSB SP, a CSB SP, or an LSB SP.

[0060] In some embodiments, a logical block address (LBA) managed by the host 110 can represent 512 bytes (bytes, B) of user data, and each physical page can be further divided into eight 512B sections. The LBA number can be referred to as the logical address managed by the host 110. Superblocks, physical pages, and sections can be identified using super-block numbers, physical page numbers, and section numbers, respectively. The combination of these numbers can be referred to as the physical address of the flash memory module 150. In other embodiments, a host page number (Host Page Number) managed by the host 110 can represent 4KB of user data, and each physical page does not need to be further divided into sections. The host page number can be referred to as the logical address managed by the host 110. Superblocks and physical pages can be identified using super-block numbers and physical page numbers, respectively. The combination of these numbers can be referred to as the physical address of the flash memory module 150.

[0061] Each superblock can be classified as a data block or a current block based on its function. The processing unit 134 can select an empty superblock as the current block to prepare for writing user data received from the host 110. The processing unit 134 can maintain an F2H table for each current block in the RAM 136. The table contains multiple records, which store information about which logical address the user data at each physical address in the current block is associated with (or mapped to) in order of physical addresses (e.g., page numbers and sector numbers). Logical addresses can be represented using LBA numbers, main page numbers, or other methods and are managed by the host 110. After all physical pages in a current block are filled with user data, or after the remaining pages in a current block are filled with dummy values, the processing unit 134 can drive the flash memory interface 139 to write the corresponding F2H table in the RAM 136 to the data portion of the specified physical page of the current block. For example, a current block can be divided into multiple banks, and the record in the F2H table corresponding to a bank of the current block can be written to the last physical page in that bank. When all records of the corresponding F2H table have been written into the flash memory module 150, the current block is changed to a data block, and the user data stored in the data block will not be changed. Then, the processing unit 134 can select another empty super block as a new current block.

[0062] In addition to writing the F2H table to the specified physical page in the current block, the processing unit 134 also needs to update the H2F table based on the content of the F2H table of the current block, so that when executing a host read command in the future, it can quickly find out from the H2F table which physical address the user data associated with a specific logical address is actually stored. The H2F table contains multiple records, which store information about which logical address the user data of each logical address is actually stored in the order of the logical addresses. However, since the RAM 136 cannot provide enough space to store the entire H2F table for the processing unit 134 to quickly find it during future data read operations, the H2F table can be divided into multiple H2F sub-tables and stored in the flash memory module 150, so that the corresponding H2F sub-table can be read from the flash memory module 150 to the RAM 136 during future data read operations. Reference Figure 4 , the entire H2F table can be divided into H2F sub-tables 430#0 to 430#15. The processing unit 134 also maintains a high-order comparison table 410, which includes multiple records and stores the physical address information of the H2F sub-table associated with each logical address segment in the order of the logical address. For example, the H2F sub-table 430#0 associated with the 0th to 65535th LBA is stored in the 0th physical page in a specific super block (the letter "Z" can represent the number of the super block), the H2F sub-table 430#1 associated with the 65536th to 131071th LBA is stored in the 1st physical page in the specific super block, and so on. Although Figure 4 The 16 H2F sub-tables are included, but those skilled in the art may set more or fewer H2F sub-tables according to the capacity of the flash memory module 150, and the present invention is not limited thereto.

[0063] The space required for each H2F subtable can be 16KB, 32KB, 64KB, 128KB, etc. Figure 5 . For example, the H2F subtable 430#0 stores the physical address information mapped to each logical address in the order of multiple logical addresses in a logical address range. The logical address can be represented by an LBA number, and each LBA number corresponds to a physical storage space of a fixed size, such as 512B. Those skilled in the art can also use the main page number to represent the logical address, and the present invention is not limited to this. For example, the H2F subtable 430#0 stores the physical address information from LBA#0 to LBA#65535 in sequence. The physical address information 530 can be represented by four bytes: the first two bytes 530-0 record the super block number; the last two bytes 530-1 record the physical page number and the segment number. For example, the physical address information 530 corresponding to LBA#2 can point to the segment in the physical page 510 in the super block 500#1 (as shown by the square filled with diagonal lines). Byte 530-0 records the number of super block 500#1, and byte 530-1 records the number of physical page 510 and the number of the designated sector.

[0064] While the flash memory controller 130 executes a host write command to write user data to the flash memory module 150 via the flash memory interface 139, the flash memory controller 130 also needs to periodically execute an H2F table refresh procedure to read necessary H2F sub-tables from the flash memory module 150 according to the mapping information of the F2H table, update the mapping information of these H2F sub-tables, and write the updated results to the flash memory module 150. This is to avoid the situation where, in the event of a sudden power off (SPO), most of the H2F sub-tables are not stored in the non-volatile flash memory module 150, and the user data already written to the flash memory module 150 needs to spend a lot of computing resources in the sudden power off recovery (SPOR) procedure to rebuild the H2F sub-tables. For example, referring to Figure 6 Schematic diagram of refreshing the H2F sub-table based on the mapping information in the F2H table. Because RAM 136 is a scarce resource, RAM 136 can only allocate a fixed amount of space, less than one superblock, to store a portion of F2H table 610. F2H table 610 in RAM 136 stores the following information: physical addresses P0 through P15 of flash memory module 150 store user data at logical addresses LBA#1024 through LBA#1039, respectively; physical addresses P16 through P23 of flash memory module 150 store user data at logical addresses LBA#65560 through LBA#65567, respectively; and physical addresses P24 through P31 of flash memory module 150 store user data at logical addresses LBA#133120 through LBA#133127, respectively. In the refresh procedure of the H2F table, the processing unit 134 updates the mapping information associated with the logical addresses LBA#1024 to LBA#1039 in the H2F sub-table 430#0 according to the mapping information associated with the physical addresses P0 to P15 in the F2H table 610; updates the mapping information associated with the logical addresses LBA#65560 to LBA#65567 in the H2F sub-table 430#1 according to the mapping information associated with the physical addresses P16 to P23 in the F2H table 610; updates the mapping information associated with the logical addresses LBA#133120 to LBA#133127 in the H2F sub-table 430#2 according to the mapping information associated with the physical addresses P24 to P31 in the F2H table 610; and writes the updated H2F sub-tables 430#0, 430#1 and 430#2 to the specified physical address in the flash memory module 150 through the flash memory interface 139.

[0065] The H2F table refresh procedure described above consumes computing resources of the processing unit 134 and RAM 136, as well as the bandwidth of the flash memory interface 139. If the H2F table refresh procedure is executed too frequently, the efficiency of executing host write commands will be reduced. If the H2F table refresh procedure is executed too leniently, if an SPO occurs, more computing resources may be expended in future SPOR procedures to rebuild the H2F sub-table. The processing unit 134 can control the number of F2H table record refreshes during the H2F table refresh procedure to influence the execution cycle of the H2F table refresh procedure. However, in some embodiments, the number of F2H table record refreshes during the H2F table refresh procedure is fixed and cannot be adjusted based on the actual storage conditions of the flash memory module 150.

[0066] RAM 136 is allocated a fixed space (which may be referred to as an F2H temporary buffer) to store multiple records in the F2H table. In some embodiments, the allocated space is sufficient to store all records in the entire F2H table. In other embodiments, the allocated space is insufficient to store all records in the entire F2H table, for example, only one-third, one-quarter, or one-fifth of the records in the F2H table may be stored. To respond to the actual storage status of flash memory module 150, embodiments of the present invention provide an adjustment mechanism for controlling the refresh count in the H2F table refresh process based on information about whether there is sufficient available space in flash memory module 150 or whether a garbage collection (GC) process is also performed while writing user data to flash memory module 150. This mechanism is used to update the associated H2F sub-table based on mapping information of records corresponding to the refresh count in the F2H table. If the available space in the flash memory module 150 is insufficient (for example, fewer than 30 empty super blocks remain in the flash memory module 150), or if a GC process needs to be performed while writing user data, the refresh number is set to the number of records in the F2H table corresponding to n super pages, where n can be set to any positive integer between 2 and 4. For example, if the current block is an SLC super block, n can be set to 2, 3, or 4. If the current block is an MLC super block, n can be set to 2 or 4. If the current block is a TLC super block, n can be set to 3. If the current block is a QLC super block, n can be set to 4. If the available space in the flash memory module 150 is sufficient (for example, greater than or equal to 30 empty super blocks remain in the flash memory module 150), or if a GC process does not need to be performed while writing user data, the refresh number is set to the number of records in the F2H table corresponding to m multiplied by n super pages, where m can be set to any positive integer between 32 and 256. It should be noted that the refresh count recorded in the F2H table indirectly affects the execution time of the next iteration of the H2F table refresh procedure. After the user data is written to the physical address of the current block corresponding to the checkpoint, the mapping information in the multiple H2F lookup sub-tables is updated based on the mapping information recorded in the F2H temporary area, and the updated H2F lookup sub-table is written to the designated physical address in the flash memory module 150 via the flash memory interface 139.

[0067] When the processing unit 134 loads and executes the program code of the Firmware Translation Layer (FTL), it implements the following Figure 7 The update method of the H2F table shown includes a repeated execution loop, which is detailed as follows:

[0068] Step S710: Write the user data transmitted from the host end 110 starting from the first empty page in the current block through the flash memory interface 139, and store the mapping information of the write result in the specified part of the RAM 136 in sequence until the specified part of the RAM 136 is full. For example, a super page can store user data of 512 LBAs, and a fixed space of 256KB is configured in the RAM 136 to temporarily store the F2H table (which can be called the F2H temporary storage area). If each record in the F2H table uses 4B to record the mapping information (that is, the LBA number mapped to the specified physical address), the space of the F2H temporary storage area can store 65536 records in the F2H table. After the processing unit 134 writes the user data of 65536 LBAs to the flash memory module 150 through the flash memory interface 139, the F2H temporary storage area in the RAM 136 will be filled with the mapping information. Figure 8A As indicated by the reference number A-1 in FIG, when the super block 810 has written user data from the first physical address to the physical address 812, the F2H temporary storage area 830 has been filled with mapping information for 65,536 records. The areas of the super block 810 filled with dots represent areas where user data has been written, and the areas of the super block 810 that are blank represent areas where user data has not yet been written. The F2H temporary storage area 830 has been filled with slashes, indicating that it has been filled with mapping information. Since the F2H temporary storage area 830 in the RAM 136 is already full, it is necessary to refresh the mapping information of a portion of the records in the F2H temporary storage area 830 to the associated H2F sub-table in subsequent steps, and release the space of these refreshed records so that subsequent records in the F2H table can be stored in the released space.

[0069] Step S720: Set the refresh address in RAM 136 to the starting address of the F2H temporary area, calculate the refresh number, and update the physical address in the current block corresponding to the next checkpoint. For example, if the useful space in the flash memory module 150 is insufficient, or when the GC program needs to be executed during the writing of user data, the refresh number is set to the number of records in the F2H table corresponding to n super pages, and n can be set to any integer from 2 to 4. If the useful space in the flash memory module 150 is sufficient, or when the GC program does not need to be executed during the writing of user data, the refresh number is set to the number of records in the F2H table corresponding to m multiplied by n super pages, and m can be set to any integer from 32 to 128. The processing unit 134 can calculate the physical address of the next checkpoint using the following formula:

[0070] Addr CHK =Addr CHK +Addr(dChunk)

[0071] Addr on the left side of the equal sign CHK Represents the physical address in the current block corresponding to the next checkpoint, the Addr on the right side of the equal sign CHK represents the physical address in the current block corresponding to the last record in the F2H temporary storage area 830, dChunk represents the refresh number calculated in this step, and Addr(dChunk) represents the delta physical address in the current block corresponding to the refresh number in the F2H table. It should be noted here that the calculation result is the physical address corresponding to the physical setting of the super page, for example, including information such as a specific super block number, a specific physical page number, and a specific segment number. Figure 8B In the example shown, label B-1 indicates that the refresh address is set to the start address 832 of the F2H temporary area 830, label B-2 indicates the calculated refresh number dChunk, and label B-3 indicates the calculated physical address 814.

[0072] Step S730: Update the associated H2F sub-table according to the mapping information of the record of the refresh number starting from the refresh address in RAM 136. The part of the record that has been refreshed stored in RAM 136 can be called the refresh part. For an example of updating the H2F sub-table, please refer to Figure 6 Then, the updated H2F sub-table is written to the designated physical address in the flash memory module 150 through the flash memory interface 139. Figure 8C In the example shown, reference numeral C-1 indicates a refresh portion in the F2H temporary storage area 830 .

[0073] Step S740: Set the refresh address in RAM 136 to the next address of the last address of the refresh part, and calculate the refresh number. For the technical details of the calculation of the refresh number, please refer to the description of step S720. Figure 8D In the example shown, reference numeral D-1 indicates that the refresh address is set to the next address 834 after the last address of the refresh part, and reference numeral D-2 indicates the calculated refresh number dChunk.

[0074] Next, the processing unit 134 repeatedly executes a loop formed by steps S750 to S780 to refresh the H2F table multiple times.

[0075] Step S750: Write the user data sent by the host 110 starting from the next empty page in the current block through the flash memory interface 139, and store the mapping information of the write result in the F2H temporary area of ​​the RAM 136 in sequence until the physical address of the checkpoint is reached. Figure 8EIn the example of , in the first iteration, as indicated by reference numeral E-1, the processing unit 134 starts writing user data from the next physical address of the physical address 812 of the super block 810 until the checkpoint at the physical address 814. When entering the checkpoint, the mapping information of the write result has been filled as shown in FIG. Figure 8C The refresh portion of the F2H temporary storage area 830 is shown in FIG. 8 (ie, the portion from address 832 to the previous address 834).

[0076] Step S760: Update the associated H2F sub-table according to the mapping information of the refresh number starting from the refresh address in the RAM 136, and write the updated H2F sub-table to the specified physical address in the flash memory module 150 through the flash memory interface 139. For an example of updating the H2F sub-table, refer to Figure 6 Reference Figure 8F In the example shown, in the first iteration, reference numeral F-1 indicates a refresh location in the F2H temporary buffer 830 .

[0077] Step S770: Update the physical address of the checkpoint. The processing unit 134 may calculate the physical address of the next checkpoint using the following formula:

[0078] Addr CHK =Addr CHK +Addr(dChunk)

[0079] Addr on the left side of the equal sign CHK Represents the physical address in the current block corresponding to the checkpoint in the next iteration. CHK represents the physical address in the current block corresponding to the checkpoint in the current iteration, dChunk represents the refresh number used in step S760 (which can be the refresh number calculated in step S740 or step S780 of the previous iteration), and Addr(dChunk) represents the incremental physical address in the current block corresponding to the record of the refresh number in the F2H table.

[0080] refer to Figure 8G In the example shown, in the first iteration, label G-1 indicates the calculated physical address 816. In some embodiments, if the calculated physical address of the checkpoint exceeds the last physical address of the current block, the physical address of the checkpoint can be set to the last physical address of the current block.

[0081] Step S780: Set the refresh address in RAM 136 to the next address of the last address of the refresh part, and calculate the refresh number. For the technical details of the calculation of the refresh number, please refer to the description of step S720. Figure 8HIn the example shown, in the first iteration, reference numeral H-1 indicates that the refresh address is set to the next address 836 of the last address of the refresh part, and reference numeral H-2 indicates the calculated refresh number dChunk.

[0082] Although the present invention is illustrated and described herein with reference to specific embodiments, the present invention is not intended to be limited to the details shown. On the contrary, various modifications may be made to the details within the scope and equivalents of the claims without departing from the present invention. It should be understood that the above description is an illustration of the present invention and should not be construed as limiting the present invention. Various modifications, applications, and / or combinations of the embodiments may be envisioned by those of ordinary skill in the art without departing from the scope of the present invention as defined by the claims.

[0083] Those skilled in the art will readily appreciate that the present invention discussed above may be implemented using different configurations of hardware components than those disclosed. Thus, while the present invention has been described based on these preferred embodiments, certain modifications, variations, and alternative configurations will be apparent to those skilled in the art and are within the scope of the present invention.

[0084] It must be understood that the words "comprise", "include", etc. used in this specification are used to indicate the existence of specific technical features, values, method steps, operation processes, parts and / or components, but do not exclude the addition of more technical features, values, method steps, operation processes, components, parts, or any combination of the above.

[0085] The terms "first", "second", "third", etc. used in the present invention are used to modify the components in the claims and are not used to indicate a priority order or a precedence relationship between them, or that one component precedes another, or the temporal order of executing method steps. They are only used to distinguish components with the same name.

[0086] It should be understood that when a component is described as being "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, and intervening components may be present. Conversely, when a component is described as being "directly connected" or "directly coupled" to another component, there are no intervening components. Other words used to describe the relationship between components should be interpreted in a similar manner, for example, "between" versus "directly between," or "adjacent" versus "directly adjacent," etc.

[0087] The word "device" or "module" is not limited to one or a specific number of physical objects (e.g., a smart mobile phone, a controller, a processing system, etc.). As used herein, a device can be any electronic device having one or more components that can implement at least some of the functions of the present invention in this disclosure. Although the description and examples use the word "device" or "module" to describe various aspects of the present disclosure, the word "device" or "module" is not limited to a specific configuration, type, or number of objects. In addition, the word "system" or "module" is not limited to multiple components or a specific direction. For example, a system can be implemented on one or more printed circuit boards or other substrates and can have movable or static components. Although the description and examples use the word "system" to describe various aspects of the present invention in this disclosure, the word "system" is not limited to a specific configuration, type, or number of objects.

[0088] Specific details are provided in the above description to assist in a thorough understanding of various inventive aspects. However, it will be understood by those skilled in the art that these aspects may be practiced in the absence of these specific details. To enable clarity of explanation, in some instances, the present technology may be presented as comprising separate functional blocks comprising devices, device components, steps or subroutines embodied in methods of software, or a combination of hardware and software. Other additional components other than those shown in the figures and / or described herein may also be used. For example, circuits, systems, networks, processes, and other components may be displayed as components in block diagram form to avoid obscuring these aspects with unnecessary details. In other instances, to avoid obscuring these aspects with unnecessary details, known circuits, processes, algorithms, structures, and techniques may be displayed without unnecessary details.

[0089] Some aspects may be described herein as processes or methods, which may be shown as flow charts, data flow diagrams, structure diagrams, or block diagrams. Although a flow chart may describe operations as sequential processes, multiple operations may be performed in parallel or simultaneously. Furthermore, the order of the operations may be rearranged. A process terminates when the operations are completed, but there may be additional steps not included in the diagram. A process may correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination may correspond to the function returning to the calling function or the main function.

[0090] All or part of the steps in the method described in the present invention can be implemented by a computer program, such as a firmware translation layer (FTL) in the device end, a driver for specific hardware, etc. In addition, it can also be implemented in other types of programs as shown above. Those skilled in the art can write the method of the embodiment of the present invention into program code, which will not be described again for the sake of simplicity. The computer program implemented according to the method of the embodiment of the present invention can be stored in an appropriate computer-readable storage medium, or it can be placed on a network server that can be accessed through a network (e.g., the Internet, or other appropriate media).

[0091] Computer-readable storage media include volatile and non-volatile, removable and non-removable media that implement the storage of information, such as computer-readable instructions, data structures, program modules, or other data, by any method or technology. Computer-readable storage media include but are not limited to RAM, ROM, EEPROM, flash memory or other memory, CD-ROM, DVD, Blu-ray disc or other optical storage media, magnetic cards, magnetic tape, hard disk or other magnetic storage media, or other carriers that can be used to store information required and accessed by the instruction execution system. It should be noted that the computer-readable storage medium can be paper or other suitable media for printing program code so that the program code can be obtained electronically, such as by optically scanning the paper or other media, and then, if necessary, compiled, interpreted or processed in other suitable ways, and then stored in the memory of the electronic device.

[0092] The program code may be executed by a processor, which may include one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits, field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Such a processor may be configured to perform any of the techniques described in the disclosure. A general-purpose processor may be a microprocessor; however, in an alternative embodiment, the processor may be any conventional processor, controller, microprocessor, or state machine. The processor may be implemented as a combination of multiple computing devices, such as a DSP and a microprocessor, multiple microprocessors, one or more microprocessors with a DSP core, or any other similar configuration. Accordingly, the term "processor" as used herein may represent any of the foregoing structures, any combination of the foregoing structures, or any other structure or device suitable for implementing the counting described herein.

[0093] The various illustrative logic blocks, modules, engines, circuits, and algorithmic steps described in conjunction with the inventive aspects disclosed herein may be implemented as electronic hardware, computer software, firmware, or any combination thereof. In order to clearly represent the interchangeability of hardware and software, various illustrative components, blocks, modules, engines, circuits, and steps have been generally described above in terms of their functions. Whether these functions are to be implemented in hardware or software depends on the specific application scenario and the design constraints imposed on the entire system. Those of ordinary skill in the art may implement the described functions in different ways for each specific application scenario, but such implementation decisions should not be interpreted as departing from the scope of this application.

[0094] Although Figures 1 to 3 The components described above are included in the invention, but it does not exclude the use of more additional components to achieve better technical effects without violating the spirit of the invention. Figure 7 The flowchart is executed in the specified order. However, those skilled in the art may modify the order of these steps without violating the spirit of the invention, provided that the same effect is achieved. Therefore, the present invention is not limited to the above-described order. In addition, those skilled in the art may also combine several steps into one step, or perform more steps sequentially or in parallel in addition to these steps, and the present invention should not be limited thereby.

[0095] The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Those skilled in the art may make further improvements and changes on this basis without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the content defined in the claims of this application.

Claims

1. A method for updating a host-flash memory comparison table, executed by a processing unit, characterized in that: The method for updating the host-flash memory comparison table includes: Allocating a flash memory-host comparison temporary area in the random access memory to store a flash memory-host comparison table corresponding to the current block, wherein the flash memory-host comparison table includes a plurality of records for storing information indicating, in order of first physical addresses, which logical address the user data stored at each first physical address in the current block is mapped to; setting the refresh number based on information about whether there is sufficient available space in the flash memory module or whether a garbage collection process is also to be performed during writing of the messenger data to the flash memory module; and After the user data is written to the second physical address of the current block corresponding to the checkpoint, the mapping information in multiple host-flash comparison sub-tables is updated according to the mapping information of the record of the refresh number in the flash memory-host comparison temporary area, and the updated host-flash comparison sub-table is written to the specified physical address in the flash memory module.

2. The method for updating the host-flash memory comparison table according to claim 1, wherein: The refresh number is calculated in the previous iteration, and the updating and writing of the host-flash mapping subtable is performed in the current iteration.

3. The method for updating the host-flash memory comparison table according to claim 2, wherein: Also includes: In the current iteration, a third physical address in the current block corresponding to a checkpoint in a next iteration is calculated based on the second physical address and the refresh number.

4. The method for updating the host-flash memory comparison table according to claim 3, wherein: The third physical address in the current block is calculated using the following formula: Addr CHK =Addr CHK +Addr(dChunk) Addr on the left side of the equal sign CHK Represents the third physical address in the current block corresponding to the checkpoint in the next iteration, and the Addr on the right side of the equal sign CHK represents the second physical address, dChunk represents the refresh number, and Addr(dChunk) represents the incremented physical address in the current block of the record corresponding to the refresh number in the flash-host mapping table.

5. The method for updating the host-flash memory comparison table according to claim 1, wherein: Also includes: When the available space in the flash memory module is insufficient, or when the garbage collection process is also performed during writing the user data to the flash memory module, the refresh number is set to a first value; as well as When there is sufficient available space in the flash memory module, or when the garbage collection process is not performed during writing the user data to the flash memory module, the refresh number is set to a second value, The first value and the second value are integers greater than zero, and the second value is greater than the first value.

6. The method for updating the host-flash memory comparison table according to claim 5, wherein: The first value is the number of records corresponding to n superpages in the current block, where n is any integer from 2 to 4, and the second value is the number of records corresponding to m multiplied by n superpages in the current block, where m is any integer from 32 to 128.

7. The method for updating the host-flash memory comparison table according to claim 6, wherein: When the current block is a single-layer unit super block, n is any integer from 2 to 4; when the current block is a multi-layer unit super block, n is 2 or 4; when the current block is a three-layer unit super block, n is 3; and when the current block is a four-layer unit super block, n is 4.

8. A computer-readable storage medium for storing program code that can be executed by a processing unit, characterized in that: When the program code is executed by the processing unit, the method for updating the host-flash memory reference table according to any one of claims 1 to 7 is implemented.

9. A device for updating a host-flash memory comparison table, characterized in that: include: a random access memory configured to configure a flash memory-host comparison temporary area for storing a flash memory-host comparison table corresponding to a current block, wherein the flash memory-host comparison table includes a plurality of records for storing information indicating, in order of first physical addresses, which logical address the user data stored at each first physical address in the current block is mapped to; a flash memory interface coupled to the flash memory module; and A processing unit is coupled to the random access memory and the flash memory interface, and is configured to set a refresh number based on information about whether there is sufficient useful space in the flash memory module, or based on information about whether a garbage collection program is also to be performed during the writing of the messenger data to the flash memory module; and after the user data is written to the second physical address of the current block corresponding to the checkpoint, update the mapping information in multiple host-flash memory comparison sub-tables based on the mapping information of the record of the refresh number in the flash memory-host comparison temporary area, and drive the flash memory interface to write the updated host-flash memory comparison sub-table into the specified physical address in the flash memory module.

10. The device for updating the host-flash memory comparison table according to claim 9, wherein: The refresh number is calculated in the previous iteration, and the updating and writing of the host-flash mapping subtable is performed in the current iteration.

11. The device for updating the host-flash memory comparison table according to claim 10, wherein: The processing unit is configured to calculate, in the current iteration, a third physical address in the current block corresponding to a checkpoint in a next iteration based on the second physical address and the refresh number.

12. The device for updating the host-flash memory comparison table according to claim 11, wherein: The third physical address in the current block is calculated using the following formula: Addr CHK =Addr CHK +Addr(dChunk) Addr on the left side of the equal sign CHK Represents the third physical address in the current block corresponding to the checkpoint in the next iteration, and the Addr on the right side of the equal sign CHK represents the second physical address, dChunk represents the refresh number, and Addr(dChunk) represents the incremented physical address in the current block of the record corresponding to the refresh number in the flash-host mapping table.

13. The device for updating the host-flash memory comparison table according to claim 9, wherein: The processing unit is configured to set the refresh number to a first value when the useful space in the flash memory module is insufficient, or when the garbage collection program is also executed during the writing of the user data to the flash memory module; and to set the refresh number to a second value when the useful space in the flash memory module is sufficient, or when the garbage collection program does not need to be executed during the writing of the user data to the flash memory module, wherein the first value and the second value are integers greater than zero, and the second value is greater than the first value.

14. The device for updating the host-flash memory comparison table according to claim 13, wherein: The first value is the number of records corresponding to n superpages in the current block, where n is any integer from 2 to 4, and the second value is the number of records corresponding to m multiplied by n superpages in the current block, where m is any integer from 32 to 128.

15. The device for updating the host-flash memory comparison table according to claim 14, wherein: When the current block is a single-layer unit super block, n is any integer from 2 to 4; when the current block is a multi-layer unit super block, n is 2 or 4; when the current block is a three-layer unit super block, n is 3; and when the current block is a four-layer unit super block, n is 4.

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