Instruction processing method and device, electronic equipment, storage medium and program

Abstract

The invention provides an instruction processing method and device, electronic equipment, a storage medium and a program, relates to the technical field of data processing, in particular to a chip technology, and can be applied to the field of artificial intelligence. The method is applied to an instruction fusion processing module of a target processor, and comprises the following steps: acquiring a plurality of current instructions currently cached in an operand buffer; wherein each current instruction comprises a plurality of pieces of thread data; performing fusion processing on the current instruction to obtain a fusion instruction; and transmitting the fusion instruction to a target instruction execution unit in a target processor. The embodiment of the invention can improve the utilization rate of the instruction execution unit in the processor and the execution efficiency of the instruction.

Description

Technical Field

[0001] The present disclosure relates to the field of data processing technology, specifically chip technology, and can be applied to the field of artificial intelligence. Background Art

[0002] SIMT (Single Instruction Multiple Threads) is a single-instruction, multiple-threaded execution method. Its core feature is that the same instruction is executed in parallel by multiple threads, and each thread can have different branching behaviors and execution paths, thus achieving thread-level parallel computing. In the SIMT architecture, computing tasks are broken down into multiple thread blocks, each containing multiple thread warps. The scheduler selects the active thread warps and sends instructions to the execution units. Threads within each thread warp execute the same instruction synchronously but can independently select different branch paths. This architecture is particularly well-suited for tasks that require highly parallel processing, such as graphics rendering and artificial intelligence processing tasks like deep learning. Summary of the Invention

[0003] The embodiments of the present disclosure provide an instruction processing method, apparatus, electronic device, storage medium, and program, which can improve the utilization rate of the instruction execution unit in the processor and the execution efficiency of the instructions.

[0004] In a first aspect, an embodiment of the present disclosure provides an instruction processing method, which is applied to an instruction fusion processing module of a target processor, comprising:

[0005] Obtaining a plurality of current instructions currently cached in an operand buffer; wherein each of the current instructions includes a plurality of thread data;

[0006] Performing fusion processing on the current instruction to obtain a fused instruction;

[0007] The fused instruction is issued to a target instruction execution unit in a target processor.

[0008] In a second aspect, an embodiment of the present disclosure provides an instruction processing device, configured in an instruction fusion processing module of a target processor, comprising:

[0009] A current instruction acquisition module, configured to acquire a plurality of current instructions currently cached in an operand buffer; wherein each of the current instructions includes a plurality of thread data;

[0010] An instruction fusion processing module, configured to perform fusion processing on the current instruction to obtain a fused instruction;

[0011] The fused instruction transmitting module is used to transmit the fused instruction to the target instruction execution unit in the target processor.

[0012] In a third aspect, an embodiment of the present disclosure provides an electronic device, including:

[0013] at least one processor; and

[0014] a memory communicatively connected to the at least one processor; wherein,

[0015] The processor is internally configured with an instruction fusion processing module;

[0016] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the instruction fusion processing module of the at least one processor can execute the instruction processing method provided by the embodiment of the first aspect.

[0017] In a fourth aspect, an embodiment of the present disclosure further provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute the instruction processing method provided by the embodiment of the first aspect.

[0018] In a fifth aspect, an embodiment of the present disclosure further provides a computer program product, comprising a computer program, which, when executed by a processor, implements the instruction processing method provided in the embodiment of the first aspect.

[0019] The disclosed embodiment obtains multiple current instructions currently cached in the operand buffer through the instruction fusion processing module in the target processor. Each current instruction includes multiple thread data. By fusing the current instructions to obtain a fused instruction, and then transmitting the fused instruction to the target instruction execution unit in the target processor, the frequency of instruction transmission can be reduced. The above technical solution solves the problems of insufficient resource utilization of the instruction execution unit and low instruction transmission efficiency when the existing processor transmits instructions by fusing and transmitting the instructions when facing discrete threads of instructions through the instruction execution unit, and can improve the utilization rate of the instruction execution unit in the processor and the execution efficiency of instructions.

[0020] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0022] Figure 1 is a flowchart of an instruction processing method provided by an embodiment of the present disclosure;

[0023] Figure 2is a flowchart of another instruction processing method provided by an embodiment of the present disclosure;

[0024] Figure 3 This is a flow chart of instruction fusion processing performed by a target processor through an instruction fusion module according to an embodiment of the present disclosure;

[0025] Figure 4 is a structural diagram of an instruction processing device provided by an embodiment of the present disclosure;

[0026] Figure 5 Schematic diagram of the structure of an electronic device used to implement the instruction processing method of the embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0028] The SIMT execution method achieves thread-level parallelism by organizing multiple threads into warps (v-form). In this execution method, a single instruction can carry data from multiple threads to perform the same type of data operations, and the execution of each thread of each instruction is affected by a predicate register. The predicate register acts as an active mask for each instruction, and each bit of the predicate register is used to control whether each thread in the instruction is executed. There are many types of processors that use SIMT execution, and GPGPU (General-Purpose Computing on Graphics Processing Units) is a typical example.

[0029] When a program encounters a conditional branch, the SIMT architecture faces the challenge of diverging execution paths. At this point, the SIMT architecture dynamically constructs an active mask through a predicate register system to provide fine-grained execution control for each thread within a bundle. This allows only a subset of threads to be activated each time an instruction is executed. Processors that typically use SIMT execution (hereinafter referred to as target processors), such as GPGPUs, typically have a number of instruction execution units (IEUs) corresponding to the number of threads executing the instruction. Therefore, when encountering threads where only a subset of the active mask is activated, the IEUs in the target processor are underutilized.

[0030] To solve the above problem, the number of instruction execution units in the target processor is usually reduced to make it less than the number of threads per instruction, and then each instruction is issued multiple times, thereby reducing the problem of insufficient resource utilization of the instruction execution units.

[0031] However, in the design where the number of instruction execution units in the target processor is less than the number of threads per instruction, although the problem of low resource utilization of the instruction execution units is alleviated for instructions with discrete threads, all threads are activated for each instruction, so an instruction needs to be issued multiple times. Therefore, in this case, the instruction issuance efficiency is also reduced.

[0032] In one example, Figure 1 This is a flowchart of an instruction processing method provided by an embodiment of the present disclosure. This embodiment is applicable to the case where a processor transmits a fusion instruction after fusing instructions. The method can be executed by an instruction processing device, which can be implemented by software and / or hardware and can generally be integrated into the instruction fusion processing module of the target processor in the electronic device. The electronic device equipped with the instruction fusion processing module of the target processor can be a terminal device or a server device. The embodiment of the present disclosure does not limit the specific device type of the electronic device. Accordingly, if Figure 1 As shown, the method includes the following operations:

[0033] S110. Acquire multiple current instructions currently cached in the operand buffer; wherein each current instruction includes multiple thread data.

[0034] The operand buffer may be a buffer in the target processor for buffering operands, so that the data of these operands can be quickly accessed when executing instructions. The target processor may be a processor using SIMT execution mode, such as a GPGPU. The embodiments of the present disclosure do not limit the type of target processor. The current instruction may be the instruction currently cached and stored in the operand buffer. The current instruction may be any type of instruction that the target processor can process, such as, but not limited to, arithmetic operation instructions, data transfer instructions, logical operation instructions, control transfer instructions, and input / output instructions. The embodiments of the present disclosure do not limit the instruction type of the current instruction processed by the target processor. Arithmetic operation instructions may be instructions for performing mathematical calculations such as addition, subtraction, multiplication, division, and modulo. Data transfer instructions may be instructions for transferring data or addresses between registers, storage units, or input / output ports. Logical operation instructions may be instructions for performing Boolean logic operations, mainly including AND, OR, NOT, and XOR operations. Control transfer instructions may be instructions for changing the execution flow of a program, including unconditional transfers, conditional transfers, and subroutine calls. Input and output instructions can be instructions for transmitting information between a host and a peripheral device, including instructions for inputting and outputting data, sending control commands, or reading peripheral status.

[0035] Before the target processor sends all instructions that need to be processed to the operand buffer, it first needs to decode the instruction execution unit corresponding to the instruction to determine which instruction execution unit needs to be used to execute the instruction, thereby establishing a mapping relationship between the instruction and the corresponding instruction execution unit. Optionally, the target processor can establish a mapping relationship between the instruction and the IP of the corresponding instruction execution unit (IP is used to uniquely identify the instruction execution unit). At the same time, the target processor can also mark the active thread mask of all threads in the instruction. That is, for an instruction, the target processor can establish a mapping relationship between the instruction and the IP of the corresponding instruction execution unit and the corresponding active thread mask.

[0036] In order to further improve the instruction emission efficiency of the target processor and avoid an instruction being emitted multiple times, different instructions can be fused to send multiple instructions simultaneously during a one-time instruction emission process. In order to realize the target processor's instruction fusion function, the embodiment of the present disclosure creatively configures an instruction fusion processing module in the target processor. Among them, the instruction fusion processing module is a functional module inside the target processor, which is used to perform fusion processing on the instructions cached in the operand buffer. Optionally, the instruction fusion processing module can be a hardware module, and its internal structure can be composed of a variety of logic circuits; optionally, the instruction fusion processing module can also be a software module. As long as it can have the instruction fusion function, the embodiment of the present disclosure does not limit the implementation method of the specific internal hardware structure of the instruction fusion processing module.

[0037] The target processor sends all current instructions to the operand buffer. At the same time, the operand buffer can also store the IP of the instruction execution unit corresponding to each current instruction and the corresponding active thread mask and other related information. The operand buffer is communicatively connected to the instruction fusion processing module of the target processor. When it is necessary to process the current instructions cached in the operand buffer, the multiple current instructions currently cached in the operand buffer can first be sent to the instruction fusion processing module of the target processor, so that the current instructions to be transmitted can be logically combined by the instruction fusion processing module to realize the fusion processing of different instructions. Since the target processor uses SIMT execution mode to execute instructions, each instruction in the target processor can include multiple thread data.

[0038] S120: Perform fusion processing on the current instruction to obtain a fused instruction.

[0039] Correspondingly, after the instruction fusion processing module obtains multiple current instructions currently cached in the operand buffer, it can parse each current instruction to classify each current instruction, classify the current instructions that can be fused into a category of instructions, and fuse this category of instructions to obtain fused instructions.

[0040] S130: Send the fusion instruction to a target instruction execution unit in a target processor.

[0041] The target instruction execution unit may be a functional unit in the target processor capable of executing the fused instruction. For example, the target instruction execution unit may be an arithmetic unit, register, or memory capable of executing the fused instruction. The embodiments of this disclosure do not limit the specific type of the target instruction execution unit.

[0042] After the instruction fusion processing module fuses the current instruction to generate a fused instruction, it can then transmit the fused instruction to the target instruction execution unit in the target processor for processing, based on the fused instruction's requirements for the type of instruction execution unit. Accordingly, the target instruction execution unit can process the multiple different instructions included in the fused instruction in parallel.

[0043] For example, when the current instruction is an arithmetic operation instruction, the instruction fusion processing module may fuse multiple arithmetic operation instructions that meet the fusion conditions and transmit the fused instruction to the corresponding operation unit. When the current instruction is a data transfer instruction, the instruction fusion processing module may fuse multiple data transfer instructions that meet the fusion conditions and transmit the fused instruction to the corresponding register or memory.

[0044] It can be seen that the above-mentioned instruction processing method can reduce the number of instruction execution units and the emission frequency of each instruction by utilizing the instruction fusion processing module of the target processor to fuse the instructions according to the type of instruction and active thread information and then transmit them, thereby improving the utilization rate of the instruction execution units in the processor and the execution efficiency of the instructions.

[0045] The disclosed embodiment obtains multiple current instructions currently cached in the operand buffer through the instruction fusion processing module in the target processor. Each current instruction includes multiple thread data. By fusing the current instructions to obtain a fused instruction, and then transmitting the fused instruction to the target instruction execution unit in the target processor, the frequency of instruction transmission can be reduced. The above technical solution solves the problems of insufficient resource utilization of the instruction execution unit and low instruction transmission efficiency when the existing processor transmits instructions by fusing and transmitting the instructions when facing discrete threads of instructions through the instruction execution unit, and can improve the utilization rate of the instruction execution unit in the processor and the execution efficiency of instructions.

[0046] In one example, Figure 2 This is a flowchart of another instruction processing method provided by an embodiment of the present disclosure. Based on the technical solutions of the above embodiments, the embodiment of the present disclosure has been optimized and improved, and provides multiple specific optional implementation methods for obtaining multiple current instructions currently cached in the operand buffer, determining the instruction type of the current instruction, fusing each current instruction, and transmitting the fused instruction to the target instruction execution unit in the target processor.

[0047] like Figure 2 An instruction processing method shown includes:

[0048] S210: Acquire multiple current instructions currently cached in the operand buffer.

[0049] In an optional embodiment of the present disclosure, obtaining multiple current instructions currently cached in the operand buffer may include: initiating a read request to the target register corresponding to the current instruction; obtaining response information fed back by each of the target registers in response to the read request; and obtaining each of the current instructions currently cached in the operand buffer when it is determined that the operands of each of the current instructions are completely collected based on the response information fed back by each of the target registers in response to the read request.

[0050] The target register may be the register corresponding to the current instruction. It is understandable that different current instructions may correspond to different registers.

[0051] Before the instruction fusion processing module obtains multiple current instructions currently cached in the operand buffer, it is first necessary to determine whether the operand buffer has completely collected all the operands of the current instructions cached by it. If the operand buffer has completely collected all the operands of the current instructions cached by it, it means that the operands required by the current instruction are complete, and the instruction can be transmitted. If the operand buffer has not completely collected all the operands of the current instructions cached by it, it means that the operands required by the current instruction are incomplete, and the instruction cannot be transmitted. Specifically, the instruction fusion processing module can initiate a read request to the target register corresponding to each current instruction respectively, so as to request the target register corresponding to each current instruction to feedback the operand information corresponding to the current instruction. Accordingly, the instruction fusion processing module can receive the response information fed back by each target register to the read request, thereby determining whether the operands of each current instruction are completely collected based on the response information fed back by each target register to the read request. If it is determined that the operands of the current instruction are completely collected, the current instructions currently cached by the operand buffer can be obtained.

[0052] The above technical solution determines whether the operands of each current instruction are collected completely before obtaining the current instructions currently cached in the operand buffer, which can avoid the erroneous transmission of instructions with incomplete operands, thereby improving the accuracy and reliability of instruction transmission.

[0053] S220: Determine the instruction type of the current instruction and obtain active thread information of the current instruction.

[0054] The active thread information may be information related to the current active thread in the instruction. The fused instruction may be an instruction obtained by fusion of multiple current instructions.

[0055] It is understandable that the instruction types of different instructions currently cached in the operand buffer may be the same or different. Instructions of the same instruction type may be emitted to the same instruction execution unit for execution. For example, multiplication instructions and addition instructions can be emitted to the multiplication accumulator for execution at the same time. However, instructions of different instruction types usually need to be emitted to different instruction execution units for execution. Therefore, before the instruction fusion processing module performs fusion processing on each current instruction, the instruction type of each current instruction can be first determined, and the analysis results of the instruction type of each current instruction can be used as reference data to determine which current instructions have the same type and can be fused with each other.

[0056] In addition to considering the limitations of instruction types, the active thread information of each instruction also needs to be considered as a factor in instruction fusion processing. For example, when the number of active threads of an instruction is greater than the total number of instruction execution units, it indicates that the total number of instruction execution units required for executing active threads of the instruction is greater than the total number of instruction execution units that the target processor can currently provide, and the instruction cannot be issued temporarily. When the number of active threads of an instruction is less than the total number of instruction execution units, it indicates that the total number of instruction execution units required for executing active threads of the instruction is less than the total number of instruction execution units that the target processor can currently provide, and the instruction can be fused with other instructions and issued synchronously. Therefore, the instruction fusion processing module can also obtain the active thread information of each current instruction.

[0057] Optionally, the embodiments of the present disclosure are applicable to application scenarios where the total number of instruction execution units in the target processor is less than the number of threads per instruction.

[0058] S230 , performing fusion processing on each of the current instructions according to the instruction type of the current instruction and the active thread information of the current instruction to obtain a fused instruction.

[0059] After determining the instruction type and corresponding active thread information of each current instruction, the instruction fusion processing module can use the instruction type and corresponding active thread information of each current instruction as a basis to classify each current instruction according to the instruction type, and determine the resource requirements of the current instruction for the instruction execution unit based on the active thread information of the instruction, thereby determining the fusion strategy of each current instruction, and fuse each current instruction according to the determined fusion strategy to obtain a fused instruction.

[0060] The above technical solution can ensure that instructions of the same type are fused by fusing each current instruction according to the instruction type of the current instruction and the active thread information of the current instruction, and can ensure that the target processor can meet the resource requirements of the target instruction execution unit of the fused instruction.

[0061] S240: Send the fusion instruction to a target instruction execution unit in a target processor.

[0062] Optionally, if the current instructions are not of the same type, it indicates that the current instructions can be fused and processed. In this case, the instruction fusion processing module can transmit the current instructions to the corresponding target instruction execution unit for processing according to the conventional instruction transmission method.

[0063] In an optional embodiment of the present disclosure, determining the instruction type of the current instruction may include: obtaining instruction decoding information including identification information of the target instruction execution unit corresponding to the current instruction, and determining the instruction type of the current instruction based on the identification information of the target instruction execution unit corresponding to the current instruction.

[0064] The instruction decoding information may be related information obtained by the target processor when decoding the current instruction. Optionally, the instruction decoding information may include, but is not limited to, identification information of the target instruction execution unit to which the current instruction is to be transmitted, such as the IP address of the target instruction execution unit, and may also include thread mask information of the current instruction. The embodiments of this disclosure do not limit the specific information content of the instruction decoding information of the current instruction.

[0065] In the embodiment of the present disclosure, when parsing the instruction type of each current instruction, the instruction fusion processing module can obtain the instruction decoding information of the current instruction, and determine the identification information of the target instruction execution unit corresponding to each current instruction through the instruction decoding information of the current instruction. Figure 3 FIG. 1 is a flow chart of a target processor performing instruction fusion processing through an instruction fusion module according to an embodiment of the present disclosure. In a specific example, Figure 3 As shown, the operand buffer can store the corresponding instruction decoding information for each current instruction. The Valid field in the instruction decoding information represents the identification information of the target instruction execution unit corresponding to each current instruction. The value of alu_type corresponding to Valid is the specific identification information of the target instruction execution unit, such as the IP address of the target instruction execution unit. The info field in the instruction decoding information represents the thread mask information for each current instruction. The thread mask information can determine which threads are active in the current instruction.

[0066] It is understood that the identification information of the target instruction execution unit corresponding to the current instruction can reflect the specific type of the target instruction execution unit. Therefore, the instruction type of the current instruction can be determined specifically based on the identification information of the target instruction execution unit corresponding to the current instruction. By analyzing and determining the instruction type of the current instruction based on the identification information of the target instruction execution unit corresponding to the current instruction, the instruction type does not need to be repeatedly parsed, thereby improving the efficiency of instruction type analysis.

[0067] For example, taking an arithmetic operation instruction as an example, the identification information of the operation unit corresponding to the arithmetic operation instruction can reflect the specific type of the operation unit, such as an addition logic operation unit, a subtraction logic operation unit, a multiplication logic operation unit, and a division logic operation unit. If the identification information of the target instruction execution unit corresponding to an arithmetic operation instruction is an addition logic operation unit, it can be determined that the instruction type of the arithmetic operation instruction is an addition instruction.

[0068] In an optional embodiment of the present disclosure, the instruction decoding information of the current instruction also includes the thread mask information of the current instruction; the fusing processing of each current instruction according to the instruction type of the current instruction and the active thread information of the current instruction to obtain a fused instruction may include: filtering a set of instructions of the same type from each current instruction according to the instruction type of the current instruction; wherein the set of instructions of the same type includes at least one current instruction; determining the number of currently active threads of each current instruction in the set of instructions of the same type according to the thread mask information of the current instruction; and fusing the current instructions in the set of instructions of the same type according to the number of currently active threads of each current instruction in the set of instructions of the same type to obtain a fused instruction.

[0069] The same type of instruction set may be an instruction set consisting of current instructions of the same type. The number of currently active threads may be the number of threads currently activated in the current instruction.

[0070] Accordingly, after determining the instruction type of each current instruction, the instruction fusion processing module can classify current instructions of the same type, with each type of current instruction constituting a set of instructions of the same type. If a current instruction has no instructions of the same type, no classification processing is required for it. It is understood that only instructions of the same type can be subjected to instruction fusion processing.

[0071] The so-called same type of instructions can be understood as instructions of the same type that can be processed by the same instruction execution unit. For example, addition instructions can be classified as one type of instruction, subtraction instructions can be classified as one type of instruction, and data transfer instructions that require register A to be processed can also be classified as one type of instruction.

[0072] Furthermore, the instruction fusion processing module can analyze the active threads of each current instruction based on the thread mask information of each current instruction. Specifically, the instruction fusion processing module can analyze the active threads of each current instruction included in each instruction set of the same type, taking the instruction set of the same type as the unit, to determine the number of current active threads of each current instruction in the instruction set of the same type. It is understandable that different numbers of current active threads of the current instruction will also result in different resource requirements for the instruction execution unit.

[0073] Because the currently active thread of the current instruction directly determines the resource requirements of the corresponding target instruction execution unit, each current instruction of the same type included in the same instruction set can be fused by referring to the number of its currently active threads to obtain a fused instruction. The benefits of this setup are: it can meet the target processor's instruction execution requirements for the fused instruction, improve the utilization rate of the processor's instruction execution unit, reduce the frequency of instruction issuance, and improve the success rate of fused instruction processing and instruction execution efficiency.

[0074] In an optional embodiment of the present disclosure, the fusing of each current instruction in the same type of instruction set according to the number of currently active threads of each current instruction in the same type of instruction set to obtain a fused instruction may include: determining the total number of target instruction execution units in the target processor; when it is determined that the number of currently active threads of each current instruction in the same type of instruction set is less than or equal to the total number of target instruction execution units, and when it is determined that the total number of currently active threads of each current instruction is less than or equal to the total number of target instruction execution units, taking each current instruction in the same type of instruction set as an instruction to be fused; and fusing the instructions to be fused to obtain the fused instruction.

[0075] The instructions to be fused are instructions waiting to be fused.

[0076] Specifically, if the instruction fusion processing module determines that the number of current active threads of each current instruction in the same type of instruction set is less than or equal to the sum of the number of target instruction execution units, and determines that the sum of the number of current active threads of each current instruction is less than or equal to the sum of the number of target instruction execution units, it indicates that the instruction execution unit of the target processor meets the processing requirements of the current instruction. At this time, the instruction fusion processing module can use each current instruction in the same type of instruction set as an instruction to be fused, and fuse the instructions to be fused in the same type of instruction set to obtain a fused instruction. It can be understood that each instruction set of the same type can be fused to generate a fused instruction. Since the current instructions can all be emitted at this time, after determining that all current instructions have been emitted, the operand buffer can release the corresponding table entry and cache new instructions, and the instruction fusion processing module can start the next round of instruction fusion and emission processing.

[0077] The above technical solution directly fuses the current instructions in the same type of instruction set whose total number of currently active threads is less than or equal to the total number of target instruction execution units, thereby improving the efficiency of instruction fusion processing.

[0078] In an optional embodiment of the present disclosure, the fusing of each current instruction in the same type of instruction set according to the number of currently active threads of each current instruction in the same type of instruction set to obtain a fused instruction may include: determining the total number of target instruction execution units in the target processor; when it is determined that the number of currently active threads of each current instruction in the same type of instruction set is less than or equal to the total number of target instruction execution units, and when it is determined that the total number of currently active threads of each current instruction is greater than the total number of target instruction execution units, filtering instructions to be fused from each current instruction in the same type of instruction set according to an instruction index; and fusing the instructions to be fused to obtain the fused instruction.

[0079] Specifically, if the instruction fusion processing module determines that the number of currently active threads for each current instruction in the same type of instruction set is less than or equal to the total number of target instruction execution units, and determines that the total number of currently active threads for each current instruction is greater than the total number of target instruction execution units, it indicates that the instruction execution unit of the target processor does not meet the processing requirements of the current instruction. In this case, the instruction fusion processing module can sequentially select instructions to be fused from each current instruction in the same type of instruction set according to the instruction index, and fuse the instructions to be fused within the same type of instruction set to obtain a fused instruction.

[0080] The above technical solution filters out some of the instructions to be fused for each current instruction in the same type of instruction set where the sum of the current number of active threads is greater than the sum of the number of target instruction execution units, and then performs fusion processing. This can ensure the accuracy and reliability of instruction processing and avoid abnormal instruction processing flow due to insufficient resources of the target instruction execution unit after the instruction is issued.

[0081] Optionally, if the total number of currently active threads of each current instruction in the same type of instruction set is equal to the total number of target instruction execution units, the current instruction may not be fused, and the instruction may be selected according to the priority of the instruction index of the table entry in the operand buffer and sent to the corresponding target instruction execution unit. The embodiments of the present disclosure do not limit this.

[0082] It should be noted that different types of instruction sets of the same type may correspond to different target instruction execution units. For example, when the instructions included in the same type of instruction set are arithmetic operation instructions, the target instruction execution unit corresponding to the same type of instruction set may be the operation unit. When the instructions included in the same type of instruction set are data transfer instructions, the target instruction execution unit corresponding to the same type of instruction set may be the memory.

[0083] It should also be noted that when determining the total number of target instruction execution units in the target processor, statistics can be specifically performed based on the type of target instruction execution units corresponding to the same type of instruction set. For example, when the instructions included in the same type of instruction set are arithmetic operation instructions, the total number of operation units for the same type of instruction set can be counted, and it can be determined whether the total number of currently active threads of each arithmetic operation instruction in the same type of instruction set is less than or equal to the total number of operation units. If it is determined that the total number of currently active threads of each arithmetic operation instruction in the same type of instruction set is less than or equal to the total number of operation units, then each arithmetic operation instruction in the same type of instruction set is directly used as an instruction to be fused. If it is determined that the total number of currently active threads of each arithmetic operation instruction in the same type of instruction set is greater than the total number of operation units, then the instruction to be fused is filtered from each arithmetic operation instruction in the same type of instruction set according to the instruction index.

[0084] In an optional embodiment of the present disclosure, the above method may also include: determining an unfused instruction thread based on the same type of instruction set and the instruction to be fused; returning the unfused instruction thread to the operand buffer; and modifying the thread mask information of the instruction corresponding to the unfused instruction thread based on the bit position corresponding to the thread mask information of the unfused instruction thread.

[0085] The unfused instruction thread may be an active thread among the remaining unfused instructions in the instruction set of the same type.

[0086] If it is determined that the sum of the number of current active threads of each current instruction in the same type of instruction set is greater than the sum of the number of target instruction execution units, the instruction fusion processing module can only fuse and emit the current instructions corresponding to the current active threads that are at most the sum of the number of target instruction execution units. The remaining active threads in the same type of instruction set are regarded as unfused instruction threads. The instruction fusion processing module needs to return the unfused instruction threads to the operand buffer, and modify the thread mask information of the instructions corresponding to the unfused instruction threads according to the bit position corresponding to the thread mask information of the unfused instruction threads. The instructions with the modified thread mask information can be fused and emitted in the next round. The advantage of this setting is: strictly control the number of active threads emitted corresponding to the fused instructions, and ensure the stability and reliability of instruction processing after the instruction is emitted.

[0087] Optionally, the instruction fusion processing module can determine the total number of active threads included in the instruction to be fused based on the total number of target instruction execution units in the target processor, and determine the total number of unfused instruction threads based on the total number of current active threads of each current instruction in the same type of instruction set and the total number of target instruction execution units. Specifically, the total number of unfused instruction threads is the difference between the total number of current active threads of each current instruction in the same type of instruction set and the total number of target instruction execution units. Further, the instruction fusion processing module can determine to filter out unfused instructions from each current instruction in the same type of instruction set based on the instruction index and the total number of unfused instruction threads, and determine the unfused instruction threads from the current active thread information in the unfused instruction according to the bit order in the thread mask information in the unfused instruction, for example, the order of bits from low to high.

[0088] In a specific example, assume that the operand buffer currently caches two operation instructions, namely:

[0089] Warp0: add.0011r2 r1,r0

[0090] Warp1:mul.1101r3,r1,r0

[0091] Warp0 represents the instruction index of the first operation instruction, and Warp1 represents the instruction index of the second operation instruction. "add" indicates that the type of the first operation instruction is an addition instruction. "mul" indicates that the type of the second operation instruction is a multiplication instruction. "0011" is the thread mask information of the first operation instruction. This thread mask information indicates that the first operation instruction includes a total of four threads, of which two threads are active. "1101" is the thread mask information of the second operation instruction. This thread mask information indicates that the second operation instruction includes a total of four threads, of which three threads are active. r2, r1, and r0 are the operands of the first operation instruction, and r3, r1, and r0 are the operands of the second operation instruction.

[0092] In the two aforementioned arithmetic instructions, the operands for each instruction have been fully collected. Since the two instructions belong to different warps, there can be no dependencies between the registers of these two instructions. The active thread mask for the warp0 instruction is 0011, and the active thread mask for the warp1 instruction is 1101. Both instructions must be processed by the same arithmetic unit (MAC). It is understood that the MAC can process both addition and multiplication instructions. When these two instructions are sent to the instruction fusion processing module, the module detects that they belong to the same arithmetic unit (IP). If the total number of currently available arithmetic units in the target processor is 4, the instruction fusion processing module determines that the current number of active threads for both instructions is less than the total number of arithmetic units, and that the total number of active threads for both instructions is greater than the total number of arithmetic units. Therefore, the module determines that the two instructions can be fused and fuses them into a single instruction, which is then issued to the arithmetic unit (MAC).

[0093] The sum of the number of remaining unfused instruction threads is the difference between the sum of the number of current active threads of each current instruction in the same type of instruction set and the sum of the number of target instruction execution units, that is, 5-4=1. According to the instruction index, the two active threads with low bits can be selected from the thread mask information in the second operation instruction in order from low to high bits to be issued through the second instruction. Correspondingly, the active thread with the highest bit in the thread mask information of the second instruction is used as the unfused instruction thread. The instruction fusion processing module returns the unfused instruction thread to the operand buffer, and modifies the thread mask information of the instruction corresponding to the unfused instruction thread according to the bit position corresponding to the thread mask information of the unfused instruction thread. That is, the thread mask information mask corresponding to the current active thread of the second instruction in the operand buffer is re-modified to 1000. It can be seen that the second instruction needs to go through multiple instruction issuance processes.

[0094] It should be noted that in the existing SIMT architecture, each instruction execution unit only needs to be configured with one piece of identification information, and the identification information of the target instruction execution unit can be simply referred to as the type. For example, although the multiplier-accumulator can simultaneously perform operations such as addition, multiplication, and multiplication-accumulation, the multiplier-accumulator is usually only configured with one type to identify the type of the multiplier-accumulator. In the embodiment of the present disclosure, each instruction execution unit needs to be configured with a type according to its instruction execution function. For example, the multiplier-accumulator performs operations such as addition, multiplication, and multiplication-accumulation at the same time, then multiple types for identifying operations such as addition, multiplication, and multiplication-accumulation can be configured for the multiplier-accumulator. For example, the addition function of the multiplier-accumulator can be configured with one type, the multiplication function of the multiplier-accumulator can be configured with another type, and the multiplication-accumulation function of the multiplier-accumulator can be configured with another type, that is, a total of three types can be configured for a multiplier-accumulator.

[0095] In an optional embodiment of the present disclosure, fusing the instructions to be fused to obtain the fused instruction may include: extracting operands from the instructions to be fused in sequence according to the instruction index of the instructions to be fused; and shifting and splicing the extracted operands until it is determined that the number of spliced ​​operands reaches the total number of the target instruction execution units.

[0096] Specifically, when the instruction fusion processing module performs fusion processing on the instructions to be fused, it can extract the corresponding operands from the instructions to be fused in sequence according to the instruction index of the instructions to be fused. Furthermore, the instruction fusion processing module sequentially shifts and splices the extracted operands according to the order in which the operands were extracted until it is determined that the number of spliced ​​operands reaches the total number of target instruction execution units. At this point, the operand extraction and splicing process can be stopped, and the currently spliced ​​operands can be emitted as the fused instruction.

[0097] The above technical solution, in the application scenario where the total number of instruction execution units in the target processor is less than the number of threads per instruction, can not only alleviate the resource utilization of the instruction execution units by thread-discrete instructions by reducing the number of instruction execution units, but also reduce the instruction issuance frequency by instruction fusion, thereby improving the instruction issuance efficiency.

[0098] The disclosed embodiment obtains multiple current instructions currently cached in the operand buffer through the instruction fusion processing module in the target processor, and then determines the instruction type of the current instruction and obtains the active thread information of the current instruction. Since each current instruction includes multiple thread data, each current instruction can be fused according to the instruction type of the current instruction and the active thread information of the current instruction to obtain a fused instruction, and then the fused instruction is transmitted to the target instruction execution unit in the target processor. When facing the discrete threads of the instruction, the instruction execution unit fuses and transmits the instruction according to the instruction type, thereby solving the problems of insufficient resource utilization of the instruction execution unit and low instruction transmission efficiency when the existing processor transmits instructions, and improving the utilization rate of the instruction execution unit in the processor and the execution efficiency of the instruction.

[0099] In the technical solutions disclosed herein, the collection, storage, use, processing, transmission, provision and disclosure of user personal information are in compliance with the relevant laws and regulations and do not violate public order and good morals.

[0100] It should be noted that any arrangement and combination of the technical features in the above embodiments also falls within the protection scope of this disclosure.

[0101] In one example, Figure 4 This is a structural diagram of an instruction processing device provided by an embodiment of the present disclosure. The instruction processing device is configured in the instruction fusion processing module of a target processor. The embodiment of the present disclosure is applicable to situations where the processor transmits fused instructions after fusing instructions. The device is implemented through software and / or hardware and is specifically configured in the instruction fusion processing module of the target processor in an electronic device. The electronic device configured with the instruction fusion processing module of the target processor can be a terminal device or a server device. The embodiment of the present disclosure does not limit the specific device type of the electronic device.

[0102] like Figure 4 The instruction processing device 300 shown includes: a current instruction acquisition module 410, an instruction fusion processing module 420 and a fusion instruction transmission module 430.

[0103] The current instruction acquisition module 410 is used to acquire multiple current instructions currently cached in the operand buffer; wherein each current instruction includes multiple thread data;

[0104] An instruction fusion processing module 420 is used to perform fusion processing on the current instruction to obtain a fused instruction;

[0105] The fused instruction transmitting module 430 is configured to transmit the fused instruction to a target instruction execution unit in a target processor.

[0106] The disclosed embodiment obtains multiple current instructions currently cached in the operand buffer through the instruction fusion processing module in the target processor. Each current instruction includes multiple thread data. By fusing the current instructions to obtain a fused instruction, and then transmitting the fused instruction to the target instruction execution unit in the target processor, the frequency of instruction transmission can be reduced. The above technical solution solves the problems of insufficient resource utilization of the instruction execution unit and low instruction transmission efficiency when the existing processor transmits instructions by fusing and transmitting the instructions when facing discrete threads of instructions through the instruction execution unit, and can improve the utilization rate of the instruction execution unit in the processor and the execution efficiency of instructions.

[0107] Optionally, the current instruction acquisition module 410 is also used to: initiate a read request to the target register corresponding to the current instruction; obtain response information fed back by each target register in response to the read request; and when it is determined that the operands of each current instruction are completely collected based on the response information fed back by each target register in response to the read request, obtain each current instruction currently cached in the operand buffer.

[0108] Optionally, the instruction fusion processing module 420 is further used to: determine the instruction type of the current instruction; obtain the active thread information of the current instruction; and fuse each of the current instructions according to the instruction type of the current instruction and the active thread information of the current instruction to obtain the fused instruction.

[0109] Optionally, the instruction fusion processing module 420 is also used to: obtain instruction decoding information of the current instruction; wherein the instruction decoding information includes identification information of the target instruction execution unit corresponding to the current instruction; and determine the instruction type of the current instruction based on the identification information of the target instruction execution unit corresponding to the current instruction.

[0110] Optionally, the instruction decoding information of the current instruction also includes the thread mask information of the current instruction; the instruction fusion processing module 420 is also used to: filter a set of instructions of the same type from each of the current instructions according to the instruction type of the current instruction; wherein the set of instructions of the same type includes at least one of the current instructions; determine the number of currently active threads of each of the current instructions in the set of instructions of the same type according to the thread mask information of the current instruction; and fuse each of the current instructions in the set of instructions of the same type according to the number of currently active threads of each of the current instructions in the set of instructions of the same type to obtain a fused instruction.

[0111] Optionally, the instruction fusion processing module 420 is also used to: determine the total number of the target instruction execution units in the target processor; when it is determined that the number of current active threads of each current instruction in the same type of instruction set is less than or equal to the total number of the target instruction execution units, and when it is determined that the total number of current active threads of each current instruction is less than or equal to the total number of the target instruction execution units, take each current instruction in the same type of instruction set as an instruction to be fused; and fuse the instructions to be fused to obtain the fused instruction.

[0112] Optionally, the instruction fusion processing module 420 is also used to: determine the total number of the target instruction execution units in the target processor; when it is determined that the number of current active threads of each of the current instructions in the same type of instruction set is less than or equal to the total number of the target instruction execution units, and when it is determined that the total number of current active threads of each of the current instructions is greater than the total number of the target instruction execution units, filter the instructions to be fused from each of the current instructions in the same type of instruction set according to the instruction index; and fuse the instructions to be fused to obtain the fused instruction.

[0113] Optionally, the above-mentioned device also includes a thread mask information modification module, which is used to: determine the unfused instruction thread based on the same type of instruction set and the instruction to be fused; return the unfused instruction thread to the operand buffer; and modify the thread mask information of the instruction corresponding to the unfused instruction thread based on the bit position corresponding to the thread mask information of the unfused instruction thread.

[0114] Optionally, the instruction fusion processing module 420 is also used to: extract operands from the instructions to be fused in sequence according to the instruction index of the instructions to be fused; shift and splice the extracted operands until it is determined that the number of spliced ​​operands reaches the total number of the target instruction execution units.

[0115] The above-mentioned instruction processing device can execute the instruction processing method provided by any embodiment of the present disclosure, and has the functional modules and beneficial effects corresponding to the execution method. For technical details not fully described in this embodiment, please refer to the instruction processing method provided by any embodiment of the present disclosure.

[0116] Since the instruction processing device described above is a device that can execute the instruction processing method in the embodiments of the present disclosure, based on the instruction processing method described in the embodiments of the present disclosure, those skilled in the art will be able to understand the specific implementation of the instruction processing device of the present embodiment and its various variations. Therefore, how the instruction processing device implements the instruction processing method in the embodiments of the present disclosure will not be described in detail here. As long as those skilled in the art can implement the device used in the instruction processing method in the embodiments of the present disclosure, it falls within the scope of protection of the present disclosure.

[0117] In one example, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0118] Figure 5 A schematic block diagram of an example electronic device 500 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are provided as examples only and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0119] like Figure 5 As shown, the device 500 includes a computing unit 501, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 into a random access memory (RAM) 503. Various programs and data required for the operation of the device 500 can also be stored in the RAM 503. The computing unit 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0120] Various components in device 500 are connected to I / O interface 505, including: an input unit 506, such as a keyboard, mouse, etc.; an output unit 507, such as various types of displays, speakers, etc.; a storage unit 508, such as a magnetic disk, optical disk, etc.; and a communication unit 509, such as a network card, modem, wireless communication transceiver, etc. The communication unit 509 allows device 500 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0121] The computing unit 501 can be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. Optionally, an instruction fusion processing module can be configured inside the computing unit 501. The computing unit 501 executes the various methods and processes described above, such as the instruction processing method, through the internally configured instruction fusion processing module.

[0122] For example, in some embodiments, the instruction processing method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as storage unit 508. In some embodiments, part or all of the computer program can be loaded and / or installed on device 500 via ROM 502 and / or communication unit 509. When the computer program is loaded into RAM 503 and executed by computing unit 501, one or more steps of the instruction processing method described above can be performed. Alternatively, in other embodiments, computing unit 501 can be configured to perform the instruction processing method in any other suitable manner (e.g., by means of firmware).

[0123] Various embodiments of the systems and techniques described above can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0124] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0125] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0126] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0127] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0128] A computer system may include a client and a server. The client and server are typically remote from each other and typically interact via a communication network. This client-server relationship arises through computer programs running on the respective computers, creating a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host. This server is a hosting product within the cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosting and VPS services. The server may also be a server in a distributed system or a server integrated with blockchain.

[0129] The disclosed embodiment obtains multiple current instructions currently cached in the operand buffer through the instruction fusion processing module in the target processor, and then determines the instruction type of the current instruction and obtains the active thread information of the current instruction. Since each current instruction includes multiple thread data, each current instruction can be fused according to the instruction type of the current instruction and the active thread information of the current instruction to obtain a fused instruction, and then the fused instruction is transmitted to the target instruction execution unit in the target processor. When facing the discrete threads of the instruction, the instruction execution unit fuses and transmits the instruction according to the instruction type, thereby solving the problems of insufficient resource utilization of the instruction execution unit and low instruction transmission efficiency when the existing processor transmits instructions, and improving the utilization rate of the instruction execution unit in the processor and the execution efficiency of the instruction.

[0130] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not a limitation herein.

[0131] The above specific embodiments do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims

1. An instruction processing method, applied to an instruction fusion processing module of a target processor, comprising: Obtaining a plurality of current instructions currently cached in an operand buffer; wherein each of the current instructions includes a plurality of thread data; Performing fusion processing on the current instruction to obtain a fused instruction; The fused instruction is issued to a target instruction execution unit in a target processor.

2. The method according to claim 1, wherein The step of obtaining a plurality of current instructions currently cached in the operand buffer comprises: Initiate a read request to the target register corresponding to the current instruction; Obtaining response information fed back by each of the target registers in response to the read request; When it is determined that the operands of each current instruction are completely collected according to the response information fed back by each target register to the read request, each current instruction currently cached in the operand buffer is obtained.

3. The method according to claim 1, wherein The fusing process of the current instruction to obtain a fused instruction includes: Determining the instruction type of the current instruction; Obtaining active thread information of the current instruction; The current instructions are fused according to the instruction type of the current instruction and the active thread information of the current instruction to obtain the fused instruction.

4. The method according to claim 3, wherein: The determining the instruction type of the current instruction includes: Obtaining instruction decoding information of the current instruction; wherein the instruction decoding information includes identification information of a target instruction execution unit corresponding to the current instruction; The instruction type of the current instruction is determined according to identification information of a target instruction execution unit corresponding to the current instruction.

5. The method according to claim 4, wherein The instruction decoding information of the current instruction also includes thread mask information of the current instruction; The fusing the current instructions according to the instruction type of the current instruction and the active thread information of the current instruction to obtain the fused instruction includes: Filtering a set of instructions of the same type from each of the current instructions according to the instruction type of the current instruction; wherein the set of instructions of the same type includes at least one of the current instructions; Determining the number of currently active threads of each current instruction in the set of instructions of the same type according to the thread mask information of the current instruction; The current instructions in the same type of instruction set are fused according to the number of currently active threads of each current instruction in the same type of instruction set to obtain a fused instruction.

6. The method according to claim 5, wherein: The fusing the current instructions in the same type of instruction set according to the number of currently active threads of the current instructions in the same type of instruction set to obtain a fused instruction includes: Determining the total number of the target instruction execution units in the target processor; When it is determined that the number of currently active threads of each current instruction in the instruction set of the same type is less than or equal to the total number of target instruction execution units, and when it is determined that the total number of currently active threads of each current instruction is less than or equal to the total number of target instruction execution units, each current instruction in the instruction set of the same type is used as an instruction to be fused; The instructions to be fused are fused to obtain the fused instructions.

7. The method according to claim 5, wherein: The fusing the current instructions in the same type of instruction set according to the number of currently active threads of the current instructions in the same type of instruction set to obtain a fused instruction includes: Determining the total number of the target instruction execution units in the target processor; When it is determined that the number of currently active threads of each current instruction in the instruction set of the same type is less than or equal to the total number of target instruction execution units, and when it is determined that the total number of currently active threads of each current instruction is greater than the total number of target instruction execution units, selecting instructions to be fused from each current instruction in the instruction set of the same type according to instruction index; The instructions to be fused are fused to obtain the fused instructions.

8. The method according to claim 7, further comprising: Determining an unfused instruction thread according to the same type of instruction set and the to-be-fused instruction; returning the unfused instruction thread to the operand buffer; The thread mask information of the instruction corresponding to the unfused instruction thread is modified according to the bit position corresponding to the thread mask information of the unfused instruction thread.

9. The method according to any one of claims 6-7, wherein: The step of fusing the instructions to be fused to obtain the fused instruction includes: Extracting operands from the instructions to be fused in sequence according to the instruction indexes of the instructions to be fused; The extracted operands are shifted and spliced ​​until it is determined that the number of spliced ​​operands reaches the total number of the target instruction execution units.

10. An instruction processing device, configured in an instruction fusion processing module of a target processor, comprising: A current instruction acquisition module, configured to acquire a plurality of current instructions currently cached in an operand buffer; wherein each of the current instructions includes a plurality of thread data; An instruction fusion processing module, configured to perform fusion processing on the current instruction to obtain a fused instruction; The fused instruction transmitting module is used to transmit the fused instruction to the target instruction execution unit in the target processor.

11. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The processor is internally configured with an instruction fusion processing module; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the instruction fusion processing module of the at least one processor can execute the instruction processing method according to any one of claims 1 to 9.

12. A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute the instruction processing method according to any one of claims 1 to 9.

13. A computer program product comprising a computer program / instructions, wherein: When the computer program / instruction is executed by a processor, the instruction processing method according to any one of claims 1 to 9 is implemented.

Images