FPGA self-oscillation signal detection method and device based on signal feedback loop

Abstract

This invention discloses a method and apparatus for detecting self-oscillation signals in FPGAs based on signal feedback loops. The method includes: first, reading the received FPGA hardware description language code file and integrating the various modules in the FPGA code to form a top-down overall code file; second, mapping the overall FPGA code file into a signal transmission network based on the transmission relationships between various signals in the overall code file; third, finding all signal feedback loops in the signal transmission network and calculating the signal feedback probability, selecting and recording signal feedback loops with a signal feedback probability greater than a set threshold, and extracting the signals in the signal feedback loops as self-oscillation signals for output. This invention can effectively detect self-oscillation signals and their occurrence probabilities in FPGA designs. It is simple to use, requires minimal investment, and can well meet the needs of self-oscillation signal detection when conducting triple-modular redundancy designs.

Description

Technical Field

[0001] This invention belongs to the field of FPGA testing technology, and in particular, it is a method and device for detecting FPGA self-excited signals based on a signal feedback loop. Background Technology

[0002] In recent years, SRAM-based FPGAs have been widely used in various fields due to their unique reconfigurability, low latency, real-time processing, and high parallel computing capabilities. However, FPGAs are highly sensitive to space particle radiation and are prone to single-event upsets (SEE), leading to logic failures and signal output errors. Therefore, it is crucial to implement fault-tolerant designs for FPGAs to prevent such failures. Triple Mode Redundancy (TMR) design involves implementing three identical modules in the FPGA. When one module fails, the other two can continue to operate, thus maintaining the normal operation of the FPGA. Therefore, TMR design is widely used for fault-tolerant design of FPGAs against SEE due to its simplicity and reliability.

[0003] While triple mode redundancy (TMR) design can effectively improve the reliability of FPGA designs, it increases additional resources and power consumption. Typically, TMR design is only implemented for logic modules in the FPGA that process critical signals. Self-oscillating signals are a special type of signal in FPGAs; their output may affect themselves again through a feedback loop. This means that once an error occurs with such a signal, its impact can persist for a long time, even indefinitely. Therefore, fault-tolerant design for such signals is particularly important, and TMR design is generally required for logic modules that process them. However, currently, there are no mature methods in the industry to accurately detect self-oscillating signals, and as FPGAs become larger and the number of signals increases, detecting self-oscillating signals becomes increasingly difficult. Especially due to the limited resources of FPGAs, fault-tolerant design can generally only be implemented for self-oscillating signals with a high probability of occurrence. Therefore, estimating the probability of self-oscillating after identifying the signal is even more challenging. Patent CN114692551A discloses a method for detecting safety-critical signals in Verilog design files. This method can detect safety-critical signals of FPGAs based on Verilog designs. However, the definition of safety-critical signals in this method is based on the extent to which the signal affects other signals, and it is not applicable to the detection of self-excited signals.

[0004] To meet the need for accurate detection of self-oscillation signals in FPGA triple mode redundancy (TMR) design, there is an urgent need to propose an effective technical means that can effectively detect potential self-oscillation signals in FPGA design and estimate the probability of self-oscillation of each self-oscillation signal. This would provide effective guidance for FPGA developers in selecting self-oscillation signal-related logic modules for TMR design, thereby improving the quality and reliability of FPGA design. Summary of the Invention

[0005] The purpose of this invention is to address the current situation where there is no effective method in the industry to accurately detect potential self-oscillation signals and provide the probability of self-oscillation in FPGA designs. This invention proposes an FPGA self-oscillation signal detection method and device based on a signal feedback loop, which can effectively detect self-oscillation signals and their occurrence probability in FPGA designs. It is simple to use, requires minimal investment, and can well meet the needs of self-oscillation signal detection when carrying out triple modular redundancy (TMR) designs.

[0006] The technical solution for achieving the objective of this invention is as follows: Firstly, this invention provides a method for detecting self-oscillating signals in an FPGA based on a signal feedback loop, comprising the following steps:

[0007] Step 1: Read the received FPGA hardware description language code file, integrate the various modules in the FPGA hardware description language code to form a top-down overall code file;

[0008] Step 2: Based on the transmission relationship between various signals in the overall FPGA code file, map the overall FPGA code file into a signal transmission network;

[0009] Step 3: Locate all signal feedback loops in the signal transmission network and calculate the signal feedback probability. Select and record signal feedback loops whose signal feedback probability is greater than a set threshold.

[0010] Step 4: Extract the signal from the signal feedback loop as the self-excited signal output.

[0011] Secondly, the present invention provides an FPGA self-excited signal detection device based on a signal feedback loop, used to implement the method described in the first aspect, the device comprising:

[0012] The signal transmission network generation module is used to read the received FPGA hardware description language code file, form a top-down overall code file, and map it into a signal transmission network.

[0013] The signal feedback loop detection module is used to find all signal feedback loops in the signal transmission network and calculate the signal feedback probability, and select and record signal feedback loops whose signal feedback probability is greater than a set threshold.

[0014] The self-excited signal output module is used to extract and output the self-excited signal of the FPGA based on the signal feedback loop.

[0015] Thirdly, the present invention provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the method described in the first aspect.

[0016] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in the first aspect.

[0017] Fifthly, the present invention provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method described in the first aspect.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: 1) The method of the present invention can accurately detect the self-oscillation signal in FPGA design and estimate the probability of self-oscillation; 2) The method of the present invention is easy to implement, has high detection efficiency, low investment cost, and strong practicality; 3) The method of the present invention can be easily implemented by computer, which can further improve the detection efficiency of self-oscillation signal in FPGA design.

[0019] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0020] Figure 1 This is a flowchart of the FPGA self-excited signal detection method based on signal feedback loop proposed in this invention.

[0021] Figure 2 This is a code example for an FPGA hardware description language.

[0022] Figure 3 This is an instance of the module code.

[0023] Figure 4 This is an example of the integrated FPGA hardware description language code.

[0024] Figure 5 This is an example of the extracted signal list.

[0025] Figure 6 This is an example of calculating the probability of a directed edge.

[0026] Figure 7 This is an example of a signal transmission network.

[0027] Figure 8 This is an instance of the signal feedback probability for transmission loopback.

[0028] Figure 9 This is a schematic diagram of the FPGA self-excited signal detection device based on a signal feedback loop proposed in this invention. Detailed Implementation

[0029] Combination Figure 1 The present invention proposes an FPGA self-excited signal detection method based on a signal feedback loop, which specifically includes the following steps:

[0030] Step 1: Read the received FPGA hardware description language code file, integrate the various modules in the FPGA code to form a top-down overall code file;

[0031] Step 2: Based on the transmission relationship between various signals in the overall FPGA code file, map the overall FPGA code file into a signal transmission network;

[0032] Step 21: Locate and record all signals defined in the overall FPGA code file, and construct a corresponding signal transmission network. Each signal in the FPGA corresponds to a node in the signal transmission network.

[0033] Step 22: Find all right-hand assignment statements for FPGA signals, i.e., assignment statements that contain the signal in the right-hand expression, and record all right-hand assignment statements whose right-hand expressions are not constants; classify all recorded right-hand assignment statements according to their respective control branches, where right-hand assignment statements belonging to the same control branch belong to the same category, and record the total number of categories M.

[0034] Step 23: Extract the signals from the left-hand expressions of all FPGA signal records in turn, construct a directed edge from the FPGA signal node to the extracted left-hand signal node, and analyze the right-hand assignment statements of the FPGA signal. Count the total number N of right-hand assignment statement classes containing the aforementioned left-hand signal, calculate N / M to obtain the transmission probability of the constructed directed edge, and thus obtain the signal transmission network corresponding to the overall FPGA code file.

[0035] Step 3: Locate all signal feedback loops in the signal transmission network and calculate the signal feedback probability. Select and record signal feedback loops whose signal feedback probability is greater than a set threshold.

[0036] Step 31: Determine the threshold for signal feedback probability based on the remaining available logic resources of the FPGA. That is, if the proportion of the remaining logic resources of the FPGA to the total resources is A, then the feedback probability threshold is 1-A.

[0037] Step 32: Find all signal feedback loops in the signal transmission network, and multiply the transmission probabilities corresponding to all directed edges in the found signal feedback loops to obtain the signal feedback probability of the signal feedback loop; where a signal feedback loop refers to a circular path in the signal transmission network consisting of multiple signal nodes and their directed edges, on which transmission can eventually return to the starting signal node of the transmission by taking any signal node as the starting point along the path.

[0038] Step 33: Record all signal feedback loops whose signal feedback probability is greater than the set threshold.

[0039] Step 4: Extract the signal from the signal feedback loop as the self-excited signal output.

[0040] Based on the same inventive concept, the present invention also provides an FPGA self-excited signal detection device based on a signal feedback loop, such as... Figure 9 As shown, the device includes a signal transmission network generation module, a signal feedback loop detection module, and a self-excited signal output module. The signal transmission network generation module reads the received FPGA hardware description language code file, forms a top-down overall code file, and maps it to a signal transmission network. The signal feedback loop detection module searches for all signal feedback loops in the signal transmission network and calculates the signal feedback probability, selecting and recording signal feedback loops with a signal feedback probability greater than a set threshold. The self-excited signal output module extracts and outputs the FPGA's self-excited signal based on the signal feedback loops.

[0041] The specific implementation methods of the above modules are the same as those described above, and will not be repeated here.

[0042] The present invention will now be described in further detail with reference to the embodiments.

[0043] Example

[0044] The FPGA hardware description language code given in this embodiment contains two files, TOP.vhd and MA.vhd, where module MA is an instantiated submodule of module TOP.

[0045] The following describes the processing of the RTL code file using an FPGA self-oscillation signal detection method based on a signal feedback loop proposed in this invention. The specific processing steps are as follows:

[0046] Step 1: Read the received FPGA hardware description language code file TOP.vhd, such as... Figure 2 As shown, the instantiation module code file MA.vhd in the FPGA code is as follows: Figure 3As shown, the instantiation module MA code and the top-level module TOP are integrated into a single, top-down code file, as follows. Figure 4 As shown;

[0047] Step 2: Based on the transmission relationship between various signals in the overall FPGA code file, map the overall FPGA code file into a signal transmission network;

[0048] Step 21: Locate and record all signals defined in the overall FPGA code file, such as... Figure 5 As shown, each of the above signals corresponds to a node in the signal transmission network;

[0049] Step 22: Locate all right-hand assignment statements for FPGA signals, i.e., assignment statements that contain the signal in the right-hand expression, and record all right-hand assignment statements whose right-hand expressions are not constants, such as... Figure 6 As shown, all recorded right-hand assignment statements are categorized according to their respective control branches. Right-hand assignment statements belonging to the same control branch are classified into the same category, and the total number of categories is recorded. Figure 6 As shown;

[0050] Step 23: Extract the signals from the left-hand side of the right-hand assignment statements of all FPGA signal records sequentially, and construct a directed edge from the FPGA signal node to the extracted left-hand signal node, such as... Figure 6 As shown, the right-hand assignment statements of the FPGA signal are analyzed simultaneously, and the total number of right-hand assignment statement classes containing the aforementioned left-hand signal is counted. Figure 6 As shown, the transmission probabilities of each of the above directed edges are calculated, such as... Figure 6 As shown, the signal transmission network corresponding to the overall FPGA code file is obtained, such as... Figure 7 As shown.

[0051] Step 3: Locate all signal feedback loops in the signal transmission network and calculate the signal feedback probability. Select and record signal feedback loops whose signal feedback probability is greater than a set threshold.

[0052] Step 31: In this example, the remaining available logic resources of the FPGA to which the FPGA hardware description language code belongs account for 70% of the total resources. Therefore, the threshold for the signal feedback probability is set to 30%.

[0053] Step 32: Locate all signal feedback loops in the signal transmission network, resulting in one signal feedback loop, such as... Figure 8 As shown, the transmission probabilities of all directed edges in the signal feedback loop are multiplied together, resulting in a signal feedback probability of 37.5%. Figure 8 As shown;

[0054] Step 33: Record all signal feedback loops with a probability greater than the set threshold of 30%. There is one such loop. Figure 8 As shown.

[0055] Step 4: Extract the self-excited signals from the signal feedback loop: Y, A, B, C.

[0056] The above description is merely a preferred embodiment of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention. All components not explicitly stated in this embodiment can be implemented using existing technology.

Claims

1. A method for detecting self-excited signals in an FPGA based on a signal feedback loop, characterized in that, Includes the following steps: Step 1: Read the received FPGA hardware description language code file, integrate the various modules in the FPGA hardware description language code to form a top-down overall code file; Step 2: Based on the transmission relationships between various signals in the overall FPGA code file, map the overall FPGA code file into a signal transmission network, including the following steps: Step 21: Locate and record all signals defined in the overall FPGA code file, and construct a corresponding signal transmission network. Each signal in the FPGA corresponds to a node in the signal transmission network. Step 22: Find all right-hand assignment statements for FPGA signals, i.e., assignment statements that contain the signal in the right-hand expression, and record all right-hand assignment statements whose right-hand expressions are not constants; classify all recorded right-hand assignment statements according to their respective control branches, where right-hand assignment statements belonging to the same control branch belong to the same category, and record the total number of categories M. Step 23: Extract the signals from the left-hand expressions of all FPGA signal records in turn, construct a directed edge from the FPGA signal node to the extracted left-hand signal node, and analyze the right-hand assignment statements of the FPGA signal. Count the total number N of right-hand assignment statement classes containing the left-hand signal mentioned above, and calculate N / M to obtain the transmission probability of the constructed directed edge, thereby obtaining the signal transmission network corresponding to the overall FPGA code file. Step 3: Locate all signal feedback loops in the signal transmission network and calculate the signal feedback probability. Select and record signal feedback loops whose signal feedback probability is greater than a set threshold. Step 4: Extract the signal from the signal feedback loop as the self-excited signal output.

2. The FPGA self-oscillating signal detection method based on a signal feedback loop according to claim 1, characterized in that, In step 3, all signal feedback loops in the signal transmission network are located and the signal feedback probability is calculated. Signal feedback loops with a signal feedback probability greater than a set threshold are selected and recorded. This includes the following steps: Step 31: Determine the threshold for signal feedback probability based on the remaining available logic resources of the FPGA. That is, if the proportion of the remaining logic resources of the FPGA to the total resources is A, then the feedback probability threshold is 1-A. Step 32: Find all signal feedback loops in the signal transmission network, and multiply the transmission probabilities corresponding to all directed edges in the found signal feedback loops to obtain the signal feedback probability of the signal feedback loop; where a signal feedback loop refers to a circular path in the signal transmission network consisting of multiple signal nodes and their directed edges, on which transmission can eventually return to the starting signal node of the transmission by taking any signal node as the starting point. Step 33: Record all signal feedback loops whose signal feedback probability is greater than the set threshold.

3. An FPGA self-excited signal detection device based on a signal feedback loop, characterized in that, The device includes: The signal transmission network generation module is used to read the received FPGA hardware description language code file, form a top-down overall code file, and map it into a signal transmission network. Specifically: Find and record all signals defined in the overall FPGA code file, and build a corresponding signal transmission network, where each signal in the FPGA corresponds to a node in the signal transmission network. Find all right-hand assignment statements for FPGA signals, i.e., assignment statements that contain the signal in the right-hand expression, and record all right-hand assignment statements whose right-hand expressions are not constants; classify all recorded right-hand assignment statements according to their control branches, and right-hand assignment statements belonging to the same control branch belong to the same category, and record the total number of categories M; The signals in the left-hand expressions of the right-hand assignment statements of all FPGA signal records are extracted sequentially. A directed edge is constructed from the FPGA signal node to the extracted left-hand signal node. At the same time, the right-hand assignment statements of the FPGA signal are analyzed, and the total number N of right-hand assignment statement classes containing the above left-hand signal is counted. The transmission probability of the constructed directed edge is obtained by calculating N / M, thus obtaining the signal transmission network corresponding to the overall FPGA code file. The signal feedback loop detection module is used to find all signal feedback loops in the signal transmission network and calculate the signal feedback probability, and select and record signal feedback loops whose signal feedback probability is greater than a set threshold. The self-excited signal output module is used to extract and output the self-excited signal of the FPGA based on the signal feedback loop.

4. The FPGA self-oscillating signal detection device based on a signal feedback loop according to claim 3, characterized in that, Locate all signal feedback loops in the signal transmission network and calculate the signal feedback probability. Select and record signal feedback loops whose signal feedback probability is greater than a set threshold. Specifically: The threshold for signal feedback probability is determined based on the remaining available logic resources of the FPGA. That is, if the proportion of the remaining logic resources of the FPGA to the total resources is A, then the feedback probability threshold is 1-A. Find all signal feedback loops in the signal transmission network, and multiply the transmission probabilities corresponding to all directed edges in the found signal feedback loops to obtain the signal feedback probability of the signal feedback loop; where a signal feedback loop is a circular path in the signal transmission network consisting of multiple signal nodes and their directed edges, on which transmission can eventually return to the starting signal node of the transmission by taking any signal node as the starting point. Record all signal feedback loops whose signal feedback probability is greater than the set threshold.

5. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method as described in any one of claims 1-2.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps of the method as described in any one of claims 1-2.

7. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the steps of the method described in any of claims 1-2.

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