Storage system

Abstract

The invention provides a storage system capable of improving the processing capability of data transfer. A memory system according to an embodiment includes: a memory chip including a first terminal group for transmitting and receiving data and a second terminal group for receiving a packet; and a memory controller that controls the memory chip. When a data transfer operation is executed between the memory controller and the memory chip, the memory controller transmits to the memory chip a first packet indicating the start of data transfer and a second packet indicating the end of data transfer. When the storage controller continuously performs two data transfer operations with the storage chip, the storage controller transmits a first data packet corresponding to the second data transfer to the storage chip between the first data transfer and the second data transfer, and does not transmit a second data packet corresponding to the first data transfer to the storage chip.

Description

Technical Field

[0001] Embodiments of the present invention relate to a storage system. Background Art

[0002] As a storage system, an SSD (Solid State Drive) equipped with a nonvolatile memory such as a NAND flash memory is known. Summary of the Invention

[0003] Provided is a storage system capable of improving the processing capability of data transmission.

[0004] A storage system according to an embodiment includes: a memory chip including a first terminal group for transmitting and receiving data and a second terminal group for receiving data packets, configured to store data in a non-volatile manner; and a memory controller that controls the memory chip and is configured to transmit and receive data to and from the memory chip via the first terminal group and to send data packets to the memory chip via the second terminal group. When the memory controller performs a single data transfer operation with the memory chip, the memory controller sends a first data packet indicating the start of the data transfer and a second data packet indicating the end of the data transfer to the memory chip. When the memory controller performs two consecutive data transfer operations with the memory chip, between the first and second data transfers, the memory controller sends a first data packet corresponding to the second data transfer to the memory chip, but does not send a second data packet corresponding to the first data transfer to the memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 This is a block diagram showing an example of the overall configuration of the storage system according to the first embodiment.

[0006] Figure 2 This is a block diagram showing an example of the configuration of a memory chip included in the memory system according to the first embodiment.

[0007] Figure 3 This is a circuit diagram of a memory cell array included in the memory system according to the first embodiment.

[0008] Figure 4 This is a diagram showing an example of a sequence of command and address input operations in the storage system according to the first embodiment.

[0009] Figure 5 This is a diagram showing an example of a sequence of status information output operations in the storage system according to the first embodiment.

[0010] Figure 6This is a diagram showing an example of a sequence of data input operations in the storage system according to the first embodiment.

[0011] Figure 7 This is a diagram showing an example of a sequence of data output operations in the storage system according to the first embodiment.

[0012] Figure 8 This is a diagram showing an example of a sequence in which the data input operation in the storage system according to the first embodiment is performed twice consecutively.

[0013] Figure 9 This is a diagram showing an example of a sequence in which the data output operation in the storage system according to the first embodiment is performed twice in succession.

[0014] Figure 10 This is a diagram showing an example of a sequence in which data input and output operations are continuously performed in the storage system according to the first embodiment.

[0015] Figure 11 This is a diagram showing an example of a sequence in which data output operations and data input operations are continuously performed in the storage system according to the first embodiment.

[0016] Figure 12 This is a block diagram showing an example of the overall configuration of a storage system according to the second embodiment.

[0017] Figure 13 This diagram shows an example of a sequence in which data output operations are performed multiple times consecutively in a memory chip connected to a channel CH0a and a memory chip connected to a channel CH0b of a bridge chip included in the storage system according to the second embodiment.

[0018] Figure 14 This is a block diagram showing an example of the overall configuration of a storage system according to the third embodiment.

[0019] Figure 15 This is a diagram showing an example of a case where data is output from a bridge chip to a memory controller in a memory system according to a third embodiment.

[0020] Figure 16 This is a diagram showing an example of a case where data is output from a bridge chip to a memory controller in a memory system according to a third embodiment.

[0021] Label Description

[0022] 1…Memory system, 10…Non-volatile memory, 11…Memory chip, 20…Memory controller, 21…Host interface circuit, 22…CPU, 23…ROM, 24, 35, 35a, 35b…RAM, 25…ECC circuit, 26…Memory interface circuit, 30…Bridge chip, 31…SCE determination unit, 32…Data size setting unit, 33…Data counter, 34…Channel switch, 101…I / O circuit, 102…Logic control circuit, 103…Address register, 104…Command register, 105…Status register, 106…Sequencer, 107…Ready / busy circuit, 108…Voltage generation circuit, 110…Memory cell array, 111…Row decoder, 112…Sense amplifier, 113…Data register, 114…Column decoder DETAILED DESCRIPTION

[0023] Hereinafter, the embodiment will be described with reference to the accompanying drawings. In addition, in the following description, components having the same function and structure are marked with common reference numerals. In addition, in the case of distinguishing multiple components having a common reference numeral, the common reference numeral is distinguished by adding a footnote (footnote). In addition, in the case where there is no need to distinguish multiple components, the multiple components are only marked with a common reference numeral without adding a footnote. Here, the footnote is not limited to subscript characters and superscript characters, for example, it includes lowercase letters added at the end of the reference numeral, and indexes indicating arrangement, etc.

[0024] 1. First Implementation

[0025] The storage system according to the first embodiment will be described.

[0026] 1.1 Composition

[0027] 1.1.1 Storage System Structure

[0028] First, refer to Figure 1 , an example of the structure of the storage system 1 is described. Figure 1 1 is a block diagram showing an example of the overall structure of the storage system 1. Figure 1 In the illustrated example, a portion of the connections between the components are indicated by arrow lines, but the connections between the components are not limited to this.

[0029] like Figure 1 As shown, the storage system 1 is, for example, an SSD (Solid State Drive). The storage system 1 is connected to a host device (not shown). For example, the storage system 1 is controlled by the host device.

[0030] The memory system 1 includes a nonvolatile memory 10 and a memory controller 20 .

[0031] The nonvolatile memory 10 is a nonvolatile storage medium and stores data received from the memory controller 20 in a nonvolatile manner.

[0032] The memory controller 20 is, for example, a SoC (System on a Chip). Based on requests (commands) from a host device, the memory controller 20 commands read, write, and erase operations to the nonvolatile memory 10. Furthermore, the memory controller 20 manages the storage space of the nonvolatile memory 10.

[0033] Next, an example of the internal structure of the nonvolatile memory 10 will be described. The nonvolatile memory 10 includes a plurality of memory chips 11 .

[0034] The memory chip 11 is, for example, a semiconductor memory device equipped with a NAND flash memory. The memory chip 11 stores data in a nonvolatile manner. Alternatively, the memory chip 11 may be another nonvolatile memory.

[0035] The multiple memory chips 11 can operate independently. Each memory chip 11 is connected to the memory controller 20 via a NAND bus NB. The number of NAND buses NB and the number of memory chips 11 connected to a single NAND bus NB are arbitrary. Communication between the memory controller 20 and the memory chips 11 follows, for example, a toggle DDR (Toggle Double Data Rate) interface or ONFI (Open NAND Flash Interface).

[0036] The memory chip 11 exchanges signals NB_dat and NB_pkt with the memory controller 20 (more specifically, the memory interface circuit 26) via the NAND bus NB. The signal group NB_dat includes multiple signals related to data transmission and reception. The signal group NB_pkt includes multiple signals related to data packet transmission and reception. Furthermore, the memory chip 11 transmits the signal R / B_n to the memory controller 20 via the NAND bus NB. Details of the signal groups NB_dat, NB_pkt, and R / B_n will be described later.

[0037] Next, an example of the internal structure of the memory controller 20 will be described. The memory controller 20 includes a host interface circuit (host I / F) 21, a CPU (Central Processing Unit) 22, a ROM (Read Only Memory) 23, a RAM (Random Access Memory) 24, an ECC (Error Check and Correction) circuit 25, and a memory interface circuit (memory I / F) 26. These circuits are interconnected via, for example, an internal bus of the memory controller 20. The functions of the host interface circuit 21, the ECC circuit 25, and the memory interface circuit 26 can be implemented using dedicated circuits or by having the CPU 22 execute firmware.

[0038] The host interface circuit 21 is an interface circuit connected to a host device. It controls communication between the host device and the storage controller 20. It transmits requests and data received from the host device to the CPU 22 and RAM 24, respectively. Furthermore, the host interface circuit 21 transmits data in the RAM 24 to the host device under the control of the CPU 22.

[0039] The CPU 22 is a processor. The CPU 22 controls the overall operation of the memory controller 20. For example, based on a request from the host device, the CPU 22 instructs the nonvolatile memory 10 (memory chip 11) to write, read, and erase data. Furthermore, the CPU 22 manages the storage area of ​​the nonvolatile memory 10.

[0040] ROM23 is a non-volatile memory. For example, ROM23 is EEPROM TM (Electrically Erasable Programmable Read-Only Memory) The ROM 23 is a non-transitory storage medium that stores firmware and programs, etc. For example, the CPU 22 expands the firmware loaded from the ROM 23 into the RAM 24 .

[0041] RAM 24 is a volatile memory. RAM 24 is, for example, DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). RAM 24 can be used as a workspace for CPU 22. For example, RAM 24 stores firmware and various management tables for managing non-volatile memory 10. RAM 24 also temporarily stores data read from non-volatile memory 10 and data received from the host device.

[0042] The ECC circuit 25 is a circuit that performs ECC processing. ECC processing includes data encoding and decoding. For example, when writing data, the ECC circuit 25 performs data encoding processing to generate error correction codes (parity bits). Furthermore, the ECC circuit 25 adds parity bits to the data. Furthermore, when reading data, the ECC circuit 25 performs decoding processing. In other words, the ECC circuit 25 uses parity bits to perform data error correction processing. Hereinafter, when the ECC circuit 25 performs encoding and decoding, the data processed together will be referred to as an "ECC frame" or "data frame."

[0043] The memory interface circuit 26 controls communication between the memory controller 20 and the nonvolatile memory 10. The memory interface circuit 26 may include a plurality of channels CH (CH0, CH1, ...). One or more memory chips 11 are connected to each channel CH via a NAND bus NB.

[0044] 1.1.2 Composition of Memory Chips

[0045] Next, refer to Figure 2 , an example of the structure of the memory chip 11 is described. Figure 2 1 is a block diagram showing an example of the structure of the memory chip 11. Figure 2 In the illustrated example, a portion of the connections between the components are indicated by arrow lines, but the connections between the components are not limited to this.

[0046] In this embodiment, different signals (signal lines) on the NAND bus NB are used to input and output data DAT between the memory controller 20 and the memory chip 11, and to input commands CMD and addresses ADD from the memory controller 20 to the memory chip 11. This communication protocol is hereinafter referred to as the "SCA (Separate Command Address Input) protocol."

[0047] like Figure 2As shown, the memory chip 11 includes an input-output circuit 101, a logic control circuit 102, an address register 103, a command register 104, a status register 105, a sequencer 106, a ready / busy circuit 107, a voltage generating circuit 108, a memory cell array 110, a row decoder 111, a sense amplifier 112, a data register 113, and a column decoder 114.

[0048] The input-output circuit 101 is a circuit for inputting and outputting data DAT. The input-output circuit 101 is connected to the NAND bus NB, that is, the storage controller 20 (more specifically, the memory interface circuit 26) via a plurality of terminals TM (external connection terminals). Hereinafter, the set of the plurality of terminals TM connected to the input-output circuit 101 will be referred to as the "first terminal group TMG1". For example, the input-output circuit 101 transmits and receives 8-bit (bit) signals DQ<7:0> and signals DQS and DQS_c with the storage controller 20 via the first terminal group TMG1. In addition, the input-output circuit 101 receives signals RE_t and RE_c from the storage controller 20 via the first terminal group TMG1. Hereinafter, without limiting any of the signals DQ<7:0>, it will be simply referred to as "signal DQ". Signal DQ is data DAT. Signals DQS and DQS_c are selection signals (clock signals) for inputting and outputting signal DQ. Signal DQS_c is an inverted signal of signal DQS. Signals RE_t and RE_c are read enable signals used by the memory controller 20 to read data DAT from the memory chip 11. Signal RE_c is an inverted signal of signal RE_t. Signals RE_t and RE_c are asserted, for example, at a Low ("L") level. For example, when outputting data DAT, the input / output circuit 101 generates signals DQS and DQS_c based on signals RE_t and RE_c. Furthermore, signals RE_t and RE_c are not used for outputting data packets.

[0049] Hereinafter, the set of signals DQ, DQS, and DQS_c, as well as signals RE_t and RE_c used for inputting and outputting data DAT will be referred to as "signal group NB_dat." Specifically, the set of multiple signals inputted and outputted by the input / output circuit 101 constitutes the signal group NB_dat. In other words, the input / output circuit 101 transmits and receives the signal group NB_dat to and from the memory controller 20 via the first terminal group TMG1. Furthermore, the input / output circuit 101 is connected to the logic control circuit 102 and the data register 113. Data DAT is transmitted and received between the input / output circuit 101 and the data register 113.

[0050] The logic control circuit 102 is a circuit that performs logical control of the memory chip 11. The logic control circuit 102 controls the input / output circuit 101 and the sequencer 106. The logic control circuit 102 is connected to the NAND bus NB, that is, the memory controller 20, via a plurality of terminals TM. Hereinafter, the set of the plurality of terminals TM connected to the logic control circuit 102 will be referred to as the "second terminal group TMG2." The logic control circuit 102 transmits and receives a plurality of signals to and from the memory controller 20 via the second terminal group TMG2. Hereinafter, in the logic control circuit 102, the set of a plurality of signals input and output via the second terminal group TMG2 will be referred to as the "signal group NB_pkt." The logic control circuit 102 transmits and receives the signal group NB_pkt to and from the memory controller 20 via the second terminal group TMG2. More specifically, the logic control circuit 102 receives the signal CA_CE# and the signal CA_CLK from the memory controller 20. Furthermore, the logic control circuit 102 transmits and receives the signal CA1 and the signal CA0 to and from the memory controller 20. For example, the signals CA1, CA0, and CA_CLK are used for input and output of data packets, which will be described later. Therefore, the signal group NB_pkt is used for input and output of data packets.

[0051] The signal CA_CE# is a signal for enabling the memory chip 11. The signal CA_CE# is set to be active at, for example, the "L" level.

[0052] Signals CA0 and CA1 are signals indicating information other than data DAT, such as a command CMD, an address ADD, status information STS, or information related to set values ​​for various operations. Signals CA0 and CA1 will be described later.

[0053] Signal CA_CLK is a selection signal for signals CA0 and CA1. For example, logic control circuit 102 receives signals CA0 and CA1 at rising and falling edges of signal CA_CLK.

[0054] The logic control circuit 102 is connected to the input / output circuit 101, the address register 103, the command register 104, the status register 105, and the sequencer 106. The logic control circuit 102 sends an address ADD to the address register 103. The logic control circuit 102 sends a command CMD to the command register 104. The logic control circuit 102 receives status information STS from the status register 105. For example, the status information STS includes information regarding the results of write operations, read operations, and erase operations. Furthermore, the logic control circuit 102 receives information regarding various settings such as voltages from registers (not shown) within the sequencer 106.

[0055] The address register 103 temporarily stores the address ADD. The address register 103 is connected to the logic control circuit 102, the sequencer 106, the row decoder 111, and the column decoder 114. The address ADD includes the row address RAD and the column address CAD. The address register 103 transmits the row address RAD to the row decoder 111. Furthermore, the address register 103 transmits the column address CAD to the column decoder 114.

[0056] The command register 104 is a register for temporarily storing a command CMD. The command register 104 is connected to the logic control circuit 102 and the sequencer 106. The command register 104 transmits the command CMD to the sequencer 106.

[0057] The status register 105 is a register that temporarily stores status information STS. The status register 105 is connected to the logic control circuit 102 and the sequencer 106. The status register 105 receives status information STS from the sequencer 106.

[0058] The sequencer 106 is a circuit that controls the overall operation of the memory chip 11. The sequencer 106 is connected to the logic control circuit 102, the address register 103, the command register 104, the status register 105, the ready / busy circuit 107, the voltage generating circuit 108, the row decoder 111, and the sense amplifier 112. The sequencer 106 controls the status register 105, the ready / busy circuit 107, the voltage generating circuit 108, the row decoder 111, and the sense amplifier 112. The sequencer 106 executes write, read, and erase operations based on the command CMD.

[0059] The ready / busy circuit 107 is a circuit that generates the signal R / B_n. The signal R / B_n is a signal indicating whether the memory chip 11 is in a state (ready state) in which it can receive the command CMD from the memory controller 20, or in a state (busy state) in which it cannot receive the command CMD. For example, the signal R / B_n is set to an "L" level when the memory chip 11 is in a busy state. For example, the ready / busy circuit 107 is connected to the sequencer 106. The ready / busy circuit 107 generates the signal R / B_n based on the control of the sequencer 106. The ready / busy circuit 107 is connected to the NAND bus NB, that is, the memory controller 20, via the terminal TM. The ready / busy circuit 107 sends the signal R / B_n to the memory controller 20.

[0060] The voltage generating circuit 108 generates various voltages used in programming, reading, and erasing operations based on control of the sequencer 106. The voltage generating circuit 108 supplies various voltages to the memory cell array 110, the row decoder 111, the sense amplifier 112, and the like.

[0061] The memory cell array 110 is a collection of a plurality of arranged memory cell transistors (also referred to as "memory cells"). The memory cell array 110 includes a plurality of blocks BLK. A block BLK is, for example, a collection of a plurality of memory cell transistors from which data is erased collectively. Figure 2 In the example shown, the memory cell array 110 includes four blocks BLK0, BLK1, BLK2, and BLK3. The number of blocks BLK in the memory cell array 110 is arbitrary.

[0062] The row decoder 111 is a circuit that decodes the row address RAD. It is connected to the address register 103, the sequencer 106, the voltage generation circuit 108, and the memory cell array 110. Based on the decoded row address RAD, the row decoder 111 selects a block BLK. The row decoder 111 applies a voltage to the row-direction wiring (the word lines and select gate lines described later) of the selected block BLK.

[0063] Sense amplifier 112 is a circuit that writes and reads data. Sense amplifier 112 is connected to sequencer 106, voltage generator circuit 108, memory cell array 110, and data register 113. During a read operation, sense amplifier 112 reads data from memory cell array 110. During a write operation, sense amplifier 112 supplies a voltage corresponding to the write data to memory cell array 110.

[0064] The data register 113 is a register that temporarily stores data DAT. The data register 113 is connected to the input / output circuit 101, the sequencer 106, the sense amplifier 112, and the column decoder 114. The data register 113 includes a plurality of latch circuits. Each latch circuit temporarily stores write data or read data.

[0065] The column decoder 114 is a circuit that decodes the column address CAD. The column decoder 114 is connected to the address register 103, the sequencer 106, and the data register 113. The column decoder 114 receives the column address CAD from the address register 103. Based on the result of decoding the column address CAD, the column decoder 114 selects a latch circuit within the data register 113.

[0066] 1.1.3 Circuit Structure of Memory Cell Array

[0067] Next, refer to Figure 3 , an example of the circuit structure of the memory cell array 110 is described. Figure 3 is a circuit diagram of the memory cell array 110. In addition, Figure 3 The example shown shows the circuit configuration of one block BLK.

[0068] like Figure 3As shown, the block BLK includes a plurality of string units SU. The string unit SU is, for example, a collection of a plurality of NAND strings NS selected together in a write operation or a read operation. Figure 3 In the example shown, the block BLK includes four string units SU0 to SU3. The number of string units SU included in the block BLK is arbitrary.

[0069] Next, the internal structure of the string unit SU is described. A string unit SU includes multiple NAND strings NS. NAND strings NS include multiple memory cell transistors MC connected in series. For example, m+1 (m is an integer greater than or equal to 1) NAND strings NS within a string unit SU are each connected to m+1 bit lines BL0 to BLm.

[0070] Next, the internal structure of the NAND string NS is described. Each NAND string NS includes a plurality of memory cell transistors MC and selection transistors ST1 and ST2. Figure 3 In the example shown, NAND string NS includes eight memory cell transistors MC0 to MC7. The number of memory cell transistors MC in NAND string NS is arbitrary.

[0071] Memory cell transistor MC stores data in a nonvolatile manner. Memory cell transistor MC includes a control gate and a charge storage layer. Memory cell transistor MC can be either a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or an FG (Floating Gate) type. MONOS uses an insulating layer in the charge storage layer. FG uses a conductive layer in the charge storage layer.

[0072] The selection transistors ST1 and ST2 are used to select the string unit SU during various operations. The number of selection transistors ST1 and ST2 is arbitrary. It is sufficient that at least one selection transistor ST1 and ST2 is included in the NAND string NS.

[0073] The current paths of the memory cell transistors MC and select transistors ST1 and ST2 within each NAND string NS are connected in series. More specifically, the current paths of select transistor ST2, memory cell transistors MC0-MC7, and select transistor ST1 are connected in series in this order. The drain of select transistor ST1 is connected to any bit line BL. The source of select transistor ST2 is connected to source line SL.

[0074] The control gates of multiple memory cell transistors MC0-MC7 within the same block BLK are commonly connected to word lines WL0-WL7. More specifically, for example, block BLK includes four string units SU0-SU3. Furthermore, each string unit SU0-SU3 includes multiple memory cell transistors MC0. The control gates of these multiple memory cell transistors MC0 within block BLK are commonly connected to a single word line WL0. The same applies to memory cell transistors MC1-MC7.

[0075] The gates of the multiple select transistors ST1 within a string unit SU are commonly connected to a single select gate line SGD. More specifically, string unit SU0 includes multiple select transistors ST1. The gates of the multiple select transistors ST1 within string unit SU0 are commonly connected to select gate line SGD0. Similarly, the gates of the multiple select transistors ST1 within string unit SU1 are commonly connected to select gate line SGD1. The gates of the multiple select transistors ST1 within string unit SU2 are commonly connected to select gate line SGD2. The gates of the multiple select transistors ST1 within string unit SU3 are commonly connected to select gate line SGD3.

[0076] The gates of multiple select transistors ST2 within the same block BLK are commonly connected to a single select gate line SGS. More specifically, for example, block BLK includes four string units SU0-SU3. Furthermore, each string unit SU0-SU3 includes multiple select transistors ST2. The gates of these multiple select transistors ST2 within block BLK are commonly connected to a single select gate line SGS. Furthermore, similar to the select gate line SGD, a different select gate line SGS can be provided for each string unit SU.

[0077] Word lines WL0 to WL7 , select gate lines SGD0 to SGD3 , and select gate line SGS are respectively connected to the row decoder 111 .

[0078] The bit line BL is commonly connected to one NAND string NS in each string unit SU of each block BLK. The same column address CAD is assigned to the multiple NAND strings NS connected to one bit line BL. Each bit line BL is connected to a sense amplifier 112.

[0079] The source line SL is shared by, for example, a plurality of blocks BLK.

[0080] In one string unit SU, a collection of multiple memory cell transistors MC connected to one word line WL is referred to as a "cell unit CU". In other words, the cell unit CU is a collection of multiple memory cell transistors MC selected together in a write operation or a read operation. A page is a unit of data written to (or read out together from) the cell unit CU. For example, when the memory cell transistor MC stores 1 bit of data, the storage capacity of the cell unit CU is 1 page. That is, the cell unit CU stores 1 page of data. Either 1 page of data is the same size as the data of the ECC frame, or 1 page of data contains multiple ECC frames. In addition, the cell unit CU can have a storage capacity of more than 2 pages based on the number of bits of data stored in the memory cell transistor MC.

[0081] 1.2 Sequence of Input and Output Actions

[0082] Next, the sequence of input and output operations between the memory controller 20 and the memory chip 11 will be described.

[0083] 1.2.1 Sequence of Data Packet Input Actions

[0084] First, refer to Figure 4 , an example of a sequence of input operations of a data packet PK is described. Figure 4 1 is a diagram showing an example of a sequence of input operations of a data packet PK. Figure 4 In the example shown, signals other than the signal group NB_pkt are omitted.

[0085] like Figure 4As shown, signals CA0 and CA1 are each 1-bit signals. Signals CA0 and CA1 are transmitted in sync with the timing of the rising and falling edges of signal CA_CLK. For example, during three cycles of signal CA_CLK, signals CA0 and CA1 are combined to transmit 12 bits of data. Hereinafter, the 12-bit data obtained by combining signals CA0 and CA1 is defined as a "data packet PK." Data packet PK includes 4 bits of data indicating the type of information and 8 bits of data indicating the content of the information. Examples of information types include commands CMD, addresses ADD, CA_Data_Output, SCE packets, and SCT packets. CA_Data_Output is a data output action using signals CA0 and CA1 (hereinafter also referred to as a "CA_Data_Output action"). The size of the data read out by the CA_Data_Output action is smaller than the data DAT (read data) read out from the memory cell array 110. Specifically, the CA_Data_Output action corresponds to reading status information STS from status register 105 or reading values ​​(information related to setting values ​​for various actions) from a register (not shown) in sequencer 106. The SCE packet indicates the start of data transfer using signal DQ. The SCT packet indicates the end of data transfer using signal DQ. Hereinafter, the 4-bit data indicating the type of information is referred to as the "packet header PH." The 8-bit data indicating the content of the information is referred to as the "packet body PB." That is, a packet PK consists of a combination of the packet header PH and the packet body PB.

[0086] The packet header PH is a 4-bit set consisting of the first two bits of signal CA0 and the first two bits of signal CA1 within the packet PK. Hereinafter, each bit of the packet header PH will be referred to as "header HD." More specifically, in each of signals CA0 and CA1, the first bit of the packet header PH will be referred to as "first header HD1." The second bit of the packet header PH will be referred to as "second header HD2."

[0087] The packet body PB is an 8-bit collection consisting of the last 4 bits of signal CA0 and signal CA1 within the packet PK. Hereinafter, each bit of the packet body PB is referred to as "body BD." More specifically, in each of signals CA0 and CA1, the first bit within the packet body PB is referred to as "first body BD1." The second bit within the packet body PB is referred to as "second body BD2." The third bit within the packet body PB is referred to as "third body BD3." The fourth bit within the packet body PB is referred to as "fourth body BD4."

[0088] The memory controller 20 first sets the signal CA_CE# corresponding to the target memory chip 11 to the “L” level. As a result, the target memory chip 11 is enabled.

[0089] The memory controller 20 sends the signal CA0 and the first header HD1 of the signal CA1 to the memory chip 11. The memory controller 20 also starts sending the signal CA_CLK to the memory chip 11. The memory chip 11 captures the first header HD1 in response to the rising edge of the signal CA_CLK at time t0.

[0090] Next, the memory controller 20 transmits the signal CA0 and the second header HD2 of the signal CA1 to the memory chip 11. The memory chip 11 captures the second header HD2 in response to the falling edge of the signal CA_CLK at time t1.

[0091] Next, the memory controller 20 transmits the signal CA0 and the first body BD1 of the signal CA1 to the memory chip 11. The memory chip 11 captures the first body BD1 in response to the rising edge of the signal CA_CLK at time t2.

[0092] Next, the memory controller 20 transmits the signal CA0 and the second body BD2 of the signal CA1 to the memory chip 11. The memory chip 11 captures the second body BD2 in response to the falling edge of the signal CA_CLK at time t3.

[0093] Next, the memory controller 20 transmits the third body BD3 of the signal CA0 and the signal CA1 to the memory chip 11. The memory chip 11 captures the third body BD3 in response to the rising edge of the signal CA_CLK at time t4.

[0094] Next, the memory controller 20 transmits the fourth body BD4 of the signal CA0 and the signal CA1 to the memory chip 11. The memory chip 11 captures the fourth body BD4 in response to the falling edge of the signal CA_CLK at time t5.

[0095] For example, when transmission of the data packet PK is completed, the memory controller 20 sets the signal CA_CE# to a High (“H”) level.

[0096] The signal group NB_dat (signals DQ, DQS and DQS_c, and RE_t and RE_c) is not used for inputting data packets PK (commands CMD, addresses ADD, SCE and SCT packets, etc.). Therefore, the inputting of data packets PK (commands CMD, addresses ADD, SCE and SCT packets, etc.) can be performed in parallel with the inputting and outputting of data DAT using the signal group NB_dat.

[0097] 1.2.2 CA_Data_Output Action Sequence

[0098] Next, refer to Figure 5 , as an example of the CA_Data_Output action, the sequence of the output action of the status information STS is explained. Figure 5 : is a diagram showing an example of a sequence of output operations of the status information STS. Figure 5 In the example shown, signals other than the signal group NB_pkt are omitted.

[0099] like Figure 5 As shown, the memory controller 20 first sets the signal CA_CE# corresponding to the target memory chip 11 to an "L" level. This enables the target memory chip 11. Next, from time t10 to t15, the memory controller 20 executes an input operation for a data packet PK (PK(CMD)) corresponding to the command CMD instructing the execution of the CA_Data_Output operation.

[0100] More specifically, first, at time t10 , for example, the first header HD1 of the signal CA0 indicating “0” and the first header HD1 of the signal CA1 indicating “0” are input to the memory chip 11 .

[0101] Next, at time t11, the second header HD2 of the signal CA0 indicating "1" and the second header HD2 of the signal CA1 indicating "1" are input to the memory chip 11. For example, a packet header PH of "0," "0," "1," "1" indicates that the next packet body PB to be input is a command CMD.

[0102] Next, between times t12 and t15, the data packet body PB of the command CMD is input to the memory chip 11. At this time, for example, the data packet body PB corresponding to the status information STS is input. Furthermore, when reading values ​​from the sequencer 106, a different data packet body PB is input. More specifically, at time t12, the signal CA0 and the first body BD1 of the signal CA1 are input to the memory chip 11. Next, at time t13, the signal CA0 and the second body BD2 of the signal CA1 are input to the memory chip 11. Next, at time t14, the signal CA0 and the third body BD3 of the signal CA1 are input to the memory chip 11. Next, at time t15, the signal CA0 and the fourth body BD4 of the signal CA1 are input to the memory chip 11.

[0103] Next, during the period from time t16 to time t21, the input operation of the data packet PK (PK(ADD)) corresponding to the address ADD is executed.

[0104] More specifically, first, at time t16 , for example, the first header HD1 of the signal CA0 indicating “0” and the first header HD1 of the signal CA1 indicating “0” are input to the memory chip 11 .

[0105] Next, at time t17, the second header HD2 of the signal CA0 indicating "0" and the second header HD2 of the signal CA1 indicating "1" are input to the memory chip 11. For example, a packet header PH of "0," "0," "0," "1" indicates that the next packet body PB to be input is the address ADD.

[0106] Next, between times t18 and t21, a data packet body PB with address ADD is input to memory chip 11. More specifically, at time t18, signal CA0 and the first body BD1 of signal CA1 are input to memory chip 11. Next, at time t19, signal CA0 and the second body BD2 of signal CA1 are input to memory chip 11. Next, at time t20, signal CA0 and the third body BD3 of signal CA1 are input to memory chip 11. Next, at time t21, signal CA0 and the fourth body BD4 of signal CA1 are input to memory chip 11.

[0107] When the input of the address ADD is completed at time t21, the sequencer 106 starts to read the status information STS from the target address of the status register 105 to the logic control circuit 102. When a value is read from the sequencer 106, the read operation from the sequencer 106 to the logic control circuit 102 is started.

[0108] During the period from time t21 to time t22, a read operation is performed to the logic control circuit 102. The value read from the logic control circuit 102 (in this example, the status information STS) is stored in a register (not shown) of the logic control circuit 102.

[0109] During the period from time t22 to time t23 , the memory controller 20 transmits a data packet header PH (PH(STT)) instructing output of a value read to the logic control circuit 102 to the memory chip 11 .

[0110] More specifically, first, at time t22 , for example, the first header HD1 of the signal CA0 indicating “0” and the first header HD1 of the signal CA1 indicating “0” are input to the memory chip 11 .

[0111] Next, at time t23, the second header HD2 of the signal CA0 indicating "0" and the second header HD2 of the signal CA1 indicating "0" are input to the memory chip 11. For example, the packet header PH of "0," "0," "0," "0" indicates the output of the value to be read to the logic control circuit 102.

[0112] The period from time t23 to t24 is a standby period (period tW2R) for switching the input and output of signals CA0 and CA1. Signals CA0 and CA1 from time t10 to t23 are input signals to memory chip 11. In contrast, signals CA0 and CA1 from time t24 onward are output signals from memory chip 11.

[0113] Next, the memory controller 20 sends the signal CA_CLK to the memory chip 11, specifying the timing for outputting the status information STS. More specifically, at time t24, the memory controller 20 sends the signal CA_CLK at an "H" level to the memory chip 11. Furthermore, at time t25, the memory controller 20 sends the signal CA_CLK at an "L" level to the memory chip 11. After time t24, the memory controller 20 repeats the toggling of the signal CA_CLK (switching between the "L" and "H" levels) four times.

[0114] The value read to logic control circuit 102 is output based on signal CA_CLK. Logic control circuit 102 outputs signal CA1 as the value read to logic control circuit 102. In addition, logic control circuit 102 outputs signal CA0 as a strobe signal for signal CA1. Logic control circuit 102 generates signal CA0 based on signal CA_CLK.

[0115] The value read into logic control circuit 102 is output as signal CA1 in sync with the rising and falling timing of signal CA0. The 8-bit data packet body PB output as signal CA1 corresponds to the 8-bit data output. Furthermore, signal CA1 is output in sync with the rising or falling edge of signal CA0. Therefore, even when signal CA1 continuously outputs "0" or "1," data division (separation) can be determined.

[0116] When the output of the 8-bit data packet body PB (signal CA1) is completed, the memory controller 20 sets the signal CA_CE# to "H." This completes the CA_Data_Output operation. When the CA_Data_Output operation is complete, signals CA0 and CA1 return (switch) from output signals to input signals to the memory chip 11. Furthermore, if the output value is larger than 8 bits, the 8-bit data packet body PB can be output multiple times consecutively.

[0117] The signal group NB_dat is not used in the CA_Data_Output action. Therefore, the CA_Data_Output action can be executed in parallel with the input and output of the data DAT using the signal group NB_dat.

[0118] 1.2.3 Sequence of Data Input Actions

[0119] Next, refer to Figure 6 , an example of a sequence of input operations for data DAT is described. Figure 6 1 is a diagram showing an example of a sequence of input operations of data DAT. In the following description, the input data in data DAT that is input from the memory controller 20 to the memory chip 11 is referred to as "input data DIN". For example, the input data DIN is write data. In addition, Figure 6 In the example shown, the signal DQS_c, the signal CA_CE#, the signal RE_c, and the signal R / B_n are omitted. Figure 6 In the example shown, for simplicity of description, the command CMD and the address ADD, which instruct execution of an input operation (for example, a write operation) of the input data DIN, are omitted.

[0120] like Figure 6 As shown, first, during the period from time t30 to time t31, the memory controller 20 sends an SCE data packet ( Figure 6 In accordance with the rising and falling edges of the signal CA_CLK, a packet header PH and a packet body PB corresponding to the SCE packet are input to the memory chip 11.

[0121] At time t32 , the memory controller 20 sets the signal DQS to “L” level.

[0122] From time t33 to t35, the memory controller 20 repeatedly toggles the signal DQS while transmitting the signal DQ corresponding to the input data DIN to the memory chip 11. In other words, the input data DIN is input to the input / output circuit 101. Hereinafter, the period from the transmission of the SCE packet to the start of data transfer is also referred to as the "preamble period." For example, the period from time t31 to t33 is the preamble period.

[0123] During the period from time t34 to time t36, the memory controller 20 sends an SCT packet to the memory chip 11 ( Figure 6 The SCT (DIN) shown in Figure 1 is a 10-bit byte. In sync with the rising and falling edges of the CA_CLK signal, the packet header PH and packet body PB corresponding to the SCT packet are input to the memory chip 11. During the period from time t34 to t35, the input data DIN and the SCT packet are input in parallel. Hereinafter, the period from the end of data transfer to the completion of SCT packet transmission is also referred to as the "postamble period." For example, the period from time t35 to t36 is the postamble period.

[0124] 1.2.4 Sequence of Data Output Actions

[0125] Next, refer to Figure 7 , an example of a sequence of output operations of data DAT is described. Figure 7 1 is a diagram showing an example of a sequence of output operations of data DAT. In the following description, the output data output from the memory chip 11 to the memory controller 20 in the data DAT is referred to as "output data DOUT". For example, the output data DOUT is read data. In addition, Figure 7 In the example shown, the signal DQS_c, the signal CA_CE#, the signal RE_c, and the signal R / B_n are omitted. Figure 7 In the example shown, for simplicity of description, the command CMD and the address ADD, which instruct execution of an output operation (for example, a read operation) of the output data DOUT, are omitted.

[0126] like Figure 7 As shown, first, during the period from time t40 to t41, the memory controller 20 sends an SCE data packet ( Figure 7 In accordance with the rising and falling edges of the signal CA_CLK, a packet header PH and a packet body PB corresponding to the SCE packet are input to the memory chip 11.

[0127] At time t42 , the memory controller 20 sets the signal RE_t to “L” level (sets the signal RE_c to “H” level).

[0128] At time t43 , the memory controller 20 sets the signal DQS to “L” level.

[0129] At time t44, the memory controller 20 begins toggling signal RE_t (and signal RE_c). From time t44 to t47, the memory controller 20 repeatedly toggles signal RE_t (and signal RE_c). The memory chip 11 generates signal DQS (and signal DQS_c) based on signal RE_t (and signal RE_c).

[0130] During the period from time t45 to time t48, the memory chip 11 repeatedly toggles the signal DQS and transmits the signal DQ corresponding to the output data DOUT to the memory controller 20. For example, the period from time t41 to time t45 is a preamble period.

[0131] During the period from time t46 to time t49, the memory controller 20 sends an SCT packet to the memory chip 11 ( Figure 7 In conjunction with the rising and falling edges of the CA_CLK signal, the packet header PH and packet body PB corresponding to the SCT packet are input to the memory chip 11. During the period from time t46 to t48, the output data DOUT and the input of the SCT packet are performed in parallel. For example, time t48 to t49 is the postamble period.

[0132] 1.3 Sequence when multiple data transfer operations are performed continuously

[0133] Next, a description will be given of a sequence in which the data DAT transfer operation (input operation and output operation) is performed multiple times in succession.

[0134] In this embodiment, when multiple data DAT transfer operations (input and output operations) are performed consecutively, the memory controller 20 sends an SCT packet to the memory chip 11 only at the end of the last transfer operation. In other words, the memory controller 20 omits the transmission of an SCT packet in transfer operations other than the last transfer operation and instead transmits an SCE packet corresponding to the next transfer operation. More specifically, for example, when the memory controller 20 performs two consecutive data DAT transfer operations, it omits the transmission of an SCT packet corresponding to the first transfer operation and instead transmits an SCE packet corresponding to the second transfer operation. Upon receiving the SCE packet corresponding to the second transfer operation, the memory chip 11 recognizes the end of the first transfer operation and prepares for the next transfer operation.

[0135] 1.3.1 Sequence when two data input actions are executed consecutively

[0136] Next, refer to Figure 8 , an example of a sequence in which the input operation of the data DAT is performed twice continuously will be described. Figure 8 This is a diagram showing an example of a sequence in which the operation of inputting data DAT is performed twice in succession. Figure 8 The input operation of input data DIN1 and the input operation of input data DIN2 are shown as being executed consecutively. For example, input data DIN1 and input data DIN2 correspond to write operations of different pages. Figure 8 In the example shown, the signal DQS_c, the signal CA_CE#, the signal RE_c, and the signal R / B_n are omitted. Figure 8 In the illustrated example, for simplicity of description, the command CMD and the address ADD, which instruct the execution of the input operation (for example, the write operation) of the data DAT, are omitted.

[0137] like Figure 8 As shown, the memory controller 20 first performs the input operation of the input data DIN1. During the period from time t50 to t51, the memory controller 20 sends the SCE data packet ( Figure 8 SCE (DIN1) shown). Data packet input operation and use during time t50 to t51 Figure 6 The packet input operation during the period from time t30 to time t31 described above is the same.

[0138] At time t52 , the memory controller 20 sets the signal DQS to “L” level.

[0139] During the period from time t53 to t55, the memory controller 20 repeatedly triggers the signal DQS and transmits the signal DQ corresponding to the input data DIN1 to the memory chip 11. That is, the input data DIN1 is input to the input / output circuit 101. Figure 6 The data input operation during the time period from t33 to t35 described above is the same.

[0140] During the period from time t54 to time t56, similarly to the period from time t50 to time t51, the memory controller 20 transmits an SCE packet corresponding to the input data DIN2 to the memory chip 11 ( Figure 8In other words, the transmission of the SCT packet corresponding to the input data DIN1 is omitted. During the period from time t54 to t55, the input of the input data DIN1 and the input of the SCE packet corresponding to the input data DIN2 are executed in parallel.

[0141] The period from time t55 to time t57 is a standby period from the completion of input of input data DIN1 to the start of input of input data DIN2 in the signal DQ.

[0142] During the period from time t57 to t59, similarly to the period from time t53 to t55, the memory controller 20 repeatedly toggles the signal DQS and transmits the signal DQ corresponding to the input data DIN2 to the memory chip 11. That is, the input data DIN2 is input to the input / output circuit 101.

[0143] During the period from time t58 to time t60, the memory controller 20 sends an SCT data packet corresponding to the input data DIN2 to the memory chip 11 ( Figure 8 SCT (DIN2) shown). Data packet input operation and use during time t58 to t60 Figure 6 The packet input operation during the time period t34 to t36 described above is the same. During the time period t58 to t59, the input data DIN2 and the SCT packet are input in parallel.

[0144] 1.3.2 Sequence when executing two consecutive data output actions

[0145] Next, refer to Figure 9 , an example of a sequence in which the output operation of the data DAT is performed twice continuously will be described. Figure 9 This is a diagram showing an example of a sequence in which the output operation of the data DAT is performed twice in succession. Figure 9 This shows a case where the output action of output data DOUT1 and the output action of output data DOUT2 are executed consecutively. For example, output data DOUT1 and output data DOUT2 correspond to read actions of different pages. Figure 9 In the example shown, the signal DQS_c, the signal CA_CE#, the signal RE_c, and the signal R / B_n are omitted. Figure 9 In the example shown, for simplicity of description, the command CMD and the address ADD, which instruct the execution of the output operation (for example, the read operation) of the data DAT, are omitted.

[0146] like Figure 9As shown, the memory controller 20 first performs the output operation of the output data DOUT1. During the period from time t70 to t71, the memory controller 20 sends the SCE data packet ( Figure 9 The data packet input operation and usage during time t70 to t71 Figure 7 The packet input operation during the period from time t40 to time t41 described above is the same.

[0147] At time t72 , the memory controller 20 sets the signal RE_t to “L” level (sets the signal RE_c to “H” level).

[0148] At time t73 , the memory controller 20 sets the signal DQS to “L” level.

[0149] At time t74, the memory controller 20 begins toggling signal RE_t (and signal RE_c). From time t74 to t77, the memory controller 20 repeatedly toggles signal RE_t (and signal RE_c). The memory chip 11 generates signal DQS (and signal DQS_c) based on signal RE_t (and signal RE_c).

[0150] During the period from time t75 to t78, the memory chip 11 repeatedly toggles the signal DQS and transmits the signal DQ corresponding to the output data DOUT1 to the memory controller 20. Figure 7 The data output operation during the period from time t45 to time t48 described above is the same.

[0151] During the period from time t76 to time t79, similarly to the period from time t70 to time t71, the memory controller 20 transmits an SCE packet corresponding to the output data DOUT2 to the memory chip 11 ( Figure 9 In other words, the transmission of the SCT packet corresponding to the output data DOUT1 is omitted. During the period from time t76 to t78, the output of the output data DOUT1 and the input of the SCE packet corresponding to the output data DOUT2 are performed in parallel.

[0152] During the period from time t80 to time t83, the memory controller 20 repeatedly toggles the signal RE_t (and the signal RE_c) similarly to the period from time t74 to time t77. The memory chip 11 generates the signal DQS (and the signal DQS_c) based on the signal RE_t (and the signal RE_c).

[0153] The period from time t78 to time t81 is a standby period from the completion of output of the output data DOUT1 to the start of output of the output data DOUT2 in the signal DQ.

[0154] During the period from time t81 to time t84 , similarly to the period from time t75 to time t78 , the memory chip 11 transmits the signal DQ corresponding to the output data DOUT2 to the memory controller 20 while repeatedly toggling the signal DQS.

[0155] During the period from time t82 to time t85, the memory controller 20 sends an SCT packet corresponding to the output data DOUT2 to the memory chip 11 ( Figure 9 SCT (DOUT2) shown). Data packet input operation and use during time t82 to t85 Figure 7 The packet input operation during the time period t46 to t49 described above is the same. During the time period t82 to t84, the output of the output data DOUT2 and the input of the SCT packet are performed in parallel.

[0156] 1.3.3 Sequence of Continuous Data Input and Output

[0157] Next, refer to Figure 10 , an example of a sequence in which an input operation and an output operation of data DAT are continuously executed will be described. Figure 10 This is a diagram showing an example of a sequence in which the input operation and the output operation of the data DAT are continuously executed. Figure 10 It shows the case where the input action of input data DIN1 and the output action of output data DOUT2 are executed continuously. Figure 10 In the example shown, the signal DQS_c, the signal CA_CE#, the signal RE_c, and the signal R / B_n are omitted. Figure 10 In the example shown, for simplicity of description, the command CMD and the address ADD, etc., which instruct the execution of the transfer operation (input operation and output operation) of the data DAT, are omitted.

[0158] like Figure 10 As shown, the memory controller 20 first performs the input operation of the input data DIN1. The input operation of the input data DIN1 performed during the period of time t90 to t95 is the same as that performed using Figure 8 The input operation of the input data DIN1 during the period from time t50 to time t55 described above is the same.

[0159] During the period from time t94 to time t96, the memory controller 20 sends an SCE packet corresponding to the output data DOUT2 to the memory chip 11 ( Figure 10In other words, the transmission of the SCT packet corresponding to the input data DIN1 is omitted. During the period from time t94 to t95, the input of the input data DIN1 and the input of the SCE packet corresponding to the output data DOUT2 are executed in parallel.

[0160] At time t97 , the memory controller 20 sets the signal RE_t to “L” level (sets the signal RE_c to “H” level).

[0161] During the period from time t98 to t101, Figure 9 Similarly, during the period from time t80 to time t83 described above, the memory controller 20 repeatedly toggles the signal RE_t (and the signal RE_c). The memory chip 11 generates the signal DQS (and the signal DQS_c) based on the signal RE_t (and the signal RE_c).

[0162] The period from time t95 to time t99 is a standby period from the completion of input of the input data DIN1 to the start of output of the output data DOUT2 in the signal DQ.

[0163] During the period from time t99 to t102, Figure 9 Similarly, during the period from time t81 to time t84 described above, the memory chip 11 transmits the signal DQ corresponding to the output data DOUT2 to the memory controller 20 while repeatedly toggling the signal DQS.

[0164] During the period from time t100 to time t103, the memory controller 20 sends an SCT data packet corresponding to the output data DOUT2 to the memory chip 11 ( Figure 10 During the period from time t100 to time t102, the output of the output data DOUT2 and the input of the SCT data packet are executed in parallel.

[0165] 1.3.4 Sequence of Continuously Executing Data Output and Input Actions

[0166] Next, refer to Figure 11 , an example of a sequence in which the output action and the input action of the data DAT are continuously executed will be described. Figure 11 This is a diagram showing an example of a sequence in which the output operation and the input operation of the data DAT are continuously executed. Figure 11 It shows the case where the output action of the output data DOUT1 and the input action of the input data DIN2 are executed continuously. Figure 11 In the example shown, the signal DQS_c, the signal CA_CE#, the signal RE_c, and the signal R / B_n are omitted. Figure 11In the example shown, for simplicity of description, the command CMD and the address ADD, etc., which instruct the execution of the transfer operation (input operation and output operation) of the data DAT, are omitted.

[0167] like Figure 11 As shown, the memory controller 20 first performs the output operation of the output data DOUT1. The output operation of the output data DOUT1 performed during the period t110 to t118 is the same as that performed using Figure 9 The output operation of the output data DOUT1 during the time period t70 to t78 described above is the same.

[0168] During the period from time t116 to time t119, the memory controller 20 sends an SCE data packet corresponding to the input data DIN2 to the memory chip 11 ( Figure 11 In other words, the transmission of the SCT packet corresponding to the output data DOUT1 is omitted. During the period from time t116 to time t118, the output of the output data DOUT1 and the input of the SCE packet corresponding to the input data DIN2 are performed in parallel.

[0169] At time t120 , the memory controller 20 sets the signal RE_t to “H” level (sets the signal RE_c to “L” level).

[0170] The period from time t118 to time t121 is a standby period from the completion of output of the output data DOUT1 to the start of input of the input data DIN2 in the signal DQ.

[0171] During the period from time t121 to t123, Figure 8 Similarly, during the period from time t57 to time t59 described above, the memory controller 20 repeatedly toggles the signal DQS and transmits the signal DQ corresponding to the input data DIN2 to the memory chip 11. That is, the input data DIN2 is input to the input / output circuit 101.

[0172] During the period from time t122 ​​to time t124, the memory controller 20 sends an SCT data packet corresponding to the input data DIN2 to the memory chip 11 ( Figure 11 During the period from time t122 ​​to time t123, the input of the input data DIN2 and the input of the SCT data packet are executed in parallel.

[0173] 1.4 Effects of this embodiment

[0174] According to the configuration of this embodiment, the storage system 1 can improve the processing capacity of data transfer. This effect will be described in detail.

[0175] When the SCA protocol is used for communication between the memory controller 20 and the memory chip 11, the memory controller 20 can concurrently transmit and receive data DAT and send data packets PK (such as commands CMD, addresses ADD, SCE packets, and SCT packets). In this case, the signal DQ corresponding to the data DAT and the signals CA0 and CA2 corresponding to the data packets PK are transmitted between the memory controller 20 and the memory chip 11 via separate signal lines. For example, when transferring data DAT between the memory controller 20 and the memory chip 11, the memory controller 20 transmits an SCE packet indicating the start of the data DAT transfer and an SCT packet indicating the end of the data DAT transfer to the memory chip 11. For example, when transferring data DAT twice in succession, the memory controller 20 transmits an SCT packet corresponding to the first transfer and an SCE packet corresponding to the second transfer between the first and second transfers. Therefore, in the signal line corresponding to the signal DQ, a standby period caused by the transmission of the SCT packet and the SCE packet occurs between the transmission of the data DAT corresponding to the first transmission action and the transmission of the data DAT corresponding to the second transmission action, and the data transmission processing capacity is reduced.

[0176] In contrast, with the configuration of this embodiment, when multiple data DAT transfer operations are executed consecutively, the memory controller 20 can send an SCT packet to the memory chip 11 only at the end of the last transfer operation. In other words, the memory controller 20 can omit the transmission of the SCT packet in transfer operations other than the last transfer operation and instead transmit the SCE packet for the next transfer operation. This shortens the standby period between data transmissions on the DQ signal. In other words, the data transfer processing capacity of the memory system 1 can be improved.

[0177] 2. Second Implementation

[0178] Next, the second embodiment will be described. In the second embodiment, the configuration of the storage system 1 will be described, which is different from the first embodiment. The following description will focus on the differences from the first embodiment.

[0179] 2.1 Storage System Composition

[0180] First, refer to Figure 12 , an example of the structure of the storage system 1 is described. Figure 12 1 is a block diagram showing an example of the overall configuration of the storage system 1. Figure 12 In the example shown, a part of the connection between each component is indicated by an arrow line, but the connection between each component is not limited to this. Figure 12 In the example shown, the signal R / B_n transmitted via the NAND bus NB is omitted for simplicity of description.

[0181] like Figure 12 As shown, the memory system 1 includes a non-volatile memory 10 , a memory controller 20 and a bridge chip 30 .

[0182] The configurations of the nonvolatile memory 10 and the memory controller 20 are the same as those in the first embodiment. In this embodiment, the memory controller 20 is connected to the nonvolatile memory 10 (memory chip 11 ) via the bridge chip 30 .

[0183] The bridge chip 30 is an interface chip provided between the memory controller 20 and the nonvolatile memory 10. The bridge chip 30 controls communication between the memory controller 20 and the nonvolatile memory 10. The bridge chip 30 is connected to, for example, one channel CH of the memory controller 20 via a NAND bus NB. Furthermore, the bridge chip 30 has multiple channels CH corresponding to connections with the nonvolatile memory 10. Each channel CH of the bridge chip 30 is connected to a NAND bus NB. One or more memory chips 11 are connected to each NAND bus NB connecting the bridge chip 30 and the nonvolatile memory 10. Figure 12 In the example shown, the bridge chip 30 is connected to the channel CH0 of the memory controller 20 via the NAND bus NB. Furthermore, the bridge chip 30 has two channels, CH0a and CH0b. Multiple memory chips 11 are connected to each of the channels CH0a and CH0b of the bridge chip 30 via the NAND bus NB. Communication between the memory controller 20 and the bridge chip 30, as well as between the bridge chip 30 and the memory chips 11, complies with, for example, a DDR (double data rate) interface or ONFI (Open NAND flash interface).

[0184] For example, the bridge chip 30 includes a RAM (data buffer) (not shown). By storing data DAT corresponding to each channel CH in the RAM, data transfer operations in each channel CH can be performed in parallel.

[0185] For example, the data transfer speed between the memory controller 20 and the bridge chip 30 is set to N times (N is an integer greater than 1) the data transfer speed between the bridge chip 30 and the memory chips 11. This speeds up data transfer between the memory controller 20 and the plurality of memory chips 11.

[0186] 2.2 Sequence when multiple data transfer operations are performed continuously

[0187] Next, refer to Figure 13 , an example of a sequence in which a plurality of data DAT transfer operations (input operations and output operations) are performed continuously will be described. Figure 13 1 is a diagram showing an example of a sequence in which the output operation of the data DAT in the memory chip 11 connected to the channel CH0a of the bridge chip 30 and the memory chip 11 connected to the channel CH0b is executed multiple times in succession. Figure 13 In the example shown, the signal group NB_pkt corresponding to the data packet PK and the signal group NB_dat corresponding to the data DAT are shown, and the specific signals corresponding to each signal group (signals DQ, DQS, DQS_c, CA_CE#, CA0, CA1, CA_CLK, RE_t, and RE_c), and the signal R / B_n are omitted. Figure 13 In the example shown, for simplicity of description, the command CMD and the address ADD, which instruct the execution of the output operation (for example, the read operation) of the data DAT, are omitted.

[0188] In this embodiment, when a data DAT transmission operation is performed between the storage controller 20 and the bridge chip 30, as shown in FIG. Figure 6 as well as Figure 7 As explained above, the memory controller 20 sends the SCE data packet and the SCT data packet to the bridge chip 30. In addition, when the data DAT transmission operation is performed multiple times between the memory controller 20 and the bridge chip 30, as shown in FIG. Figures 8 to 11 As described above, the SCT packets between consecutive transfer operations are omitted, and the memory controller 20 sends the SCT packet to the bridge chip 30 only when the last transfer operation is completed.

[0189] On the other hand, when the data DAT is transferred between the bridge chip 30 and the memory chip 11 for a plurality of times, as shown in FIG. Figure 6 as well as Figure 7 As described above, the bridge chip 30 transmits an SCE packet and an SCT packet to the memory chip 11 for each transfer operation. That is, between successive transfer operations, the SCT packet corresponding to the previous transfer operation and the SCE packet corresponding to the next transfer operation are continuously transmitted.

[0190] like Figure 13As shown, for example, the output operations of output data DOUT01 and output data DOUT02 are performed sequentially between the bridge chip 30 and the memory chip 11 connected to the channel CH0a of the bridge chip 30. At this time, the bridge chip 30 transmits an SCE packet and an SCT packet corresponding to output data DOUT01, and an SCE packet and an SCT packet corresponding to output data DOUT02, respectively, to the memory chip 11. That is, the SCT packet and the SCE packet are transmitted between the transmission of output data DOUT01 and the transmission of output data DOUT02.

[0191] For example, the output operations of output data DOUT11 and output data DOUT12 are executed sequentially between the bridge chip 30 and the memory chip 11 connected to channel CH0b of the bridge chip 30. At this time, the bridge chip 30 transmits the SCE packet and SCT packet corresponding to output data DOUT11, and the SCE packet and SCT packet corresponding to output data DOUT12, respectively, to the memory chip 11. In other words, the SCT packet and SCE packet are transmitted between the transmission of output data DOUT11 and the transmission of output data DOUT12. The transmission operations in channel CH0a and channel CH0b can be at least partially executed in parallel.

[0192] Furthermore, at least partially in parallel with the above-described operations, the memory controller 20 and the bridge chip 30 successively execute the output operations for output data DOUT01, DOUT11, DOUT02, and DOUT12. At this time, the memory controller 20 transmits an SCE packet corresponding to output data DOUT01, an SCE packet corresponding to output data DOUT11, an SCE packet corresponding to output data DOUT02, and an SCE packet and SCT packet corresponding to output data DOUT11, respectively, to the bridge chip 30. Specifically, the SCT packet is omitted between consecutive transmission operations.

[0193] also, Figure 13 The example shown illustrates a case where the transfer operation is an output operation of data DAT, but the same applies to a case where the transfer operation is an input operation of data DAT. In addition, in the transfer operation between the bridge chip 30 and the memory chip 11, SCT packets may be omitted between consecutive transfer operations.

[0194] 2.3 Effects of this embodiment

[0195] With the configuration according to this embodiment, the same effects as those of the first embodiment can be obtained.

[0196] Furthermore, with the configuration of this embodiment, the storage system 1 can include a bridge chip 30 between the storage controller 20 and the memory chip 11. During data transfer between the storage controller 20 and the bridge chip 30, SCT packets can be omitted between consecutive transfer operations. Furthermore, the data transfer speed between the storage controller 20 and the bridge chip 30 can be set to N times the data transfer speed between the bridge chip 30 and the memory chip 11. This improves data transfer processing capabilities.

[0197] Furthermore, according to the configuration of this embodiment, the storage system 1 can utilize a data transfer method using an SCE packet and an SCT packet in each transfer operation in the data transfer operation between the bridge chip 30 and the memory chip 11 .

[0198] 3. Third Implementation Method

[0199] Next, the third embodiment will be described. In the third embodiment, the configuration of the storage system 1 will be described, which is different from the first and second embodiments. The following description will focus on the differences from the first and second embodiments.

[0200] 3.1 Storage System Composition

[0201] First, refer to Figure 14 , an example of the structure of the storage system 1 is described. Figure 14 1 is a block diagram showing an example of the overall configuration of the storage system 1. Figure 14 In the example shown, a part of the connection between each component is indicated by an arrow line, but the connection between each component is not limited to this. Figure 14 In the example shown, the signal R / B_n transmitted via the NAND bus NB is omitted for simplicity of description.

[0202] like Figure 14 As shown, the memory system 1 includes a non-volatile memory 10 , a memory controller 20 , and a bridge chip 30 .

[0203] The configurations of the nonvolatile memory 10 and the memory controller 20 are the same as those in the first embodiment. As in the second embodiment, the memory controller 20 is connected to the nonvolatile memory 10 (memory chip 11 ) via a plurality of channels CH of the bridge chip 30 .

[0204] The bridge chip 30 includes an SCE determination unit 31 , a data size setting unit 32 , a data counter 33 , a channel switch 34 , and RAMs 35 a and 35 b .

[0205] The SCE determination unit 31 receives the signal group NB_pkt (ie, signals CA_CE#, CA0, CA1, and CA_CLK) from the memory controller 20 via the NAND bus NB. If the packet PK is an SCE packet, the SCE determination unit 31 notifies the data counter 33 of the reception of the SCE packet.

[0206] The data size setting unit 32 sets the data size of the data DAT sent and received between the memory chip 11 connected to one channel CH and the memory controller 20, based on the control of the memory controller 20. In other words, the data size setting unit 32 sets the division position of the data between the switching channels CH0a and CH0b. The data size setting unit 32 sends the information of the set data size to the data counter 33. For example, in the case of a memory chip 11 with a large average data size per page, it takes time to transmit the entire page of data. Therefore, in such a memory chip 11, one page of data is divided into several frames, and only the necessary frames are read during the read operation, thereby reducing the data transmission time. This frame is a combination of data (user data) and error correction code, hereinafter referred to as an "ECC frame". Because the ECC frame contains the error correction code, the memory controller 20 can safely read data in units of ECC frames. The data size setting unit 32 sets the data size of the ECC frame through register settings.

[0207] The data counter 33 counts the number of bits of data DAT transmitted and received with the memory controller 20. When the count reaches the data size set by the data size setting unit 32, the data counter 33 instructs the channel switch 34 to switch the channel CH. The data size is dynamically switched by the data counter 33.

[0208] The channel switch 34 has a plurality of channels CH. Figure 14 In the example shown, the channel switch 34 has two channels, CH0a and CH0b. The two channels CH0a and CH0b are connected to the plurality of memory chips 11 via NAND buses NB connected to the two channels.

[0209] Channel switch 34 is connected to RAMs 35a and 35b corresponding to channels CH0a and CH0b, respectively. RAM 35a temporarily stores data DAT transmitted and received via channel CH0a. Similarly, RAM 35b temporarily stores data DAT transmitted and received via channel CH0b. Hereinafter, when neither RAM 35a nor RAM 35b is specified, they will be referred to as "RAM 35." The number of RAMs 35 connected to channel switch 34 is arbitrary. The number of RAMs 35 depends on the number of channels in channel switch 34.

[0210] The channel switch 34 transmits and receives the signal group NB_dat with the memory controller 20. Specifically, the channel switch 34 transmits and receives data DAT with the memory controller 20. The channel switch 34 selects one of the multiple RAMs 35 corresponding to the multiple channels CH to transmit and receive the corresponding data DAT with the memory controller 20. In other words, the channel switch 34 selects the RAM 35 with which to transmit and receive data DAT with the memory controller 20. The channel switch 34 switches channels CH, or RAM 35, based on control by the data counter 33. For example, if the memory chip 11 connected to channel CH0a and the memory chip 11 connected to channel CH0b each output output data DOUT, the channel switch 34 switches channels CH based on control by the data counter 33. Specifically, the channel switch 34 switches the RAM 35 that transmits the output data DOUT to the memory controller 20 based on the number of data counts. This allows the channel switch 34 to dynamically switch data between the multiple channels CH without requiring idle time between data DAT transfers.

[0211] 3.2 Sequence when multiple data output actions are executed continuously

[0212] Next, refer to Figure 15 as well as Figure 16 , an example of a sequence in which the output operation of the data DAT is performed multiple times in succession will be described. Figure 15 as well as Figure 16 This is a diagram showing an example of a case where output data DOUT is output from the bridge chip 30 to the memory controller 20 . Figure 15 as well as Figure 16 In the example shown, the bridge chip 30 continuously performs a plurality of data DAT output operations while alternately switching between the channel CH0 a and the channel CH0 b .

[0213] Figure 15 The example shown shows a case where the bridge chip 30 continuously outputs the output data DOUTa received from the memory chip 11 connected to the channel CH0a and the output data DOUTb received from the memory chip 11 connected to the channel CH0b to the memory controller 20. Figure 15 In the example shown, the signals DQ, DQS, and RE_t of the signal group NB_pkt and the signal group NB_dat corresponding to the data packet PK are shown, and other signals (signals DQS_c, RE_c, and R / B_n) are omitted.

[0214] In this embodiment, similar to the second embodiment, when a data DAT transfer operation is performed between the memory controller 20 and the bridge chip 30, the memory controller 20 sends an SCE packet and an SCT packet to the bridge chip 30. Furthermore, when multiple data DAT transfer operations are performed consecutively between the memory controller 20 and the bridge chip 30, the SCT packets between the consecutive transfer operations are omitted. Furthermore, the memory controller 20 sends an SCT packet to the bridge chip 30 only at the completion of the last transfer operation.

[0215] like Figure 15 As shown, first, at time t201, the memory controller 20 transmits a DO command (and corresponding data packet PK) to the bridge chip 30 via channel CH0, instructing the memory chip 11 connected to CH0a to output data DAT. The bridge chip 30 then transmits the DO command to the target memory chip 11 connected to channel CH0a.

[0216] Next, at time t202, the memory controller 20 transmits a DO command instructing the memory chip 11 connected to CH0b to output data DAT to the bridge chip 30 via channel CH0. The bridge chip 30 transmits the DO command to the target memory chip 11 connected to channel CH0b.

[0217] In the case of the data DAT output operation (read operation), the data DAT output from the memory chip 11 to the bridge chip 30 is started before the data DAT is output from the bridge chip 30 to the memory controller 20 .

[0218] More specifically, at time t203, before receiving an SCE packet from the memory controller 20, the bridge chip 30 issues an SCE packet and transmits it to the target memory chip 11 connected to channel CH0a. After transmitting the SCE packet, the bridge chip 30 sets signal RE_t to an "L" level. The bridge chip 30 then begins toggling signal RE_t. The target memory chip 11 connected to channel CH0a generates signal DQS based on signal RE_t. The target memory chip 11 connected to channel CH0a begins outputting signals DQ and DQS to the bridge chip 30. In other words, the target memory chip 11 connected to channel CH0a begins outputting output data DOUTa to the bridge chip 30. Output data DOUTa is stored in RAM 35a.

[0219] Next, at time t204, before receiving an SCE packet from the memory controller 20, the bridge chip 30 issues an SCE packet and transmits the SCE packet to the target memory chip 11 connected to channel CH0b. After transmitting the SCE packet and setting signal RE_t to an "L" level, the bridge chip 30 begins toggling signal RE_t. The target memory chip 11 connected to channel CH0b generates signal DQS based on signal RE_t. The target memory chip 11 connected to channel CH0b begins outputting signals DQ and DQS to the bridge chip 30. In other words, the target memory chip 11 connected to channel CH0b begins outputting output data DOUTb to the bridge chip 30. Output data DOUTb is stored in RAM 35b.

[0220] Next, at time t205, the memory controller 20 transmits an SCE packet corresponding to channel CH0a to the bridge chip 30 via channel CH0. The SCE determination unit 31 notifies the data counter 33 of receipt of the SCE packet corresponding to channel CH0a. The channel switch 34, under the control of the data counter 33, selects the RAM 35a corresponding to channel CH0a. Furthermore, after transmitting the SCE packet corresponding to channel CH0a and setting the RE_t signal to an "L" level, the memory controller 20 begins toggling the RE_t signal. The bridge chip 30 generates the DQS signal based on the RE_t signal. The bridge chip 30 selects the RAM 35a and begins outputting the DQ and DQS signals to the memory controller 20. In other words, the bridge chip 30 begins outputting the output data DOUTa from the RAM 35a to the memory controller 20. The data counter 33 counts the number of bits of the output data DOUTa outputted from the channel switch 34 to the memory controller 20.

[0221] Next, at time t206, while data counter 33 is counting the number of bits of output data DOUTa, memory controller 20 transmits an SCE packet corresponding to channel CH0b to bridge chip 30 via channel CH0. In other words, memory controller 20 can complete transmission of the SCE packet corresponding to the next data DAT before transmission of the previous data DAT is complete. SCE determination unit 31 notifies data counter 33 of receipt of the SCE packet corresponding to channel CH0b.

[0222] Next, at time t207, when the data counter 33 reaches the counted number of output data DOUTa, it instructs the channel switch 34 to switch channels CH. The channel switch 34 switches from RAM 35a corresponding to channel CH0a to RAM 35b corresponding to channel CH0b. In other words, the bridge chip 30 switches the output data to the memory controller 20 from output data DOUTa to output data DOUTb. Simultaneously with the switch from RAM 35a corresponding to channel CH0a to RAM 35b corresponding to channel CH0b, the bridge chip 30 issues an SCT packet and transmits it to the target memory chip 11 connected to channel CH0a. Furthermore, the bridge chip 30 terminates the activation of signal RE_t in channel CH0a, setting signal RE_t to an "H" level. Consequently, the memory chip 11 connected to channel CHa terminates its output operation.

[0223] The bridge chip 30 starts outputting the output data DOUTb without providing a standby period between outputting the output data DOUTa and outputting the output data DOUTb. The data counter 33 counts the number of bits of the output data DOUTb outputted from the channel switch 34 to the memory controller 20.

[0224] Next, at time 208, while data counter 33 is counting the number of bits of output data DOUTb, memory controller 20 transmits an SCT packet corresponding to channel CH0b via channel CH0 to bridge chip 30. Furthermore, memory controller 20 terminates activation of signal RE_t, setting signal RE_t to an "H" level.

[0225] Next, at time t209, the bridge chip 30 issues an SCT packet based on the SCT packet received from the memory controller 20 and transmits it to the target memory chip 11 connected to channel CH0b. Furthermore, the bridge chip 30 terminates the activation of signal RE_t in channel CH0b, setting signal RE_t to an "H" level. Consequently, the memory chip 11 connected to channel CHb terminates its output operation.

[0226] Next, focusing on the ECC frame EF, the relationship between the switching timing of the SCE packet and the channel CH will be described.

[0227] Figure 16 In the illustrated example, the bridge chip 30 sequentially outputs output data DOUT_A, output data DOUT_B, and output data DOUT_C ​​to the memory controller 20 . Figure 16 In the example shown, each output data DOUT includes one or more ECC frames FE. Figure 16In the example shown, the signal group NB_pkt corresponding to the data packet PK and the signal group NB_dat corresponding to the data DAT are shown, and the specific signals corresponding to each signal group (signals DQ, DQS, DQS_c, CA_CE#, CA0, CA1, CA_CLK, RE_t, and RE_c) and the signal R / B_n are omitted. Figure 16 In the illustrated example, transmission and reception of the signal group NB_pkt and the signal group NB_dat between the bridge chip 30 and the memory chip 11 are omitted for simplicity of description.

[0228] like Figure 16 As shown, for example, the memory controller 20 sends an SCE packet (SCE A) corresponding to output data DOUT_A to the bridge chip 30. For example, SCE packet (SCE A) corresponds to channel CH0a. Based on the SCE packet (SCE A), the channel switch 34 selects channel CH0a. The bridge chip 30 begins outputting output data DOUT_A to the memory controller 20. For example, output data DOUT_A includes four ECC frames EF1 to EF4. In this case, while the memory controller 20 is receiving ECC frame EF4 of output data DOUT_A, it sends an SCE packet (SCE B) corresponding to output data DOUT_B to the bridge chip 30. For example, SCE packet (SCE B) corresponds to channel CH0b.

[0229] When the data counter 33 completes counting of ECC frames EF4 for output data DOUT_A, it instructs the channel switch 34 to switch from channel CH0a to channel CH0b. Based on the instruction from the data counter 33, the channel switch 34 switches from channel CH0a to channel CH0b. The bridge chip 30 transmits an SCT packet to the target memory chip 11 connected to channel CH0a and stops triggering signals RE_t and RE_c. This halts output operations using channel CH0a. When the bridge chip 30 completes counting of ECC frames EF4 for output data DOUT_A, it begins outputting output data DOUT_B without providing a standby period between outputting output data DOUT_A and outputting output data DOUT_B. For example, output data DOUT_B includes J (J is an integer greater than or equal to 2) ECC frames EF1 to EF(J). In this case, the memory controller 20 transmits an SCE packet (SCE C) corresponding to output data DOUT_C ​​to the bridge chip 30 while receiving ECC frame EF(J). For example, the SCE data packet (SCEC) corresponds to the channel CH0a.

[0230] When the data counter 33 completes counting of the ECC frame EF(J) for output data DOUT_B, it instructs the channel switch 34 to switch from channel CH0b to channel CH0a. Based on the instruction from the data counter 33, the channel switch 34 switches from channel CH0b to channel CH0a. The bridge chip 30 transmits an SCT packet to the target memory chip 11 connected to channel CH0b and stops triggering signals RE_t and RE_c. This halts output operations using channel CH0b. When the bridge chip 30 completes counting of the ECC frame EF(J) for output data DOUT_B, it begins outputting output data DOUT_C ​​without providing a standby period between the output operations of output data DOUT_B and output data DOUT_C.

[0231] 3.3 Effects of this embodiment

[0232] With the configuration according to this embodiment, the same effects as those of the first and second embodiments can be obtained.

[0233] Furthermore, in the configuration of this embodiment, the bridge chip 30 can set the ECC frame size of the data DAT sent and received between the memory chip 11 connected to one channel CH and the memory controller 20. Thus, the bridge chip 30 can set the division position of the data DAT for switching between channel CH0a and channel CH0b. The bridge chip 30 can count the number of bits of the data DAT sent and received with the memory controller 20. Thus, the bridge chip 30 can switch channels CH based on the data size of the data DAT. Therefore, the memory controller 20 can complete the transmission of the SCE data packet corresponding to the output action of the next data DAT during the output of the previous data DAT. Therefore, when the counted number of the previous data DAT reaches the set value, the bridge chip 30 can switch channels CH and start outputting the next data DAT without providing a standby period. This can improve the processing capacity of data transmission.

[0234] Furthermore, with the configuration of this embodiment, when multiple data DAT transfer operations are executed consecutively, the storage controller 20 can begin transmitting the SCE packet corresponding to the next transfer operation during the previous data transfer. This shortens the standby period between data transmissions on the signal DQ. In other words, the data transfer processing capacity of the storage system 1 can be improved.

[0235] 4. Modifications, etc.

[0236] The memory system according to the above embodiment includes: a memory chip (11) including a first terminal group (TM of signals DQ, DQS, and DQS_c) for transmitting and receiving data and a second terminal group (TM of signals CA0 and CA1, and CA_CLK) for receiving data packets (PK), configured to store data in a non-volatile manner; and a memory controller (20) that controls the memory chip and is configured to transmit and receive data to and from the memory chip via the first terminal group and to send data packets to the memory chip via the second terminal group. When the memory controller performs a single data transfer operation with the memory chip, the memory controller sends a first data packet (SCE) indicating the start of data transfer and a second data packet (SCT) indicating the end of data transfer to the memory chip. When the memory controller performs two consecutive data transfer operations with the memory chip, the memory controller sends a first data packet corresponding to the second data transfer to the memory chip between the first data transfer and the second data transfer, but does not send a second data packet corresponding to the first data transfer to the memory chip.

[0237] According to the configuration according to the above-described embodiment, the processing capability of data transfer can be improved.

[0238] In addition, the present invention is not limited to the above-mentioned embodiment, and various modifications can be applied.

[0239] Furthermore, the term “connected” in the above-mentioned embodiment also includes a state of indirect connection with another element such as a transistor or a resistor interposed therebetween.

[0240] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other ways, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and / or their variations are intended to be included within the scope and spirit of the invention, and are intended to be included within the invention set forth in the claims and their equivalents.

Claims

1. A storage system comprising: a memory chip including a first terminal group for transmitting and receiving data and a second terminal group for receiving data packets, and configured to store the data in a nonvolatile manner; and a memory controller that controls the memory chip and is configured to transmit and receive the data to and from the memory chip via the first terminal group and to send the data packet to the memory chip via the second terminal group; When the storage controller performs the data transfer operation once with the storage chip, the storage controller sends a first data packet indicating the start of the data transfer and a second data packet indicating the end of the data transfer to the storage chip. When the storage controller performs the data transfer operation twice consecutively with the storage chip, the storage controller sends the first data packet corresponding to the second data transfer to the storage chip between the first data transfer and the second data transfer, and does not send the second data packet corresponding to the first data transfer to the storage chip.

2. The storage system according to claim 1, When the storage controller performs the data transfer action twice consecutively with the storage chip, the storage controller sends the first data packet corresponding to the first data transfer to the storage chip before the first data transfer, and sends the second data packet corresponding to the second data transfer to the storage chip after the second data transfer.

3. The storage system according to claim 1, The memory controller executes, in parallel, a portion of transmission of the first data packet or the second data packet to the memory chip and a portion of transmission and reception of the data with the memory chip.

4. The storage system according to claim 1, Each of the first data packet and the second data packet includes a data packet header indicating a type of information and a data packet body indicating content of the information.

5. The storage system according to claim 4, The types of information include command, address and status information.

6. The storage system according to claim 1, The first terminal group includes a first terminal for inputting and outputting a first signal representing the data, a second terminal for inputting and outputting a strobe signal of the first signal, and a third terminal for inputting a read enable signal.

7. The storage system according to claim 1, The second terminal group includes a fourth terminal for inputting and outputting a second signal representing the first and second data packets, a fifth terminal for transmitting a strobe signal for the second signal, and a sixth terminal for inputting a chip enable signal.

8. The storage system according to claim 7, The memory chip takes in the second signal received from the fourth terminal based on the rising and falling edges of the strobe signal received via the fifth terminal.

9. A storage system comprising: The first memory chip and the second memory chip each include a first terminal group for transmitting and receiving data and a second terminal group for receiving data packets, and each is configured to store the data in a nonvolatile manner; a bridge chip connected to the first terminal group and the second terminal group of the first memory chip via a first channel and connected to the first terminal group and the second terminal group of the second memory chip via a second channel; as well as a memory controller connected to the bridge chip, and transmitting and receiving the data to and from the first memory chip and the second memory chip via the bridge chip; When the storage controller performs the data transfer action once with the bridge chip, the storage controller sends a first data packet indicating the start of the data transfer from the bridge chip to the storage controller and a second data packet indicating the end of the data transfer from the bridge chip to the storage controller to the bridge chip. When the data transfer action is performed twice consecutively with the bridge chip, the first data packet corresponding to the second data transfer is sent to the bridge chip between the first data transfer and the second data transfer, and the second data packet corresponding to the first data transfer is not sent to the bridge chip.

10. The storage system according to claim 9, When the storage controller performs the data transmission action twice consecutively with the bridge chip, the storage controller sends the first data packet corresponding to the first data transmission to the bridge chip before the first data transmission, and sends the second data packet corresponding to the second data transmission to the bridge chip after the second data transmission.

11. The storage system according to claim 9, The memory controller concurrently executes: a portion of transmission of the first data packet or the second data packet to the bridge chip, and a portion of transmission and reception of the data with the bridge chip.

12. The storage system according to claim 9, When the bridge chip performs the data transfer action twice consecutively with the first storage chip, it sends to the first storage chip: the third data packet indicating the start of the data transfer corresponding to the first transfer action from the first storage chip to the bridge chip, the fourth data packet indicating the end of the data transfer corresponding to the first transfer action from the first storage chip to the bridge chip, the third data packet corresponding to the second transfer action from the first storage chip to the bridge chip, and the fourth data packet corresponding to the second transfer action from the first storage chip to the bridge chip.

13. The storage system according to claim 9, The bridge chip executes, in parallel, a portion of the data transfer operation with the first memory chip and a portion of the data transfer operation with the second memory chip.

14. The storage system according to claim 9, When the data is sent from the first storage chip to the storage controller, the bridge chip sends a third data packet to the first storage chip before receiving the first data packet from the storage controller. The third data packet indicates the start of the transmission of the data from the first storage chip to the bridge chip.

15. The storage system according to claim 9, A data transmission speed between the memory controller and the bridge chip is faster than a data transmission speed between the bridge chip and the first memory chip or the second memory chip.

16. A storage system comprising: The first memory chip and the second memory chip each include a first terminal group for transmitting and receiving data and a second terminal group for receiving data packets, and each is configured to store the data in a nonvolatile manner; a bridge chip connected to the first terminal group and the second terminal group of the first memory chip via a first channel and connected to the first terminal group and the second terminal group of the second memory chip via a second channel; as well as a memory controller connected to the bridge chip, and transmitting and receiving the data to and from the first memory chip and the second memory chip via the bridge chip; The bridge chip includes: a determination unit configured to determine whether a first data packet indicating the start of data transfer is received from the storage controller; A setting unit, for setting the data size of the transmitted data; a counter for counting the transmitted data; a first memory corresponding to the first channel; a second memory corresponding to the second channel; and The switch connects one of the first memory and the second memory to the memory controller and switches the connection to the other of the first memory and the second memory based on the counted number of the transferred data.

17. The storage system according to claim 16, When the first data transmission action from the first memory chip to the memory controller and the second data transmission action from the second memory chip to the memory controller are continuously performed, when the count number of the first data reaches the set data size, the counter instructs the switch to switch the connection with the memory controller from the first memory to the second memory.

18. The storage system according to claim 17, During the period when the first data is transmitted from the bridge chip to the storage controller, the storage controller sends the first data packet corresponding to the transmission action of the second data to the bridge chip, but does not send the second data packet corresponding to the transmission action of the first data indicating the end of the data transmission to the bridge chip.

19. The storage system according to claim 18, The first data includes a plurality of data frames, and the memory controller sends the first data packet corresponding to the transmission operation of the second data to the bridge chip while the bridge chip transmits a last data frame of the plurality of data frames to the memory controller.

20. The storage system according to claim 17, When the bridge chip receives a command from the storage controller instructing the first storage chip to perform an output action of outputting the first data, before receiving the first data packet corresponding to the transfer action of the first data from the storage controller, the bridge chip sends a third data packet to the first storage chip, wherein the third data packet corresponds to the output action of the first data from the first storage chip to the bridge chip and indicates the start of the data transfer.

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