Transmitter circuit and method thereof for adapting to different protocol standards

Abstract

The invention discloses a transmitter circuit and a method thereof for adapting to different protocol standards, the circuit comprises at least one driving circuit module, each driving circuit module comprises: a first pre-amplification unit for receiving a first input signal, a first delay control signal and a duty ratio control signal and outputting a pair of differential pull-up signals; the grid electrodes of the first pull-up transistor and the second pull-up transistor receive a pair of differential pull-up signals respectively, and the source electrode of the first pull-up transistor and the drain electrode of the second pull-up transistor are connected and connected to a power supply voltage; one end of the pull-up resistor is connected with the drain electrode of the first pull-up transistor and the source electrode of the second pull-up transistor, and the other end of the pull-up resistor is connected with the output port; the second pre-amplification unit is used for receiving a second input signal, a second delay control signal and a duty ratio control signal and outputting a pull-down signal; the grid electrode of the pull-down transistor receives a pull-down signal, and the source electrode is connected with the ground end; one end of the pull-down resistor is connected to the drain electrode of the pull-down transistor, and the other end of the pull-down resistor is connected with the output port. The transmitter circuit can be applied to various working modes, and the signal duty ratio can be optimized in different working modes.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a transmitter circuit and a method for adapting the same to different protocol standards. Background Art

[0002] In modern computing systems, data transmission between the central processing unit (CPU) and memory is a key factor affecting overall system performance. To meet the ever-increasing demands for memory read and write speeds in scenarios such as high-performance computing, artificial intelligence, and big data processing, the speed and stability of memory interfaces are becoming increasingly important. As a core component of the memory controller interface circuitry, the performance of the transmitter circuit directly impacts signal transmission quality and system stability.

[0003] In recent years, with the continuous evolution of memory standards, DDR (Double Data Rate) synchronous dynamic random access memory (SDRAM) has reached its fifth generation (DDR5), boasting data transfer rates reaching 6400Mbps and beyond, significantly increasing bandwidth and gradually reducing I / O voltage. Meanwhile, NAND Flash, another type of non-volatile memory, has gained widespread application in solid-state drives (SSDs), embedded systems, mobile devices, and other fields. High-speed interface specifications such as ONFI, Toggle DDR, and NV-DDR3 / 4 have also been developed, with interface transfer rates and electrical parameters approaching similar design requirements to DDR memory.

[0004] However, traditional transmitter circuits are generally only compatible with a single type or standard of memory protocol—specifically, one operating mode within DDR or NAND Flash—and cannot flexibly switch between different standards. More importantly, in different memory operating modes, the output port's terminal impedance matching differs, causing the output signal's duty cycle to shift. For example, a pull-up terminal impedance match can result in a higher duty cycle, while a pull-down terminal impedance match can result in a lower duty cycle.

[0005] Furthermore, some existing designs adjust the duty cycle by varying the number of parallel output MOS transistors. This approach often affects output impedance, leading to signal reflections and reduced transmission quality, particularly in high-speed interfaces. Therefore, designing a transmitter circuit that is compatible with multiple memory interface standards, adapts to different impedance matching methods, and offers high-precision duty cycle adjustment has become a key technical challenge in current chip interface design. Summary of the Invention

[0006] The purpose of this application is to provide a transmitter circuit that is compatible with multiple memory interface standards, adapts to different impedance matching methods, and has high-precision duty cycle adjustment capabilities.

[0007] A first aspect of the present application provides a transmitter circuit, comprising at least one driving circuit module, wherein each driving circuit module comprises:

[0008] a first pre-amplifier unit, which receives a first input signal, a first delay control signal, and a duty cycle control signal and outputs a pair of differential pull-up signals;

[0009] a first pull-up transistor and a second pull-up transistor, wherein gates of the first pull-up transistor and the second pull-up transistor respectively receive the pair of differential pull-up signals, and a source of the first pull-up transistor and a drain of the second pull-up transistor are connected to a power supply voltage;

[0010] a pull-up resistor, one end of the pull-up resistor being connected to the drain of the first pull-up transistor and the source of the second pull-up transistor, and the other end being connected to the output port;

[0011] a second pre-amplifier unit, which receives a second input signal, a second delay control signal, and the duty cycle control signal and outputs a pull-down signal;

[0012] a pull-down transistor, wherein a gate of the pull-down transistor receives the pull-down signal and a source of the pull-down transistor is connected to a ground terminal;

[0013] A pull-down resistor, one end of which is connected to the drain of the pull-down transistor, and the other end of which is connected to the output port.

[0014] In a preferred example, the transmitter circuit includes a plurality of driving circuit modules, and the plurality of driving circuit modules are connected in parallel.

[0015] In a preferred example, the first pull-up transistor is a PMOS transistor, and the second pull-up transistor and the first pull-down transistor are NMOS transistors.

[0016] In a preferred embodiment, the first pre-amplification unit includes:

[0017] a first conversion and adjustment unit, which receives the first input signal, adjusts the duty cycle of the first input signal according to the duty cycle control signal, converts the voltage domain of the first input signal, adjusts the delay of the first input signal according to the first delay control signal, and outputs a first amplified signal;

[0018] a first inverter, wherein an input terminal of the first inverter is connected to an output terminal of the first conversion and regulation unit and outputs an inverted signal of the first amplified signal, thereby obtaining a pair of first differential amplified signals;

[0019] A first front driver receives the pair of first differential amplified signals and outputs the pair of differential pull-up signals.

[0020] In a preferred embodiment, the first conversion and adjustment unit includes:

[0021] a duty cycle adjustment unit, configured to receive the first input signal and adjust the duty cycle of the first input signal according to the duty cycle control signal;

[0022] a level converter, the level converter receiving the output of the duty cycle adjustment unit and converting the first input signal voltage domain;

[0023] A delay adjustment unit receives the output of the level converter, adjusts the delay of the first input signal according to the first delay control signal, and outputs the first amplified signal.

[0024] In a preferred embodiment, the second pre-amplification unit includes:

[0025] a second conversion and adjustment unit, which receives the second input signal, adjusts the duty cycle of the second input signal according to the duty cycle control signal, converts the voltage domain of the second input signal, adjusts the delay of the second input signal according to the second delay control signal, and outputs a second amplified signal;

[0026] A second front driver receives the second amplified signal and outputs the pull-down signal.

[0027] In a preferred embodiment, the second conversion and adjustment unit includes:

[0028] a duty cycle adjustment unit, configured to receive the second input signal and adjust the duty cycle of the second input signal according to the duty cycle control signal;

[0029] a level converter, the level converter receiving the output of the duty cycle adjustment unit and converting the second input signal voltage domain;

[0030] A delay adjustment unit receives the output of the level converter and adjusts the delay of the second input signal according to the second delay control signal, and outputs the second amplified signal.

[0031] In a preferred embodiment, the duty cycle adjustment unit includes:

[0032] a second inverter, wherein an input terminal of the second inverter receives the first input signal;

[0033] A first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the gates of the first to fourth transistors are all coupled to the output terminal of the second inverter, the source of the first transistor is coupled to a digital domain power supply voltage, the source of the second transistor is coupled to the digital domain power supply voltage via a first switch, the source of the third transistor is coupled to the ground terminal, the source of the fourth transistor is coupled to the ground terminal via a second switch, and the drains of the first to fourth transistors are connected and coupled to the input terminal of the level shifter, wherein the first switch and the second switch are controlled by the duty cycle control signal.

[0034] In a preferred example, when the first switch is closed and the second switch is open, the duty cycle of the positive-phase amplified signal in the pair of first differential amplified signals increases, and the duty cycle of the negative-phase amplified signal decreases; when the first switch is open and the second switch is closed, the duty cycle of the positive-phase amplified signal in the pair of first differential amplified signals decreases, and the duty cycle of the negative-phase amplified signal increases; when the first switch and the second switch are closed or open at the same time, the duty cycle of the pair of differential first amplified signals remains unchanged.

[0035] In a preferred example, when the first switch is closed and the second switch is open, the duty cycle of the second amplified signal increases; when the first switch is open and the second switch is closed, the duty cycle of the second amplified signal decreases; when the first switch and the second switch are closed or open at the same time, the duty cycle of the second amplified signal remains unchanged.

[0036] In a preferred example, the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.

[0037] In a preferred example, the first switch is a PMOS transistor.

[0038] In a preferred example, the second switch is an NMOS transistor.

[0039] In a preferred embodiment, the delay adjustment unit includes:

[0040] a third inverter, wherein an input terminal of the third inverter is coupled to an output terminal of the level converter;

[0041] a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein the gates of the fifth to eighth transistors are all coupled to the output terminal of the third inverter, the source of the fifth transistor is coupled to the analog domain power supply voltage, the source of the sixth transistor is coupled to the analog domain power supply voltage via a third switch, the source of the seventh transistor is coupled to the ground terminal, the source of the eighth transistor is coupled to the ground terminal via a fourth switch, the drains of the fifth to eighth transistors are connected and output the positive phase amplified signal or the second amplified signal of the pair of first differential amplified signals, wherein the third switch and the fourth switch are controlled by the first delay control signal or the second delay control signal.

[0042] In a preferred example, when the third switch and the fourth switch are simultaneously opened, the delay of the pair of first differential amplified signals relative to the first input signal is increased; when the third switch and the fourth switch are simultaneously closed, the delay of the pair of first differential amplified signals relative to the first input signal remains unchanged.

[0043] In a preferred example, when the third switch and the fourth switch are simultaneously opened, the delay of the second amplified signal relative to the second input signal is increased; when the third switch and the fourth switch are simultaneously closed, the delay of the second amplified signal relative to the second input signal remains unchanged.

[0044] In a preferred example, the third switch is a PMOS transistor.

[0045] In a preferred example, the fourth switch is an NMOS transistor.

[0046] In a preferred example, the fifth transistor and the sixth transistor are PMOS transistors, and the seventh transistor and the eighth transistor are NMOS transistors.

[0047] In a preferred embodiment, the first pre-amplification unit includes:

[0048] a first conversion and adjustment unit, which receives the first input signal, adjusts the duty cycle of the first input signal according to the duty cycle control signal, converts the voltage domain of the first input signal, adjusts the delay of the first input signal according to the first delay control signal, and outputs a first amplified signal;

[0049] a first front driver, the first front driver receiving the first amplified signal and outputting a first pull-up signal;

[0050] A first inverter has an input terminal connected to an output terminal of the first front driver and outputs an inverted signal of the first pull-up signal, thereby obtaining the pair of differential pull-up signals.

[0051] A second aspect of the present application provides a method for the transmitter circuit to adapt to different protocol standards, the method comprising:

[0052] When the power supply voltage is a higher voltage protocol standard, the first pull-up transistor is turned on and the second pull-up transistor is turned off; when the power supply voltage is a lower voltage protocol standard, the first pull-up transistor is turned off and the second pull-up transistor is turned on.

[0053] In a preferred embodiment, in different impedance matching modes, the method further includes:

[0054] performing a coarse adjustment on the duty cycle of the signal of the output port by increasing, decreasing or not changing the duty cycle of the pair of pull-up signal and pull-down signal through the duty cycle adjustment signal;

[0055] The first delay control signal and the second delay control signal are used to adjust the delay of the pair of pull-up signals and the pull-down signals relative to the first input signal and the second input signal, respectively, to adjust the time interval between the pair of pull-up signals and the pull-down signals, thereby fine-tuning the duty cycle of the signal of the output port.

[0056] In a preferred example, the higher voltage is a voltage greater than 1V, and the lower voltage is a voltage less than or equal to 0.6V.

[0057] It should be understood that within the scope of the present invention, the above-mentioned technical features of the present invention and the technical features described in detail below (such as in the embodiments) can be combined with each other to form new or preferred technical solutions. Due to space limitations, they will not be listed here one by one. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 It is a structural diagram of a transmitter circuit according to one embodiment of the present application.

[0059] Figure 2 Schematic diagram of the structure of a driving circuit module according to one embodiment of the present application.

[0060] Figure 3 It is a structural diagram of the first conversion and regulation unit according to one embodiment of the present application.

[0061] Figure 4 2 is a schematic structural diagram of a second conversion and regulation unit according to an embodiment of the present application.

[0062] Figure 5 It is a structural diagram of a driving circuit module according to another embodiment of the present application. DETAILED DESCRIPTION

[0063] In the following description, many technical details are provided to help readers better understand this application. However, those skilled in the art will understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can be implemented.

[0064] The following is a summary of some of the innovative features of the embodiments of this application:

[0065] The transmitter circuit of the present application includes two pull-up transistors and one pull-down transistor. The first pull-up transistor, the second pull-up transistor, and the pull-down transistor can be enabled in an operating mode with a higher power supply voltage and an operating mode with a lower power supply voltage, respectively, making the transmitter circuit compatible with operating modes with different power supply voltages. Furthermore, by setting different register values ​​(i.e., the values ​​of the delay control signal and the duty cycle control signal), the duty cycle and time interval of the pull-up and pull-down signals can be changed, thereby adjusting the duty cycle of the transmitter circuit's output signal.

[0066] Furthermore, the present application can perform a second-order adjustment on the duty cycle of the transmitter's output signal. The first adjustment (coarse adjustment) is performed by the value of the duty cycle control signal, and the second adjustment (fine adjustment) is performed by the value of the delay control signal, so that the duty cycle of the output signal is closer to the target value.

[0067] Compared with the prior art, the transmitter circuit of the present application has at least the following effective effects:

[0068] 1) Traditional transmitter circuits can only be applied to one operating mode. The transmitter circuit of the present invention is compatible with multiple memory interface standards. For example, it can be applied to multiple operating modes such as DDR4, LPDDR4, DDR5, LPDDR4X, LPDDR5, NV-DDR3, and NV-LPDDR4, thereby saving design costs.

[0069] 2) The transmitter circuit of the present invention adjusts the duty cycle of the transmitter output signal without changing the impedance of the transmitter output terminal. Furthermore, the duty cycle of the signal can be adjusted for different deviation directions, that is, the duty cycle of the transmitter terminal signal can be adjusted for different operating modes.

[0070] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0071] Figure 1FIG1 is a schematic diagram of the structure of a transmitter circuit 1 in an embodiment of the present invention, wherein the transmitter circuit 1 includes at least one driver circuit module 100. In this specific embodiment, the transmitter circuit 1 is composed of multiple driver circuit modules 100 connected in parallel, and the driver circuit modules 100 are multiplexed.

[0072] Figure 2 1 is a schematic diagram of the structure of the driver circuit module 100. The driver circuit module 100 includes a register DELAY_CTR_P, a register DELAY_CTR_N, a register DUTY_CTR<1:0>, a first pre-amplifier unit 101, a first pull-up transistor Mp1, a second pull-up transistor Mn1, a pull-up resistor R1, a second pre-amplifier unit 102, a pull-down transistor Mn2, a pull-down resistor R2, and an output port DQ. The first pull-up transistor Mp1 is a PMOS transistor, and the second pull-up transistor Mn1 and the pull-down transistor Mn2 are NMOS transistors.

[0073] The input terminals of the first pre-amplifier unit 101 are connected to the first input signal DATAP, the register DELAY_CTR_P, and the register DUTY_CTR<1:0>. The differential output terminals are connected to the gates of the pull-up PMOS transistor Mp1 and the pull-up NMOS transistor Mn1, respectively. The gate of the pull-up PMOS transistor Mp1 is connected to the output terminal PU of the first pre-amplifier unit 101, the source is connected to the power supply voltage VDDQ, and the drain is connected to the first terminal of the pull-up resistor R1. The gate of the pull-up NMOS transistor Mn1 is connected to the output terminal PUB of the first pre-amplifier unit 101, the drain is connected to the power supply voltage VDDQ, and the source is connected to the first terminal of the pull-up resistor R1. The first terminal of the pull-up resistor R1 is connected to the drain of the pull-up PMOS transistor Mp1 and the source of the pull-up NMOS transistor Mn1, and the second terminal is connected to the output port DQ.

[0074] The input terminal of the second pre-amplifier unit 102 is connected to the second input signal DATAN, the register DELAY_CTR_N, and the register DUTY_CTR<1:0>. The output terminal is connected to the gate of the pull-down NMOS transistor Mn2. The gate of the pull-down NMOS transistor Mn2 is connected to the output terminal of the second pre-amplifier unit 102. The source terminal is grounded VSSQ, and the drain terminal is connected to the first terminal of the pull-down resistor R2. The second terminal of the pull-down resistor R2 is connected to the output port DQ.

[0075] As used below, the terms "output port DQ" and "signal DQ" are used interchangeably to refer to the signal on the output port, which serves as the output signal of the driving circuit module. The terms "output terminal PU", "signal PU", and "pull-up signal PU" are used interchangeably to refer to the signal on the output terminal of the first pre-amplifier unit, which serves as the control signal of the first pull-up transistor. The terms "output terminal PUB", "signal PUB", and "pull-up signal PUB" are used interchangeably to refer to the signal on the output terminal of the first pre-amplifier unit, which serves as the control signal of the second pull-up transistor. The terms "output terminal PD", "signal PD", and "pull-down signal PD" are used interchangeably to refer to the signal on the output terminal of the second pre-amplifier unit, which serves as the control signal of the pull-down transistor. The terms "register DUTY_CTR<1:0>" and "duty cycle control signal" are used interchangeably to refer to the value of the register, which serves as the control signal of the duty cycle adjustment unit. The terms "register DELAY_CTR_P" and "first delay control signal" are used interchangeably to refer to the value of the register, which serves as the control signal for delay adjustment in the first pre-amplifier unit. The terms “register DELAY_CTR_N” and “second delay control signal” are used interchangeably to refer to the value of the register, which serves as a control signal for delay adjustment in the second pre-amplifier unit.

[0076] Continue to refer Figure 2 As shown, the first pre-amplifier unit 101 includes at least one first conversion and regulation unit 103, a first pre-driver 104, and a first inverter 107. The first conversion and regulation unit 103, the first inverter 107, and the first pre-driver 104 are connected sequentially. Specifically, the input of the first conversion and regulation unit 103 is connected to the input signal DATAP, the register DELAY_CTR_P, and the register DUTY_CTR<1:0>, and the output is connected to the input of the first inverter 107 and one input of the first pre-driver 104. The output of the first inverter 107 is connected to the other input of the first pre-driver 104. The differential output of the first pre-driver 104 is connected to the gates of the pull-up PMOS transistor Mp1 and the pull-up NMOS transistor Mn1.

[0077] The second pre-amplifier unit 102 includes at least one second conversion and regulation unit 105 and a second pre-driver 106. The second conversion and regulation unit 105 and the second pre-driver 106 are connected sequentially. Specifically, the input of the second conversion and regulation unit 105 is connected to the input signal DATAN, the register DELAY_CTR_N, and the register DUTY_CTR<1:0>, and the output is connected to the input of the second pre-driver 106. The output of the second pre-driver 106 is connected to the gate of the pull-down NMOS transistor Mn2.

[0078] The transmitter circuit's input signals, DATAP and DATAN, are identical signals that have been converted from parallel to serial mode by the previous stage. The first conversion and regulation unit 103 amplifies the input signal DATAP and outputs a first amplified signal DATAP_bur. The first inverter 107 outputs an inverted version of the first amplified signal DATAP_bur, thereby forming two differential amplified signals, DATAP_bur and DATAPB_bur. The first amplified signal DATAP_bur has the same polarity as the input signal DATAP, or is referred to as a positive-phase amplified signal. The inverted version of the first amplified signal DATAPB_bur has the opposite polarity as the input signal DATAP, or is referred to as a negative-phase amplified signal. The register DUTY_CTR<1:0> is used to adjust the duty cycle of the two differential amplified signals DATAP_bur and DATAPB_bur. Specifically, setting DUTY_CTR<1:0> to 10 increases the duty cycle of the positive-phase amplified signal DATAP_bur and decreases the duty cycle of the negative-phase amplified signal DATAPB_bur. When DUTY_CTR<1:0>=01 is set, the duty cycle of the positive-phase amplified signal DATAP_bur can be reduced and the duty cycle of the negative-phase amplified signal DATAPB_bur can be increased. When DUTY_CTR<1:0>=00 or 11 is set, the duty cycle of the amplified signals DATAP_bur and DATAPB_bur is not changed. Furthermore, the register DELAY_CTR_P is used to adjust the delay time of the positive-phase amplified signal DATAP_bur and the negative-phase amplified signal DATAPB_bur relative to the input signal DATAP. When DELAY_CTR_P=1 is set, the delay time of the positive-phase amplified signal DATAP_bur and the negative-phase amplified signal DATAPB_bur relative to the input signal DATAP can be increased. When DELAY_CTR_P=0 is set, the delay time of the amplified signals DATAP_bur and DATAPB_bur relative to the input signal DATAP is not changed. The first pre-driver 104 is used to enhance the driving capability of the amplified signals DATAP_bur and DATAPB_bur, and outputs the signal PU as the driving signal for the pull-up PMOS transistor Mp1, and outputs the signal PUB as the driving signal for the pull-up NMOS transistor Mn1, wherein the polarity of PU is opposite to that of the positive-phase amplified signal DATAP_bur, and the polarity of PUB is opposite to that of the negative-phase amplified signal DATAPB_bur.

[0079] The second conversion adjustment unit 105 amplifies the input signal DATAN and outputs a second amplified signal DATAN_bur. The second amplified signal DATAN_bur has the same polarity as the input signal DATAN. ​​The register DUTY_CTR<1:0> is used to adjust the duty cycle of the second amplified signal DATAN_bur. When DUTY_CTR<1:0>=10 is set, the duty cycle of the second amplified signal DATAN_bur can be increased. When DUTY_CTR<1:0>=01 is set, the duty cycle of the second amplified signal DATAN_bur is reduced. When DUTY_CTR<1:0>=00 or 11 is set, the duty cycle of the second amplified signal DATAN_bur is not changed. The register DELAY_CTR_N is used to adjust the delay time of the second amplified signal DATAN_bur relative to the input signal DATAN. ​​When DELAY_CTR_N=1 is set, the delay time of the second amplified signal DATAN_bur relative to the input signal DATAN is increased. When DELAY_CTR_N=0, the delay time of the second amplified signal DATAN_bur relative to the input signal DATAN is unchanged. The second pre-driver 106 is used to enhance the driving capability of the second amplified signal DATAN_bur and outputs a signal PD as a driving signal for the pull-down NMOS transistor Mn2. The polarity of PD is opposite to that of the amplified signal DATAN_bur.

[0080] In operating modes with a relatively high power supply voltage VDDQ, such as DDR4, LPDDR4, DDR5, NVDDR3, and NVLPDDR4, the pull-up PMOS transistor Mp1 is turned on, while the pull-up NMOS transistor Mn1 is turned off. In operating modes with a relatively low power supply voltage VDDQ, such as LPDDR4X and LPDDR5, the pull-up PMOS transistor Mp1 is turned off, while the pull-up NMOS transistor Mn1 is turned on. Therefore, the transmitter circuit of the present invention operates normally regardless of whether operating in an operating mode with a relatively high VDDQ, such as DDR5, or in an operating mode with a relatively low VDDQ, such as LPDDR5.

[0081] For different operating modes, the duty cycle and time interval of the pull-up signals PU, PUB and the pull-down signal PD are changed by setting different register values, thereby adjusting the duty cycle of the output port DQ of the transmitter circuit. The principle of adjusting the duty cycle of the output signal DQ by the transmitter circuit is described in detail below.

[0082] When the output port DQ is pull-up resistor-matched, the transmitter's pull-up resistor is strong while the pull-down resistor is weak, resulting in a higher (or larger) duty cycle for the output signal. Assuming the duty cycle of the input signals DATAP and DATAN is 50%, the first step is to coarsely adjust the duty cycle of the output signal: Set DUTY_CTR<1:0> = 01, reduce the duty cycle of the positive-phase amplified signal DATAP_bur and the second-phase amplified signal DATAN_bur, and increase the duty cycle of the negative-phase amplified signal DATAPB_bur. This increases the duty cycle of the pull-up signal PU and the pull-down signal PD, reduces the duty cycle of the pull-up signal PUB, and thus reduces the duty cycle of the signal DQ. The second step is to fine-tune the duty cycle of the output signal: if the duty cycle of the signal DQ is still greater than 50% at this time, DELAY_CTR_P can be set to 1 to increase the delay time of the positive phase amplified signal DATAP_bur and the negative phase amplified signal DATAPB_bur relative to the input signal DATAP, and DELAY_CTR_N can be set to 0 without changing the delay time of the second amplified signal DATAN_bur relative to the input signal DATAN. ​​In this case, the pull-up signals PU and PUB lag behind the pull-down signal PD, and the pull-up PMOS transistor Mp1 or the pull-up NMOS transistor Mn1 is turned on later and the pull-down NMOS transistor Mn2 is turned on first, that is, the pull-up resistor becomes weaker and the pull-down resistor becomes smaller. The pull-up resistor becomes stronger, thereby reducing the duty cycle of DQ. If the duty cycle of DQ is less than 50% at this time, DELAY_CTR_P is set to 0, leaving the delay of the positive-phase amplified signal DATAP_bur and the negative-phase amplified signal DATAPB_bur relative to the input signal DATAP unchanged. DELAY_CTR_N is set to 1, increasing the delay of the second amplified signal DATAN_bur relative to the input signal DATAN. ​​At this point, PU and PUB advance before PD, turning on the pull-up PMOS transistor Mp1 or the pull-up NMOS transistor Mn1 before the pull-down NMOS transistor Mn2. This means that the pull-up resistor becomes stronger and the pull-down resistor becomes weaker, thereby increasing the duty cycle of signal DQ. In the present invention, register DUTY_CTR<1:0> performs a first adjustment on the duty cycle of signal DQ, and registers DELAY_CTR_P and DELAY_CTR_N perform a second adjustment on the duty cycle of signal DQ, bringing the duty cycle of signal DQ closer to 50%.

[0083] When the output port DQ is pull-down resistor-matched, the transmitter pull-up resistor is weak and the pull-down resistor is strong, so the duty cycle of the DQ signal decreases. Assuming the duty cycle of the input signals DATAP and DATAN is 50%, setting DUTY_CTR<1:0> to 10 increases the duty cycle of the positive-phase amplified signal DATAP_bur and the second-phase amplified signal DATAN_bur, while decreasing the duty cycle of the negative-phase amplified signal DATAPB_bur. This reduces the duty cycle of the pull-up signal PU and the pull-down signal PD, while increasing the duty cycle of the pull-up signal PUB, thereby increasing the duty cycle of the DQ signal. If the duty cycle of the signal DQ is still less than 50% at this time, DELAY_CTR_P can be set to 0, without changing the delay time of the positive-phase amplified signal DATAP_bur and the negative-phase amplified signal DATAPB_bur relative to the input signal DATAP, and DELAY_CTR_N can be set to 1 to increase the delay time of the second amplified signal DATAN_bur relative to the input signal DATAN. ​​In this case, the pull-up signals PU and PUB lead the pull-down signal PD, and the pull-up PMOS transistor Mp1 or the pull-up NMOS transistor Mn1 turns on first, while the pull-down NMOS transistor Mn2 turns on later. That is, the pull-up resistor becomes stronger and the pull-down resistor becomes weaker, thereby increasing the duty cycle of the signal DQ. If the duty cycle of signal DQ is greater than 50%, DELAY_CTR_P can be set to 1 to increase the delay of the positive-phase amplified signal DATAP_bur and the negative-phase amplified signal DATAPB_bur relative to the input signal DATAP. Setting DELAY_CTR_N to 0 does not change the delay of the second amplified signal DATAN_bur relative to the input signal DATAN. ​​This causes the pull-up signals PU and PUB to lag behind the pull-down signal PD. The pull-up PMOS transistor Mp1 or the pull-up NMOS transistor Mn1 turns on later, while the pull-down NMOS transistor Mn2 turns on first. This weakens the pull-up resistor and strengthens the pull-down resistor, thereby reducing the duty cycle of signal DQ. Registers DUTY_CTR<1:0> adjust the duty cycle of signal DQ for the first time, while registers DELAY_CTR_P and DELAY_CTR_N adjust the duty cycle of signal DQ for the second time, bringing the duty cycle of signal DQ closer to 50%.

[0084] When the output port DQ is matched with both a pull-up resistor and a pull-down resistor, the pull-up and pull-down resistors have the same strength, so the duty cycle of the signal DQ remains unchanged. Assuming the duty cycle of the input signals DATAP and DATAN is 50%, you can set DUTY_CTR<1:0> = 00 or 11, the register DELAY_CTR_P = 0, and the register DELAY_CTR_N = 0 to maintain the duty cycle of the signal DQ.

[0085] Figure 31 is a schematic diagram of the structure of the first conversion and adjustment unit 103. The first conversion and adjustment unit 103 includes a first duty cycle adjustment unit 108, a first level shifter 109, and a first delay adjustment unit 110. The input of the first duty cycle adjustment unit 108 is connected to the input signal DATAP, and the output is connected to the input of the first level shifter 109. The output of the first level shifter 109 is connected to the input of the first delay adjustment unit 110. The output of the first delay adjustment unit 110 outputs the positive-phase amplified signal DATAP_bur. The output of the first delay adjustment unit 110 is connected to the input of the first inverter 107 to obtain the negative-phase amplified signal DATAB_bur.

[0086] Furthermore, the first duty cycle adjustment unit 108 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a second inverter 111. The first delay adjustment unit 110 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a second inverter 112. The first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 are PMOS transistors, and the third transistor M3, the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8 are NMOS transistors. The input end of the second inverter 111 is connected to the input signal DATAP, and the output end is connected to the gates of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4. The drains of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are connected together and connected to the input end of the first level converter 109. The source of the first transistor M1 is connected to the digital domain power supply voltage DVDD, the drain of the second transistor M2 is connected to the first end of the first switch s1, and the other end of the first switch s1 is connected to the digital domain power supply voltage DVDD. The source of the third transistor M3 is grounded, the source of the fourth transistor M4 is connected to the first end of the second switch s2, and the other end of the second switch s2 is grounded. An output terminal of the first level shifter 109 is connected to an input terminal of the second inverter 112. The gates of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are connected together and connected to the output terminal of the second inverter 112. The drains of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are connected together and output the positive-phase amplified signal DATAP_bur. The source of the fifth transistor M5 is connected to the analog domain power supply voltage AVDD. The source of the sixth transistor M6 is connected to a first terminal of the third switch s3, the other terminal of the third switch s3 is connected to the analog domain power supply voltage AVDD. The source of the seventh transistor M7 is grounded. The source of the eighth transistor M8 is connected to a first terminal of the fourth switch s4, the other terminal of the fourth switch s4 is grounded. An input terminal of the first inverter 107 is connected to the positive-phase amplified signal DATAP_bur, and an output terminal of the first inverter 107 outputs the negative-phase amplified signal DATAPB_bur.

[0087] In one embodiment, the first switch s1 , the second switch s2 , the third switch s3 , and the fourth switch s4 may be MOS transistors. For example, the first switch s1 and the third switch s3 are PMOS transistors, and the second switch s2 and the fourth switch s4 are NMOS transistors.

[0088] Furthermore, the first switch s1 is controlled by the register DUTY_CTR <1> The second switch s2 is controlled by the register DUTY_CTR <0> Control. When the register DUTY_CTR<1:0> = 10, the first switch s1 is turned on and the second switch s2 is turned off. The output charging capability of the first duty cycle adjustment unit 108 is strong but the discharging capability is weak, and the duty cycle of the output signal out1 increases. That is, the duty cycle of the output signal DATAP_bur increases while the duty cycle of DATAPB_bur decreases. When the register DUTY_CTR<1:0> = 01, the first switch s1 is turned off and the second switch s2 is turned on. The output charging capability of the first duty cycle adjustment unit 108 is weak but the discharging capability is strong. The duty cycle of the output signal out1 decreases. That is, the duty cycle of the positive-phase amplified signal DATAP_bur decreases while the duty cycle of the negative-phase amplified signal DATAPB_bur increases. When the register DUTY_CTR<1:0> = 00 or 11, the first switch s1 and the second switch s2 are turned off or on simultaneously, and the duty cycles of the positive-phase amplified signal DATAP_bur and the negative-phase amplified signal DATAPB_bur remain unchanged. The third switch s3 and the fourth switch s4 are controlled by the register DELAY_CTR_P. When the register DELAY_CTR_P=1, the third switch s3 and the fourth switch s4 are closed, increasing the delay of the positive-phase amplified signal DATAP_bur and the negative-phase amplified signal DATAPB_bur relative to the input signal DATAP. When the register DELAY_CTR_P=0, the third switch s3 and the fourth switch s4 are opened, without changing the delay of the positive-phase amplified signal DATAP_bur and the negative-phase amplified signal DATAPB_bur relative to the input signal DATAP.

[0089] Figure 4 1 is a schematic diagram of the structure of the second conversion and adjustment unit 105. The second conversion and adjustment unit 105 includes a second duty cycle adjustment unit 113, a second level shifter 114, and a second delay adjustment unit 115. The input of the second duty cycle adjustment unit 113 is connected to the input signal DATAN, and the output of the second duty cycle adjustment unit 113 is connected to the input of the second level shifter 114. The output of the second level shifter 114 is connected to the input of the second delay adjustment unit 115. The output of the second delay adjustment unit 115 outputs the second amplified signal DATAN_bur.

[0090] It should be noted that the second conversion adjustment unit 105 can adopt the same structure as the first conversion adjustment unit 103, that is, the structure and control method of the second duty cycle adjustment unit 113 can be the same as those of the first duty cycle adjustment unit 108, the structure of the second level converter 114 can be the same as the first level converter 109, and the structure and control method of the second delay adjustment unit 115 can be the same as those of the first delay adjustment unit 110.

[0091] Furthermore, the second duty cycle adjustment unit 113 includes a first transistor M1', a second transistor M2', a third transistor M3', a fourth transistor M4', and a second inverter 111'. The second delay adjustment unit 115 includes a fifth transistor M5', a sixth transistor M6', a seventh transistor M7', an eighth transistor M8', and a second inverter 112'. The first transistor M1', the second transistor M2', the fifth transistor M5', and the sixth transistor M6' are PMOS transistors, and the third transistor M3', the fourth transistor M4', the seventh transistor M7', and the eighth transistor M8' are NMOS transistors. An input terminal of the second inverter 111' is connected to the input signal DATAN, and an output terminal is connected to the gates of the first transistor M1', the second transistor M2', the third transistor M3', and the fourth transistor M4'. The drains of the first transistor M1', the second transistor M2', the third transistor M3', and the fourth transistor M4' are connected together and connected to the input terminal of the second level shifter 114. The source of the first transistor M1' is connected to the digital domain power supply voltage DVDD, the source of the second transistor M2' is connected to the first terminal of the first switch s1', and the other terminal of the first switch s1' is connected to the digital domain power supply voltage DVDD. The source of the third transistor M3' is grounded, the source of the fourth transistor M4' is connected to the first terminal of the second switch s2', and the other terminal of the second switch s2' is grounded. An output terminal of the second level shifter 114 is connected to an input terminal of the second inverter 112'. The gates of the fifth transistor M5', the sixth transistor M6', the seventh transistor M7', and the eighth transistor M8' are connected together and connected to the output terminal of the second inverter 112'. The drains of the fifth transistor M5', the sixth transistor M6', the seventh transistor M7', and the eighth transistor M8' are connected together and output the second amplified signal DATAN_bur. The source of the fifth transistor M5' is connected to the analog domain power supply voltage AVDD. The source of the sixth transistor M6' is connected to a first terminal of the third switch s3'. The other terminal of the third switch s3' is connected to the analog domain power supply voltage AVDD. The source of the seventh transistor M7' is grounded. The source of the eighth transistor M8' is connected to a first terminal of the fourth switch s4'. The other terminal of the fourth switch s4' is grounded.

[0092] Furthermore, the first switch s1' is controlled by the register DUTY_CTR <1> The second switch s2' is controlled by the register DUTY_CTR <0> Control. When the register DUTY_CTR<1:0> = 10, the first switch s1' is turned on and the second switch s2' is turned off. The output charging capability of the second duty cycle adjustment unit 113 is strong but the discharging capability is weak, and the duty cycle of the output signal out1' increases, that is, the duty cycle of the second amplified signal DATAN_bur increases. When the register DUTY_CTR<1:0> = 01, the first switch s1' is turned off and the second switch s2' is turned on. The output charging capability of the second duty cycle adjustment unit 113 is weak but the discharging capability is strong, and the duty cycle of the output signal out1' decreases, that is, the duty cycle of the second amplified signal DATAP_bur decreases. When the register DUTY_CTR<1:0> = 00 or 11, the first switch s1' and the second switch s2' are turned off or on at the same time, and the duty cycle of the second amplified signal DATAP_bur remains unchanged. The third switch s3' and the fourth switch s4' are controlled by the register DELAY_CTR_N. When the register DELAY_CTR_N=1, the third switch s3' and the fourth switch s4' are closed, increasing the delay of the second amplified signal DATAN_bur relative to the input signal DATAN. ​​When the register DELAY_CTR_N=0, the third switch s3' and the fourth switch s4' are opened, without changing the delay of the second amplified signal DATAN_bur relative to the input signal DATAN.

[0093] Figure 5 This is a structural diagram of a driving circuit module 100' in another embodiment of the present application. The difference between the driving circuit module 100' and the driving circuit module 100 is that the first inverter 107' is not arranged between the first conversion adjustment unit 103 and the first front driver 104, but is arranged behind the first front driver 104. The first front driver 104 outputs the first pull-up signal PU to the first inverter 107'. The first inverter 107' inverts the first pull-up signal PU and obtains a pull-up signal PUB, thereby obtaining a pair of differential pull-up signals.

[0094] Other embodiments of the present application further disclose a method for adapting the transmitter circuit to different protocol standards, the method comprising: when the power supply voltage VDDQ is a higher voltage (e.g., greater than 1V) protocol standard (e.g., DDR5, NVLPDDR4, etc.), the first pull-up transistor Mp1 is turned on and the second pull-up transistor Mn1 is turned off. When the power supply voltage is a lower voltage (e.g., less than or equal to 0.6V) protocol standard (e.g., LPDDR5, LPDDR4X, etc.), the first pull-up transistor Mp1 is turned off and the second pull-up transistor Mn1 is turned on.

[0095] The transmitter circuit can adjust the duty cycle of the output port signal DQ in different impedance matching modes. First, the duty cycle of the output port signal DQ is coarsely adjusted by increasing, decreasing, or not changing the duty cycle of the pair of pull-up signals PU and PUB and the pull-down signal PD using a duty cycle adjustment signal. Then, the delay of the pair of pull-up signals PU and PUB relative to the first input signal DATAP is adjusted using a first delay control signal, and the delay of the pull-down signal PD relative to the second input signal DATAN is adjusted using a second delay control signal. This adjusts the time interval between the pair of pull-up signals PU and PUB and the pull-down signal PD, thereby fine-tuning the duty cycle of the output port signal DQ.

[0096] In summary, the transmitter of the present invention is compatible with multiple memory interface standards, thereby reducing design costs. The duty cycle of the transmitter output signal can be adjusted without changing the impedance of the transmitter output terminal. Furthermore, the duty cycle of the transmitter terminal signal can be adjusted for different operating modes.

[0097] The term "coupled to" and its derivatives may be used herein. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.

[0098] The specification of this application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too lengthy. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be deemed to have been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be technically combined with feature C. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, while the solution of A+B+C+E should be deemed to have been recorded.

[0099] All documents mentioned in this specification are considered to be included in their entirety in the disclosure of this application so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above description is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.

Claims

1. A transmitter circuit, characterized in that: The system comprises at least one driving circuit module, wherein each driving circuit module comprises: a first pre-amplifier unit, which receives a first input signal, a first delay control signal, and a duty cycle control signal and outputs a pair of differential pull-up signals; a first pull-up transistor and a second pull-up transistor, wherein gates of the first pull-up transistor and the second pull-up transistor respectively receive the pair of differential pull-up signals, and a source of the first pull-up transistor and a drain of the second pull-up transistor are connected to a power supply voltage; a pull-up resistor, one end of the pull-up resistor being connected to the drain of the first pull-up transistor and the source of the second pull-up transistor, and the other end being connected to the output port; a second pre-amplifier unit, which receives a second input signal, a second delay control signal, and the duty cycle control signal and outputs a pull-down signal; a pull-down transistor, wherein a gate of the pull-down transistor receives the pull-down signal and a source of the pull-down transistor is connected to a ground terminal; A pull-down resistor, one end of which is connected to the drain of the pull-down transistor, and the other end of which is connected to the output port.

2. The transmitter circuit according to claim 1, wherein The first pre-amplification unit includes: a first conversion and adjustment unit, which receives the first input signal, adjusts the duty cycle of the first input signal according to the duty cycle control signal, converts the voltage domain of the first input signal, adjusts the delay of the first input signal according to the first delay control signal, and outputs a first amplified signal; a first inverter, wherein an input terminal of the first inverter is connected to an output terminal of the first conversion and regulation unit and outputs an inverted signal of the first amplified signal, thereby obtaining a pair of first differential amplified signals; A first front driver receives the pair of first differential amplified signals and outputs the pair of differential pull-up signals.

3. The transmitter circuit according to claim 2, wherein: The first conversion and adjustment unit includes: a duty cycle adjustment unit, configured to receive the first input signal and adjust the duty cycle of the first input signal according to the duty cycle control signal; a level converter, the level converter receiving the output of the duty cycle adjustment unit and converting the first input signal voltage domain; A delay adjustment unit receives the output of the level converter, adjusts the delay of the first input signal according to the first delay control signal, and outputs the first amplified signal.

4. The transmitter circuit according to claim 1, wherein The second pre-amplification unit includes: a second conversion and adjustment unit, which receives the second input signal, adjusts the duty cycle of the second input signal according to the duty cycle control signal, converts the voltage domain of the second input signal, adjusts the delay of the second input signal according to the second delay control signal, and outputs a second amplified signal; A second front driver receives the second amplified signal and outputs the pull-down signal.

5. The transmitter circuit according to claim 4, wherein The second conversion and adjustment unit includes: a duty cycle adjustment unit, configured to receive the second input signal and adjust the duty cycle of the second input signal according to the duty cycle control signal; a level converter, the level converter receiving the output of the duty cycle adjustment unit and converting the second input signal voltage domain; A delay adjustment unit receives the output of the level converter and adjusts the delay of the second input signal according to the second delay control signal, and outputs the second amplified signal.

6. The transmitter circuit according to claim 3 or 5, characterized in that The duty cycle adjustment unit includes: a second inverter, wherein an input terminal of the second inverter receives the first input signal; A first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the gates of the first to fourth transistors are all coupled to the output terminal of the second inverter, the source of the first transistor is coupled to a digital domain power supply voltage, the source of the second transistor is coupled to the digital domain power supply voltage via a first switch, the source of the third transistor is coupled to the ground terminal, the source of the fourth transistor is coupled to the ground terminal via a second switch, and the drains of the first to fourth transistors are connected and coupled to the input terminal of the level shifter, wherein the first switch and the second switch are controlled by the duty cycle control signal.

7. The transmitter circuit according to claim 6, wherein: When the first switch is closed and the second switch is open, the duty cycle of the positive-phase amplified signal in the pair of first differential amplified signals increases, while the duty cycle of the negative-phase amplified signal decreases; when the first switch is open and the second switch is closed, the duty cycle of the positive-phase amplified signal in the pair of first differential amplified signals decreases, while the duty cycle of the negative-phase amplified signal increases; when the first switch and the second switch are closed or open at the same time, the duty cycle of the pair of first differential amplified signals remains unchanged.

8. The transmitter circuit according to claim 3 or 5, characterized in that The delay adjustment unit includes: a third inverter, wherein an input terminal of the third inverter is coupled to an output terminal of the level converter; a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein the gates of the fifth to eighth transistors are all coupled to the output terminal of the third inverter, the source of the fifth transistor is coupled to the analog domain power supply voltage, the source of the sixth transistor is coupled to the analog domain power supply voltage via a third switch, the source of the seventh transistor is coupled to the ground terminal, the source of the eighth transistor is coupled to the ground terminal via a fourth switch, and the drains of the fifth to eighth transistors are connected, wherein the third switch and the fourth switch are controlled by the first delay control signal or the second delay control signal.

9. The transmitter circuit according to claim 8, wherein When the third switch and the fourth switch are simultaneously opened, the delay of the pair of first differential amplified signals relative to the first input signal is increased; when the third switch and the fourth switch are simultaneously closed, the delay of the pair of first differential amplified signals relative to the first input signal remains unchanged.

10. The transmitter circuit according to claim 1, wherein The first pre-amplification unit includes: a first conversion and adjustment unit, which receives the first input signal, adjusts the duty cycle of the first input signal according to the duty cycle control signal, converts the voltage domain of the first input signal, adjusts the delay of the first input signal according to the first delay control signal, and outputs a first amplified signal; a first front driver, the first front driver receiving the first amplified signal and outputting a first pull-up signal; A first inverter has an input terminal connected to an output terminal of the first front driver and outputs an inverted signal of the first pull-up signal, thereby obtaining the pair of differential pull-up signals.

11. A method for adapting a transmitter circuit to different protocol standards according to any one of claims 1 to 10, characterized in that: The method comprises: When the power supply voltage is a higher voltage protocol standard, the first pull-up transistor is turned on and the second pull-up transistor is turned off; when the power supply voltage is a lower voltage protocol standard, the first pull-up transistor is turned off and the second pull-up transistor is turned on.

12. The method according to claim 11, wherein In different impedance matching modes, the method further includes: performing a coarse adjustment on the duty cycle of the signal of the output port by increasing, decreasing or not changing the duty cycle of the pair of pull-up signal and pull-down signal through the duty cycle adjustment signal; The first delay control signal and the second delay control signal are used to adjust the delay of the pair of pull-up signals and the pull-down signals relative to the first input signal and the second input signal, respectively, to adjust the time interval between the pair of pull-up signals and the pull-down signals, thereby fine-tuning the duty cycle of the signal of the output port.

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