Non-uniform automatic arrangement method and device applied to superconducting quantum chip indium columns

Abstract

The embodiment of the invention discloses a non-uniform automatic arrangement method and device applied to superconducting quantum chip indium bumps. A specific embodiment of the method comprises the following steps: performing geometric joint operation on polygons corresponding to a polygon information set and similar polygons to generate an internal region set which is in unified geometric representation and corresponds to the polygons; performing buffer area expansion on the unified geometric representation and the internal area set respectively; according to the unified geometric representation extension buffer region, the internal region set extension buffer region and the definition analysis region, determining an indium column placement region in the superconducting quantum chip; regular grid points are created in the area where the indium columns can be placed, a random offset is added to each grid point, and the indium columns are non-uniformly arranged in the area where the indium columns can be placed. According to the embodiment, the indium column layout can be optimized through a non-uniform distribution strategy, random offset is introduced to break a regular grid mode, the heat conduction characteristic of the superconducting quantum chip is improved, and the problems of local hot spots and non-uniform heat conduction are avoided.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of chip indium pillar arrangement, and more particularly to a method and apparatus for non-uniform automatic arrangement of indium pillars in superconducting quantum chips. Background Art

[0002] Currently, the placement of indium pillars in superconducting quantum chips primarily relies on manual labor, requiring designers to determine the placement of each pillar individually within the GDS layout. This approach presents numerous problems. First, manual labor is extremely inefficient. For complex quantum chip layouts containing thousands to tens of thousands of polygons, designers must spend considerable time analyzing the placement of each area, severely impacting the design cycle. Second, manual placement struggles to ensure consistent and optimal indium pillar distribution, and can easily lead to localized over- or under-density, impacting the chip's thermal conductivity and mechanical stability. Third, manual labor is prone to errors, such as placing indium pillars too close to functional structures or spacing between indium pillars that doesn't meet process requirements. These errors can lead to chip manufacturing failure or performance degradation. Furthermore, existing technologies lack the ability to automatically recognize and process complex geometric structures (such as rings and nested polygons) within GDS files. Designers must rely on empirical judgment to determine suitable placement areas, which is highly subjective and prone to omissions. Finally, while the traditional uniform grid layout method is simple, it fails to consider the thermal conductivity characteristics of superconducting quantum chips and can result in unfavorable thermal conduction patterns. Therefore, there is an urgent need for an automated method that can automatically identify the GDS layout structure, intelligently determine the placement area, and achieve non-uniform optimized arrangement of indium pillars. Summary of the Invention

[0003] The content of this disclosure is used to briefly introduce concepts that will be described in detail in the detailed description section below. The content of this disclosure is not intended to identify key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0004] Some embodiments of the present disclosure provide methods, devices, electronic devices, and computer-readable media for non-uniform automatic arrangement of indium pillars in superconducting quantum chips to address the technical issues mentioned in the background technology section above.

[0005] In a first aspect, some embodiments of the present disclosure provide a method for non-uniform automatic arrangement of indium pillars in a superconducting quantum chip, the method comprising: reading a database file corresponding to the superconducting quantum chip, and extracting each polygon information included in the database file to obtain a polygon information set, wherein one polygon information corresponds to one polygon; for each two polygon information in the polygon information set, performing the following processing steps: determining the similarity between the polygons corresponding to the two polygon information; in response to determining that the similarity is greater than or equal to a preset similarity, determining that the polygons corresponding to the two polygon information are similar polygons and marking them; and comparing each polygon corresponding to the polygon information set with each identified polygon; A geometric union operation is performed on similar polygons to generate a unified geometric representation and an internal region set corresponding to each polygon; a buffer extension is performed on the unified geometric representation and the internal region set respectively to obtain a unified geometric representation extended buffer and an internal region set extended buffer; an indium pillar placement area in the superconducting quantum chip is determined based on the defined analysis area corresponding to the unified geometric representation extended buffer, the internal region set extended buffer, and the superconducting quantum chip; regular grid points are created in the indium pillar placement area, and a random offset is added to each grid point to offset the grid point to obtain an indium pillar placement grid point area, and indium pillars are non-uniformly arranged in the indium pillar placement grid point area.

[0006] In a second aspect, some embodiments of the present disclosure provide a non-uniform automatic arrangement device for indium pillars of superconducting quantum chips, the device comprising: an extraction unit configured to read a database file corresponding to the superconducting quantum chip and extract each polygon information included in the database file to obtain a polygon information set, wherein one polygon information corresponds to one polygon; a determination unit configured to perform the following processing steps for each two polygon information in the polygon information set: determining the similarity between the polygons corresponding to the two polygon information; in response to determining that the similarity is greater than or equal to a preset similarity, determining that the polygons corresponding to the two polygon information are similar polygons and marking them; a joint operation unit configured to perform a joint operation on each polygon corresponding to the polygon information set and each identified polygon; A geometric union operation is performed on similar polygons to generate a unified geometric representation and an internal region set corresponding to each polygon; an expansion unit is configured to perform buffer expansion on the unified geometric representation and the internal region set respectively to obtain a unified geometric representation expansion buffer and an internal region set expansion buffer; a region determination unit is configured to determine an indium pillar placement area in the superconducting quantum chip based on a defined analysis area corresponding to the unified geometric representation expansion buffer, the internal region set expansion buffer, and the superconducting quantum chip; and a placement unit is configured to create regular grid points in the indium pillar placement area, add a random offset to each grid point to offset the grid point, obtain an indium pillar placement grid point area, and non-uniformly arrange indium pillars in the indium pillar placement grid point area.

[0007] In a third aspect, some embodiments of the present disclosure provide an electronic device comprising: one or more processors; a storage device on which one or more programs are stored, and when the one or more programs are executed by one or more processors, the one or more processors implement the method described in any implementation of the first aspect above.

[0008] In a fourth aspect, some embodiments of the present disclosure provide a computer-readable medium having a computer program stored thereon, wherein when the program is executed by a processor, the method described in any implementation of the first aspect is implemented.

[0009] The above-mentioned various embodiments of the present disclosure have the following beneficial effects: through the non-uniform automatic arrangement method applied to the indium pillars of superconducting quantum chips in some embodiments of the present disclosure, the fully automated arrangement of the indium pillars of superconducting quantum chips can be achieved, completely getting rid of the inefficient mode of traditional manual operation, and significantly improving the design efficiency and product development speed; it is conducive to accurately identifying complex geometric structures in GDS files, including ring structures, nested polygons and repeated patterns, ensuring that the indium pillars are not placed inside the functional structure or too close to key components, effectively avoiding manufacturing defects and performance interference; the indium pillar layout can be optimized through a non-uniform distribution strategy, and random offsets can be introduced to break the regular grid pattern , improve the thermal conductivity characteristics of superconducting quantum chips, avoid local hot spots and uneven heat conduction problems; it is conducive to strictly controlling the spacing and safety distance of indium pillars, automatically verifying that the position of each indium pillar meets the process requirements, eliminating human errors, and improving chip manufacturing yield and product reliability; it can process large-scale GDS files containing thousands to tens of thousands of polygons, with high algorithm efficiency, meeting the design requirements of complex superconducting quantum chips, and has good scalability; it can realize a complete automated process from GDS file parsing to indium pillar coordinate output without human intervention, ensuring the consistency and repeatability of layout results, and providing technical support for the large-scale production of superconducting quantum chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that components and elements are not necessarily drawn to scale.

[0011] Figure 1 is a flow chart of some embodiments of the method for non-uniform automatic arrangement of indium pillars in a superconducting quantum chip according to the present disclosure; Figure 2 This is a schematic diagram of a GDS layout file used in a non-uniform automatic arrangement method of indium pillars in a superconducting quantum chip according to some embodiments of the present disclosure; Figure 3 This is a schematic diagram of various polygon information extracted in a method for non-uniform automatic arrangement of indium pillars in a superconducting quantum chip according to some embodiments of the present disclosure; Figure 4 This is a schematic diagram of marking similar polygons in a non-uniform automatic arrangement method for indium pillars in a superconducting quantum chip according to some embodiments of the present disclosure; Figure 5 is a schematic diagram of a marking of an internal region identified in a method for non-uniform automatic arrangement of indium pillars in a superconducting quantum chip according to some embodiments of the present disclosure; Figure 6This is a schematic diagram of an area where indium pillars can be placed in a method for non-uniform automatic arrangement of indium pillars in a superconducting quantum chip according to some embodiments of the present disclosure; Figure 7 This is a schematic diagram of a grid point area where indium pillars can be placed in a non-uniform automatic arrangement method of indium pillars in a superconducting quantum chip according to some embodiments of the present disclosure; Figure 8 This is a schematic diagram of a superconducting quantum chip indium pillar arrangement diagram in a non-uniform automatic arrangement method for superconducting quantum chip indium pillars according to some embodiments of the present disclosure; Figure 9 Schematic diagrams of the structures of some embodiments of the non-uniform automatic arrangement device for indium pillars of superconducting quantum chips according to the present disclosure; Figure 10 It is a structural diagram of an electronic device suitable for implementing some embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0013] It should also be noted that, for ease of description, only the parts related to the invention are shown in the drawings. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0014] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0015] It should be noted that the modifications of "one" and "multiple" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, they should be understood as "one or more".

[0016] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0017] The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0018] Figure 1This is a process 100 of some embodiments of the method for non-uniform automatic arrangement of indium pillars in superconducting quantum chips according to some embodiments of the present disclosure. The method for non-uniform automatic arrangement of indium pillars in superconducting quantum chips according to some embodiments of the present disclosure includes the following steps: Step 101: read the database file corresponding to the superconducting quantum chip, and extract each polygon information included in the database file to obtain a polygon information set.

[0019] In some embodiments, the execution subject (e.g., a computing device) of the non-uniform automatic arrangement method for the superconducting quantum chip indium pillars can read the database file corresponding to the superconducting quantum chip and extract the polygon information included in the database file to obtain a polygon information set. Wherein, one polygon information corresponds to one polygon. The database file can be a GDS layout file of the superconducting quantum chip (e.g., Figure 2 (as shown in the example).

[0020] It should be noted that: Data structure 1: GDS layout file data structure; GDS layout files contain geometric information for multiple levels of structures, each defined by a sequence of points forming a polygon. This disclosure parses all levels of polygons, extracting boundary and feature information. The geometric shapes in a GDS file are organized into a hierarchical structure, encompassing the geometric layout of various semiconductor components, such as quantum bits, resonators, transmission lines, and other superconducting structures. Each structure has a specific layer and data type, and this hierarchical information must be processed to correctly identify areas where indium pillars can be placed.

[0021] Data structure 2: polygon representation structure; A polygon is represented by a set of points: P = {(x1, y1), (x2, y2), ..., (x n ,y n )}, where (x i ,y i ) represent the coordinates of the polygon vertices. These coordinate points are arranged in a clockwise or counterclockwise order to form a closed geometric shape. Each polygon may represent a different functional area on a superconducting quantum chip, such as a qubit, coupler, transmission line, or ground plane. The polygon can be simple or contain internal holes (such as a ring structure), which is crucial for the placement of indium pillars.

[0022] Data structure 3: polygonal feature representation; The following features are extracted for each polygon P: , represents the geometric center of the polygon; area A P , calculate the area covered by the polygon; perimeter L P , calculate the total length of the polygon boundary; compactness , which indicates how similar the polygon shape is to a circle.

[0023] Data structure 4: Indium column representation structure; Indium column is represented as a set of coordinate points: I = {(X1, Y1), (X2, Y2), ..., (X m , Y m )}, where (X i , Y i ) represents the center coordinates of the indium pillars. Each indium pillar is physically a micron-sized cylindrical structure that connects the superconducting quantum chip to the packaging substrate, providing mechanical support and a thermal conduction path. The size and spacing of the indium pillars must meet specific process requirements. They typically range from tens to hundreds of microns in diameter and tens of microns in height, with spacing no less than the specified minimum safety distance.

[0024] As an example, first, the above-mentioned execution entity can open the GDS layout file through the GDS parsing library gdspy, traverse all hierarchical structures and units, identify the top-level unit and extract the polygon information therein. For nested structures, all subunits can be accessed recursively to ensure that complete geometric information is captured. During the extraction process, attention is paid to all polygons located within the user-defined analysis area [x1, y1] to [x2, y2]. This area usually covers the entire quantum chip or its specific functional area. For each extracted polygon, the system calculates its characteristic parameters, including the center of mass position, area size, perimeter length and shape compactness. These characteristic parameters constitute the characteristic vector of the polygon, providing a data basis for subsequent pattern recognition and similarity analysis. The polygon information is stored in a structured manner, containing a list of vertex coordinates and calculated characteristic values, which is convenient for subsequent processing and analysis. The results of step 101 can be found in Figure 3 , which displays all the geometric elements extracted from the original GDS file.

[0025] Step 102: For every two polygons in the polygon information set, perform the following processing steps: Step 1021: Determine the similarity between the polygons corresponding to the two polygon information.

[0026] In some embodiments, the execution entity may determine the similarity between the polygons corresponding to the two polygon information.

[0027] In practice, the execution entity may determine the similarity between the polygons corresponding to the two polygon information by the following steps: The first step is to determine the polygon area, perimeter, and compactness of each polygon in the above two polygon information as a polygon vector. First, the feature vector F of each polygon P =[A P , LP , Compactness P ] are standardized to ensure the consistency of the dimensions of each feature.

[0028] The second step is to determine the feature similarity between the two polygon vectors. For example, the DBSCAN density clustering algorithm can be applied to the normalized feature vectors, with parameters set to ϵ = 0.5 (neighborhood radius) and "min_samples = 2" (minimum number of samples). These parameters have been shown to be effective for identifying repetitive patterns in quantum chips. The clustering process groups polygons with similar features into the same category. Another example is the cosine similarity formula, which can be used to determine the feature similarity between the two polygon vectors.

[0029] The third step is to perform polygon transformation on the second polygon corresponding to the above two polygon information to obtain a transformed polygon.

[0030] For example, by applying a rotation matrix with different angles Transform the second polygon to obtain the transformed polygon. Indicates the rotation angle.

[0031] The fourth step is to determine the shape similarity between the first polygon corresponding to the above two polygon information and the transformed polygon.

[0032] For example, the geometric distance matrix can be used to calculate the similarity of shapes after rotation: Sim geo =mean(min(cdist(P1,P2 rot ))).

[0033] When Sim geo When the value is less than 10 μm, it is considered as a rotational variant. Where P1 represents the point set corresponding to the first polygon. P2 rot Represents the point set corresponding to the transformed polygon. geo Indicates shape similarity. cdist(P1, P2 rot ) means calculating the pairwise distance matrix between two point sets. min(cdist(P1, P2 rot )) means taking the minimum value along the column direction of the distance matrix. mean(min(…)) means taking the average value of the minimum distance vector (physical meaning: all points in P1 to P2 rot the average closest distance).

[0034] In the fifth step, the feature similarity and the shape similarity are combined to form the similarity between the polygons corresponding to the two polygon information.

[0035] Step 1022: In response to determining that the similarity is greater than or equal to a preset similarity, the polygons corresponding to the two polygon information are determined to be similar polygons, and are marked.

[0036] In some embodiments, the execution entity may determine that the polygons corresponding to the two polygon information are similar polygons in response to determining that the similarity is greater than or equal to a preset similarity, and mark them. For example, for polygons of the same category or the same rotation variant, they are marked as polygons with a repeated pattern, and the identified polygons with a repeated pattern are highlighted in the Figure 4 The middle markers are shown, where the red areas represent polygons identified as repeating patterns.

[0037] Step 103 : Performing a geometric union operation on each polygon corresponding to the polygon information set and each identified similar polygon to generate a unified geometric representation and a set of internal regions corresponding to each polygon.

[0038] In some embodiments, the execution entity may perform a geometric union operation on each polygon corresponding to the polygon information set and each identified similar polygon to generate a unified geometric representation of the internal regions corresponding to each polygon. In computer graphics, CAD (computer-aided design), 3D modeling, and geometry processing, a geometric union operation (often abbreviated as "Union") refers to a Boolean operation used to combine two or more geometric bodies (typically polygon meshes, solids, or surfaces) into a single, new geometric body.

[0039] In practice, the execution entity may perform a geometric union operation on each polygon corresponding to the polygon information set and each identified similar polygon through the following steps: The first step is to geometrically union each polygon with each similar polygon to obtain a unified geometric representation. all ∪P repeated ), where P all Represents each polygon (all polygons). P repeated Individual similar polygons representing a repeating pattern.

[0040] In the second step, internal ring detection is performed on each polygon in the unified geometric representation to generate internal ring detection results and obtain an internal ring detection result set. Internal ring detection is performed by accessing the interiors attribute of the joint geometry (polygon). The detection process: First, determine whether the geometric object has an internal ring attribute, and then verify whether the internal ring set is non-empty. For a single polygon type, its internal ring attribute is directly accessed; for a multi-polygon set type, the internal ring attribute of each sub-polygon is traversed and tested one by one. The internal ring detection result can indicate whether the polygon has an internal ring. If an internal ring is present, the internal ring coordinate sequence is marked.

[0041] In the third step, for each inner ring detection result in the inner ring detection result set that meets the target conditions, perform the following processing steps: 1. Convert the internal ring coordinate sequence corresponding to the above internal ring detection results into an independent polygon entity.

[0042] 2. Perform a geometric union operation on the areas corresponding to the above inner ring detection results to generate the inner area.

[0043] For example, the execution entity may convert each detected internal ring coordinate sequence into an independent polygon entity I pj =Polygon(interior j ). All internal regions are merged through geometric union operations to form a complete set of internal regions I all =unary_union([I p1 , I p2 ,...,I pk ]).

[0044] It's important to note that step 103 relies on the sophisticated algorithms of the GEOS geometry engine, which automatically handles topological consistency checks, boundary ring correctness verification, and the decomposition and reconstruction of complex polygons. By directly accessing object properties, the system can efficiently identify ring structures within polygons without implementing complex boundary tracking algorithms.

[0045] The internal regions identified by the execution entity are marked as prohibited areas during the subsequent indium pillar layout. A buffer zone is then extended to ensure that the indium pillars maintain a safe distance from these functional voids. These internal regions typically correspond to specialized functional structures within a superconducting quantum chip, such as the interior of a coupler or resonator. Proper identification of these areas ensures that the indium pillars do not interfere with the performance of critical functional structures.

[0046] Due to the presence of the inner ring structure, indium pillars should not be placed in these inner areas, so accurate identification of these areas is crucial for indium pillar layout. The processing result of step 103 is Figure 5The pink area represents the identified inner ring region. These regions typically correspond to special functional structures in superconducting quantum chips, such as the inner regions of couplers or resonators. Correctly identifying these regions ensures that the indium pillars do not interfere with the performance of these critical functional structures.

[0047] Step 104 : performing buffer expansion on the unified geometric representation and the internal region set respectively to obtain a unified geometric representation expansion buffer and an internal region set expansion buffer.

[0048] In some embodiments, the execution entity may perform buffer expansion on the unified geometric representation and the internal region set respectively to obtain a unified geometric representation expansion buffer and an internal region set expansion buffer.

[0049] For example, the above implementation can apply a buffer operation to all shapes (including regular polygons and interior regions) to extend the original boundary outward by r polygon distance, forming buffer zone B shapes =U⊕r polygon and B interiors =I all ⊕r polygon , where ⊕ represents the Minkowski sum operation. The Minkowski sum operation is a geometric operation used to calculate the sum of two sets (usually geometric shapes). This operation ensures a minimum safe distance between the indium pillars and the polygon, preventing the indium pillars from being too close to the functional structures on the chip, which may cause process problems or performance interference. The buffer size r polygon It is set according to the process requirements, usually tens of microns. polygon The distance may be a preset distance.

[0050] Step 105 : determining an area in which an indium pillar in the superconducting quantum chip can be placed based on the unified geometric representation extended buffer, the internal region set extended buffer, and the defined analysis area corresponding to the superconducting quantum chip.

[0051] In some embodiments, the execution subject may determine the placement area of ​​the indium pillar in the superconducting quantum chip based on the unified geometric representation expansion buffer, the internal region set expansion buffer, and the defined analysis area corresponding to the superconducting quantum chip. The defined analysis area may refer to a predefined analysis area of ​​the superconducting quantum chip. For example, the defined analysis area may be A analysis =[x1, y1, x2, y2]. This area represents the maximum range where the indium column can be placed.

[0052] For example, by excluding all polygons and their buffer zones from the analysis area, the actual available area (the indium column placement area A) is calculated. available ): A available =A analysis ∖(B shapes ∪B interiors ), where ∖ represents the set difference operation.

[0053] This calculation involves complex Boolean operations and computational geometry processing, and is specifically implemented based on the Python Shapely geometry library calling the underlying GEOS (Geometry Engine Open Source) C++ engine. Buffer operations are implemented by calling the buffer method of the Shapely library, and the GEOSBuffer function of the GEOS engine is used internally to generate a geometric buffer. Set difference operations are implemented by calling the difference method of the Shapely library, and the underlying GEOSDifference function of the GEOS engine is called to perform polygon Boolean operations. The GEOS engine uses a precise topology-based geometry algorithm that can handle complex polygon intersections, self-intersections, and degenerate situations to ensure the geometric correctness and topological consistency of the calculation results. The calculated available area may contain multiple discontinuous polygonal areas, which together constitute the candidate placement area for the indium pillar. The result of step 105 is in Figure 6 The light green areas represent the areas where indium can be placed, which meet the requirements of maintaining a safe distance from all functional structures.

[0054] Step 106: create regular grid points in the indium pillar placement area, add a random offset to each grid point to offset the grid point, obtain an indium pillar placement area, and non-uniformly arrange indium pillars in the indium pillar placement area.

[0055] In some embodiments, the above-mentioned execution entity can create regular grid points in the above-mentioned indium column placement area, and add a random offset to each grid point to offset the grid point to obtain the indium column placement grid point area, and unevenly arrange the indium columns in the above-mentioned indium column placement grid point area.

[0056] In practice, the execution entity may create regular grid points in the indium pillar placement area through the following steps, and add a random offset to each grid point to offset the grid point, thereby obtaining the indium pillar placement grid point area: The first step is to create regular grid points in the above-mentioned indium column placement area according to the preset grid spacing. For example, regular grid points can be created in the indium column placement area with a grid spacing of d min This parameter is determined by the process requirements and is usually tens to hundreds of microns. The grid points are used as candidates for the initial indium column positions.

[0057] The second step is to add a random offset to each grid point to get the offset grid point. Each offset grid point corresponds to the grid point coordinate. The system adds a random offset to each grid point (x, y): x offset ∈[-δ,δ] and y offset ∈[-δ,δ], where δ is the maximum allowed offset, typically set to 10%-30% of the grid spacing. The offset is generated based on uniformly distributed random numbers to ensure uniform sampling within the allowed range.

[0058] After the offset, the offset grid point is obtained: (x', y') = (x + x offset , y+y offset ).

[0059] In the third step, for each offset grid point, the following processing steps are performed: 1. According to the grid point coordinates corresponding to the offset grid point, determine whether the offset grid point is within the indium column placement area. For example, perform regional verification on the offset grid point to ensure that it is within the indium column placement area: (x', y')∈A available .

[0060] 2. According to the grid point coordinates corresponding to the above offset grid points, the grid point coordinates corresponding to the above offset grid points meet the indium column safety distance condition. The indium column safety distance condition can be: 3. In response to determining that the offset grid point is within the indium pillar placement area and meets the indium pillar safety distance condition, the offset grid point is added to the current indium pillar set. I represents the indium pillar set.

[0061] The fourth step is to mark each offset grid point in the indium pillar set within the above-mentioned indium pillar placement area to obtain the indium pillar placement grid point area. The non-uniformly distributed indium pillars have better heat conduction characteristics than the uniform grid distribution, which can reduce the regular pattern in heat conduction and improve the heat conduction efficiency. The results of the indium pillar placement grid point area are shown in Figure 7 In the figure, the green dots indicate the final positions of the indium pillars. It can be seen that the indium pillars are unevenly distributed, but still maintain the minimum spacing requirements.

[0062] Optionally, safety verification is performed on the arranged indium columns.

[0063] Optionally, in response to determining that the security verification is passed, a superconducting quantum chip indium pillar layout diagram is generated.

[0064] For example, first count the total number of indium pillars |I| and calculate the average density of indium pillars in the analysis area : , These metrics are used to assess the adequacy of the indium pillar layout. A final layout visualization is then generated, showing the original GDS elements, internal regions, identified repeating patterns, and indium pillar locations. The visualization uses different colors and patterns to distinguish between different elements: blue represents the original GDS elements, pink represents the internal regions, red represents the repeating patterns, and green dots represent the indium pillar locations. Furthermore, the indium pillar layout is rigorously verified to ensure that all indium pillars are located within the available area and are at least a minimum safe distance d from each other. min The verification process calculates the Euclidean distance matrix between indium pillars and checks whether all distance values ​​meet the minimum distance requirements. If an indium pillar that does not meet the requirements is found, the system will give a warning and mark the corresponding position. After the verification is passed, the system will export the indium pillar coordinate information into a standard format file for use in subsequent process steps. The final superconducting quantum chip indium pillar layout diagram is in Figure 8 The figure shows the complete structure of the chip, which integrates all elements and the position of the indium pillars, and intuitively shows the spatial relationship between the indium pillars and the chip structure.

[0065] Further references Figure 9 As an implementation of the methods shown in the above figures, the present disclosure provides some embodiments of a non-uniform automatic arrangement device for indium pillars in superconducting quantum chips. These device embodiments are similar to Figure 1 Corresponding to the method embodiments shown, the non-uniform automatic arrangement device for indium pillars of superconducting quantum chips can be specifically applied to various electronic devices.

[0066] like Figure 9As shown, some embodiments of the non-uniform automatic arrangement device 600 for indium pillars of superconducting quantum chips include: an extraction unit 901, a determination unit 902, a joint operation unit 903, an expansion unit 904, a determination unit 905, and an arrangement unit 906. The extraction unit 901 is configured to read a database file corresponding to the superconducting quantum chip and extract each polygon information included in the database file to obtain a polygon information set, wherein one polygon information corresponds to one polygon; the determination unit 902 is configured to perform the following processing steps for each two polygon information in the polygon information set: determining the similarity between the polygons corresponding to the two polygon information; in response to determining that the similarity is greater than or equal to a preset similarity, determining that the polygons corresponding to the two polygon information are similar polygons and marking them; the joint operation unit 903 is configured to perform a geometric joint operation on each polygon corresponding to the polygon information set and each identified similar polygon to generate a unified geometric table. The internal region sets corresponding to the respective polygons are shown; an expansion unit 904 is configured to perform buffer expansion on the unified geometric representation and the internal region set respectively to obtain a unified geometric representation expansion buffer and an internal region set expansion buffer; a region determination unit 905 is configured to determine an indium pillar placement area in the superconducting quantum chip according to the defined analysis area corresponding to the unified geometric representation expansion buffer, the internal region set expansion buffer, and the superconducting quantum chip; an arrangement unit 906 is configured to create regular grid points in the indium pillar placement area, add a random offset to each grid point to offset the grid point, obtain an indium pillar placement grid point area, and non-uniformly arrange indium pillars in the indium pillar placement grid point area.

[0067] It is understood that the units described in the non-uniform automatic arrangement device 900 for superconducting quantum chip indium pillars are similar to those described in the reference Figure 1 Therefore, the operations, features and beneficial effects described above for the method are also applicable to the non-uniform automatic arrangement device 900 for indium pillars in superconducting quantum chips and the units contained therein, and will not be described in detail here.

[0068] Reference below Figure 10 , which shows a schematic structural diagram of an electronic device (such as a computing device) suitable for implementing some embodiments of the present disclosure. Figure 10 The electronic device shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure. Figure 10As shown, the computer device includes a processor, a memory and a network interface connected via a system bus, wherein the memory may include a non-volatile storage medium and an internal memory. The non-volatile storage medium can store an operating system and a computer program. The computer program includes program instructions, which, when executed, can enable the processor to execute any one of the non-uniform automatic arrangement methods applied to indium pillars of superconducting quantum chips. The processor is used to provide computing and control capabilities to support the operation of the entire computer device. The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium, which, when executed by the processor, can enable the processor to execute any one of the non-uniform automatic arrangement methods applied to indium pillars of superconducting quantum chips. The network interface is used for network communication, such as sending assigned tasks, etc. Those skilled in the art will understand that Figure 10 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present disclosure, and does not constitute a limitation on the computer device to which the solution of the present disclosure is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0069] It should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0070] In one embodiment, the processor is configured to run a computer program stored in a memory to implement the following steps: reading a database file corresponding to the superconducting quantum chip, and extracting each polygon information included in the database file to obtain a polygon information set, wherein one polygon information corresponds to one polygon; for each two polygon information in the polygon information set, performing the following processing steps: determining the similarity between the polygons corresponding to the two polygon information; in response to determining that the similarity is greater than or equal to a preset similarity, determining that the polygons corresponding to the two polygon information are similar polygons and marking them; comparing each polygon corresponding to the polygon information set with each identified similar polygon; The polygons are geometrically joined to generate a unified geometric representation and an internal region set corresponding to each polygon; the unified geometric representation and the internal region set are buffer-extended to obtain a unified geometric representation extended buffer and an internal region set extended buffer; an indium pillar placement region in the superconducting quantum chip is determined based on the defined analysis region corresponding to the unified geometric representation extended buffer, the internal region set extended buffer, and the superconducting quantum chip; regular grid points are created within the indium pillar placement region, and a random offset is added to each grid point to offset the grid point to obtain an indium pillar placement grid point region; and indium pillars are non-uniformly arranged within the indium pillar placement grid point region.

[0071] An embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored. The computer program includes program instructions. The method implemented when the program instructions are executed can refer to the various embodiments of the present disclosure for the method for non-uniform automatic arrangement of indium pillars in a superconducting quantum chip.

[0072] The computer-readable storage medium may be an internal storage unit of the computer device described in the aforementioned embodiment, such as a hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, a SmartMedia Card (SMC), a Secure Digital (SD) card, a flash memory card, etc., provided on the computer device.

[0073] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0074] The above descriptions are merely some preferred embodiments of the present disclosure and illustrate the underlying technical principles. Those skilled in the art should understand that the scope of the invention encompassed by the embodiments of the present disclosure is not limited to technical solutions formed by specific combinations of the aforementioned technical features. It also encompasses other technical solutions formed by any combination of the aforementioned technical features or their equivalents, without departing from the aforementioned inventive concept. For example, a technical solution formed by replacing the aforementioned features with (but not limited to) technical features with similar functions disclosed in the embodiments of the present disclosure.

Claims

1. A non-uniform automatic arrangement method for indium pillars in superconducting quantum chips, characterized in that: include: Reading a database file corresponding to the superconducting quantum chip, and extracting each polygon information included in the database file to obtain a polygon information set, wherein one polygon information corresponds to one polygon; For every two polygons in the polygon information set, perform the following processing steps: Determine the similarity between the polygons corresponding to the two polygon information; In response to determining that the similarity is greater than or equal to a preset similarity, determining that the polygons corresponding to the two polygon information are similar polygons and marking them; Performing a geometric union operation on each polygon corresponding to the polygon information set and each identified similar polygon to generate a unified geometric representation and an internal region set corresponding to each polygon; Performing buffer expansion on the unified geometric representation and the internal region set respectively to obtain a unified geometric representation expansion buffer and an internal region set expansion buffer; Determining an area in which an indium pillar in the superconducting quantum chip can be placed based on the unified geometric representation extended buffer, the internal region set extended buffer, and a defined analysis area corresponding to the superconducting quantum chip; Regular grid points are created in the indium column placement area, and a random offset is added to each grid point to offset the grid point to obtain an indium column placement grid point area, and indium columns are non-uniformly arranged in the indium column placement grid point area.

2. The method according to claim 1, characterized in that Determining the similarity between the polygons corresponding to the two polygon information includes: Determine the polygon area, perimeter, and compactness of each polygon information in the two polygon information as a polygon vector; Determine the feature similarity between two polygon vectors; Performing polygon transformation on the second polygon corresponding to the two polygon information to obtain a transformed polygon; Determining shape similarity between a first polygon corresponding to the two polygon information and the transformed polygon; The feature similarity and the shape similarity are combined into the similarity between the polygons corresponding to the two polygon information.

3. The method according to claim 2, characterized in that The performing of a geometric union operation on each polygon corresponding to the polygon information set and each identified similar polygon to generate a unified geometric representation and an internal region set corresponding to each polygon includes: Perform geometric union of each polygon with each similar polygon to obtain a unified geometric representation; Performing internal ring detection on each polygon in the unified geometric representation to generate internal ring detection results, thereby obtaining an internal ring detection result set; For each inner ring detection result in the inner ring detection result set that meets the target condition, perform the following processing steps: Converting the internal ring coordinate sequence corresponding to the internal ring detection result into an independent polygon entity; A geometric union operation is performed on the areas corresponding to the inner ring detection results to generate an inner area.

4. The method according to claim 3, characterized in that The step of creating regular grid points in the indium pillar placement area and adding a random offset to each grid point to offset the grid point to obtain the indium pillar placement area includes: Creating regular grid points in the indium pillar placement area according to a preset grid spacing; For each grid point, add a random offset to obtain an offset grid point, and each offset grid point corresponds to the grid point coordinate; For each offset grid point, the following processing steps are performed: Determining whether the offset grid point is within an indium column placement area based on the grid point coordinates corresponding to the offset grid point; According to the grid point coordinates corresponding to the offset grid point, the indium column safety distance condition is satisfied according to the grid point coordinates corresponding to the offset grid point; In response to determining that the offset grid point is within the indium pillar placement area and satisfies the indium pillar safety distance condition, adding the offset grid point to the current indium pillar set; Each offset grid point in the indium pillar set is marked in the indium pillar placement area to obtain the indium pillar placement grid point area.

5. The method according to claim 3, characterized in that The method further comprises: Conduct safety verification on the arranged indium columns; In response to determining that the security verification passes, a superconducting quantum chip indium pillar layout diagram is generated.

6. A non-uniform automatic arrangement device for indium pillars in superconducting quantum chips, characterized in that: include: An extraction unit is configured to read a database file corresponding to the superconducting quantum chip and extract each polygon information included in the database file to obtain a polygon information set, wherein one polygon information corresponds to one polygon; The determining unit is configured to perform the following processing steps for each pair of polygon information in the polygon information set: determining a similarity between polygons corresponding to the two polygon information; in response to determining that the similarity is greater than or equal to a preset similarity, determining that the polygons corresponding to the two polygon information are similar polygons and marking them; a union operation unit configured to perform a geometric union operation on each polygon corresponding to the polygon information set and each identified similar polygon to generate a unified geometric representation and an internal region set corresponding to each polygon; an expansion unit configured to perform buffer expansion on the unified geometric representation and the internal region set respectively to obtain a unified geometric representation expansion buffer and an internal region set expansion buffer; an area determination unit configured to determine an area in which an indium pillar can be placed in the superconducting quantum chip based on the unified geometric representation extension buffer, the internal area set extension buffer, and a defined analysis area corresponding to the superconducting quantum chip; The arrangement unit is configured to create regular grid points in the indium column placement area, add a random offset to each grid point to offset the grid point, obtain the indium column placement grid point area, and non-uniformly arrange the indium columns in the indium column placement grid point area.

7. An electronic device, characterized in that: include: one or more processors; a storage device having one or more programs stored thereon; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 5.

8. A computer-readable medium, characterized in that A computer program is stored thereon, wherein when the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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