Multi-quantum gate Kirschner product operation accelerator and method supporting mixing precision

Abstract

The invention discloses a multi-quantum gate Kirschner product operation accelerator and method supporting mixing precision, and the method comprises the steps: storing A, B and C quantum gates which need to be operated in a memory in a matrix form; respectively reading data of the matrix A and the matrix B, performing Kirschner product, and storing an operation result in a memory; the Kirschner product operation result is divided into a operation matrixes, Kirschner product of each operation matrix and the matrix C is carried out, a operation results are obtained, and a is the number of data of the matrix A; and rearranging the a operation results to obtain a Kirschner product operation result. According to the method, complex operation required by Kirschner product operation between quantum gates can be better matched, meanwhile, mixing precision is achieved through the multiplication and addition process of the complex operation, cascade connection is supported for a plurality of operation cores, therefore, a large matrix is partitioned, and operation time and resources are reduced.

Description

Technical Field

[0001] The present invention belongs to the field of digital chip design and relates to an accelerator for Krögert product operations between quantum gates, and in particular to an accelerator and method for multi-quantum gate Krögert product operations supporting mixed precision. Background Art

[0002] Tensor calculations based on the Kronecker product are the fundamental unit of quantum computing. For a quantum circuit, its final state can be simplified to U gates x initial state. In U gate calculations, quantum gates of different levels perform matrix multiplications, while operations between quantum gates of the same level are Kronecker products.

[0003] The basic form of the Krüger product operation can be understood as multiplying each element of matrix A by matrix B, ultimately expanding the result into a single large matrix. However, as the number of qubits, the number of matrices, and the dimensionality of the matrix increase, traditional iterative algorithms significantly increase computation time. Using FPGAs to perform block-based Krüger product operations can accelerate the Krüger product calculation process and improve the efficiency of quantum circuit simulation.

[0004] Currently, the hardware accelerator for the Krishna product is not yet perfect. There are two designs for software implementation and hardware implementation:

[0005] (1) Referring to Grout IA, Mullin L. Realization of the kronecker product in VHDL using multi-dimensional arrays [C] / / 2019 7th International Electrical Engineering Congress (iEECON). IEEE, 2019: 1-4., the Kronecker product operation of three integer matrices was designed and implemented on an FPGA. Multidimensional array variable types were defined using VHDL to simulate storage. After the matrix is ​​input, different operations can be performed through the combination of control signals (C0, C1, C2). The multiplier completes the multiplication and outputs the result.

[0006] (2) Referring to Mullin L, Raynolds J. Scalable, Portable, Verifiable Kronecker Products on Multi-scale Computers. Constraint Programming and Decision Making [J]. Studies in Computational Intelligence, 2014, 539., several new operators were proposed to expand the software implementation method of Kronecker product and use op in MoA (mathematic of array) environment. × The operator uses generalized transposition to rearrange data, which has inspiring significance for hardware block operations and address reordering.

[0007] To achieve the Kröger product of multiple quantum gates from a hardware perspective, using only a single computational core to perform the Kröger product of n quantum gates inevitably faces the problem of exponentially increasing time and energy consumption. Specifically, as the number of operations increases, the size of the matrix continues to expand, and the overhead of data access, multiplication, and addition inevitably increases rapidly. Furthermore, this core does not support complex domain architectures and lacks address permutation. On the one hand, it cannot support the needs of quantum gate Kröger product operations and cannot support mixed-precision operations. On the other hand, if multiple operations are performed, it is difficult to obtain the desired row-major matrix through simple permutation, and it cannot be directly used to obtain the final state. Therefore, it is impossible to implement the Kröger product of multiple quantum gates using the existing design. From a software perspective, although block operations are cleverly implemented through operators and address permutation is achieved through transposition, achieving hardware implementation still requires some effort. Summary of the Invention

[0008] The purpose of the present invention is to provide a multi-quantum gate Kirchner product operation accelerator and method that supports mixed precision. The accelerator can better match the complex operations required for the Kirchner product operations between quantum gates, while utilizing the multiplication and addition processes inherent in complex operations to achieve mixed precision. The accelerator also supports cascading multiple operation cores, thereby partitioning large matrices into blocks and reducing operation time and resources.

[0009] In order to achieve the above object, the solution of the present invention is:

[0010] A method for accelerating a multi-quantum Gatekeeper product operation supporting mixed precision includes the following steps:

[0011] Step 1: Store the required quantum gates A, B, and C in the memory in matrix form.

[0012] Step 2: Read the A and B matrix data respectively and perform The Krzysztof product is calculated and the result of the operation is stored in the memory;

[0013] Step 3, The Kerchian product operation result of is divided into a operation matrix, and the Kerchian product of each operation matrix and the C matrix is ​​performed respectively to obtain a operation results, where a is the number of data in the A matrix;

[0014] Step 4: rearrange the a operation results to obtain The result of Krzysztof product operation.

[0015] In the above step 1, the parameters of the memory include the global data bit width DATA_WIDTH, the address bit width ADDR_WIDTH, and the fixed-point number position FN.

[0016] In step 2 above, data A and B are read in a row-first order, and the real and imaginary parts are respectively calculated using a complex multiplication architecture. The data are truncated according to the set FN, and the calculation results are stored in order.

[0017] In the above step 2, the data of matrix B is traversed first. After reading the last data in matrix B, a data switching signal is sent to matrix A, and matrix B data is traversed again. If matrix A has traversed to the last data, a termination signal is sent to matrix B. Matrix B then completes this traversal and stops reading data.

[0018] The specific process of step 3 above is:

[0019] Step 31, The K-product operation result is divided into a parts according to the address from low to high, and a operation matrix is ​​obtained, which is distributed to a K-product operator cores;

[0020] Step 32: Perform Kilpatrick product of each operation matrix and the C matrix in blocks to obtain a operation results.

[0021] In step 3 above, the calculation results of each Kilpatrick product operator kernel are as follows:

[0022]

[0023] Among them, a ij is the data in matrix A, i=1,2,…,k,j=1,2,…,k;

[0024] In step 4 above, define the result of the operation

[0025] Among them, k is the number of rows and columns of the square matrix A; sel_row and sel_column are two custom k-bit registers, which ensure that only 1 bit of data is 1 at the same time, and the rest are 0, and the initial bit 0 is 1; if the allocation of the operation core is regarded as an array according to the element subscript of the A matrix, then sel_row and sel_column are the output data of the sub-operation core corresponding to the subscript in the control array; at the same time, two counters row1 and row2 are also defined, where the initial value of row1 is set to NUM_B*NUM_C-1, corresponding to the number of data in a row of the block operation result ; The initial value of row2 is set to NUM_A*NUM_B*NUM_C-1, which corresponds to the total number of data in the operation cores in the same row of the array; both counters decrease by one each time a data is output. When row1 decreases to 0, it means that the output of a row of data in the operation core has been completed. At this time, sel_column is controlled to shift left one position in a loop, thereby controlling the output data of the next operation core in the same row of the array; when row2 decreases to 0, it means that the data in all operation cores in a row of the array has been output. At this time, sel_row is controlled to shift left one position in a loop, switching to the next row of the array to output data, and then repeating the process of switching within the row.

[0026] A multi-quantum gate Kirkpatrick product operation accelerator supporting mixed precision includes a first memory, a second memory, a third memory, an operation circuit and a controller, wherein the operation circuit communicates data with the first memory, the second memory and the third memory respectively via a bus, the operation circuit is used to extract quantum gates in the first memory, the second memory and the third memory and perform Kirkpatrick product operations, and the controller is used to control the operation circuit to complete the Kirkpatrick product operations according to a preset program or instruction.

[0027] The first memory is used to store quantum gate A, the second memory is used to store quantum gate B, and the third memory is used to store quantum gate C. In each memory, quantum gates are stored in the form of a matrix. Each memory has three global variables: DATA_WIDTH, ADDR_WIDTH, and FN. DATA_WIDTH represents the global data bit width, which is the sum of the integer part and the fractional part. ADDR_WIDTH represents the address bit width, and its setting depends on the amount of data to be stored. The amount of data < 2 ADDR_WIDTH ; FN indicates the global decimal point position.

[0028] The above-mentioned operation circuit includes a first operation unit, a second operation unit and a fourth memory. The first operation unit is used to read the data in the first memory and the second memory respectively, and perform the Kirschner product operation, and store the first operation result obtained in the fourth memory; the second operation unit is used to read the data in the fourth memory and the third memory respectively, and perform the Kirschner product operation in blocks to obtain the operation result.

[0029] After adopting the above scheme, the beneficial effects of the present invention are as follows:

[0030] (1) The present invention adopts a parameter-controlled fixed-point format. The complex domain architecture design broadens the matrix types that the operation core can operate on, providing the possibility of achieving mixed precision. The adjustable fixed-point number ensures different precision requirements.

[0031] (2) The present invention adopts the idea of ​​matrix blocking and distributes the result of the first operation to multiple sub-operation cores through the natural blocking property of the Kermit product operation, thereby realizing the parallel algorithm of the second Kermit product. By controlling the read / write address and the scheduling between multiple modules, the row-first arrangement of the final matrix is ​​achieved, which not only solves the problems of long operation time and low efficiency, but also solves the problem of matrix data arrangement. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a flow chart of the acceleration method of the present invention;

[0033] Figure 2 This is a single-core overall architecture diagram;

[0034] Figure 3 This is a schematic diagram of single-core operation address rearrangement (taking the Kronos product of two 2*2 quantum gates as an example);

[0035] Figure 4 It is a mixed precision multiply-add design diagram;

[0036] Figure 5 It is a cascade architecture diagram (assuming A is a 2*2 matrix). DETAILED DESCRIPTION

[0037] The technical solutions and beneficial effects of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] The present invention provides a multi-quantum gate Kirkpatrick product operation accelerator supporting mixed precision, comprising a first memory, a second memory, a third memory, an operation circuit and a controller, wherein the operation circuit communicates data with the first memory, the second memory and the third memory respectively via a bus, the operation circuit is used to extract quantum gates in the first memory, the second memory and the third memory and perform Kirkpatrick product operations, and the controller is used to control the operation circuit to complete the Kirkpatrick product operations according to a preset program or instruction.

[0039] The first memory is used to store quantum gate A, the second memory is used to store quantum gate B, and the third memory is used to store quantum gate C. In each memory, quantum gates are stored in the form of a matrix. Three global variables are designed for storage: DATA_WIDTH, ADDR_WIDTH, and FN. DATA_WIDTH represents the global data bit width, which is the sum of the integer and fractional bits. ADDR_WIDTH represents the address bit width, and its setting depends on the amount of data to be stored. The amount of data < 2 ADDR _WIDTH ; FN represents the global decimal point position. By adjusting the value of FN, the number of decimal places of the fixed-point number can be adjusted. It also adjusts the accuracy of complex number addition and subtraction.

[0040] The operation circuit first reads the data of the first memory and the second memory, and performs The first operation result is obtained by performing a Kerch product operation on the first operation result and reading data from the third memory. The Kerch product operation is continued in blocks with the first operation result to obtain a final operation result. The operation circuit includes a first operation unit, a second operation unit and a fourth memory. The first operation unit is used to read data from the first memory and the second memory respectively, perform a Kerch product operation, and store the obtained first operation result in the fourth memory.

[0041] like Figure 1 As shown, the present invention also provides a method for accelerating multi-quantum gate Kermit product operations supporting mixed precision, comprising the following steps:

[0042] S1: The matrix form of quantum gates A, B, and C (hereinafter referred to as matrix instead of quantum gate) is stored. Three global variables are designed for storage: DATA_WIDTH, ADDR_WIDTH, and FN. DATA_WIDTH represents the global data bit width, the sum of the integer part and the fractional part. ADDR_WIDTH represents the address bit width, and its setting depends on the number of data to be stored. The number of data < 2 ADDR_WIDTH FN represents the global decimal point position. By adjusting the value of FN, the number of decimal places of the fixed-point number can be adjusted. It also adjusts the precision of complex number addition and subtraction.

[0043] S2: proceed The Krishna product.

[0044] S2.1: Controls the reading of the A and B matrix data. When all the data in the B matrix are traversed once, the data in the A matrix is ​​switched once.

[0045] S2.2: If Figure 4As shown, the real and imaginary part operations are implemented separately using the complex multiplication architecture, i.e., (a+bi)×(c+di)=(ac-bd)+(ad+bc)i. Full precision is retained when performing multiplication between the real and imaginary parts, and truncation is performed according to the set FN when adding two partial products, thereby achieving mixed precision.

[0046] S2.3: Store the calculation result in BRAM.

[0047] S3: Blocked Operation.

[0048] S3.1: The result of the operation is divided into a parts according to the address from low to high, and distributed to a Kilpatrick product operator cores, where a is the number of data in the A matrix.

[0049] S3.2: Perform the Kilpatrick product of each small matrix and C respectively. The operation process is the same as the above step S2.

[0050] S4: Rearrange the data of each operator core and store it in a BRAM to obtain the final result.

[0051] A specific embodiment will be provided below. Figure 2 The architecture diagram shown is complete The operation of ij Represents the element in the i-th row and j-th column of the matrix, i = 1, 2, j = 1, 2:

[0052] Step 1: Store the A, B, and C matrices in BRAM and define the relevant parameters:

[0053] In step 1, the data related parameters are mainly DATA_WIDTH, ADDR_WIDTH, FN, which represent the global data width, address width, and fixed-point number position respectively. Data width and address width are mainly used for the definition of BRAM, indicating that BRAM can store a total of 2 ADDR_WIDTH Each data bit is DATA_WIDTH. Using xpm_bram, you can parameterize BRAM creation. FN is used to implement mixed-precision operations, truncating excess decimals after complex multiplication and addition. For example, the input signal [DATA_WIDTH - 1:0] becomes [2 * DATA_WIDTH - 1:0] after multiplication, and truncates to [DATA_WIDTH + FN - 1:FN] after addition.

[0054] Step 2: Transfer the A and B matrices to the first-level operation core for Operation.

[0055] In the first-level operation core, the data extraction and storage of the operation results will not be rearranged, which means that the A and B matrices are directly output in row-first order, and after the operation, they are also directly stored in the BRAM in order. This is designed to facilitate subsequent block segmentation.

[0056] When Matrix B reads the last data point, it sends a data switching signal to Matrix A. Upon receiving this switching signal, Matrix A's controller switches data points, while Matrix B begins traversing the data from the beginning. If Matrix A has already traversed the last matrix, it sends a termination signal to Matrix B, and Matrix B stops traversing after completing this traversal.

[0057] The read data will be sent to the multiplier for multiplication, and the final result will be stored in another BRAM.

[0058] Step 3: Distribute the result of the first operation to multiple sub-operation cores of the second level, and perform operations with C in blocks.

[0059] Step 3.1: When partitioning the matrix, we need to consider how many data are in matrix A. We can refer to the following Kolmogorov product operation form:

[0060]

[0061] It is observed that the above operation process is the operation process of the first-level operation core, and the operation results are naturally divided into blocks according to the data of the A matrix and stored in the BRAM one by one. We only need to call the sub-operation cores equal to the number of data in the A matrix, and distribute the operation results to these sub-operation cores in sequence by blocks, so that the Kolmogorov product of multiple matrices can be calculated in a block-by-block manner.

[0062] Step 3.2: Perform K-product with C in blocks:

[0063] In the sub-core, in order to avoid further block storage of the result and simplify the data rearrangement of the final matrix, the sub-core is designed with a rearrangement function. Its address access method is as follows: Figure 3 As shown in the address rearrangement diagram.

[0064] First, when reading data, the result of the first operation is read by column. This is to facilitate address switching when storing block operation results. After traversing the B matrix once, the A matrix switches the data to the next data in the same column. If it has reached the last data in the current column, it switches to the first data in the next column. This operation is implemented by a column register: the column register stores the next column to be switched. Whenever a column jump occurs, the column value will increase by one until it is reset at the last element of the entire matrix. The specific jump is Where A_raddr represents the read address of the A matrix, HIGH = NUM_A 2 -NUM_A corresponds to the address of the last data in the first column of matrix A. If the read address is greater than this value, it means that matrix A has read the last row and needs to jump.

[0065] Secondly, when storing elements, since the calculation process can be viewed as a block-by-block operation, each time a row of matrix B is read, the storage address of the result should jump to the corresponding position in the next row within the block. Reading matrix A by column preserves the continuity of the result matrix storage address jumps. This means that when matrix A switches columns, the initial value of the result matrix storage address in that round of calculation simply needs to be changed to achieve data switching in the same manner. In the actual implementation, two global variables, NUM_A and NUM_B, are defined to represent the number of rows of quantum gates A and B. Two register variables, pause and change, are defined to control address jumps. Pause's initial value is set to NUM_B-1, and writing a data value minus one. It is used to indicate that the address of matrix C is incremented by one when matrix B has not yet output a row, and jumps to the next row when matrix B has output a row. Change is used to record the number of jumps and is initially set to 0. Because the number of rows in the result matrix is ​​NUM_A*NUM_B, when the change count reaches NUM_A*NUM_B-1, the write address of the C matrix needs to jump to a new column. The specific jump process is

[0066] Where C_waddr represents the write address of the C matrix.

[0067] With the above changes, we can get the following calculation results for each sub-core:

[0068]

[0069] That is, the results of each small part are arranged row-first.

[0070] Step 4: Schedule the final calculation results and store them in the last BRAM to achieve row-first arrangement of the results.

[0071] According to the previous step, we have obtained the row-first arrangement matrix of each block. Finally, we only need to design a set of enable signals to separate the sub-cores that store partial results by row, and then output the results in turn and store them in a BRAM to achieve row-first arrangement of the final result. The output result is

[0072] The expanded expression is

[0073]

[0074] To achieve the above data selection function, you can use Figure 5 As shown, two counters, row1 and row2, are defined. The initial value of row1 is set to NUM_B*NUM_C-1, corresponding to the number of data in a row of the block operation result; the initial value of row2 is set to NUM_A*NUM_B*NUM_C-1, corresponding to the total number of data in the computation cores in the same row of the array. Both counters decrement by one each time a new data item is output. When row1 decrements to 0, it indicates that the computation core has finished outputting a row of data. At this point, sel_column is shifted left one position, thus controlling the next computation core in the same row of the array to output data. When row2 decrements to 0, it indicates that all computation cores in a row of the array have finished outputting data. At this point, sel_row is shifted left one position, switching to the next row of the array for output data, and then repeating the intra-row switching process.

[0075] It will be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of the present invention may be implemented in various computer languages, for example, the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0076] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0077] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0078] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0079] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0080] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A method for accelerating multi-quantum gate Kermit product operations supporting mixed precision, characterized in that The steps include: Step 1: Store the required quantum gates A, B, and C in the memory in matrix form. Step 2: Read the A and B matrix data respectively and perform The Krzysztof product is calculated and the result of the operation is stored in the memory; Step 3, The Kerchian product operation result of is divided into a operation matrix, and the Kerchian product of each operation matrix and the C matrix is ​​performed respectively to obtain a operation results, where a is the number of data in the A matrix; Step 4: rearrange the a operation results to obtain The result of Krzysztof product operation.

2. The method according to claim 1, wherein: In step 1, the parameters of the memory include global data bit width DATA_WIDTH, address bit width ADDR_WIDTH, and fixed-point number position FN.

3. The method according to claim 1, wherein: In step 2, data A and B are read in a row-first order, and the real and imaginary parts are respectively calculated using a complex multiplication architecture. The data are truncated according to the set FN, and the calculation results are stored in order.

4. The method according to claim 1, wherein: In step 2, the B matrix data is first traversed, and after the last data in the B matrix is ​​read, a data switching signal is sent to the A matrix, and the B matrix data is traversed again at the same time; If the A matrix has traversed to the last data, a termination signal is sent to the B matrix, and the B matrix ends data reading after completing this traversal.

5. The method according to claim 1, wherein: The specific process of step 3 is: Step 31, The K-product operation result is divided into a parts according to the address from low to high, and a operation matrix is ​​obtained, which is distributed to a K-product operator cores; Step 32: Perform Kilpatrick product of each operation matrix and the C matrix in blocks to obtain a operation results.

6. The method according to claim 5, wherein: In step 3, the calculation results of each Kilpatrick product operator kernel are as follows: Among them, a ij is the data in matrix A, i=1,2,…,k,j=1,2,…,k; 7. The method according to claim 5, wherein: In the step 4, Where k is the number of rows and columns of the square matrix A; sel_row and sel_column are two k-bit registers, ensuring that only 1 bit of data is 1 at the same time and the rest are 0, and the initial bit 0 is 1; define two counters row1 and row2, where the initial value of row1 is set to NUM_B*NUM_C-1, corresponding to the number of data in a row of the block operation result; the initial value of row2 is set to NUM_A*NUM_B*NUM_C-1, corresponding to the total number of data in the operation cores in the same row of the array; both counters are decremented by one each time a data is output. When row1 is decremented to 0, it means that the output of a row of data in the operation core has been completed. At this time, sel_column is controlled to shift left one bit cyclically, thereby controlling the next operation core in the same row in the array to output data; when row2 is decremented to 0, it means that the data in all operation cores in a row of the array has been output. At this time, sel_row is controlled to shift left one bit cyclically, switching to the next row of the array to output data, and then repeating the process of switching within the row.

8. A multi-quantum gate-Kirsten product accelerator supporting mixed precision, characterized by: The system comprises a first memory, a second memory, a third memory, an operation circuit and a controller, wherein the operation circuit respectively communicates data with the first memory, the second memory and the third memory via a bus, the operation circuit is used to extract quantum gates in the first memory, the second memory and the third memory and perform Kirchner product operations, and the controller is used to control the operation circuit to complete the Kirchner product operations according to a preset program or instruction.

9. The computing accelerator according to claim 8, wherein: The first memory is used to store quantum gate A, the second memory is used to store quantum gate B, and the third memory is used to store quantum gate C. In each memory, quantum gates are stored in the form of a matrix. Each memory has three global variables: DATA_WIDTH, ADDR_WIDTH, and FN. DATA_WIDTH represents the global data bit width, which is the sum of the integer part and the fractional part. ADDR_WIDTH represents the address bit width, and its setting depends on the amount of data to be stored. The amount of data < 2 ADDR_WIDTH ; FN indicates the global decimal point position.

10. The computing accelerator according to claim 8, wherein: The operation circuit includes a first operation unit, a second operation unit and a fourth memory. The first operation unit is used to read data from the first memory and the second memory respectively, perform Kerchner product operation, and store the obtained first operation result in the fourth memory; the second operation unit is used to read data from the fourth memory and the third memory respectively, perform Kerchner product operation in blocks to obtain the operation result.

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