A machine vision-based semiconductor surface defect detection method and system

Abstract

This invention provides a semiconductor surface defect detection method and system based on machine vision. By comparing and analyzing machine vision recognition data of several wafers, the commonalities in defect distribution across all wafers are determined, system defects are extracted, and defects caused by equipment or processes within the wafer are accurately and comprehensively identified. A defect distribution characterization map of the wafer across all manufacturing threads is generated to determine the surface defect clustering characteristics. The types and distribution of defects generated by the wafer in each manufacturing thread are comprehensively identified, thereby identifying whether the defects significantly impact quality, accurately determining whether the wafer is in a failed state, and effectively evaluating the overall performance of the wafer. Furthermore, for all wafers in a failed state, defect formation reproduction identification is performed in the same manufacturing thread to identify improperly executed manufacturing threads and accurately trace the manufacturing threads that generated the defects. This helps to debug and correct the corresponding manufacturing threads and improve the wafer processing yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor inspection, and more particularly to a method and system for detecting semiconductor surface defects based on machine vision. Background Technology

[0002] Integrated circuits (ICs) are formed by integrating a large number of electronic components on the surface of semiconductor wafers to create a corresponding circuit layout. The integrity of the wafer surface directly affects the quality of ICs; the more numerous and widely distributed the defects on the wafer surface, the greater the impact on the circuit layout. Currently, machine vision technology is used to detect defects on the wafer surface, obtaining the types and quantities of defects to provide a basis for identifying wafer performance indicators. However, considering that wafers typically require multiple manufacturing processes to form a complete circuit layout on their surface, and that each manufacturing process may create defect structures on the wafer surface during execution, the aforementioned machine vision recognition only performs defect detection on wafers that have completed all manufacturing processes. It can only evaluate the overall defect status of the wafer itself and cannot comprehensively and accurately trace the defects that may occur at each manufacturing process. It cannot accurately locate the manufacturing process that caused the defect, thus preventing the corresponding manufacturing process from being debugged, which reduces the yield of subsequent wafer processing. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor surface defect detection method and system based on machine vision. By comparing and analyzing machine vision recognition data of several wafer surfaces, the commonalities in defect distribution across all wafers are determined, system defects are extracted, and defects caused by equipment or processes within the wafer are accurately and comprehensively identified. A defect distribution characterization map of the wafer across all manufacturing threads is generated to determine the surface defect clustering characteristics of the wafer. The types and distribution of defects generated by the wafer in each manufacturing thread are comprehensively identified, thereby identifying whether the defects on the wafer have a significant impact on quality, accurately determining whether the wafer is in a failed state, and effectively evaluating the overall performance of the wafer. Furthermore, for all wafers in a failed state, defect formation reproduction identification is performed in the same manufacturing thread to identify improperly executed manufacturing threads and accurately trace the manufacturing threads that generated the defects. This helps to debug and correct the corresponding manufacturing threads and improve the wafer processing yield.

[0004] This invention is achieved through the following technical solution:

[0005] A machine vision-based method for detecting semiconductor surface defects includes:

[0006] By comparing and analyzing the surface machine vision recognition data of several wafers, the commonalities in the defect distribution of all wafers are determined; based on the commonalities in the defect distribution, the system defects of the wafers are extracted.

[0007] Based on the defect morphology of the system defects of the wafer, a defect distribution characterization map of the wafer in the corresponding manufacturing thread is generated; based on the defect distribution characterization map of the wafer in all manufacturing threads, the surface defect clustering characteristics of the wafer are determined.

[0008] Based on the surface defect clustering characteristics, it is determined whether the wafer is in a failed state; for all wafers in a failed state, defect formation reproduction identification is performed to determine the improperly executed manufacturing thread.

[0009] Optionally, the surface machine vision recognition data of several wafers are compared and analyzed to determine the commonalities in defect distribution across all wafers; based on these commonalities, the system defects of the wafers are extracted, including:

[0010] After each manufacturing thread of several wafers is completed, a processing surface image is acquired, and machine vision recognition is performed on the processing surface image to obtain surface machine vision recognition data of the wafer after each manufacturing thread is completed; wherein the surface machine vision recognition data includes defect distribution location data on the wafer surface;

[0011] Spatial distribution comparison analysis was performed on the surface machine vision recognition data of all wafers after each of the same manufacturing threads to determine the commonalities in defect distribution among all wafers; wherein, the commonalities in defect distribution include the correlation of the positional distribution of surface defects among all wafers;

[0012] Based on the commonalities in defect distribution across all wafers, identify the random defects on the surface of each wafer. Compare these random defects with the overall surface defects of the wafer after completing the corresponding manufacturing thread to extract the system defects of the wafer in that manufacturing thread.

[0013] Optionally, based on the defect morphology of the system defects of the wafer, a defect distribution characterization map of the wafer in the corresponding manufacturing thread is generated; based on the defect distribution characterization map of the wafer in all manufacturing threads, the surface defect clustering characteristics of the wafer are determined, including:

[0014] Defect image pixel recognition is performed on the system defects of the wafer to obtain the three-dimensional morphology and contour data of the system defects; based on the three-dimensional morphology and contour data, a defect distribution characterization map of the wafer in the corresponding manufacturing thread is generated; wherein, the defect distribution characterization map includes a characterization map of the distribution location of structural defects and foreign matter defects formed on the wafer in the corresponding manufacturing thread.

[0015] Based on the outer contour of the wafer, the defect distribution characterization maps of the wafer across all manufacturing threads are aligned and overlapped, and the overall defect distribution characterization map after alignment and overlap is analyzed to determine the surface defect clustering characteristics of the wafer; wherein, the surface defect clustering characteristics include the clustering characteristics of structural defects and foreign matter defects on the surface of the wafer.

[0016] Optionally, based on the surface defect clustering characteristics, it is determined whether the wafer is in a failed state; for all wafers in a failed state, defect formation reproduction identification is performed to determine the improperly executed manufacturing thread, including:

[0017] Based on the clustering characteristics of structural defects and foreign matter defects on the wafer surface, the spatial proportion of the failure area on the wafer surface is estimated; wherein, the spatial proportion of the failure area refers to the spatial overlap ratio between the failure area and the circuit wiring area on the wafer surface; based on the spatial proportion of the failure area, it is determined whether the wafer is in a failure state.

[0018] For all wafers in a failed state, perform defect formation reproduction identification on the surface machine vision recognition data corresponding to the same manufacturing thread to obtain the probability of defect recurrence of the wafer in the same manufacturing thread; based on the probability of defect recurrence, determine whether the manufacturing thread is an improperly executed manufacturing thread.

[0019] Optionally, based on the clustering characteristics of structural defects and foreign matter defects on the wafer surface, the spatial proportion of the failure region on the wafer surface is estimated, including:

[0020] Extract the number of periodic defect clusters of structural defects on the surface of the wafer;

[0021] The structural defect periodicity factor is obtained based on the area of ​​the structural defect cluster corresponding to each periodic defect cluster.

[0022] The structural defect periodicity factor is obtained by the following formula:

[0023]

[0024] Where E represents the structural defect periodicity factor; N c S represents the number of periodic defect clusters representing structural defects on the surface of the wafer; i S represents the area of ​​the structural defect cluster corresponding to the i-th periodic defect cluster; p S represents the average cluster area of ​​structural defects; a α represents the surface area of ​​the wafer; α represents the process sensitivity coefficient, with a value ranging from 0.7 to 1.3.

[0025] Extract the number of foreign defects on the surface of the wafer;

[0026] The vertical distance between each foreign object defect and its adjacent structural defects is obtained based on the location of each foreign object defect.

[0027] The foreign object defect distribution factor is obtained based on the vertical distance between each foreign object defect and the adjacent structural defect.

[0028] The foreign object defect distribution factor is obtained by the following formula:

[0029]

[0030] Where K represents the foreign object defect distribution factor; N p Indicates the number of foreign object defects; D i D represents the perpendicular distance between the i-th foreign object defect and the adjacent structural defect; p R represents the average vertical distance between foreign object defects and adjacent structural defects; R represents the chi-square test critical value (3.84 at 95% confidence level);

[0031] The spatial proportion of the failure region on the surface of the wafer is obtained by using the structural defect periodicity factor and the foreign object defect distribution factor.

[0032] The proportion of the space of the failure area on the surface of the wafer is obtained by the following formula:

[0033]

[0034] Where G represents the proportion of the failure area on the wafer surface; λ represents the preset defect type weighting factor; and D(x, y) represents the circuit routing density distribution function of the circuit routing area.

[0035] A machine vision-based semiconductor surface defect detection system includes:

[0036] The defect commonality identification module is used to compare and analyze the surface machine vision recognition data of several wafers to determine the commonality of defect distribution among all wafers.

[0037] The system defect extraction module is used to extract system defects of the wafer based on the commonalities in the defect distribution.

[0038] The defect characterization map generation module is used to generate a defect distribution characterization map of the wafer in the corresponding manufacturing thread based on the defect morphology of the system defects of the wafer.

[0039] The defect clustering feature determination module is used to determine the surface defect clustering features of the wafer based on the defect distribution characterization map of the wafer across all manufacturing threads.

[0040] The failure state determination module is used to determine whether the wafer is in a failure state based on the surface defect clustering characteristics.

[0041] The manufacturing thread calibration module is used to identify defect formation reproduction in all wafers in a failed state and determine the improperly executed manufacturing thread.

[0042] Optionally, the defect commonality identification module is used to compare and analyze the surface machine vision recognition data of several wafers to determine the commonality of defect distribution among all wafers, including:

[0043] After each manufacturing thread of several wafers is completed, a processing surface image is acquired, and machine vision recognition is performed on the processing surface image to obtain surface machine vision recognition data of the wafer after each manufacturing thread is completed; wherein the surface machine vision recognition data includes defect distribution location data on the wafer surface;

[0044] Spatial distribution comparison analysis was performed on the surface machine vision recognition data of all wafers after each of the same manufacturing threads to determine the commonalities in defect distribution among all wafers; wherein, the commonalities in defect distribution include the correlation of the positional distribution of surface defects among all wafers;

[0045] The system defect extraction module is used to extract system defects of the wafer based on the commonalities in the defect distribution, including:

[0046] Based on the commonalities in defect distribution across all wafers, identify the random defects on the surface of each wafer. Compare these random defects with the overall surface defects of the wafer after completing the corresponding manufacturing thread to extract the system defects of the wafer in that manufacturing thread.

[0047] Optionally, the defect characterization map generation module is used to generate a defect distribution characterization map of the wafer in the corresponding manufacturing thread based on the defect morphology of the system defects of the wafer, including:

[0048] Defect image pixel recognition is performed on the system defects of the wafer to obtain the three-dimensional morphology and contour data of the system defects; based on the three-dimensional morphology and contour data, a defect distribution characterization map of the wafer in the corresponding manufacturing thread is generated; wherein, the defect distribution characterization map includes a characterization map of the distribution location of structural defects and foreign matter defects formed on the wafer in the corresponding manufacturing thread.

[0049] The defect clustering feature determination module is used to determine the surface defect clustering features of the wafer based on the defect distribution characterization map of the wafer across all manufacturing threads, including:

[0050] Based on the outer contour of the wafer, the defect distribution characterization maps of the wafer across all manufacturing threads are aligned and overlapped, and the overall defect distribution characterization map after alignment and overlap is analyzed to determine the surface defect clustering characteristics of the wafer; wherein, the surface defect clustering characteristics include the clustering characteristics of structural defects and foreign matter defects on the surface of the wafer.

[0051] Optionally, the failure state determination module is used to determine whether the wafer is in a failure state based on the surface defect clustering characteristics, including:

[0052] Based on the clustering characteristics of structural defects and foreign matter defects on the wafer surface, the spatial proportion of the failure area on the wafer surface is estimated; wherein, the spatial proportion of the failure area refers to the spatial overlap ratio between the failure area and the circuit wiring area on the wafer surface; based on the spatial proportion of the failure area, it is determined whether the wafer is in a failure state.

[0053] The manufacturing thread calibration module is used to identify defect formation reproduction in all wafers in a failed state and determine improperly executed manufacturing threads, including:

[0054] For all wafers in a failed state, perform defect formation reproduction identification on the surface machine vision recognition data corresponding to the same manufacturing thread to obtain the probability of defect recurrence of the wafer in the same manufacturing thread; based on the probability of defect recurrence, determine whether the manufacturing thread is an improperly executed manufacturing thread.

[0055] Optionally, based on the clustering characteristics of structural defects and foreign matter defects on the wafer surface, the spatial proportion of the failure region on the wafer surface is estimated, including:

[0056] Extract the number of periodic defect clusters of structural defects on the surface of the wafer;

[0057] The structural defect periodicity factor is obtained based on the area of ​​the structural defect cluster corresponding to each periodic defect cluster.

[0058] The structural defect periodicity factor is obtained by the following formula:

[0059]

[0060] Where E represents the structural defect periodicity factor; N c S represents the number of periodic defect clusters representing structural defects on the surface of the wafer; i S represents the area of ​​the structural defect cluster corresponding to the i-th periodic defect cluster; p S represents the average cluster area of ​​structural defects; aα represents the surface area of ​​the wafer; α represents the process sensitivity coefficient, with a value ranging from 0.7 to 1.3.

[0061] Extract the number of foreign defects on the surface of the wafer;

[0062] The vertical distance between each foreign object defect and its adjacent structural defects is obtained based on the location of each foreign object defect.

[0063] The foreign object defect distribution factor is obtained based on the vertical distance between each foreign object defect and the adjacent structural defect.

[0064] The foreign object defect distribution factor is obtained by the following formula:

[0065]

[0066] Where K represents the foreign object defect distribution factor; N p Indicates the number of foreign object defects; D i D represents the perpendicular distance between the i-th foreign object defect and the adjacent structural defect; p R represents the average vertical distance between foreign object defects and adjacent structural defects; R represents the chi-square test critical value (3.84 at 95% confidence level);

[0067] The spatial proportion of the failure region on the surface of the wafer is obtained by using the structural defect periodicity factor and the foreign object defect distribution factor.

[0068] The proportion of the space of the failure area on the surface of the wafer is obtained by the following formula:

[0069]

[0070] Where G represents the proportion of the failure area on the wafer surface; λ represents the preset defect type weighting factor; and D(x, y) represents the circuit routing density distribution function of the circuit routing area.

[0071] Compared with the prior art, the present invention has the following beneficial effects:

[0072] This application provides a machine vision-based semiconductor surface defect detection method and system that compares and analyzes surface machine vision recognition data from several wafers to determine the commonalities in defect distribution across all wafers, extracts system defects from the wafers, and accurately and comprehensively identifies defects caused by equipment or processes within the wafers. It generates defect distribution characterization maps of the wafers across all manufacturing threads to determine the surface defect clustering characteristics of the wafers. It comprehensively identifies the types and distribution of defects generated by the wafers in each manufacturing thread, thereby identifying whether the defects on the wafers have a significant impact on quality, accurately determining whether the wafers are in a failed state, and effectively evaluating the overall performance of the wafers. Furthermore, it identifies defect formation and reproduction in the same manufacturing thread for all wafers in a failed state, identifies improperly executed manufacturing threads, and accurately traces the manufacturing threads that generated the defects, which helps to debug and correct the corresponding manufacturing threads and improve the wafer processing yield. Attached Figure Description

[0073] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0074] Figure 1 This is a schematic flowchart of a semiconductor surface defect detection method based on machine vision provided by the present invention.

[0075] Figure 2 This is a schematic diagram of the random defect distribution on the surface of a wafer.

[0076] Figure 3 This is a schematic diagram of the overall defect distribution on the surface of a wafer.

[0077] Figure 4 This is a schematic diagram of a semiconductor surface defect detection system based on machine vision provided by the present invention. Detailed Implementation

[0078] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, not the entire structure. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0079] The terms “comprising” and “having”, and any variations thereof, used in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0080] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0081] Please see Figure 1 As shown in the figure, an embodiment of this application provides a semiconductor surface defect detection method based on machine vision. This machine vision-based semiconductor surface defect detection method includes:

[0082] By comparing and analyzing the surface machine vision recognition data of several wafers, the commonalities in defect distribution among all wafers are determined; based on these commonalities, the system defects of the wafers are extracted.

[0083] Based on the defect morphology of the system defects of the wafer, a defect distribution characterization map of the wafer in the corresponding manufacturing thread is generated; based on the defect distribution characterization map of the wafer in all manufacturing threads, the surface defect clustering characteristics of the wafer are determined.

[0084] Based on the clustering characteristics of surface defects, it is determined whether the wafer is in a failed state; for all wafers in a failed state, defect formation reproduction identification is performed to determine the improperly executed manufacturing thread.

[0085] The beneficial effects of the above embodiments are as follows: This machine vision-based semiconductor surface defect detection method compares and analyzes the surface machine vision recognition data of several wafers to determine the commonalities in defect distribution across all wafers, extracts system defects from the wafers, and accurately and comprehensively identifies defects caused by equipment or processes within the wafers; it generates a defect distribution characterization map of the wafers across all manufacturing threads, thereby determining the surface defect clustering characteristics of the wafers, comprehensively labeling the types and distribution of defects generated by the wafers in each manufacturing thread, thereby identifying whether the defects on the wafers have a significant impact on quality, accurately determining whether the wafers are in a failed state, and effectively evaluating the overall performance of the wafers; it also identifies the defect formation reproduction of all wafers in a failed state in the same manufacturing thread, identifies the improperly executed manufacturing thread, and accurately traces the manufacturing thread that generated the defect, which helps to debug and correct the corresponding manufacturing thread and improve the wafer processing yield.

[0086] In another embodiment, surface machine vision recognition data of several wafers are compared and analyzed to determine the commonalities in defect distribution across all wafers; based on these commonalities, system defects of the wafers are extracted, including:

[0087] After each manufacturing thread of several wafers is completed, the surface images of the processed wafers are acquired. Machine vision recognition is performed on the surface images to obtain the surface machine vision recognition data of the wafers after each manufacturing thread is completed. The surface machine vision recognition data includes the defect distribution location data of the wafer surface.

[0088] Spatial distribution comparison analysis was performed on the surface machine vision recognition data of all wafers after they completed the same manufacturing thread to determine the commonalities in defect distribution among all wafers; among which, the commonalities in defect distribution include the correlation of the positional distribution of surface defects among all wafers.

[0089] Based on the commonalities in defect distribution across all wafers, identify the random defects on the surface of each wafer. Compare these random defects with the overall surface defects of the wafer after completing the corresponding manufacturing thread to extract the system defects of the wafer in that manufacturing thread.

[0090] Integrated circuit manufacturing uses wafers as substrates and employs multiple manufacturing threads (multiple fabrication processes) to create a large number of electronic components and their wiring on the wafer surface, forming a complete circuit layout. Influenced by factors such as the manufacturing environment, hardware operating performance, and process parameters, undesirable defects may arise after each manufacturing thread on the wafer. These undesirable defects can be categorized by their causes, including but not limited to random defects and system defects, and by their physical form, including structural defects and foreign matter defects. Random defects are those generated by manufacturing environment conditions; their distribution on the wafer surface exhibits significant randomness, and their causes are difficult to pinpoint accurately. System defects are those generated by hardware operating performance and process parameters; their number and physical form are closely related to these factors, and improving hardware operating performance and process parameters can significantly reduce system defects. Structural defects refer to structural morphological defects formed on the wafer surface, such as scratches and dents. Foreign matter defects are those formed on the wafer surface due to the adhesion of foreign matter such as dust or oil. During the manufacturing process of wafers, both random and system defects are generated simultaneously. These two types of defects are superimposed on the wafer surface. Considering that random and system defects have different causes and can have the same structural and foreign object defect morphology, it is impossible to accurately distinguish between random and system defects on the same wafer. Therefore, it is impossible to identify the system defects of the wafer separately, and it cannot provide a basis for improving the hardware operation and process parameters of the manufacturing thread that generates the above-mentioned system defects.

[0091] Considering that all wafers operate under identical manufacturing environment conditions during the same manufacturing thread, it can be assumed that random defects generated by all wafers during the same manufacturing thread exhibit similar structural morphology and spatial distribution. When the number of wafers operating under the same manufacturing thread is sufficiently large, surface defect data from all wafers undergoing the same manufacturing thread can be compared and analyzed to identify similar surface defect information, thus determining the random defects generated by each wafer after passing through that manufacturing thread. Specifically, after each wafer completes an identical manufacturing thread, images of the processed surfaces of all wafers (i.e., global images of the surfaces on which electronic components are manufactured) are acquired. A deep learning neural network model is then used to perform machine vision recognition on these processed surface images to obtain surface defect distribution location data for each wafer after completing each manufacturing thread. This surface defect distribution location data includes both random and system defect distribution location data on the wafer surface. Then, the surface machine vision recognition data of all wafers after completing the same manufacturing thread are input into a neural network model such as Support Vector Machine (SVM) for spatial distribution comparison analysis to obtain the correlation of the location distribution of surface defects of all wafers. The correlation of the location distribution of surface defects can be, but is not limited to, the similarity of the distribution location vector clusters of surface defects of wafers, thereby obtaining the commonality of defect distribution of all wafers, providing a reliable basis for subsequently determining the random defects generated after all wafers complete the corresponding manufacturing thread.

[0092] The above analysis shows that random defects generated in the same manufacturing thread on all wafers exhibit similarities in structural morphology and spatial distribution. The commonalities in defect distribution across all wafers are strongly correlated with these random defects. Therefore, by applying transfer learning based on these commonalities in defect distribution across all wafers, the individual random defects on the surface of each wafer can be identified. Figure 2 As shown, the random defect distribution on the surface of a wafer is obtained after transfer learning processing of the commonalities in defect distribution. Figure 2 It is evident that defects on the wafer surface are randomly distributed, and the area occupied by defects is relatively small. This aligns with the aforementioned description of random absence. Therefore, by comparing and analyzing the machine vision recognition data of all wafer surfaces, and obtaining the commonalities in defect distribution, the random defect distribution on the wafer surface can be further determined. Furthermore, as... Figure 3 The image shows the overall defect distribution on the surface of a wafer after it has undergone a specific manufacturing process. It can be understood that... Figure 3 The overall surface defect distribution of a wafer includes both random and systematic defects. By comparing the random defects on the wafer surface with the overall surface defects after completing the corresponding manufacturing thread, the systematic defects generated by the wafer in that manufacturing thread can be extracted. Figure 2 and Figure 3 Perform pixel feature comparison, from Figure 3 Remove from Figure 2 The corresponding defect features can be used to extract the system defects generated on the wafer surface by the current manufacturing thread.

[0093] In another embodiment, a defect distribution characterization map of the wafer in the corresponding manufacturing thread is generated based on the defect morphology of the system defects of the wafer; based on the defect distribution characterization map of the wafer in all manufacturing threads, the surface defect clustering characteristics of the wafer are determined, including:

[0094] Defect image pixel recognition is performed on the system defects of the wafer to obtain the three-dimensional morphology and contour data of the system defects; based on the three-dimensional morphology and contour data, a defect distribution characterization map of the wafer in the corresponding manufacturing thread is generated; wherein, the defect distribution characterization map includes the distribution location characterization map of structural defects and foreign matter defects formed on the wafer in the corresponding manufacturing thread.

[0095] Based on the wafer's outline, the defect distribution characterization maps of the wafer across all manufacturing threads are aligned and overlapped. The overall defect distribution characterization map after alignment and overlap is then analyzed to determine the surface defect clustering characteristics of the wafer. Among these, the surface defect clustering characteristics include the clustering characteristics of structural defects and foreign matter defects on the wafer surface.

[0096] The above analysis shows that defects on the wafer surface can be physically categorized into structural defects and foreign matter defects. The causes of these two types of defects are also different. For example, structural defects can be scratches or dents caused by improper hardware operation or process parameter settings, while foreign matter defects can be caused by hardware malfunctions leading to dust or oil adhering to the wafer surface. Furthermore, structural defects and foreign matter defects differ significantly in their appearance on the wafer surface. Structural defects directly cause physical damage to a portion of the wafer surface, while foreign matter defects are foreign objects adhering to the wafer surface. To effectively eliminate structural and foreign matter defects on the wafer surface during subsequent manufacturing processes, it is necessary to accurately and comprehensively distinguish between these two types of defects. Specifically, defect image pixel recognition is performed on the system defects of the wafer to obtain the three-dimensional morphology and contour data of the system defects. This generates a defect distribution characterization map of the wafer in the corresponding manufacturing thread, and a global characterization map of the distribution location of structural and foreign matter defects formed in the corresponding manufacturing thread on the wafer surface, comprehensively characterizing the distribution of structural and foreign matter defects on the wafer surface in terms of location, shape, and size.

[0097] A wafer requires multiple manufacturing threads to fabricate a complete circuit layout on its surface. Simply looking at the defect distribution on the wafer's surface after one manufacturing thread is insufficient to accurately determine its functionality. Therefore, it's necessary to integrate and identify the defect distribution characterization maps corresponding to each of the wafer's manufacturing threads to determine if the circuit layout is affected by defects and malfunctions. Specifically, based on the wafer's outer perimeter shape, the defect distribution characterization maps from all manufacturing threads are aligned and overlapped to obtain a comprehensive defect distribution characterization map. This comprehensive map fully reflects the defects (including structural and foreign matter defects) formed on the wafer surface by all manufacturing threads. Then, a Support Vector Machine (SVM) neural network model is used to analyze the comprehensive defect distribution characterization map to determine the clustering characteristics of structural and foreign matter defects on the wafer surface. This provides a unified characterization of the spatial distribution location and spatial occupancy of all structural and foreign matter defects on the wafer surface, offering a basis for subsequent judgments on wafer failure.

[0098] In another embodiment, based on surface defect clustering characteristics, it is determined whether the wafer is in a failed state; for all wafers in a failed state, defect formation reproduction identification is performed to determine improperly executed manufacturing threads, including:

[0099] Based on the clustering characteristics of structural defects and foreign matter defects on the wafer surface, the spatial proportion of the failure area on the wafer surface is estimated; whereby the spatial proportion of the failure area refers to the spatial overlap ratio between the failure area and the circuit wiring area on the wafer surface; based on the spatial proportion of the failure area, it is determined whether the wafer is in a failure state.

[0100] For all wafers in a failed state, perform defect formation and reproduction identification on the surface machine vision recognition data corresponding to the same manufacturing thread to obtain the probability of defect recurrence of wafers in the same manufacturing thread; based on the probability of defect recurrence, determine whether the manufacturing thread is an improperly executed manufacturing thread.

[0101] When structural defects and foreign matter defects on the wafer surface significantly overlap with the circuit layout area, these defects will inevitably affect the normal operation of the circuit, leading to overall circuit failure of the wafer. To determine whether a wafer is in a failed state, the spatial proportion of the failed area on the wafer surface is estimated based on the clustering characteristics of the structural defects and foreign matter defects. A threshold comparison is then performed on this failed area proportion. If the failed area proportion exceeds a preset threshold, the wafer is determined to be in a failed state; otherwise, it is determined not to be in a failed state. This facilitates rapid and accurate quality control screening of wafers after all manufacturing processes are completed.

[0102] When a wafer is in a failed state, it must be due to a hardware malfunction and / or incorrect process parameter settings in at least one of the manufacturing threads the wafer has passed through. If a manufacturing thread is missing due to a hardware malfunction and / or incorrect process parameter settings, the surface of each wafer after passing through the aforementioned manufacturing thread will also show the same or similar defects (including structural defects and / or foreign matter defects). It can be seen that by analyzing the recurrence of surface defects after all wafers have passed through the same manufacturing thread, it is possible to inversely determine whether there are hardware malfunctions and / or improper execution of process parameter settings in the corresponding manufacturing thread. Specifically, defect formation and reproduction identification is performed on the surface machine vision recognition data of all wafers in the same manufacturing thread that are in a failed state. This yields the probability of defect recurrence on the wafers in the same manufacturing thread. In other words, the surface machine vision recognition data of all wafers after passing through the same manufacturing thread are compared by defect data indexing and defect data reproduction. This determines whether the defect types, defect locations, and defect shapes and sizes of the wafers after passing through the same manufacturing thread are the same or extremely similar. This allows for the calculation of the probability of defect recurrence on all wafers in the same manufacturing thread. If the probability of defect recurrence exceeds a preset probability threshold, the corresponding manufacturing thread is determined to be an improperly executed manufacturing thread. Otherwise, the corresponding manufacturing thread is determined not to be an improperly executed manufacturing thread. This facilitates subsequent hardware operation and process parameter debugging of improperly executed manufacturing threads, thereby improving the wafer processing yield.

[0103] In another embodiment, the spatial proportion of the failure region on the wafer surface is estimated based on the clustering characteristics of structural defects and foreign matter defects on the wafer surface, including:

[0104] Extract the number of periodic defect clusters of structural defects on the surface of the wafer;

[0105] The structural defect periodicity factor is obtained based on the area of ​​the structural defect cluster corresponding to each periodic defect cluster.

[0106] The structural defect periodicity factor is obtained by the following formula:

[0107]

[0108] Where E represents the structural defect periodicity factor; N c S represents the number of periodic defect clusters representing structural defects on the surface of the wafer; i S represents the area of ​​the structural defect cluster corresponding to the i-th periodic defect cluster; p S represents the average cluster area of ​​structural defects; a α represents the surface area of ​​the wafer; α represents the process sensitivity coefficient, with a value ranging from 0.7 to 1.3.

[0109] Extract the number of foreign defects on the surface of the wafer;

[0110] The vertical distance between each foreign object defect and its adjacent structural defects is obtained based on the location of each foreign object defect.

[0111] The foreign object defect distribution factor is obtained based on the vertical distance between each foreign object defect and the adjacent structural defect.

[0112] The foreign object defect distribution factor is obtained by the following formula:

[0113]

[0114] Where K represents the foreign object defect distribution factor; N p Indicates the number of foreign object defects; D i D represents the perpendicular distance between the i-th foreign object defect and the adjacent structural defect; p R represents the average vertical distance between foreign object defects and adjacent structural defects; R represents the chi-square test critical value (3.84 at 95% confidence level);

[0115] The spatial proportion of the failure region on the surface of the wafer is obtained by using the structural defect periodicity factor and the foreign object defect distribution factor.

[0116] The proportion of the space of the failure area on the surface of the wafer is obtained by the following formula:

[0117]

[0118] Where G represents the proportion of the failure area on the wafer surface; λ represents the preset defect type weighting factor; and D(x, y) represents the circuit routing density distribution function of the circuit routing area.

[0119] By comprehensively considering structural defects and foreign matter defects on the wafer surface, this technical solution can more accurately assess the spatial proportion of the failure area on the wafer. This helps manufacturers to promptly identify and address potential quality issues during production, thereby improving the overall quality and reliability of the product. By extracting the number of periodic defect clusters and the number of foreign matter defects on the wafer surface and calculating them using relevant factors, this technical solution can quickly and accurately identify the failure area of ​​the wafer. This significantly improves detection efficiency, shortens the production cycle, and reduces production costs. The structural defect periodicity factor and foreign matter defect distribution factor in this technical solution are closely related to the wafer manufacturing process. Through the calculation and analysis of these two factors, manufacturers can gain a deeper understanding of potential problems in the process, thereby enabling them to adjust and optimize process parameters in a targeted manner, improving the manufacturing quality and consistency of the product. The formulas and parameters in the technical solution can be customized according to different wafer types, manufacturing processes, and circuit wiring density distribution functions. This makes the technical solution more flexible and adaptable, meeting the needs of different manufacturers and products. By accurately assessing the spatial proportion of failure areas on a wafer, manufacturers can pay closer attention to these potential problem areas during product design and manufacturing, thereby taking appropriate measures to improve product reliability and stability. This helps extend product lifespan and reduce repair and replacement costs.

[0120] Please see Figure 4 As shown in the figure, an embodiment of this application provides a semiconductor surface defect detection system based on machine vision. This machine vision-based semiconductor surface defect detection system includes:

[0121] The defect commonality identification module is used to compare and analyze the surface machine vision recognition data of several wafers to determine the commonality of defect distribution among all wafers.

[0122] The system defect extraction module is used to extract system defects of wafers based on the commonalities in defect distribution;

[0123] The defect characterization map generation module is used to generate a defect distribution characterization map of the wafer in the corresponding manufacturing thread based on the defect morphology of the system defects of the wafer.

[0124] The defect clustering feature determination module is used to determine the surface defect clustering features of the wafer based on the defect distribution characterization map of the wafer across all manufacturing threads;

[0125] The failure status determination module is used to determine whether the wafer is in a failure state based on the clustering characteristics of surface defects.

[0126] The manufacturing thread calibration module is used to identify defect formation reproduction in all wafers in a failed state and determine the improperly executed manufacturing thread.

[0127] In another embodiment, the defect commonality identification module is used to compare and analyze the surface machine vision recognition data of several wafers to determine the commonality of defect distribution among all wafers, including:

[0128] After each manufacturing thread of several wafers is completed, the surface images of the processed wafers are acquired. Machine vision recognition is performed on the surface images to obtain the surface machine vision recognition data of the wafers after each manufacturing thread is completed. The surface machine vision recognition data includes the defect distribution location data of the wafer surface.

[0129] Spatial distribution comparison analysis was performed on the surface machine vision recognition data of all wafers after they completed the same manufacturing thread to determine the commonalities in defect distribution among all wafers; among which, the commonalities in defect distribution include the correlation of the positional distribution of surface defects among all wafers.

[0130] The system defect extraction module is used to extract system defects of the wafer based on the commonalities in defect distribution, including:

[0131] Based on the commonalities in defect distribution across all wafers, identify the random defects on the surface of each wafer. Compare these random defects with the overall surface defects of the wafer after completing the corresponding manufacturing thread to extract the system defects of the wafer in that manufacturing thread.

[0132] In another embodiment, the defect characterization map generation module is used to generate a defect distribution characterization map of the wafer in the corresponding manufacturing thread based on the defect morphology of the system defects of the wafer, including:

[0133] Defect image pixel recognition is performed on the system defects of the wafer to obtain the three-dimensional morphology and contour data of the system defects; based on the three-dimensional morphology and contour data, a defect distribution characterization map of the wafer in the corresponding manufacturing thread is generated; wherein, the defect distribution characterization map includes the distribution location characterization map of structural defects and foreign matter defects formed on the wafer in the corresponding manufacturing thread.

[0134] The defect clustering feature determination module is used to determine the surface defect clustering features of the wafer based on the defect distribution characterization map of the wafer across all manufacturing threads, including:

[0135] Based on the wafer's outline, the defect distribution characterization maps of the wafer across all manufacturing threads are aligned and overlapped. The overall defect distribution characterization map after alignment and overlap is then analyzed to determine the surface defect clustering characteristics of the wafer. Among these, the surface defect clustering characteristics include the clustering characteristics of structural defects and foreign matter defects on the wafer surface.

[0136] In another embodiment, the failure state determination module is used to determine whether the wafer is in a failure state based on surface defect clustering characteristics, including:

[0137] Based on the clustering characteristics of structural defects and foreign matter defects on the wafer surface, the spatial proportion of the failure area on the wafer surface is estimated; whereby the spatial proportion of the failure area refers to the spatial overlap ratio between the failure area and the circuit wiring area on the wafer surface; based on the spatial proportion of the failure area, it is determined whether the wafer is in a failure state.

[0138] The manufacturing thread calibration module is used to identify defect formation reproduction in all wafers in a failed state and to determine improperly executed manufacturing threads, including:

[0139] For all wafers in a failed state, perform defect formation and reproduction identification on the surface machine vision recognition data corresponding to the same manufacturing thread to obtain the probability of defect recurrence of wafers in the same manufacturing thread; based on the probability of defect recurrence, determine whether the manufacturing thread is an improperly executed manufacturing thread.

[0140] The operation and effect of the machine vision-based semiconductor surface defect detection system of the present invention are consistent with the above-mentioned machine vision-based semiconductor surface defect detection method, and the machine vision-based semiconductor surface defect detection system will not be described again here.

[0141] In another embodiment, the spatial proportion of the failure region on the wafer surface is estimated based on the clustering characteristics of structural defects and foreign matter defects on the wafer surface, including:

[0142] Extract the number of periodic defect clusters of structural defects on the surface of the wafer;

[0143] The structural defect periodicity factor is obtained based on the area of ​​the structural defect cluster corresponding to each periodic defect cluster.

[0144] The structural defect periodicity factor is obtained by the following formula:

[0145]

[0146] Where E represents the structural defect periodicity factor; N c S represents the number of periodic defect clusters representing structural defects on the surface of the wafer; i S represents the area of ​​the structural defect cluster corresponding to the i-th periodic defect cluster; p S represents the average cluster area of ​​structural defects; a α represents the surface area of ​​the wafer; α represents the process sensitivity coefficient, with a value ranging from 0.7 to 1.3.

[0147] Extract the number of foreign defects on the surface of the wafer;

[0148] The vertical distance between each foreign object defect and its adjacent structural defects is obtained based on the location of each foreign object defect.

[0149] The foreign object defect distribution factor is obtained based on the vertical distance between each foreign object defect and the adjacent structural defect.

[0150] The foreign object defect distribution factor is obtained by the following formula:

[0151]

[0152] Where K represents the foreign object defect distribution factor; N p Indicates the number of foreign object defects; D i D represents the perpendicular distance between the i-th foreign object defect and the adjacent structural defect; p R represents the average vertical distance between foreign object defects and adjacent structural defects; R represents the chi-square test critical value (3.84 at 95% confidence level);

[0153] The spatial proportion of the failure region on the surface of the wafer is obtained by using the structural defect periodicity factor and the foreign object defect distribution factor.

[0154] The proportion of the space of the failure area on the surface of the wafer is obtained by the following formula:

[0155]

[0156] Where G represents the proportion of the failure area on the wafer surface; λ represents the preset defect type weighting factor; and D(x, y) represents the circuit routing density distribution function of the circuit routing area.

[0157] By comprehensively considering structural defects and foreign matter defects on the wafer surface, this technical solution can more accurately assess the spatial proportion of the failure area on the wafer. This helps manufacturers to promptly identify and address potential quality issues during production, thereby improving the overall quality and reliability of the product. By extracting the number of periodic defect clusters and the number of foreign matter defects on the wafer surface and calculating them using relevant factors, this technical solution can quickly and accurately identify the failure area of ​​the wafer. This significantly improves detection efficiency, shortens the production cycle, and reduces production costs. The structural defect periodicity factor and foreign matter defect distribution factor in this technical solution are closely related to the wafer manufacturing process. Through the calculation and analysis of these two factors, manufacturers can gain a deeper understanding of potential problems in the process, thereby enabling them to adjust and optimize process parameters in a targeted manner, improving the manufacturing quality and consistency of the product. The formulas and parameters in the technical solution can be customized according to different wafer types, manufacturing processes, and circuit wiring density distribution functions. This makes the technical solution more flexible and adaptable, meeting the needs of different manufacturers and products. By accurately assessing the spatial proportion of failure areas on a wafer, manufacturers can pay closer attention to these potential problem areas during product design and manufacturing, thereby taking appropriate measures to improve product reliability and stability. This helps extend product lifespan and reduce repair and replacement costs.

[0158] In summary, this machine vision-based semiconductor surface defect detection method and system compares and analyzes surface machine vision recognition data from several wafers to determine the commonalities in defect distribution across all wafers, extracts system defects from the wafers, and accurately and comprehensively identifies defects caused by equipment or processes within the wafers. It generates defect distribution characterization maps of the wafers across all manufacturing threads, thereby determining the surface defect clustering characteristics of the wafers. It comprehensively labels the types and distribution of defects generated by the wafers in each manufacturing thread, thus identifying whether the defects on the wafers have a significant impact on quality, accurately determining whether the wafers are in a failed state, and effectively evaluating the overall performance of the wafers. Furthermore, it identifies defect formation reproduction in the same manufacturing thread for all wafers in a failed state, identifies improperly executed manufacturing threads, and accurately traces the manufacturing threads that generated the defects, which helps to debug and correct the corresponding manufacturing threads and improve the wafer processing yield.

[0159] The above is only one specific embodiment of the present invention, and any improvements made based on the concept of the present invention shall be considered within the scope of protection of the present invention.

Claims

1. A semiconductor surface defect detection method based on machine vision, characterized in that, include: By comparing and analyzing the surface machine vision recognition data of several wafers, the commonalities in the defect distribution of all wafers were determined. Based on the commonalities in the defect distribution, system defects of the wafer are extracted; Based on the defect morphology of the system defects of the wafer, a defect distribution characterization map of the wafer in the corresponding manufacturing thread is generated; based on the defect distribution characterization map of the wafer in all manufacturing threads, the surface defect clustering characteristics of the wafer are determined. Based on the surface defect clustering characteristics, it is determined whether the wafer is in a failed state; Defect formation reproduction identification is performed on all wafers in a failed state to determine improperly executed manufacturing threads; By comparing and analyzing the surface machine vision recognition data of several wafers, the commonalities in the defect distribution of all wafers were determined. Based on the commonalities in the defect distribution, the system defects of the wafer are extracted, including: After each manufacturing thread of several wafers is completed, a processing surface image is acquired, and machine vision recognition is performed on the processing surface image to obtain surface machine vision recognition data of the wafer after each manufacturing thread is completed; wherein the surface machine vision recognition data includes defect distribution location data on the wafer surface; Spatial distribution comparison analysis was performed on the surface machine vision recognition data of all wafers after each of the same manufacturing threads to determine the commonalities in defect distribution among all wafers; wherein, the commonalities in defect distribution include the correlation of the positional distribution of surface defects among all wafers; Based on the commonalities in defect distribution across all wafers, identify the random defects on the surface of each wafer. Compare these random defects with the overall surface defects of the wafer after completing the corresponding manufacturing thread to extract the system defects of the wafer in that manufacturing thread.

2. The semiconductor surface defect detection method based on machine vision as described in claim 1, characterized in that: Based on the defect morphology of the system defects of the wafer, a defect distribution characterization map of the wafer in the corresponding manufacturing thread is generated; based on the defect distribution characterization map of the wafer across all manufacturing threads, the surface defect clustering characteristics of the wafer are determined, including: Defect image pixel recognition is performed on the system defects of the wafer to obtain the three-dimensional morphology and contour data of the system defects; based on the three-dimensional morphology and contour data, a defect distribution characterization map of the wafer in the corresponding manufacturing thread is generated; wherein, the defect distribution characterization map includes a characterization map of the distribution location of structural defects and foreign matter defects formed on the wafer in the corresponding manufacturing thread. Based on the outer contour of the wafer, the defect distribution characterization maps of the wafer across all manufacturing threads are aligned and overlapped, and the overall defect distribution characterization map after alignment and overlap is analyzed to determine the surface defect clustering characteristics of the wafer; wherein, the surface defect clustering characteristics include the clustering characteristics of structural defects and foreign matter defects on the surface of the wafer.

3. The semiconductor surface defect detection method based on machine vision as described in claim 1, characterized in that: Based on the surface defect clustering characteristics, it is determined whether the wafer is in a failed state; Defect formation reproduction identification is performed on all wafers in a failed state to identify improperly executed manufacturing threads, including: Based on the clustering characteristics of structural defects and foreign matter defects on the wafer surface, the spatial proportion of the failure area on the wafer surface is estimated; wherein, the spatial proportion of the failure area refers to the spatial overlap ratio between the failure area and the circuit wiring area on the wafer surface; based on the spatial proportion of the failure area, it is determined whether the wafer is in a failure state. For all wafers in a failed state, perform defect formation reproduction identification on the surface machine vision recognition data corresponding to the same manufacturing thread to obtain the probability of defect recurrence of the wafer in the same manufacturing thread; based on the probability of defect recurrence, determine whether the manufacturing thread is an improperly executed manufacturing thread.

4. The semiconductor surface defect detection method based on machine vision as described in claim 3, characterized in that: Based on the clustering characteristics of structural defects and foreign matter defects on the wafer surface, the spatial proportion of the failure region on the wafer surface is estimated, including: Extract the number of periodic defect clusters of structural defects on the surface of the wafer; The structural defect periodicity factor is obtained based on the area of ​​the structural defect cluster corresponding to each periodic defect cluster. The structural defect periodicity factor is obtained by the following formula: ， Where E represents the structural defect periodicity factor; N c S represents the number of periodic defect clusters representing structural defects on the surface of the wafer; i S represents the area of ​​the structural defect cluster corresponding to the i-th periodic defect cluster; p S represents the average cluster area of ​​structural defects; a α represents the surface area of ​​the wafer; α represents the process sensitivity coefficient, with a value ranging from 0.7 to 1.

3. Extract the number of foreign defects on the surface of the wafer; The vertical distance between each foreign object defect and its adjacent structural defects is obtained based on the location of each foreign object defect. The foreign object defect distribution factor is obtained based on the vertical distance between each foreign object defect and the adjacent structural defect. The foreign object defect distribution factor is obtained by the following formula: ， Where K represents the foreign object defect distribution factor; N p Indicates the number of foreign object defects; D i D represents the perpendicular distance between the i-th foreign object defect and the adjacent structural defect; p R represents the average vertical distance between foreign body defects and adjacent structural defects; R represents the chi-square test critical value. The spatial proportion of the failure region on the surface of the wafer is obtained by using the structural defect periodicity factor and the foreign object defect distribution factor. The proportion of the space of the failure area on the surface of the wafer is obtained by the following formula: ， Where G represents the proportion of the failure area on the wafer surface; λ represents the preset defect type weighting factor; and D(x,y) represents the circuit routing density distribution function of the circuit routing area.

5. A semiconductor surface defect detection system based on machine vision, characterized in that, include: The defect commonality identification module is used to compare and analyze the surface machine vision recognition data of several wafers to determine the commonality of defect distribution among all wafers. The system defect extraction module is used to extract system defects of the wafer based on the commonalities in the defect distribution. The defect characterization map generation module is used to generate a defect distribution characterization map of the wafer in the corresponding manufacturing thread based on the defect morphology of the system defects of the wafer. The defect clustering feature determination module is used to determine the surface defect clustering features of the wafer based on the defect distribution characterization map of the wafer across all manufacturing threads. The failure state determination module is used to determine whether the wafer is in a failure state based on the surface defect clustering characteristics. The manufacturing thread calibration module is used to identify defect formation reproduction in all wafers in a failed state and determine the improperly executed manufacturing thread; The defect commonality identification module is used to compare and analyze the surface machine vision recognition data of several wafers to determine the commonalities in defect distribution across all wafers, including: After each manufacturing thread of several wafers is completed, a processing surface image is acquired, and machine vision recognition is performed on the processing surface image to obtain surface machine vision recognition data of the wafer after each manufacturing thread is completed; wherein the surface machine vision recognition data includes defect distribution location data on the wafer surface; Spatial distribution comparison analysis was performed on the surface machine vision recognition data of all wafers after each of the same manufacturing threads to determine the commonalities in defect distribution among all wafers; wherein, the commonalities in defect distribution include the correlation of the positional distribution of surface defects among all wafers; The system defect extraction module is used to extract system defects of the wafer based on the commonalities in the defect distribution, including: Based on the commonalities in defect distribution across all wafers, identify the random defects on the surface of each wafer. Compare these random defects with the overall surface defects of the wafer after completing the corresponding manufacturing thread to extract the system defects of the wafer in that manufacturing thread.

6. The semiconductor surface defect detection system based on machine vision as described in claim 5, characterized in that: The defect characterization map generation module is used to generate a defect distribution characterization map of the wafer in the corresponding manufacturing thread based on the defect morphology of the system defects of the wafer, including: Defect image pixel recognition is performed on the system defects of the wafer to obtain the three-dimensional morphology and contour data of the system defects; based on the three-dimensional morphology and contour data, a defect distribution characterization map of the wafer in the corresponding manufacturing thread is generated; wherein, the defect distribution characterization map includes a characterization map of the distribution location of structural defects and foreign matter defects formed on the wafer in the corresponding manufacturing thread. The defect clustering feature determination module is used to determine the surface defect clustering features of the wafer based on the defect distribution characterization map of the wafer across all manufacturing threads, including: Based on the outer contour of the wafer, the defect distribution characterization maps of the wafer across all manufacturing threads are aligned and overlapped, and the overall defect distribution characterization map after alignment and overlap is analyzed to determine the surface defect clustering characteristics of the wafer; wherein, the surface defect clustering characteristics include the clustering characteristics of structural defects and foreign matter defects on the surface of the wafer.

7. The semiconductor surface defect detection system based on machine vision as described in claim 5, characterized in that: The failure state determination module is used to determine whether the wafer is in a failure state based on the surface defect clustering characteristics, including: Based on the clustering characteristics of structural defects and foreign matter defects on the wafer surface, the spatial proportion of the failure area on the wafer surface is estimated; wherein, the spatial proportion of the failure area refers to the spatial overlap ratio between the failure area and the circuit wiring area on the wafer surface; based on the spatial proportion of the failure area, it is determined whether the wafer is in a failure state. The manufacturing thread calibration module is used to identify defect formation reproduction in all wafers in a failed state and determine improperly executed manufacturing threads, including: For all wafers in a failed state, perform defect formation reproduction identification on the surface machine vision recognition data corresponding to the same manufacturing thread to obtain the probability of defect recurrence of the wafer in the same manufacturing thread; based on the probability of defect recurrence, determine whether the manufacturing thread is an improperly executed manufacturing thread.

8. The semiconductor surface defect detection system based on machine vision as described in claim 7, characterized in that: Based on the clustering characteristics of structural defects and foreign matter defects on the wafer surface, the spatial proportion of the failure region on the wafer surface is estimated, including: Extract the number of periodic defect clusters of structural defects on the surface of the wafer; The structural defect periodicity factor is obtained based on the area of ​​the structural defect cluster corresponding to each periodic defect cluster. The structural defect periodicity factor is obtained by the following formula: ， Where E represents the structural defect periodicity factor; N c S represents the number of periodic defect clusters representing structural defects on the surface of the wafer; i S represents the area of ​​the structural defect cluster corresponding to the i-th periodic defect cluster; p S represents the average cluster area of ​​structural defects; a α represents the surface area of ​​the wafer; α represents the process sensitivity coefficient, with a value ranging from 0.7 to 1.

3. Extract the number of foreign defects on the surface of the wafer; The vertical distance between each foreign object defect and its adjacent structural defects is obtained based on the location of each foreign object defect. The foreign object defect distribution factor is obtained based on the vertical distance between each foreign object defect and the adjacent structural defect. The foreign object defect distribution factor is obtained by the following formula: ， Where K represents the foreign object defect distribution factor; N p Indicates the number of foreign object defects; D i D represents the perpendicular distance between the i-th foreign object defect and the adjacent structural defect; p R represents the average vertical distance between foreign body defects and adjacent structural defects; R represents the chi-square test critical value. The spatial proportion of the failure region on the surface of the wafer is obtained by using the structural defect periodicity factor and the foreign object defect distribution factor. The proportion of the space of the failure area on the surface of the wafer is obtained by the following formula: ， Where G represents the proportion of the failure area on the wafer surface; λ represents the preset defect type weighting factor; and D(x,y) represents the circuit routing density distribution function of the circuit routing area.

Images