Display device

Abstract

The invention relates to a display device. A display device includes: a display panel including pixels; a voltage generator for generating a plurality of driving voltages; an illuminance sensor for sensing an amount of ambient light of the display panel and generating a sensing value corresponding to a sensing result; and a driver for generating data signals to be transmitted to the pixels. The driver controls the voltage generator to change at least one driving voltage among the plurality of driving voltages based on the sensing value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2024-0041090, filed on March 26, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure generally relates to a display device and a method of driving the display device. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information increases. Therefore, display devices such as liquid crystal display devices and organic light emitting display devices are increasingly used.

[0005] When a display device is used outdoors rather than indoors, the driving voltage may be affected by ultraviolet light incident on the display panel of the display device. Specifically, as the intensity of ultraviolet light incident on the display panel becomes stronger, the driving voltage used in the display device may increase. This may affect the image quality of the display device. Summary of the Invention

[0006] Embodiments provide a display device capable of compensating for a driving voltage that varies according to external illuminance.

[0007] Embodiments also provide a method of driving a display device, which can compensate for a driving voltage that varies according to external illuminance.

[0008] According to one aspect of the present disclosure, a display device is provided, comprising: a display panel including pixels; a voltage generator configured to generate a plurality of driving voltages; an illuminance sensor configured to sense an amount of ambient light of the display panel and generate a sensing value corresponding to the sensing result; and a driver configured to generate a data signal transmitted to the pixels, wherein the driver controls the voltage generator based on the sensing value to change at least one driving voltage among the plurality of driving voltages.

[0009] The display device may further include a memory configured to store a driving lookup table. The driver may include a controller configured to generate a first offset value corresponding to the sensed value with reference to the driving lookup table and provide the first offset value to the voltage generator.

[0010] The pixel may include: a pixel circuit connected to a line configured to provide a first power voltage; and a light emitting element connected between the pixel circuit and the line configured to provide a second power voltage. The voltage generator may generate the second power voltage using the first offset value.

[0011] The voltage generator may generate the second power voltage by adding the first offset value to the initial second power voltage.

[0012] The pixel circuit may include at least one P-type transistor. The voltage generator may use the first offset value to generate a voltage provided to a gate of the at least one P-type transistor and used to turn on the at least one P-type transistor.

[0013] The pixel circuit may include at least one N-type transistor. The voltage generator may use the first offset value to generate a voltage provided to a gate of the at least one N-type transistor and used to turn off the at least one N-type transistor.

[0014] The controller may receive first image data and generate second image data based on the first image data. The driver may further include: a data converter configured to receive the second image data and generate a voltage value corresponding to the second image data; and a data driver connected to the pixels via data lines, the data driver generating a data signal corresponding to the voltage value and providing the generated data signal to the data lines. The controller may generate a second offset value corresponding to the sensed value with reference to a drive lookup table, and provide the second offset value to the voltage generator.

[0015] The pixel may include: a pixel circuit connected to a line configured to provide a first power voltage; and a light-emitting element connected between the pixel circuit and the line configured to provide a second power voltage. The pixel circuit may include at least one N-type transistor. The voltage generator may use a second offset value to generate a voltage that is provided to a gate of the at least one N-type transistor and is used to turn on the at least one N-type transistor.

[0016] The pixel may include: a pixel circuit connected to a line configured to provide a first power voltage; and a light-emitting element connected between the pixel circuit and the line configured to provide a second power voltage. The pixel circuit may include at least one P-type transistor. The voltage generator may use a second offset value to generate a voltage that is provided to a gate of the at least one P-type transistor and is used to turn off the at least one P-type transistor.

[0017] The voltage generator may generate a driving voltage of an operational amplifier included in the data driver using the second offset value.

[0018] The memory may further store a plurality of gamma lookup tables, and the data converter may generate a voltage value using a gamma lookup table corresponding to the sensed value among the plurality of gamma lookup tables.

[0019] According to another aspect of the present disclosure, a method for driving a display device is provided, the method comprising: generating a sensing value by an illuminance sensor; determining at least one offset value corresponding to the sensing value with reference to a driving lookup table; generating at least one driving voltage based on the offset value; and displaying an image using the driving voltage.

[0020] In generating the at least one driving voltage, when the sensed value indicates a higher illuminance, a smaller voltage may be generated as the driving voltage.

[0021] Generating at least one driving voltage based on the offset value may include generating a power voltage provided to a pixel of the display device based on the offset value.

[0022] Generating at least one driving voltage based on the offset value may include generating a voltage supplied to a gate of a P-type transistor included in a pixel of the display device based on the offset value.

[0023] Generating at least one driving voltage based on the offset value may include generating a voltage supplied to a gate of an N-type transistor included in a pixel of the display device based on the offset value.

[0024] Generating at least one driving voltage based on the offset value may include generating a driving voltage of an operational amplifier included in a data driver configured to generate a data signal to be provided to a data line connected to a pixel of the display device based on the offset value.

[0025] According to another aspect of the present disclosure, a method for driving a display device is provided, the method comprising: generating a sensing value by an illuminance sensor; determining at least one offset value and a gamma lookup table corresponding to the sensing value with reference to a driving lookup table; generating at least one driving voltage based on the offset value; generating a voltage value corresponding to input image data using the gamma lookup table; and displaying an image using the driving voltage and the voltage value.

[0026] In generating the at least one driving voltage, when the sensed value indicates a higher illuminance, a smaller voltage may be generated as the driving voltage.

[0027] Generating at least one driving voltage based on the offset value may include generating a power voltage provided to a pixel of the display device based on the offset value. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0029] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may be present. The same reference numerals represent the same elements throughout.

[0030] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0031] Figure 2 yes Figure 1 An exemplary circuit diagram of a pixel is shown.

[0032] Figure 3 yes Figure 1 An exemplary circuit diagram of a data driver is shown.

[0033] Figure 4 It shows Figure 1 A block diagram of an embodiment of a controller is shown.

[0034] Figure 5 It shows Figure 1 A block diagram of the operation of the data converter is shown.

[0035] Figure 6A and Figure 6B are diagrams each illustrating a method of changing the second power voltage and the first low voltage using a first offset value.

[0036] Figure 7A and Figure 7B are diagrams each illustrating a method of changing the voltage and the first high voltage using the second offset value.

[0037] Figure 8 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure.

[0038] Figure 9 is a flowchart illustrating a method of driving a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] The present disclosure can be applied to various variations and different shapes, so only specific examples are used to illustrate in detail. However, the embodiments are not limited to specific shapes, but are applicable to all variations and equivalent materials and replacements. For better understanding, the included drawings are shown in an expanded manner.

[0040] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present disclosure, the "first" element discussed below may also be referred to as the "second" element. As used herein, unless the context clearly indicates otherwise, the singular is intended to include the plural.

[0041] The terms used herein are only used to describe the purpose of specific embodiments and are not intended to be limiting. As used herein, "one", "the" and "at least one" do not represent a limit to quantity and are intended to include both the singular and the plural, unless the context clearly indicates otherwise. For example, "an element" has the same meaning as "at least one element" unless the context clearly indicates otherwise. "At least one" should not be interpreted as limiting "one" or "one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It will also be understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of stated features, wholes, steps, operations, elements and / or parts, but do not exclude the presence and / or addition of one or more other features, wholes, steps, operations, elements, parts and / or their groups.

[0042] In the accompanying drawings, some embodiments are described about functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, line connectors and other electronic circuits. This can be formed by using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, these units and / or modules are programmed and controlled by using software to perform the various functions discussed in this disclosure, and these units and / or modules can be selectively driven by firmware and / or software. In addition, each block, each unit and / or each module can be implemented by dedicated hardware or combined dedicated hardware for performing some functions of blocks, units and / or modules, and processors (e.g., one or more programmed microprocessors and associated circuits) for performing other functions of blocks, units and / or modules. In some embodiments, without departing from the scope of this disclosure, blocks, units and / or modules can be physically divided into two or more discrete blocks, two or more discrete units and / or two or more discrete modules. Furthermore, in some embodiments, blocks, units and / or modules may be physically divided into more complex blocks, more complex units and / or more complex modules without departing from the scope of the present disclosure.

[0043] Hereinafter, a display device according to an embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0044] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0045] refer to Figure 1 , the display device 100 may include a display unit 110 (or display panel), a scan driver 120 , a driver 130 , a memory 140 (or storage unit), an emission driver 150 , a voltage generator 160 (or power supply), and an illuminance sensor 170 .

[0046] The display unit 110 may include scan lines SIL1 to SILn, SCL1 to SCLn, and SWL1 to SWLn (n is a positive integer), data lines DL1 to DLm (m is a positive integer), emission control lines EL1 to ELn, and pixels PXL. The pixels PXL may be arranged in an area defined by the scan lines SIL1 to SILn, SCL1 to SCLn, and SWL1 to SWLn, the data lines DL1 to DLm, and the emission control lines EL1 to ELn.

[0047] Each pixel PXL can be connected to one of the scan lines SIL1 to SILn, one of the scan lines SCL1 to SCLn, at least one of the scan lines SWL1 to SWLn, one of the data lines DL1 to DLm, and one of the emission control lines EL1 to ELn. For example, the pixel PXL located in the i-th row and j-th column can be connected to the i-th scan lines SILi, SCLi, and SWLi, the i+1-th scan line SWLi+1, the j-th data line DLj, and the i-th emission control line ELi (each of i and j is a positive integer).

[0048] The pixel PXL can store or record the data signal (or data voltage) provided through the j-th data line DLj in response to the scan signal provided through the i-th scan line SWLi, and emit light having a brightness corresponding to the stored data signal in response to the emission control signal provided through the i-th emission control line ELi. Figure 2 Let's describe the pixel PXL.

[0049] The scan driver 120 may generate a scan signal based on the scan control signal SCS and sequentially provide the scan signal to the scan lines SIL1 to SILn, SCL1 to SCLn, and SWL1 to SWLn. The scan control signal SCS may include a start signal, a clock signal, etc., and may be provided from the driver 130. For example, the scan driver 120 may include a shift register that sequentially outputs a scan signal corresponding to the start signal in a pulse form using a clock signal.

[0050] The scan driver 120 may be formed in the display unit 110 through the same process as that of forming the pixels PXL, or may be implemented as a separate integrated circuit.

[0051] The emission driver 150 may generate an emission control signal based on the emission drive control signal ECS and sequentially or simultaneously provide the emission control signal to the emission control lines EL1 to ELn. The emission drive control signal ECS may include an emission start signal, an emission clock signal, etc., and may be provided from the driver 130. For example, the emission driver 150 may include a shift register that sequentially outputs an emission control signal corresponding to the emission start signal in a pulse form using an emission clock signal.

[0052] The driver 130 may generate a data signal based on input image data DATA1 provided from the outside (eg, a graphic processor) and a control signal CS.

[0053] The driver 130 may include a controller 131 (or a timing controller), a data converter 132, and a data driver 133. The controller 131, the data converter 132, and the data driver 133 may be implemented as one integrated circuit. However, this is merely exemplary, and the present disclosure is not limited thereto. For another example, the controller 131 may include the data converter 132 to be implemented as one integrated circuit, and the data driver 133 may be implemented as an integrated circuit independent of the controller 131.

[0054] The controller 131 may receive input image data DATA1 and a control signal CS from the outside, generate a scan control signal SCS and a data control signal DCS based on the control signal CS, and convert the input image data DATA1 to generate image data DATA2. The control signal CS may include a vertical synchronization signal, a horizontal synchronization signal, a clock, etc. For example, the controller 131 may convert input image data DATA1 in an RGB format into image data DATA2 in an RGBG format that matches the pixels arranged in the display unit 110.

[0055] The data converter 132 may convert the input grayscale value included in the image data DATA2 into a voltage value VDATA using a gamma lookup table GLUT. The gamma lookup table GLUT may include voltage values ​​VDATA corresponding to the input grayscale value. The gamma lookup table GLUT may be provided to the data converter 132 from the memory 140.

[0056] The data driver 133 may generate a data signal based on the data control signal DCS provided from the controller 131 and the voltage value VDATA provided from the data converter 132, and provide the data signal to the display unit 110 (or the pixel PXL). The data control signal DCS may be a signal for controlling the operation of the data driver 133 and includes a load signal (or a data enable signal) indicating the output of a valid data signal, etc.

[0057] For example, the data driver 133 may be configured to include a shift register, a latch, a decoder, an output buffer, etc. The data driver 133 may sequentially provide or arbitrarily store a voltage value VDATA to the shift register and the latch based on the data control signal DCS, and output a data signal corresponding to the voltage value VDATA to the data line through the decoder.

[0058] The memory 140 may store a gamma lookup table GLUT. For example, the memory 140 may be implemented as a flash memory and may be mounted on a flexible circuit board on which the driver 130 is mounted to be connected to the driver 130 (eg, the data converter 132).

[0059] The memory 140 may further store a driving lookup table CLUT. The driving lookup table CLUT may be transmitted to the controller 131.

[0060] The voltage generator 160 may provide a first power voltage ELVDD and a second power voltage ELVSS. The first power voltage ELVDD and the second power voltage ELVSS are voltages for the operation of the pixel PXL, and the first power voltage ELVDD may have a voltage level higher than that of the second power voltage ELVSS. In addition, an initialization power voltage Vint may be provided to the display unit 110. The initialization power voltage Vint may be provided from the voltage generator 160 to the display unit 110 through the driver 130 (e.g., the data driver 133). In an example, the initialization power voltage Vint may include a first initialization power voltage Vint1 and a second initialization power voltage Vint2.

[0061] In addition, the voltage generator 160 can provide a gate voltage VG to the scan driver 120 and the emission driver 150. The gate voltage VG may be a voltage input to the gate of the transistor included in the pixel PXL in the display device 100. Exemplarily, the gate voltage VG may include a first high voltage VGH1, a first low voltage VGL1, a second high voltage VGH2, and a second low voltage VGL2. The first high voltage VGH1 may be a voltage for turning off the P-type transistor included in the pixel PXL. The first low voltage VGL1 may be a voltage for turning on the P-type transistor included in the pixel PXL. The second high voltage VGH2 may be a voltage for turning on the N-type transistor included in the pixel PXL. The second low voltage VGL2 may be a voltage for turning off the N-type transistor included in the pixel PXL.

[0062] In addition, the voltage generator 160 may provide the first power voltage ELVDD and voltages VLIN1 and AVC_VREF1 to the data driver 133. The voltage VLIN1 may be a voltage for driving an operational amplifier included in the data driver 133. In an embodiment, the voltage AVC_VREF1 may be a black grayscale voltage.

[0063] The illuminance sensor 170 may sense the illuminance at the surrounding area of ​​the display device 100 and generate a sensing value SV corresponding to the sensing result. The sensing value SV may be transmitted to the controller 131 of the driver 130.

[0064] According to the display device 100 of an embodiment of the present disclosure, the driver 130 can receive a sensed value SV from the illuminance sensor 170 and control the operation of the voltage generator 160 based on the received sensed value SV. Specifically, the driver 130 can refer to the drive lookup table CLUT received from the memory 140 to determine the offset value Δv. In an embodiment, the offset value Δv may include a first offset value Δv1 and a second offset value Δv2. The offset value Δv may be a value used to change the value of at least one of the voltages generated by the voltage generator 160. The voltage generator 160 may change the value of at least one of the generated voltages based on the determined offset value Δv.

[0065] As described above, when the display device is used outdoors rather than indoors, the driving voltage may be affected by the ultraviolet light incident on the display panel in the display device. Specifically, as the intensity of the ultraviolet light incident on the display panel becomes stronger, the driving voltage used in the display device may increase. This may have an impact on the image quality of the display device. According to an embodiment of the present disclosure, the illuminance sensor 170 senses the amount of ambient light of the display device 100, thereby generating a sensing value SV, and the controller 131 refers to the drive lookup table CLUT to determine the offset value Δv corresponding to the sensing value SV. The voltage generator 160 changes the value of at least one of the voltages used to drive the display device 100 based on the offset value Δv received from the controller 131.

[0066] At the same time, when some of the voltages generated by the voltage generator 160 are changed, the light generated by each of the pixels PXL of the display unit 110 may be changed, and thus, the brightness and color coordinates of the image displayed by the display unit 110 may be changed. According to an embodiment of the present disclosure, the controller 131 may apply the gamma lookup table GLUT differently according to the offset value Δv determined by the controller 131. Therefore, although some of the voltages generated by the voltage generator 160 are changed, the change in the color coordinates of the image displayed by the display unit 110 can be minimized.

[0067] Figure 2 yes Figure 1 An exemplary circuit diagram of a pixel is shown.

[0068] exist Figure 2 In the figure, the following is shown as an example: Figure 1 The j-th data line DLj (hereinafter referred to as data line DLj) among the data lines DL1 to DLm shown in FIG. Figure 1 The i-th scan line SILi, SCLi and SWLi, the i+1-th scan line SWLi+1 (hereinafter referred to as the scan line SILi, SCLi, SWLi or SWLi+1) among the scan lines SIL1 to SILn, SCL1 to SCLn and SWL1 to SWLn, and Figure 1 1 and 2. An equivalent circuit diagram of a pixel PXL connected to an i-th emission control line ELi (hereinafter referred to as emission control line ELi) among the emission control lines EL1 to ELn is shown.

[0069] refer to Figure 2According to an embodiment of the present disclosure, a pixel PXL of a display device may include a pixel circuit PXC and at least one light-emitting element ED. In an embodiment, the light-emitting element ED may be a light-emitting diode. In this embodiment, an example is described in which one pixel PXL includes one light-emitting element ED. The pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor Cst.

[0070] exist Figure 2 In the illustrated embodiment, the third transistor T3 and the fourth transistor T4 among the first transistor T1 to the seventh transistor T7 can be implemented with an N-type transistor having an oxide semiconductor as a semiconductor layer, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 among the first transistor T1 to the seventh transistor T7 can be implemented with a P-type transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, the present disclosure is not limited thereto, and all of the first transistor T1 to the seventh transistor T7 can be implemented with a P-type transistor or an N-type transistor. In another embodiment, at least one of the first transistor T1 to the seventh transistor T7 can be implemented with an N-type transistor, and the other transistors can be implemented with a P-type transistor. In addition, the circuit configuration of the pixel PXL according to the present disclosure is not affected by Figure 2 restrictions. Figure 2 The illustrated pixel circuit PXC is merely one example, and the configuration of the pixel circuit PXC may be modified and implemented variously.

[0071] The scan lines SILi, SCLi, SWLi, and SWLi+1 may transmit scan signals SIi, SCi, SWi, and SWi+1, respectively, and the emission control line ELi may transmit an emission control signal Ei. The data line DLj may transmit a data signal Dj. The data signal Dj may have a similar signal to that input to the data driver 133 (see FIG. Figure 1 ). The first driving voltage line VL1, the second driving voltage line VL2, the third driving voltage line VL3, and the fourth driving voltage line VL4 can transmit the first power voltage ELVDD, the second power voltage ELVSS, the first initialization power voltage Vint1, and the second initialization power voltage Vint2, respectively.

[0072] The first transistor T1 may include a first electrode connected to the first driving voltage line VL1 via the fifth transistor T5, a second electrode electrically connected to the anode of the light emitting element ED via the sixth transistor T6, and a gate electrode connected to one end of the capacitor Cst. The first transistor T1 may receive a data signal Dj transmitted from the data line DLj according to a switching operation of the second transistor T2 to provide a driving current Id to the light emitting element ED.

[0073] The second transistor T2 may include a first electrode connected to the data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the scan line SWLi. The second transistor T2 may be turned on by a scan signal SWi transmitted through the scan line SWLi to transmit a data signal Dj transmitted from the data line DLj to the first electrode of the first transistor T1.

[0074] The third transistor T3 may include a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the scan line SCLi. The third transistor T3 may be turned on according to a scan signal SCi transmitted through the scan line SCLi to connect the gate electrode and the second electrode of the first transistor T1 to each other, thereby allowing the first transistor T1 to be diode-connected.

[0075] The fourth transistor T4 may include a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to a third driving voltage line VL3 transmitting a first initialization power voltage Vint1, and a gate electrode connected to a scan line SILi. The fourth transistor T4 may be turned on in response to a scan signal SIi transmitted through the scan line SILi to perform an initialization operation of initializing the voltage of the gate electrode of the first transistor T1 by transmitting the first initialization power voltage Vint1 to the gate electrode of the first transistor T1.

[0076] The fifth transistor T5 may include a first electrode connected to the first driving voltage line VL1 , a second electrode connected to the first electrode of the first transistor T1 , and a gate electrode connected to the emission control line ELi.

[0077] The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1 , a second electrode connected to the anode of the light emitting element ED, and a gate electrode connected to the emission control line ELi.

[0078] The fifth transistor T5 and the sixth transistor T6 may be simultaneously turned on according to the emission control signal Ei transmitted through the emission control line ELi, and thus the first power voltage ELVDD is compensated by the diode-connected first transistor T1 to be transmitted to the light emitting element ED.

[0079] The seventh transistor T7 may include a first electrode connected to the second electrode of the sixth transistor T6, a second electrode connected to the fourth driving voltage line VL4, and a gate electrode connected to the scan line SWLi+1. The seventh transistor T7 may be turned on in response to a scan signal SWi+1 transmitted through the scan line SWLi+1 to split the driving current Id into a current Ied flowing to the anode of the light-emitting element ED and a current Ibp bypassed to the fourth driving voltage line VL4.

[0080] One end of the capacitor Cst may be connected to the gate electrode of the first transistor T1 as described above, and the other end of the capacitor Cst may be connected to the first driving voltage line VL1. The cathode of the light emitting element ED may be connected to the second driving voltage line VL2 transmitting the second power voltage ELVSS. The structure of the pixel PXL according to the embodiment of the present disclosure is not limited to Figure 2 , and the numbers of transistors and capacitors included in one pixel PXL may be variously modified, and the connection relationship may be variously modified.

[0081] As described above, the first high voltage VGH1 may be a voltage for turning off the P-type transistor included in the pixel PXL. The first low voltage VGL1 may be a voltage for turning on the P-type transistor included in the pixel PXL. The second high voltage VGH2 may be a voltage for turning on the N-type transistor included in the pixel PXL. The second low voltage VGL2 may be a voltage for turning off the N-type transistor included in the pixel PXL.

[0082] Therefore, the first high voltage VGH1 or the first low voltage VGL1 may be applied to the i-th scan line SWLi, the i-th emission control line ELi, and the i+1-th scan line SWLi+1. Meanwhile, the second high voltage VGH2 or the second low voltage VGL2 may be applied to the i-th scan lines SCLi and SILi.

[0083] Figure 3 yes Figure 1 An exemplary circuit diagram of a data driver is shown.

[0084] refer to Figure 3 , the data driver 133 may include a reference voltage generator 210 and an output circuit 220 .

[0085] The reference voltage generator 210 can be Figure 1 The illustrated voltage generator 160 receives the first power voltage ELVDD and outputs a first reference voltage AVC_VREG1 and a second reference voltage AVC_VREF1 .

[0086] The reference voltage generator 210 may include a noise filter NC1 , a first voltage generator 211 , a second voltage generator 212 , and a third voltage generator 213 .

[0087] The noise filter NC1 may receive the first power voltage ELVDD and output a filtered power voltage ELVDD_F. The noise filter NC1 may output the filtered power voltage ELVDD_F obtained by removing a low-frequency component included in the first power voltage ELVDD.

[0088] The noise filter NC1 may include a resistor R11 and a capacitor C11. The resistor R11 may be connected between the input terminal IN1 and the second node N2. The capacitor C11 may be connected between the second node N2 and the ground terminal. The second node N2 may be an output node for outputting the filtered power voltage ELVDD_F. The cut-off frequency of the noise filter NC1 may be determined according to the resistance value of the resistor R11 and the capacitance of the capacitor C11. The circuit configuration of the noise filter NC1 is not affected by Figure 3 restrictions and can be changed differently.

[0089] The first voltage generator 211 may receive voltages V1, V2, V3, VLIN1, VSSA, and VSSA_REF, and output a first voltage VREG1, a second voltage NELVDD, and a third voltage VREF1. The first voltage generator 211 may include operational amplifiers AP1, AP2, and AP3. The operational amplifiers AP1, AP2, and AP3 may output a first voltage VREG1, a second voltage NELVDD, and a third voltage VREF1, respectively. In an embodiment, the first voltage VREG1, the second voltage NELVDD, and the third voltage VREF1 may have different voltage levels. In an embodiment, the first voltage VREG1, the second voltage NELVDD, and the third voltage VREF1 may have a relationship such that VREG1>NELVDD>VREF1. In an embodiment, the second voltage NELVDD output from the operational amplifier AP2 may have the same voltage level as the first power voltage ELVDD. The voltage VLIN1 may be a driving voltage input to the operational amplifiers AP1, AP2, and AP3. The first voltage VREG1, the second voltage NELVDD, and the third voltage VREF1 can be output to the third output terminal OUT3, the first node N1, and the fourth output terminal OUT4, respectively. Figure 3 restrictions and may be changed differently.

[0090] The second voltage generator 212 may receive the first voltage VREG1 , the second voltage NELVDD, and the filtered power voltage ELVDD_F, and output a first reference voltage AVC_VREG1 . The first reference voltage AVC_VREG1 may be output to the first output terminal OUT1 .

[0091] The second voltage generator 212 may include resistors R1, R2, R3, and R4, and an operational amplifier AP4. The resistor R1 may be connected between the third output terminal OUT3 and the first input terminal (+) of the operational amplifier AP4. The resistor R2 may be connected between the first input terminal (+) of the operational amplifier AP4 and the second node N2. The resistor R3 may be connected between the first node N1 and the second input terminal (-) of the operational amplifier AP4. The resistor R4 may be connected between the second input terminal (-) of the operational amplifier AP4 and the first output terminal OUT1.

[0092] The first reference voltage AVC_VREG1 output from the second voltage generator 212 may be calculated by Equation 1 below.

[0093] Formula 1

[0094] AVC_VREG1=(ELVDD_F-NELVDD)+VREG1

[0095] The circuit configuration of the second voltage generator 212 is not affected by Figure 3 restrictions and can be changed differently.

[0096] The third voltage generator 213 may receive the second voltage NELVDD, the third voltage VREF1, and the filtered power voltage ELVDD_F and output a second reference voltage AVC_VREF1. The second reference voltage AVC_VREF1 may be output to the second output terminal OUT2.

[0097] The third voltage generator 213 may include resistors R5, R6, R7, and R8, and an operational amplifier AP5. The resistor R5 may be connected between the fourth output terminal OUT4 and the first input terminal (+) of the operational amplifier AP5. The resistor R6 may be connected between the first input terminal (+) of the operational amplifier AP5 and the second node N2. The resistor R7 may be connected between the first node N1 and the second input terminal (-) of the operational amplifier AP5. The resistor R8 may be connected between the second input terminal (-) of the operational amplifier AP5 and the second output terminal OUT2.

[0098] The second reference voltage AVC_VREF1 output from the third voltage generator 213 may be calculated by Equation 2 below.

[0099] Formula 2

[0100] AVC_VREF1=(ELVDD_F-NELVDD)+VREF1

[0101] The circuit configuration of the third voltage generator 213 is not affected by Figure 3 restrictions and may be changed differently.

[0102] The output circuit 220 may output a data signal Dj having a voltage level corresponding to a voltage value VDATA to the j-th data line DLj based on the first reference voltage AVC_VREG1 and the second reference voltage AVC_VREF1 .

[0103] The output circuit 220 may include a resistor string 221, a digital-to-analog converter (DAC) 222, and a buffer 223. The resistor string 221 may include a plurality of resistors connected between a first output terminal OUT1 and a second output terminal OUT2. Although not shown in the figure, the resistor string 221 may output a voltage at a connection node between the plurality of resistors as a gamma reference voltage.

[0104] The digital-to-analog converter 222 can Figure 1 The data converter 132 shown receives a voltage value VDATA. The digital-to-analog converter 222 may output a data signal Dj corresponding to the voltage value VDATA corresponding to the j-th data line DLj among a plurality of gamma reference voltages from the resistor string 221. The buffer 223 may output the data signal Dj from the digital-to-analog converter 222 to the j-th data line DLj.

[0105] exist Figure 3 In the embodiment, only the case where the output circuit 220 outputs the data signal Dj to the j-th data line DLj is shown as an example. The output circuit 220 can be driven by the same method as the method of driving the j-th data line DLj. Figure 1 All data lines DL1 to DLm are shown.

[0106] As described above, the voltage level of the data signal Dj output from the output circuit 220 corresponds to the voltage value VDATA. However, the voltage level of the data signal Dj may vary according to the voltage levels of the first and second reference voltages AVC_VREG1 and AVC_VREF1.

[0107] Figure 4 It shows Figure 1 A block diagram of an embodiment of a controller is shown.

[0108] refer to Figure 4, the controller 131 may include a first offset determiner 310, a second offset determiner 320, and a gamma lookup table ("GLUT") determiner 330. The controller 131 may receive the driving lookup table CLUT from the memory 140. In addition, the controller 131 may receive a sensing value SV from the illuminance sensor 170.

[0109] The first offset determiner 310 may determine a first offset value Δv1 based on the received driving lookup table CLUT and the received sensing value SV. The determined first offset value Δv1 may be transmitted to the voltage generator 160.

[0110] The second offset determiner 320 may determine a second offset value Δv2 based on the received driving lookup table CLUT and the received sensing value SV. The determined second offset value Δv2 may be transmitted to the voltage generator 160.

[0111] The GLUT determiner 330 may generate a control signal SC based on the received drive lookup table CLUT and the received sensed value SV. The control signal SC may be a signal for determining the gamma lookup table GLUT to be used by the data converter 132. The control signal SC may be transmitted to the data converter 132. The data converter 132 may receive the gamma lookup table GLUT for generating the voltage value VDATA from the memory 140 based on the control signal SC.

[0112] Table 1 below shows an exemplary embodiment of the driving lookup table CLUT stored in the memory 140 .

[0113] Table 1

[0114]

[0115]

[0116] Referring to Table 1, as the illuminance outside the display device 100 becomes stronger, the absolute value of the first offset value Δv1 may become larger. At an illuminance of 500 Lux or greater, the first offset value Δv1 may have a negative value. Furthermore, as the illuminance outside the display device 100 becomes stronger, the absolute value of the second offset value Δv2 may become larger. At an illuminance of 5000 Lux or greater, the second offset value Δv2 may have a negative value.

[0117] That is, in at least part of the illuminance section, the first offset value Δv1 or the second offset value Δv2 may have a negative value. When the illuminance outside the display device 100 becomes stronger, the absolute value of the first offset value Δv1 or the second offset value Δv2 may increase.

[0118] Meanwhile, according to each illuminance range, the GLUT determiner 330 may determine a gamma lookup table GLUT to be used by the data converter 132. Meanwhile, the GLUT determiner 330 may transmit a control signal SC representing the determined gamma lookup table GLUT to the data converter 132.

[0119] For example, when the sensed value sensed by the illuminance sensor 170 indicates 60,000 Lux, the first offset determiner 310 may determine -0.6 V as the first offset value Δv1, and the second offset determiner 320 may determine -0.2 V as the second offset value Δv2. The GLUT determiner 330 may determine the sixth gamma lookup table GLUT6 as the gamma lookup table GLUT to be used by the data converter 132. The GLUT determiner 330 may transmit a control signal SC indicating the sixth gamma lookup table GLUT6 to the data converter 132.

[0120] Figure 5 It shows Figure 1 A block diagram of the operation of the data converter is shown.

[0121] refer to Figure 5 , the data converter 132 may receive the image data DATA2 and the control signal SC from the controller 131 .

[0122] Meanwhile, the memory 140 may include a plurality of gamma lookup tables GLUT (such as a first gamma lookup table GLUT1, a second gamma lookup table GLUT2, etc.). The number of gamma lookup tables GLUT (such as the first gamma lookup table GLUT1, the second gamma lookup table GLUT2, etc.) stored in the memory 140 may correspond to the number of segments of the illuminance range included in the drive lookup table CLUT. For example, when the drive lookup table CLUT is configured as shown in Table 1, the memory 140 may include the first gamma lookup table GLUT1 to the ninth gamma lookup table GLUT9.

[0123] As described above, the control signal SC may be a signal indicating the gamma lookup table GLUT to be used by the data converter 132. The data converter 132 may transmit a request signal RQ for requesting the k-th gamma lookup table GLUTk to the memory 140 in response to the control signal SC. The memory 140 may transmit the k-th gamma lookup table GLUTk to the data converter 132 in response to the request signal RQ.

[0124] For example, when Figure 4When the GLUT determiner 330 transmits a control signal SC indicating the sixth gamma lookup table GLUT6 to the data converter 132, the data converter 132 may transmit a request signal RQ for requesting the sixth gamma lookup table GLUT6 to the memory 140 in response to the control signal SC. Simultaneously, the memory 140 may transmit the sixth gamma lookup table GLUT6 to the data converter 132 in response to the request signal RQ. The data converter 132 may generate a voltage value VDATA from the image data DATA2 using the sixth gamma lookup table GLUT6. The generated voltage value VDATA may be transmitted to the data driver 133.

[0125] Figure 6A and Figure 6B 1 and 2 are graphs each illustrating a method of changing the second power voltage ELVSS and the first low voltage VGL1 using the first offset value Δv1 . Figure 7A and Figure 7B ] are diagrams each showing a method of changing the voltage VLIN1 and the first high voltage VGH1 using the second offset value Δv2.

[0126] refer to Figure 6A , the voltage generator 160 can generate the second power voltage ELVSS by adding the first offset value Δv1 to the initial second power voltage ELVSS_INT. As described above, as the illuminance outside the display device 100 (i.e., ambient light) becomes stronger, the absolute value of the first offset value Δv1 having a negative value can become larger. Therefore, when the illuminance outside the display device 100 becomes stronger, the second power voltage ELVSS can decrease.

[0127] refer to Figure 6B , the voltage generator 160 may generate the first low voltage VGL1 by adding the first offset value Δv1 to the initial first low voltage VGL1_INT. Similar to the second power voltage ELVSS, as the illumination outside the display device 100 (ie, ambient light) becomes stronger, the first low voltage VGL1 may decrease.

[0128] although Figure 6A and Figure 6B Not shown, but using something like Figure 6A or Figure 6B According to the method shown in , the second low voltage VGL2 can also be changed by the first offset value Δv1.

[0129] refer to Figure 7A , the voltage generator 160 can generate the voltage VLIN1 by adding the second offset value Δv2 to the initial voltage VLIN1_INT. Figure 3As described above, voltage VLIN1 may be a driving voltage input to operational amplifiers AP1, AP2, and AP3 included in data driver 133. That is, the driving voltage (i.e., voltage VLIN1) of operational amplifiers AP1, AP2, and AP3 included in data driver 133 may be changed by the second offset value Δv2. In addition, as the illumination outside of display device 100 (i.e., ambient light) becomes stronger, the absolute value of the second offset value Δv2 having a negative value may become larger. Therefore, as the illumination outside of display device 100 (i.e., ambient light) becomes stronger, the driving voltage (i.e., voltage VLIN1) of operational amplifiers AP1, AP2, and AP3 included in data driver 133 may decrease.

[0130] refer to Figure 7B , the voltage generator 160 may generate the first high voltage VGH1 by adding the second offset value Δv2 to the initial first high voltage VGH1_INT. Similar to the voltage VLIN1, when the illumination outside the display device 100 (ie, ambient light) becomes stronger, the magnitude of the first high voltage VGH1 may decrease.

[0131] Despite Figure 7A and Figure 7B Not shown, use Figure 7A or Figure 7B In a similar manner to that shown in , the second high voltage VGH2 and the voltage AVC_VREF1 can also be changed by the second offset value Δv2 .

[0132] Figure 8 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure.

[0133] refer to Figure 8 , the method for driving a display device may include: step S110, generating a sensing value by an illuminance sensor; step S130, referring to a driving lookup table stored in a memory, determining at least one offset value corresponding to the sensing value; step S150, generating a driving voltage based on the determined offset value; and step S170, displaying an image on a display unit using the generated driving voltage. Figure 1 Describe together Figure 8 The flowchart shown.

[0134] In step S110 , the illuminance sensor 170 of the display device 100 may sense external illuminance and generate a sensing value SV corresponding to the external illuminance. The generated sensing value SV may be transmitted to the controller 131 .

[0135] In step S130, the memory 140 may transmit the driving lookup table CLUT to the controller 131. The controller 131 may refer to the driving lookup table CLUT to determine an offset value Δv corresponding to the sensing value SV. The offset value Δv may include at least one of a first offset value Δv1 and a second offset value Δv2. When the sensing value SV generated in step S110 indicates a higher illuminance, the offset value Δv determined in step S130 may become smaller.

[0136] In step S150, the controller 131 may transmit the determined offset value Δv to the voltage generator 160. The voltage generator 160 may use the received offset value Δv to change and generate at least one value of the driving voltage generated for driving the display device. When the sensing value SV generated in step S110 indicates a higher illuminance, the voltage to be changed may become smaller.

[0137] In step S170, the voltage generator 160 may transmit the changed driving voltage to other components of the display device. Therefore, the display device may display an image on the display unit 110 using the changed driving voltage.

[0138] Figure 9 is a flowchart illustrating a method of driving a display device according to another embodiment of the present disclosure.

[0139] refer to Figure 9 , the method for driving a display device may include: step S210, generating a sensing value by an illuminance sensor; step S230, referring to a driving lookup table stored in a memory, determining at least one offset value and a gamma lookup table corresponding to the sensing value; step S250, generating a driving voltage based on the determined offset value; step S270, generating a voltage value corresponding to input image data using the determined gamma lookup table; and step S290, displaying an image on a display unit using the generated driving voltage and the generated voltage value. Hereinafter, reference will be made to Figure 1 Describe together Figure 9 The flowchart shown.

[0140] In step S210 , the illuminance sensor 170 of the display device 100 may sense external illuminance and generate a sensing value SV corresponding to the external illuminance. The generated sensing value SV may be transmitted to the controller 131 .

[0141] In step S230, the memory 140 may transmit the driving lookup table CLUT to the controller 131. The controller 131 may refer to the driving lookup table CLUT to determine an offset value Δv corresponding to the sensing value SV. The offset value Δv may include at least one of a first offset value Δv1 and a second offset value Δv2. When the sensing value SV generated in step S210 indicates a higher illuminance, the offset value Δv determined in step S230 may become smaller.

[0142] Meanwhile, in step S230 , the controller 131 may refer to the driving lookup table CLUT to determine a gamma lookup table to be used by the data converter 132 among the plurality of gamma lookup tables GLUT and transmit a control signal SC corresponding to the determined gamma lookup table to the data converter 132 .

[0143] In step S250, the controller 131 may transmit the determined offset value Δv to the voltage generator 160. The voltage generator 160 may use the received offset value Δv to change and generate at least one value of the driving voltage generated for driving the display device. When the sensing value SV generated in step S210 indicates a higher illuminance, the voltage to be changed may become smaller.

[0144] In step S270, the data converter 132 may transmit a request signal RQ corresponding to the received control signal SC to the memory 140. The memory 140 may transmit a gamma lookup table GLUT corresponding to the request signal RQ to the data converter 132. The data converter 132 may use the received gamma lookup table GLUT to generate a voltage value VDATA corresponding to the image data DATA2. The generated voltage value VDATA may be transmitted to the data driver 133.

[0145] In step S290, the voltage generator 160 may transmit the changed driving voltage to other components of the display device. In addition, in step S290, the data driver 133 may transmit the data signal to the display unit 110 according to the generated voltage value VDATA. Therefore, the display device may display an image on the display unit 110 using the changed driving voltage.

[0146] In the display device and the method of driving the display device according to the present disclosure, a driving voltage that changes according to external illuminance can be compensated.

[0147] Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art upon filing this application, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless specifically indicated otherwise. Accordingly, those skilled in the art will understand that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device comprising: a display panel, including pixels; a voltage generator configured to generate a plurality of driving voltages; an illumination sensor configured to sense an amount of ambient light of the display panel and generate a sensing value corresponding to the sensing result; as well as a driver configured to generate a data signal to be transmitted to the pixel, The driver controls the voltage generator based on the sensed value to change at least one driving voltage among the plurality of driving voltages.

2. The display device according to claim 1 , further comprising a memory configured to store a drive lookup table. in, The driver includes a controller configured to generate a first offset value corresponding to the sensed value with reference to the driving lookup table and provide the first offset value to the voltage generator.

3. The display device according to claim 2, wherein: The pixels include: a pixel circuit connected to a line configured to provide a first power voltage; and a light emitting element connected between the pixel circuit and a line configured to provide a second power voltage, wherein the voltage generator generates the second power voltage using the first offset value, and The voltage generator generates the second power voltage by adding the first offset value to an initial second power voltage.

4. The display device according to claim 3, wherein The pixel circuit includes at least one P-type transistor, and The voltage generator uses the first offset value to generate a voltage provided to a gate of the at least one P-type transistor and used to turn on the at least one P-type transistor.

5. The display device according to claim 3, wherein The pixel circuit includes at least one N-type transistor, and The voltage generator uses the first offset value to generate a voltage provided to a gate of the at least one N-type transistor and used to turn off the at least one N-type transistor. The display device according to claim 2 , wherein: The controller receives first image data and generates second image data based on the first image data, Wherein, the driver further includes: a data converter configured to receive the second image data and generate a voltage value corresponding to the second image data; and a data driver connected to the pixel through a data line, the data driver generating the data signal corresponding to the voltage value and supplying the generated data signal to the data line, and The controller generates a second offset value corresponding to the sensing value by referring to the driving lookup table, and provides the second offset value to the voltage generator.

7. The display device according to claim 6, wherein: The pixels include: a pixel circuit connected to a line configured to provide a first power voltage; and a light emitting element connected between the pixel circuit and a line configured to provide a second power voltage, Wherein, the pixel circuit includes at least one N-type transistor, and The voltage generator uses the second offset value to generate a voltage provided to a gate of the at least one N-type transistor and used to turn on the at least one N-type transistor.

8. The display device according to claim 6, wherein: The pixels include: a pixel circuit connected to a line configured to provide a first power voltage; and a light emitting element connected between the pixel circuit and a line configured to provide a second power voltage, Wherein, the pixel circuit includes at least one P-type transistor, and The voltage generator uses the second offset value to generate a voltage provided to a gate of the at least one P-type transistor and used to turn off the at least one P-type transistor.

9. The display device according to claim 6, wherein: The voltage generator generates a driving voltage of an operational amplifier included in the data driver using the second offset value.

10. The display device according to claim 6, wherein The memory also stores a plurality of gamma lookup tables, and The data converter generates the voltage value using a gamma lookup table corresponding to the sensed value among the plurality of gamma lookup tables.

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