Driving circuit and display panel

Abstract

The invention provides a driving circuit and a display panel, the driving circuit comprises cascaded multiple stages of gate driving units, and each gate driving unit comprises a pull-up control module, a pull-up module, a pull-down control module and a voltage stabilization module; and when the threshold voltage in the pull-down control module is negatively biased, the voltage stabilization module is controlled to work based on the high-level signal of the pull-down node so as to prevent electric leakage of the pull-down node in a high-level maintaining stage. When the threshold voltage of the pull-down control module is negatively biased, the voltage stabilization module is controlled to work based on the high-level signal of the pull-down node, an abnormal conduction path of the transistor in the turn-off state is effectively blocked, the electric leakage phenomenon of the pull-down node in the high-level maintaining stage is remarkably inhibited, and the reliability of the circuit is improved. The circuit power consumption is reduced; and the display quality of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving circuit and a display panel. Background Art

[0002] In the gate drive circuit of a display panel, when the threshold voltage of the transistor is negatively biased, it will cause serious leakage problems in the circuit during the high-level maintenance phase. For example, when the pull-down node is at a high level, if the transistor threshold voltage Vth becomes negative, the pull-down control transistor that should be in the off state will be abnormally turned on. The root cause of this phenomenon is that when the threshold voltage becomes negative, the original shutdown condition no longer holds, causing the transistor to remain on when it should be completely off, thereby causing unnecessary current leakage. This leakage problem not only increases the power consumption of the circuit, but also affects the stability of the gate drive signal, thereby reducing the display quality and reliability of the display panel. Especially under long-term operation or high-temperature environment, the negative bias of the threshold voltage is more obvious, making this problem more prominent. Summary of the Invention

[0003] The purpose of the present application is to provide a driving circuit and a display panel, aiming to solve the serious leakage problem in the circuit during the high-level maintenance stage when the threshold voltage of the transistor is negatively biased.

[0004] An embodiment of the present application provides a driving circuit for use in a display panel. The driving circuit includes a cascaded multi-stage gate driving unit. The gate driving unit includes:

[0005] A pull-up control module, wherein the input end of the pull-up control module is connected to the input signal line, the output end of the pull-up control module is connected to the pull-up node; and the control end of the pull-up control module is connected to the pull-up control signal line;

[0006] A pull-up module, wherein the input end of the pull-up module is connected to the high-level signal input end, the control end of the pull-up module is connected to the pull-up node, and the output end of the pull-up module is connected to the output end of the gate driving unit;

[0007] A pull-down control module, wherein the input end of the pull-down control module is connected to the input end of the pull-up control module, the output end of the pull-down control module is connected to the pull-down node; and the control end of the pull-down control module is connected to the pull-up node;

[0008] a pull-down module, wherein the input end of the pull-down module is connected to the low-level signal input end, the control end of the pull-down module is connected to the pull-down node, and the output end of the pull-down module is connected to the output end of the gate driving unit;

[0009] a voltage stabilization module, wherein a control terminal of the voltage stabilization module is connected to the pull-down node, an input terminal of the voltage stabilization module is connected to the high-level signal input terminal, and an output terminal of the voltage stabilization module is connected to the control terminal of the pull-down control module;

[0010] When the threshold voltage in the pull-down control module is negatively biased, the voltage stabilization module is controlled to operate based on the high-level signal of the pull-down node to prevent leakage during the high-level maintenance phase of the pull-down node.

[0011] In some embodiments, the voltage stabilization module includes: a tenth switch element, a control terminal of the tenth switch element is connected to the pull-down node, a first terminal of the tenth switch element is connected to the high-level signal input terminal, and a second terminal of the tenth switch element is connected to the control terminal of the pull-down control module;

[0012] When the threshold voltage in the pull-down control module is negatively biased, the tenth switch element is controlled to be turned on based on the high-level signal of the pull-down node to prevent leakage during the high-level maintenance stage of the pull-down node.

[0013] In some embodiments, the pull-up control module includes: a first switch element; a control end of the first switch element is connected to the pull-up control signal line, a first end of the first switch element is connected to the input signal line, and a second end of the first switch element is connected to the pull-up node;

[0014] The pull-up signal transmitted by the pull-up control signal line is a clock signal, and the input signal transmitted by the input signal line is a frame start signal.

[0015] In some embodiments, the pull-down control module includes: a second switch element, a third capacitor, a third switch element, and a fourth switch element; wherein,

[0016] The control end of the third switch element is connected to the input signal line, the first end of the third switch element is connected to one end of the third capacitor, and the second end of the third switch element is connected to the input end of the pull-down module;

[0017] The control end of the second switch element is connected to the first end of the third switch element, the first end of the second switch element is respectively connected to the other end of the third capacitor and the input signal line, and the second end of the second switch element is connected to the pull-down node;

[0018] The control end of the fourth switch element is connected to the pull-up node, the first end of the fourth switch element is connected to the pull-down node, and the second end of the second switch element is connected to the low-level signal input end.

[0019] In some embodiments, the second end of the tenth switch element is connected to the write node; the fourth switch element includes a first sub-element and a second sub-element; the second switch element includes a third sub-element and a fourth sub-element;

[0020] The control end of the first sub-element and the control end of the second sub-element are connected to the pull-up node, the first end of the first sub-element is connected to the low-level signal input end, the second end of the first sub-element is connected to the first end of the second sub-element and the write node respectively, and the second end of the second sub-element is connected to the pull-down node;

[0021] The control end of the third sub-element and the control end of the fourth sub-element are connected to the first end of the third switch element, the first end of the third sub-element is connected to the pull-up control signal line, the second end of the third sub-element is connected to the first end of the fourth sub-element and the write node respectively, and the second end of the fourth sub-element is connected to the pull-down node;

[0022] When the pull-down node is a high-level signal, the tenth switch element is turned on and writes the high-level signal to the write node, so that when the threshold voltage is negatively biased, the first sub-element, the second sub-element, the third sub-element and the fourth sub-element are in the off state.

[0023] In some embodiments, the driving circuit further includes: a data writing transistor, wherein an electrode of the data writing transistor is connected to the writing node;

[0024] In the data writing period, the data writing transistor is turned on when the writing node is a high level signal, and writes the data of the writing node.

[0025] In some embodiments, the pull-down module includes: a first capacitor, an eighth switch element, and a ninth switch element; wherein,

[0026] The control end of the eighth switching element and the control end of the ninth switching element are commonly connected to one end of the first capacitor; the first end of the eighth switching element is respectively connected to the low-level signal input end and the other end of the first capacitor; the second end of the eighth switching element is connected to the driving node;

[0027] A first end of the ninth switching element is connected to the driving node, and a second end of the ninth switching element is connected to the output end of the gate driving unit.

[0028] In some embodiments, the pull-up module includes: a fifth switch element, a second capacitor, a sixth switch element, and a seventh switch element; wherein,

[0029] The control terminal of the sixth switch element is connected to the high-level signal input terminal, the first terminal of the sixth switch element is connected to the pull-up node, and the second terminal of the sixth switch element is connected to the control terminal of the fifth switch element and one terminal of the second capacitor respectively;

[0030] A first end of the fifth switch element is connected to the other end of the second capacitor and the output end of the gate driving unit respectively, and a second end of the fifth switch element is connected to the high-level signal input end;

[0031] The control end of the fourth switch element is connected to the pull-up node, the first end of the fourth switch element is connected to the pull-down node, and the second end of the second switch element is connected to the low-level signal input end;

[0032] The control end of the seventh switch element is connected to the second end of the ninth switch element, the first end of the seventh switch element is connected to the high level signal input end, and the second end of the seventh switch element is connected to the driving node.

[0033] In some embodiments, the tenth switching element is an oxide transistor with a dual-gate structure or a single-gate structure.

[0034] An embodiment of the present application further provides a display panel, comprising a plurality of pixel units arranged in an array and the aforementioned driving circuit, wherein each level of gate driving units in the driving circuit is used to drive at least one row of the pixel units.

[0035] In the driving circuit and display panel provided in the present application, when the threshold voltage of the pull-down control module is negatively biased, the voltage stabilization module is controlled to operate based on the high-level signal of the pull-down node, thereby effectively blocking the abnormal conduction path of the transistor in the off state, and having the advantages of significantly suppressing the leakage phenomenon in the high-level maintenance stage of the pull-down node, reducing circuit power consumption and improving the display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The present application is further described below with reference to the accompanying drawings. It should be noted that the drawings described below are only used to illustrate some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0037] Figure 1 Schematic diagram of an application scenario of the driving circuit provided in an embodiment of the present application.

[0038] Figure 2 This is a schematic diagram of a driving circuit in an embodiment of the present application.

[0039] Figure 3A schematic diagram of the timing of the driving circuit in an embodiment of the present application.

[0040] Figure 4 This is another schematic diagram of the timing of the driving circuit in the embodiment of the present application. DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0042] In the description of this application, the terms "first," "second," and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise expressly limited. The embodiments of this application may be combined with each other.

[0043] It should be noted that the “effective potential” in this application can be understood as the potential in the signal used to control the device to turn on, which can be a high potential or a low potential.

[0044] Embodiments of the present application provide a display panel, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0045] In some embodiments, combined Figures 1 to 4As shown, the driving circuit 10 provided in the present application is applied to the display panel 30. The driving circuit 10 includes a cascaded multi-stage gate driving unit 101, and the gate driving unit 101 includes: a pull-up control module, a pull-up module, a pull-down control module, a pull-down module and a voltage stabilization scale block. The input end of the pull-up control module is connected to the input signal line (for transmitting the pull-up signal, such as but not limited to the frame start signal STV), the output end of the pull-up control module is connected to the pull-up node A; the control end of the pull-up control module is connected to the pull-up control signal line (for transmitting the pull-up control signal, such as but not limited to the clock signal CK). The input end of the pull-up module is connected to the high-level signal input end VGH, the control end of the pull-up module is connected to the pull-up node A, and the output end of the pull-up module is connected to the output end EM of the gate driving unit. The input end of the pull-down control module is connected to the input end of the pull-up control module, and the output end of the pull-down control module is connected to the pull-down node Q; the control end of the pull-down control module is connected to the pull-up node A. The input end of the pull-down module is connected to the low-level signal input end VGL, the control end of the pull-down module is connected to the pull-down node Q, and the output end of the pull-down module is connected to the output end of the gate drive unit. The control end of the voltage stabilization module is connected to the pull-down node Q, the input end of the voltage stabilization module is connected to the high-level signal input end VGH, and the output end of the voltage stabilization module is connected to the control end of the pull-down control module; wherein, when the threshold voltage Vth in the pull-down control module is negatively biased, the voltage stabilization module is controlled to work based on the high-level signal of the pull-down node Q to prevent leakage during the high-level maintenance stage of the pull-down node. Specifically, as Figure 1 As shown, Figure 1 Schematic diagram of the application scenario of the driving circuit provided in the embodiment of the present application. The driving circuit 10 is applied to the display panel 30 in the display device 100. The display panel 30 may include a plurality of sub-pixels 301 and the above-mentioned gate driving circuit 10 located on one side of the plurality of sub-pixels 301. The display device 100 may also include a timing controller 401 and at least one source driver 402. The timing controller 401 and at least one source driver 402 may be integrated into the same chip or may be independently provided. Each gate driving unit 101 may be electrically connected between the timing controller 401 and the plurality of sub-pixels 301 to output a gate signal Gate transmitted to the plurality of sub-pixels 301; each source driver 402 may be electrically connected between the timing controller 401 and the plurality of sub-pixels 301 to output a data signal Data transmitted to the plurality of sub-pixels 301.

[0046] For ease of description, an example is given herein where a plurality of sub-pixels 301 are arranged in an array of n rows and m columns (n ​​and m are both positive integers).

[0047] like Figure 1 As shown, the gate driving circuit 10 may include at least n-level gate driving units 101. The gate driving circuit 10 is controlled by a timing controller 401 so that each gate driving unit 101 generates a gate signal Gate. The n-level gate signals Gate are respectively transmitted to n rows of sub-pixels 301 through n gate lines (GL1 to GLn). The n pulses p in the n-level gate signals, which are respectively used to turn on n rows of sub-pixels 301, can be arranged in sequence on the time axis to turn on multiple rows of sub-pixels 301 in sequence.

[0048] The source driver 402 is controlled by the timing controller 401 to generate m data signals Data which are output to m columns of sub-pixels 301 respectively through m data lines (DL1 to DLm). Each data signal Data may include n data voltages corresponding to n sub-pixels 301 in the same column. When each row of sub-pixels 301 is turned on, the multiple data lines respectively receive multiple data voltages of the multiple sub-pixels 301 located in the row, so that the multiple data voltages act on the multiple sub-pixels 301 in the row, so that the multiple sub-pixels 301 in the row emit light. Similarly, the sub-pixels 301 in all rows can be controlled to emit light in sequence to present a complete picture.

[0049] Among them, the multi-stage gate driving unit 101 can load including but not limited to the above-mentioned pull-up control signal (for example, but not limited to the clock signal CK), the pull-up signal (for example, but not limited to the loading frame start signal STV), and the pull-down signal (for example, but not limited to the low voltage signal VGL). Each stage of the gate driving unit 101 can generate and output the gate signal Gate through its output terminal.

[0050] Among them, the first-stage gate driving unit 101 ( Figure 2 In the figure, the input end of the pull-up control module (only the first-stage gate driving unit 101 is used as an example) can be loaded with the frame start signal STV, and the output end can be electrically connected to at least one subsequent stage of gate driving unit 101 to provide it with the first-stage gate signal Gate; the output end of the intermediate stage gate driving unit 101 can be electrically connected to at least one subsequent stage of gate driving unit 101 to transmit the gate signal Gate generated by the gate driving unit 101 of that stage to it, that is, the gate driving units 101 from the second stage to the last stage can be electrically connected to the output end of at least one previous stage of gate driving unit 101 to obtain the required gate signal Gate; and so on, the output end of the last stage of gate driving unit 101 outputs the gate signal Gate of the last stage.

[0051] in, Figure 2The waveforms of the clock signal CK, high voltage signal VGH, low voltage signal VGL, frame start signal STV, signal of pull-up node A, signal of pull-down node Q and other signals can be referred to respectively. Figure 3 and Figure 4 , the high voltage signal VGH and the low voltage signal VGL can be constant voltage signals.

[0052] It can be understood that the pull-up control module of this embodiment is controlled by the pull-up control signal to control the potential of the pull-up node A. The pull-up module is controlled by the potential of the pull-up node A to process the pull-up signal and output it to the output terminal of the gate driving unit 101. Moreover, the pull-down control module is controlled by the potential of the output terminal of the pull-up control module (i.e., the pull-up node A) to control the potential of the pull-down node Q. Furthermore, the pull-down module is controlled by the potential of the pull-down node Q to process the pull-down signal and output it to the output terminal of the gate driving unit 101. On this basis, this embodiment further provides a voltage stabilization module controlled by the potential of the pull-down node Q. The voltage stabilization module can control at least the potential of the pull-up node A according to the potential of the pull-down node Q, thereby stabilizing the potential of the pull-up node A. At the same time, this embodiment controls the change in the potential of the signal at the output end of the gate driving unit 101 (i.e., the waveform of the gate signal Gate) through the coordinated action of the above-mentioned multiple modules, so as to achieve that the amplitude of the pulse p of the gate signal Gate is greater than the amplitude of the gate signal Gate in the period outside the pulse p, that is, the amplitude of the pulse p of the gate signal Gate is the high potential of the gate signal Gate, and through the action of the above-mentioned voltage stabilization module, the stability of the gate signal Gate can also be improved, and only the above-mentioned multiple modules are used, avoiding the use of more devices to constitute the gate driving unit 101.

[0053] In some embodiments, combined Figures 2 to 4As shown, the pull-up signal transmitted by the pull-up signal line is a clock signal, and the pull-down signal (for example, a low-voltage signal VGL) transmitted by the pull-down signal line is a constant voltage signal (a signal with a constant amplitude); wherein the pulse width of the pulse p of the gate signal Gate is equal to the duration of the effective potential of the pull-up signal. In combination with the above discussion, it can be seen that the pull-up module is controlled by the potential of the pull-up node A to process the pull-up signal and output it to the output end of the gate driving unit 101, and the pull-up control signal must include alternating effective potentials (for example, controlling the transistor in the sub-pixel 301 to be turned on) and invalid potentials (for example, controlling the transistor in the sub-pixel 301 to be turned off). This embodiment can be understood as at least controlling the potential of the pull-up node A by setting the pull-up control module, and at least controlling the pull-up module to jointly realize the processing of the pull-up signal by the pull-up module, and at the same time, controlling the potential of the pull-down node Q by at least controlling the pull-down control module, and at least controlling the pull-down module to jointly realize the processing of the pull-down signal by the pull-down module to generate a gate signal Gate having a pulse width p equal to the duration of the effective potential of the pull-up control signal, thereby avoiding a large pulse width of the pulse p of the gate signal Gate.

[0054] Furthermore, the amplitude of the pulse p of the gate signal Gate can also be equal to the effective potential of the pull-up signal. For example, by controlling the pull-up module and the pull-down module to operate in a time-sharing manner, the amplitude of the gate signal Gate outputted by the output terminal of the gate driver unit 101 can be controlled to be the amplitude of the current pull-up signal or the amplitude of the current pull-down signal. Therefore, it can be considered that the potential of the pull-up node A and the potential of the pull-down node Q can respectively control the operating period of the pull-up module and the operating period of the pull-down module, thereby controlling the waveform of the gate signal Gate.

[0055] Based on this, Figure 2 As shown, Figure 2 Schematic diagram of a driving circuit in an embodiment of the present application; the driving circuit includes a cascaded multi-stage gate driving unit, and the gate driving unit includes:

[0056] The pull-up control module 21 has an input end connected to the input signal line STV, an output end connected to the pull-up node A, and a control end connected to the pull-up control signal line CK.

[0057] The pull-up module 22 has an input end connected to the high-level signal input end VGH, a control end connected to the pull-up node A, and an output end connected to the output end EM of the gate driving unit.

[0058] The pull-down control module 23 has an input end connected to the input end of the pull-up control module 21 , an output end connected to the pull-down node Q, and a control end connected to the pull-up node A.

[0059] The pull-down module 24 has an input terminal connected to the low-level signal input terminal VGL, a control terminal connected to the pull-down node Q, and an output terminal connected to the output terminal of the gate driving unit.

[0060] The voltage stabilization module 25 has a control terminal connected to the pull-down node Q, an input terminal connected to the high-level signal input terminal VGH, and an output terminal connected to the control terminal of the pull-down control module 23 .

[0061] When the threshold voltage Vth in the pull-down control module 23 is negatively biased, the voltage stabilization module is controlled to operate based on the high level signal of the pull-down node Q to prevent leakage during the high level maintenance stage of the pull-down node.

[0062] It should be noted that the pull-up control module 21 refers to a logic unit that transmits an input signal to a pull-up node, and signal transmission can be achieved using thin-film transistors. The pull-up module 22 refers to a driving unit that controls the output voltage based on the state of the pull-up node, and can be achieved by a switching element between a high-level signal source and the output terminal. The pull-down control module 23 refers to a logic unit that controls the potential of the pull-down node based on the input signal and the state of the pull-up node, and typically includes a logic circuit composed of multiple transistors. The pull-down module 24 refers to a driving unit that pulls the output terminal down to a low level based on the state of the pull-down node, and can be achieved by a switching element between a low-level signal source and the output terminal. The voltage stabilization module 25 specifically refers to a compensation circuit that actively increases the potential of the control terminal of the pull-down control module 23 when the pull-down node is at a high level. It is typically composed of a switching element between a high-level signal source and the pull-down control module 23. This module is turned on when the pull-down node is at a high level and ensures that the pull-down control module 23 is reliably shut off by applying a compensation voltage.

[0063] Specifically, the pull-up control module 21 transmits the input signal to the pull-up node when the pull-up control signal is activated, triggering the pull-up module to conduct and causing the output end to output a high level. The pull-down control module 23 enters the working state when the pull-up node is at a high level, pulling the pull-down node potential down. When the threshold voltage is negatively biased, the voltage stabilization module 25 connects the high-level signal source to the control end of the pull-down control module 23 during the high-level phase of the pull-down node, raising the potential of the module control end to a level higher than the potential of the pull-down node, ensuring that the transistor in the pull-down control module 23 is in a completely off state. This working mode offsets the impact of the negative bias of the threshold voltage on the transistor's turn-off characteristics by actively applying a compensation voltage.

[0064] The present application actively intervenes in the circuit operation state during the high-level phase of the pull-down node, creating a forced shutdown condition through the voltage stabilization module 25. This active control method effectively overcomes the problem of threshold voltage drift caused by process deviations or long-term use, making the circuit operation state no longer completely dependent on the stability of the transistor threshold parameters.

[0065] Through the above-described technical solution, the present application effectively suppresses leakage current in the driver circuit during the high-level maintenance phase. When the transistor threshold voltage deviates negatively, the voltage at the control terminal of the pull-down control module 23 is forcibly increased to ensure that the relevant transistor is completely shut off. This compensation mechanism significantly improves the reliability of the circuit operation and is particularly suitable for display panel driver circuits using materials prone to threshold shift, such as oxide semiconductors.

[0066] In one embodiment, Figure 2 As shown, only as an alternative example, the voltage stabilization module 25 includes: a tenth switch element T10, the control end of the tenth switch element T10 is connected to the pull-down node Q, the first end of the tenth switch element T10 is connected to the high-level signal input end VGH, and the second end of the tenth switch element T10 is connected to the control end of the pull-down control module 23.

[0067] When the threshold voltage Vth in the pull-down control module 23 is negatively biased, the tenth switch element T10 is controlled to be turned on based on the high level signal of the pull-down node Q to prevent leakage during the high level maintenance stage of the pull-down node Q.

[0068] It should be noted that the tenth switch element T10 refers to a semiconductor device having on and off states, and can be implemented specifically as a thin-film transistor or a metal-oxide-semiconductor field-effect transistor. Its control terminal receives a voltage level signal from the pull-down node Q to determine its on state. A high-level signal at the pull-down node Q refers to the voltage state of the node when it is at a logically high potential, which can be achieved through capacitive coupling or charging of the switch element, and is used to trigger the tenth switch element T10 to turn on. The control terminal of the pull-down control module 23 can be the gate or base terminal of the tenth switch element T10. Specifically, the control terminal receives a voltage provided by a high-level signal input terminal to maintain the voltage level, thereby controlling the off state of the relevant transistor in the pull-down control module 23.

[0069] Specifically, when the threshold voltage is negatively biased, the high-level signal at the pull-down node Q drives the tenth switch element T10 to conduct. At this time, the high potential at the high-level signal input terminal is transmitted to the control terminal of the pull-down control module 23 through the tenth switch element T10. After the control terminal of the pull-down control module 23 is pulled high, its internal transistor remains in the off state because the gate-source voltage difference is insufficient to overcome the negatively biased threshold voltage, thereby preventing the formation of a leakage current path between the pull-down node Q and the low-level signal input terminal. For example, in the output phase of the gate drive unit, if the pull-down node Q is in the high-level maintenance phase, the conduction of the tenth switch element T10 can directly apply the voltage at the high-level signal input terminal to the transistor gate of the pull-down control module 23, offsetting the impact of the negative threshold voltage.

[0070] The present application introduces the tenth switch element T10 to actively transmit a high-level signal to the pull-down control module 23, forcing the gate potential of the relevant transistor to increase, thereby ensuring that it can still be reliably turned off when the threshold voltage is negatively biased.

[0071] Through the above technical solution, the present application effectively solves the leakage problem caused by the negative bias of the threshold voltage during the high-level maintenance stage of the pull-down node. By actively controlling the gate potential of the pull-down control module 23, the stability of the gate drive unit under long-term operation or process fluctuations is improved, avoiding output signal abnormalities.

[0072] In one embodiment, Figure 2 As shown, the pull-up control module 21 includes: a first switch element T1; a control end of the first switch element T1 is connected to the pull-up control signal line CK, a first end of the first switch element T1 is connected to the input signal line STV, and a second end of the first switch element T1 is connected to the pull-up node A;

[0073] The pull-up signal transmitted by the pull-up control signal line is a clock signal CK, and the input signal transmitted by the input signal line is a frame start signal STV.

[0074] It should be noted that the first switching element T1 refers to a three-terminal device having a control terminal, a first terminal, and a second terminal, and can be specifically implemented by a thin film transistor or a metal oxide semiconductor field effect transistor. The control terminal receives a clock signal, the first terminal receives a frame start signal, and the second terminal outputs a signal to the pull-up node, thereby realizing the potential control of the pull-up node. The clock signal refers to a pulse signal with periodic high and low level changes, for example, it can be a square wave signal with a frequency of 60Hz. The frame start signal refers to a pulse signal used to trigger the start of each frame scan, for example, it can be a high-level pulse generated at the beginning of each frame. By transmitting the clock signal and the frame start signal separately, the false triggering of the pull-up node caused by signal interference can be avoided.

[0075] Specifically, the pull-up control module 21 isolates the input signal line from the pull-up node via the first switch element T1. When the clock signal is at a high level, the first switch element T1 is turned on, and the frame start signal is transmitted from the first end to the second end, charging the pull-up node. When the clock signal is at a low level, the first switch element T1 is turned off, severing the connection between the input signal line and the pull-up node. Because the clock signal and the frame start signal are transmitted via independent paths, when the threshold voltage is negatively biased, no parasitic conduction path is formed between the control end and the input end of the first switch element T1, thereby ensuring that the pull-up node maintains a stable low level during the non-operating phase.

[0076] As an example, the first switching element T1 may include two switching sub-elements, namely T1_1 and T1_2, the control end of T1_1 and the control end of T1_2 are connected together and connected to the pull-up control signal line CK; the first end of T1_1 is connected to the input signal line STV; the second end of T1_1 is connected to the first end of T1_2; and the second end of T1_2 is connected to the pull-up node A.

[0077] This application separates the transmission paths of the clock signal and the frame start signal and uses an independent first switch element for signal isolation, effectively avoiding coupling interference caused by the shared path. At the same time, by simplifying the structure of the pull-up control module and reducing the number of transistors, the circuit complexity is reduced.

[0078] Through the above technical solution, this application solves the problem of pull-up node leakage caused by negative transistor threshold voltage. By independently controlling the transmission paths of the clock signal and the frame start signal, the pull-up node receives the frame start signal only during the period when the clock signal is valid, avoiding false triggering caused by signal overlap. This structure maintains the stability of the pull-up node potential while reducing circuit power consumption and improving the operational reliability of the gate drive unit.

[0079] In one embodiment, Figure 2As shown, the pull-down control module 23 includes: a second switch element T2, a third capacitor C3, a third switch element T3 and a fourth switch element T4.

[0080] The control end of the third switch element T3 is connected to the input signal line STV, the first end of the third switch element T3 is connected to one end C of the third capacitor C3, and the second end of the third switch element T3 is connected to the input end VGL of the pull-down module 24.

[0081] The control end of the second switch element T2 is connected to the first end of the third switch element T3, the first end of the second switch element T2 is respectively connected to the other end of the third capacitor C3 and the input signal line STV, and the second end of the second switch element T2 is connected to the pull-down node Q.

[0082] The control end of the fourth switch element T4 is connected to the pull-up node, the first end of the fourth switch element T4 is connected to the pull-down node Q, and the second end of the second switch element T2 is connected to the low-level signal input end VGL.

[0083] Among them, the second switching element T2 refers to a semiconductor device that receives a signal through the control terminal to switch the conduction state, which can be specifically implemented by a thin film transistor, and its conduction state is determined by the difference between the control terminal voltage and the threshold voltage. The third capacitor C3 refers to a passive element for storing charge, which can be specifically implemented by a metal-insulator-metal structure capacitor, which can maintain the node potential when the input signal changes. The third switching element T3 refers to a control device connected between the input signal line and the input terminal of the pull-down module, which can be specifically implemented by an oxide semiconductor transistor, and is used to connect the input terminal of the pull-down module to the low-level signal when the input signal is valid. The fourth switching element T4 refers to a control device connected between the pull-up node and the pull-down node, which can be specifically implemented by a dual-gate transistor, and is used to adjust the pull-down node potential according to the state of the pull-up node.

[0084] Specifically, the pull-down control module 23 receives the input signal through the third switch element T3 and controls the charging and discharging of the third capacitor, so that the second switch element T2 is turned on during the valid period of the input signal, and the input signal is transmitted to the pull-down node. When the pull-up node is at a high level, the fourth switch element T4 is turned on to pull the pull-down node potential down to the low-level signal input terminal. The third capacitor C3 stores charge during the invalid period of the input signal, maintains the voltage at the control terminal of the second switch element T2, and ensures that the pull-down node potential is stable. In the case of a negative threshold voltage bias, the fourth switch element T4 remains in the on state during the high level of the pull-up node, forcing the pull-down node potential to be connected to the low-level signal input terminal, thereby avoiding leakage of the pull-down node caused by the threshold voltage offset.

[0085] As an example, the tenth switching element T10 is a transistor. The gate of T10 is connected to point Q, and the source is connected to the high-level voltage VGH. The drain of T10 is connected to the sources of transistors such as T2 and T4. T10 can be a dual-gate or single-gate structure. When point Q is at a high level, the tenth switching element T10 is turned on, and the high-level voltage VGH is written to point N connected to the sources of T2 and T4. Taking T2 as an example, the voltage at the gate point C remains at the low level VGL, the voltage at the source point N is pulled up to VGH by T10, and the voltage at the drain point Q is at the high level VGH. In this way, even when Vth is negative, the gate-source voltage Vgs = VGL - VGH << Vth of T2 is much smaller than the threshold voltage, ensuring that T2 is stably turned off. Similarly, other transistors such as T4 that need to be turned off in this state can also maintain a stable off state. In this way, even when Vth has a negative bias, it can effectively prevent leakage during the high-level maintenance stage of point Q, while ensuring the normal operation of the Gate Driver on Array (GOA) function.

[0086] In this application, a multi-level control mechanism is formed by introducing the third capacitor C3 and the fourth switching element T4. By utilizing the charge storage characteristic of the capacitor to maintain the voltage at the control end of the second switching element T2, combined with the potential forced pull-down function of the fourth switching element T4, the pull-down path can still be reliably turned off when the threshold voltage of the transistor has a negative shift.

[0087] Through the above technical solutions, this application solves the leakage problem of the pull-down node caused by the negative bias of the transistor threshold voltage during the high-level maintenance stage. The cooperative action of the third capacitor C3 and the fourth switching element T4 in the pull-down control module 23 can maintain the off state of the second switching element T2 during the invalid period of the input signal, and force the potential of the pull-down node to the low level through the fourth switching element T4, effectively blocking the leakage path. This structural design significantly improves the working stability of the drive circuit under the condition of deteriorated transistor characteristics.

[0088] In one embodiment, as Figure 2 shown, the second end of the tenth switching element T10 is connected to the write node N; the fourth switching element includes a first sub-element T4-1 and a second sub-element T4-2; the second switching element includes a third sub-element T2-1 and a fourth sub-element T2-2.

[0089] The control end of the first sub-element T4-1 and the control end of the second sub-element T4-2 are connected to the pull-up node A. The first end of the first sub-element T4-1 is connected to the low-level signal input terminal VGL. The second end of the first sub-element T4-1 is respectively connected to the first end of the second sub-element T4-2 and the write node N. The second end of the second sub-element T4-2 is connected to the pull-down node Q.

[0090] The control end of the third sub-element T2-1 and the control end of the fourth sub-element are connected to the first end C of the third switching element T3, the first end of the third sub-element T2-1 is connected to the pull-up control signal line CK, the second end of the third sub-element T2-1 is respectively connected to the first end of the fourth sub-element T2-2 and the write node N, and the second end of the fourth sub-element T2-2 is connected to the pull-down node Q.

[0091] When the pull-down node Q is a high-level signal, the tenth switch element T10 is turned on and the high-level signal VGH is written to the write node N, so that the threshold voltage Vth is negatively biased, and the first sub-element T4-1, the second sub-element T4-2, the third sub-element T2-1 and the fourth sub-element T2-2 are in the off state.

[0092] The write node N refers to an intermediate node for transmitting high-level signals, which can be implemented by metal wiring or conductive layer connection, and is used to transmit high-level signals to the control terminal of the sub-element at a specific stage. The first sub-element T4-1 and the second sub-element T4-2 refer to the transistor structure connected in series in the fourth switch element T4, which can be implemented by oxide thin-film transistors, reducing the actual voltage at the control terminal through voltage division. The third sub-element T2-1 and the fourth sub-element T2-2 refer to the transistor structure connected in series in the second switch element T2, which can be implemented by dual-gate transistors, enhancing shutdown reliability through dual control signals. The high-level signal of the pull-down node is written to the write node through the tenth switch element T10, creating a potential difference between the control terminal of the sub-element and the write node, thereby maintaining the off state when the threshold voltage is negative.

[0093] Specifically, when the gate driving unit is in the stage of maintaining the high level of the pull-down node, the tenth switching element T10 is triggered to conduct by the high-level signal of the pull-down node, and the high-level signal at the high-level signal input terminal is transmitted to the write node. At this time, the control terminals of the first sub-element T4-1 and the second sub-element T4-2 are controlled by the pull-up node. Since the pull-up node is at a low level, the second terminal of the first sub-element T4-1 and the high level of the write node form a reverse bias, so that the gate-source voltages of the first sub-element T4-1 and the second sub-element T4-2 are not sufficient to overcome the negative bias threshold voltage, thus remaining in the off state. At the same time, the first terminal of the third switching element T3 transmits a low-level signal to the control terminals of the third sub-element T2-1 and the fourth sub-element T2-2 through the pull-down control module 23. Combining with the high-level signal of the write node, a reverse voltage is formed between the gates and sources of the third sub-element T2-1 and the fourth sub-element T2-2, further ensuring their off states. Thus, when the threshold voltage has a negative bias, the sub-elements of the fourth switching element T4 and the second switching element T2 cannot conduct, avoiding the generation of leakage current.

[0094] As an example, when the Q point is at a high level VGH, T10 is turned on, and the VGH voltage is transmitted to the N point. For T2_2, the gate C point voltage is VGL, the source N point voltage is VGH, and the drain Q point voltage is VGH. At this time, the gate-source voltage Vgs of T2_2 = VGL - VGH << Vth. Even when Vth has a negative bias, since Vgs is much smaller than Vth, T2_2 can still be stably turned off, effectively preventing leakage. The same principle also applies to other transistors such as T2_1 and T4 that need to be turned off in this state.

[0095] Through the synergistic effect of the high-level signal of the write node and the series structure of the sub-elements, a reverse voltage bias is formed at the control terminal of the transistor. Even when the threshold voltage has a negative bias, it can still ensure that the sub-elements are in a reliable off state, thereby blocking the leakage path.

[0096] Through the above technical solution, the present application effectively solves the leakage problem caused by the negative bias of the transistor threshold voltage in the stage of maintaining the high level of the pull-down node. By the cooperation of the high-level signal of the write node and the series structure of the sub-elements, a reverse bias voltage is formed at the control terminal of the transistor, so that the transistor with a negative bias of the threshold voltage can still maintain the off state, avoiding the influence of the leakage current on the potential of the pull-down node, thereby improving the working stability of the driving circuit.

[0097] In one embodiment, the driving circuit further includes: a data writing transistor, and the data writing transistor is connected to the write node N.

[0098] Wherein, during the data writing period, the data writing transistor conducts when the write node N is at a high-level signal and writes the data of the write node N.

[0099] It should be noted that in Figure 2 The data write transistor is not shown in the examples. A data write transistor is a switching element used to transmit data signals to a target location during a specific period of time. Specifically, it can be implemented as a thin-film transistor or a metal oxide semiconductor transistor. Its conduction state is controlled by the potential of the write node, thereby ensuring that data writing operations are performed only within a preset period of time. A write node is a connection point in the driver circuit used to temporarily store the data signal to be written. Specifically, it can be formed by a combination of a capacitor and a switch element. When the node is at a high level, it triggers the conduction of the data write transistor, enabling data signal transmission.

[0100] Specifically, during the data write period, the write node N is configured to receive a high-level signal. The data write transistor then conducts based on this high-level signal, allowing the data signal to be transmitted to the target location through the conducting data write transistor. For example, when the signal output by the pull-down control module controls the write node N to be high, the data write transistor is activated, thereby transmitting the data signal stored in the write node to the next-level module in the driver circuit or the pixel unit of the display panel. This process ensures that the data write operation is completed only within the required period by precisely controlling the duration of the high level of the write node.

[0101] The present application introduces a data writing transistor controlled by the write node N, thereby strictly limiting the data writing operation to the period when the high-level signal is valid, thereby avoiding unexpected conduction caused by transistor threshold drift.

[0102] Through the above technical solution, the present application effectively solves the leakage problem caused by the negative bias of the transistor threshold voltage in the driving circuit during the data writing stage, improves the stability and accuracy of data writing, and simplifies the circuit timing control logic.

[0103] In one embodiment, the pull-down module 24 includes: a first capacitor C1, an eighth switch element T8, and a ninth switch element T9. The control end of the eighth switch element and the control end of the ninth switch element T9 are commonly connected to one end of the first capacitor C1; a first end of the eighth switch element T8 is respectively connected to the low-level signal input end VGL and the other end of the first capacitor; and a second end of the eighth switch element T8 is connected to the driving node B.

[0104] A first end of the ninth switching element T9 is connected to the driving node B, and a second end of the ninth switching element T9 is connected to the output end EM of the gate driving unit.

[0105] It should be noted that the first capacitor C1 can be implemented as a metal-insulator-metal structure capacitor and is used to store the potential change of the driving node. The eighth switching element T8 refers to a semiconductor device that controls the on-off connection between the low-level signal and the driving node. It can be implemented as an amorphous silicon thin-film transistor, and its on-state is determined by the charge voltage of the first capacitor C1. The ninth switching element T9 refers to a transmission device that connects the driving node and the output terminal. It can be implemented as an oxide semiconductor transistor and is used to transfer the potential of the driving node to the output terminal.

[0106] Specifically, when the pull-up node is at a high level, the pull-down node is set to a low level, causing the eighth switch element T8 and the ninth switch element T9 to be in the off state. At this time, the high-level signal is directly output to the output terminal of the gate drive unit through the pull-up module 22. When the pull-up node is switched to a low level, the pull-down node becomes a high level, the first capacitor begins to charge, and controls the eighth switch element T8 to turn on. The low-level signal is transmitted to the drive node through the eighth switch element T8. At the same time, the ninth switch element T9 is turned on under the action of the low level of the drive node, transmitting the low-level signal to the output terminal. This dual-switch series structure ensures that a dual conduction path is formed between the drive node and the output terminal during the pull-down process, effectively enhancing the reliability of the pull-down operation.

[0107] The present application introduces a driving node and a dual-switch structure. Under the voltage stabilization effect of the first capacitor C1, even if the threshold voltage of one transistor in the eighth switch element T8 or the ninth switch element T9 is negative, the other transistor can still maintain a normal off state, thereby blocking the leakage path.

[0108] Through the above technical solution, this application effectively solves the leakage problem caused by the pull-down module when the transistor threshold voltage is negative. By setting up a series structure between the drive node and the dual switches, combined with the voltage stabilization effect of the first capacitor, it ensures at least one level of reliable shutdown protection during low-level signal transmission, significantly improving the stability of the gate drive unit during the high-level maintenance phase.

[0109] In one embodiment, the pull-up module 22 includes: a fifth switch element T5, a second capacitor C2, a sixth switch element T6, and a seventh switch element T7. The control terminal of the sixth switch element is connected to the high-level signal input terminal, the first terminal of the sixth switch element is connected to the pull-up node A, and the second terminal of the sixth switch element is connected to the control terminal of the fifth switch element T5 and one terminal D of the second capacitor C2, respectively.

[0110] A first end of the fifth switch element is connected to the other end of the second capacitor C2 and the output end EM of the gate driving unit, respectively, and a second end of the fifth switch element is connected to the high level signal input end VGH.

[0111] The control end of the fourth switch element is connected to the pull-up node, the first end of the fourth switch element is connected to the pull-down node Q, and the second end of the second switch element is connected to the low-level signal input end VGL.

[0112] The control end of the seventh switch element T7 is connected to the second end of the ninth switch element, the first end of the seventh switch element is connected to the high level signal input end VGH, and the second end of the seventh switch element is connected to the driving node B.

[0113] Among them, the fifth switching element refers to an element for connecting the high-level signal input terminal and the output terminal, which can be specifically implemented by an oxide transistor with a dual-gate structure, and its conduction state is controlled by the voltage of the second capacitor. The second capacitor refers to an element that stores charge to maintain the potential of the control terminal of the fifth switching element, which can be specifically implemented by a metal-insulator-metal structure capacitor, and is used to keep the fifth switching element conductive during the pull-up stage. The sixth switching element refers to an element connecting the pull-up node and the control terminal of the fifth switching element, which can be specifically implemented by a low-temperature polysilicon transistor with a single-gate structure, and is used to transfer the pull-up node potential to the control terminal of the fifth switching element when the input signal is triggered. The seventh switching element refers to an element connecting the high-level signal input terminal and the driving node, which can be specifically implemented by an oxide semiconductor transistor, and its conduction state is controlled by the output terminal of the ninth switching element, and is used to compensate the potential of the driving node at a specific stage.

[0114] Specifically, when the pull-up node is charged to a high level, the sixth switch element is turned on by the input signal, transferring the potential of the pull-up node to the control terminal of the fifth switch element, causing the fifth switch element to turn on and transmit the high-level signal to the output terminal. The second capacitor is charged during this stage to maintain the potential of the control terminal of the fifth switch element stable. The operating state of the seventh switch element is controlled by the output signal of the ninth switch element. When the ninth switch element is turned on due to the change in the potential of the pull-down node, the seventh switch element directly applies the voltage of the high-level signal input terminal to the driving node, forming a potential compensation loop for the driving node. This structure ensures that the fifth switch element remains in the on state during the maintenance phase through the charge retention capability of the second capacitor. At the same time, the active potential compensation of the driving node by the seventh switch element can offset the leakage current caused by the negative threshold voltage.

[0115] As an example, the sixth switching element T6 may include two switching sub-elements, namely T6_1 and T6_2, the control end of T6_1 and the control end of T6_2 are connected together and connected to the high-level signal input end VGH; the first end of T6_1 is connected to the pull-up node A; the second end of T6_1 is connected to the first end of T6_2; and the second end of T6_2 is connected to one end D of the second capacitor C2.

[0116] The seventh switching element T7 may include two switching sub-elements, namely T7_1 and T7_2, the control end of T7_1 and the control end of T7_2 are connected together and connected to the second end of the ninth switching element; the first end of T7_1 is connected to the high-level signal input end VGH; the second end of T7_1 is connected to the first end of T7_2; and the second end of T7_2 is connected to the driving node B.

[0117] The present application adds a potential maintenance and compensation loop composed of a second capacitor C2 and a seventh switching element T7, thereby maintaining the basic signal transmission function while adding a dynamic compensation mechanism for the control terminal potential, especially when the transistor threshold voltage is negatively biased, it can still ensure the stable output characteristics of the pull-up module.

[0118] Through the above technical solution, this application effectively solves the leakage problem caused by the negative threshold voltage offset during the high-level maintenance phase of traditional drive circuits. By combining the maintenance of the control terminal potential by the second capacitor with the active compensation of the seventh switching element, the output signal stability can be maintained even when the device characteristics degrade, thereby improving the reliability of the gate drive unit under long-term operation.

[0119] In one embodiment, the tenth switching element T10 is an oxide transistor with a dual-gate structure or a single-gate structure.

[0120] Among them, the dual-gate structure oxide transistor refers to a transistor with two independent control gates, which can be specifically realized by using a double-layer gate structure formed by a metal oxide semiconductor process. The dual-gate structure can collaboratively control the channel conduction state by adjusting the voltage of the two gates.

[0121] A single-gate oxide transistor refers to a transistor having only a single control gate, and can be implemented by using a single-layer gate structure formed using a conventional metal oxide semiconductor process. The structure is simple and the process is mature.

[0122] Specifically, when the pull-down node of the gate drive unit maintains a high level, when the threshold voltage deviates negatively, the transistor in the pull-down control module 23 may be abnormally turned on due to the threshold voltage offset. By setting the tenth switching element as an oxide transistor, its low leakage current characteristics are utilized to suppress abnormal leakage. The dual-gate structure can form a stronger electric field shielding effect by adjusting the two gate potentials, while the single-gate structure achieves stable turn-off characteristics by optimizing the channel doping concentration. Both structures ensure that when the threshold voltage deviates negatively, the tenth switching element can still effectively block the leakage current path between the pull-down node and the high-level signal input terminal.

[0123] In some embodiments, the two gates of a dual-gate oxide transistor can be connected to different potentials, for example, the first gate can be connected to a pull-down node potential, and the second gate can be connected to a constant bias voltage. The gate oxide thickness of a single-gate oxide transistor can be set to, for example, in the range of 10-30 nanometers, and the channel region can be lightly doped to reduce leakage current.

[0124] This application selects oxide semiconductor materials with stable electrical properties, combined with a dual-gate or single-gate structure design, which significantly improves the turn-off reliability of the transistor under negative bias conditions.

[0125] Through the above technical solution, the present application effectively solves the leakage problem caused by the negative bias of the threshold voltage during the high-level maintenance stage of the pull-down node. The dual-gate structure suppresses the formation of leakage channels by enhancing the gate control capability, and the single-gate structure maintains a stable off state by optimizing the device parameters. Both implementation methods can improve the working stability of the driving circuit.

[0126] The present application further proposes that the tenth switch element T10 is an oxide transistor with a dual-gate structure or a single-gate structure.

[0127] A dual-gate structure refers to a transistor with two independent gate electrodes that control the opening and closing of the conductive channel by applying voltages to each. Specifically, a dual-gate structure can be formed by stacking metal layers and semiconductor layers on top of each other or arranged in parallel. A single-gate structure refers to a transistor with only a single gate electrode, and the conductive channel is controlled by a single voltage signal. Specifically, a conventional top-gate or bottom-gate structure design can be used. An oxide transistor refers to a transistor whose channel layer is made of a metal oxide semiconductor material, such as indium gallium zinc oxide.

[0128] Specifically, in the driving circuit, the control terminal of the tenth switch element T10 is connected to the pull-down node, the first terminal is connected to the high-level signal input terminal, and the second terminal is connected to the control terminal of the pull-down control module 23. When the threshold voltage is negatively biased, the high-level signal at the pull-down node is transmitted to the write node through the oxide transistor with a dual-gate or single-gate structure. Because the oxide transistor has high carrier mobility and low leakage current characteristics, it can still maintain a stable on-state when the threshold voltage is negatively biased, ensuring that the high-level signal at the write node is effectively maintained, thereby preventing the transistor in the pull-down control module 23 from leaking during the off phase.

[0129] This application introduces oxide transistors with a dual-gate or single-gate structure and utilizes their excellent electrical properties to accurately control the on-off state of the conductive channel under negative bias conditions, significantly reducing the impact of leakage current on circuit stability.

[0130] Through the above technical solution, the present application effectively solves the leakage problem caused by the negative threshold voltage offset during the high-level maintenance stage of the pull-down node, ensures the stability of the output signal of the driving circuit during long-term operation, and at the same time is compatible with the design requirements of different transistor structures, providing more reliable gate drive control for the display panel.

[0131] As an example, in the EM circuit, when Vth is negatively offset, generally, during the high-level maintenance stage of the Q point, leakage occurs through T4 / T2. Taking T2_1 and T2_2 as examples, when in the off state, at point C, Vg = VGL; at point E, Vs = VGL; under normal circumstances, Vgs = 0V < Vth (positive value), and the TFT is cut off and turned off; when Vth is negatively offset to a negative value, Vgs = 0V > Vth (negative value), and the TFT is turned on, resulting in leakage; to avoid the leakage problem, an anti-negative-offset unit needs to be added.

[0132] As Figure 2 shown, when there is T10 and Vth is negatively offset, when the Q point is high, Vgs_T2_2 = VGL - VGH < Vth, Vgs_T4_2 = VGL - VGH < Vth, and T2_1 / T4_2 are completely turned off, reducing the leakage during the high-level maintenance stage of the Q point. T10 can be a double-gate or single-gate device, ensuring that when Vth is negative, the GOA function is normal. Taking T2_1 and T2_2 as examples, after adding the anti-leakage unit, the high potential at the Q(n) point will turn on T10, writing VGH to the N(n) point; for T2_2: at point C, Vg = VGL, at the N(n) point, Vs = VGH; at the Q(n) point, Vd = VGH; Vgs = VGL - VGH << Vth, and the TFT is stably cut off; the two N(n) indicate that these two points are connected together and both input VGH through T10.

[0133] As Figure 3 and Figure 4 shown, Figure 3 is a schematic diagram of the timing of the driving circuit in an embodiment of the present application; Figure 4 is another schematic diagram of the timing of the driving circuit in an embodiment of the present application; Figure 3 schematically shows the timings of STV, CK, A, B, C, D, Q, and EM when Vth > 0; Figure 4 schematically shows the timings of A, B, C, D, Q, and EM when Vth < 0, and there is leakage at the Q point.

[0134] Based on the above content, an embodiment of the present application further provides a display panel, including a plurality of pixel units arranged in an array and the above-mentioned driving circuit, and each stage of the gate driving unit in the driving circuit is used to drive at least one row of the pixel units. Among them, for the detailed content related to the driving circuit, reference can be made to the detailed content of the foregoing embodiments, which will not be elaborated here.

[0135] The above is a detailed introduction to the driving circuit and display panel provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A driving circuit, applied to a display panel, characterized in that: The driving circuit includes a cascade of multiple gate driving units, and the gate driving unit includes: A pull-up control module, wherein the input end of the pull-up control module is connected to the input signal line, the output end of the pull-up control module is connected to the pull-up node; and the control end of the pull-up control module is connected to the pull-up control signal line; A pull-up module, wherein the input end of the pull-up module is connected to the high-level signal input end, the control end of the pull-up module is connected to the pull-up node, and the output end of the pull-up module is connected to the output end of the gate driving unit; A pull-down control module, wherein the input end of the pull-down control module is connected to the input end of the pull-up control module, the output end of the pull-down control module is connected to the pull-down node; and the control end of the pull-down control module is connected to the pull-up node; a pull-down module, wherein the input end of the pull-down module is connected to the low-level signal input end, the control end of the pull-down module is connected to the pull-down node, and the output end of the pull-down module is connected to the output end of the gate driving unit; a voltage stabilization module, wherein a control terminal of the voltage stabilization module is connected to the pull-down node, an input terminal of the voltage stabilization module is connected to the high-level signal input terminal, and an output terminal of the voltage stabilization module is connected to the control terminal of the pull-down control module; When the threshold voltage in the pull-down control module is negatively biased, the voltage stabilization module is controlled to operate based on the high-level signal of the pull-down node to prevent leakage during the high-level maintenance phase of the pull-down node.

2. The driving circuit according to claim 1, wherein: The voltage stabilization module includes: a tenth switch element, a control end of the tenth switch element is connected to the pull-down node, a first end of the tenth switch element is connected to the high-level signal input end, and a second end of the tenth switch element is connected to the control end of the pull-down control module; When the threshold voltage in the pull-down control module is negatively biased, the tenth switch element is controlled to be turned on based on the high-level signal of the pull-down node to prevent leakage during the high-level maintenance stage of the pull-down node.

3. The driving circuit according to claim 1, wherein: The pull-up control module includes: a first switch element; a control end of the first switch element is connected to the pull-up control signal line, a first end of the first switch element is connected to the input signal line, and a second end of the first switch element is connected to the pull-up node; The pull-up signal transmitted by the pull-up control signal line is a clock signal, and the input signal transmitted by the input signal line is a frame start signal.

4. The driving circuit according to claim 2, wherein: The pull-down control module includes: a second switch element, a third capacitor, a third switch element and a fourth switch element; wherein, The control end of the third switch element is connected to the input signal line, the first end of the third switch element is connected to one end of the third capacitor, and the second end of the third switch element is connected to the input end of the pull-down module; The control end of the second switch element is connected to the first end of the third switch element, the first end of the second switch element is respectively connected to the other end of the third capacitor and the input signal line, and the second end of the second switch element is connected to the pull-down node; The control end of the fourth switch element is connected to the pull-up node, the first end of the fourth switch element is connected to the pull-down node, and the second end of the second switch element is connected to the low-level signal input end.

5. The driving circuit according to claim 4, wherein: The second end of the tenth switch element is connected to the write node; the fourth switch element includes a first sub-element and a second sub-element; the second switch element includes a third sub-element and a fourth sub-element; The control end of the first sub-element and the control end of the second sub-element are connected to the pull-up node, the first end of the first sub-element is connected to the low-level signal input end, the second end of the first sub-element is connected to the first end of the second sub-element and the write node respectively, and the second end of the second sub-element is connected to the pull-down node; The control end of the third sub-element and the control end of the fourth sub-element are connected to the first end of the third switch element, the first end of the third sub-element is connected to the pull-up control signal line, the second end of the third sub-element is connected to the first end of the fourth sub-element and the write node respectively, and the second end of the fourth sub-element is connected to the pull-down node; When the pull-down node is a high-level signal, the tenth switch element is turned on and writes the high-level signal to the write node, so that when the threshold voltage is negatively biased, the first sub-element, the second sub-element, the third sub-element and the fourth sub-element are in the off state.

6. The driving circuit according to claim 5, wherein: The driving circuit further includes: a data writing transistor, wherein an electrode of the data writing transistor is connected to the writing node; In the data writing period, the data writing transistor is turned on when the writing node is a high level signal, and writes the data of the writing node.

7. The driving circuit according to claim 6, wherein: The pull-down module includes: a first capacitor, an eighth switch element and a ninth switch element; wherein, The control end of the eighth switching element and the control end of the ninth switching element are commonly connected to one end of the first capacitor; the first end of the eighth switching element is respectively connected to the low-level signal input end and the other end of the first capacitor; the second end of the eighth switching element is connected to the driving node; A first end of the ninth switching element is connected to the driving node, and a second end of the ninth switching element is connected to the output end of the gate driving unit.

8. The driving circuit according to claim 7, wherein: The pull-up module includes: a fifth switch element, a second capacitor, a sixth switch element and a seventh switch element; wherein, The control terminal of the sixth switch element is connected to the high-level signal input terminal, the first terminal of the sixth switch element is connected to the pull-up node, and the second terminal of the sixth switch element is connected to the control terminal of the fifth switch element and one terminal of the second capacitor respectively; A first end of the fifth switch element is connected to the other end of the second capacitor and the output end of the gate driving unit respectively, and a second end of the fifth switch element is connected to the high-level signal input end; The control end of the fourth switch element is connected to the pull-up node, the first end of the fourth switch element is connected to the pull-down node, and the second end of the second switch element is connected to the low-level signal input end; The control end of the seventh switch element is connected to the second end of the ninth switch element, the first end of the seventh switch element is connected to the high level signal input end, and the second end of the seventh switch element is connected to the driving node.

9. The driving circuit according to claim 2, wherein: The tenth switching element is an oxide transistor with a double-gate structure or a single-gate structure.

10. A display panel, characterized in that: The invention comprises a plurality of pixel units arranged in an array and a driving circuit according to any one of claims 1 to 9, wherein each stage of gate driving units in the driving circuit is used to drive at least one row of the pixel units.

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