Stage circuit

Abstract

A stage circuit includes: an output unit supplying a scan signal to an output terminal in response to a voltage of a first node and a voltage of a second node; an input unit outputting a carry signal or a start signal input to the first input terminal in response to a clock signal; a first transistor connected between the input unit and the second node and set to an on state during a driving period; and a controller connected between the input unit and the first transistor or between the first transistor and the second node, in which the controller controls an electrical connection between the input unit and the second node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2024-0040387, filed on March 25, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a stage circuit, a display device including the stage circuit, and an electronic device. Background Art

[0004] With the development of information technology, the importance of display devices as a connection medium between users and information is becoming increasingly apparent. Therefore, display devices such as liquid crystal display devices and organic light emitting display devices are widely used in various fields. Summary of the Invention

[0005] A display device can display an image by selecting pixels and supplying data signals to the selected pixels while supplying scan signals using a scan driver. A technology that can ensure the reliability of the scan driver when driving the display device at a low drive frequency is desired. Furthermore, a technology that can reduce the power consumption of the display device is desired.

[0006] Embodiments of the present disclosure provide a stage circuit and a display device including the stage circuit, which can ensure driving reliability by minimizing leakage current of the stage circuit driven at a low driving frequency.

[0007] Embodiments of the present disclosure provide a stage circuit and a display device including the stage circuit, which can minimize power consumed in the stage circuit (power consumption).

[0008] According to an embodiment of the present disclosure, a stage circuit includes: an output unit, which supplies a scan signal to an output terminal in response to a voltage of a first node and a voltage of a second node; an input unit, which outputs a carry signal or a start signal input to a first input terminal in response to a clock signal; a first transistor, which is connected between the input unit and the second node and is set to an on state during a driving cycle; and a controller, which is connected between the input unit and the first transistor or between the first transistor and the second node, wherein the controller controls the electrical connection between the input unit and the second node.

[0009] According to an embodiment, the controller may be connected between the input unit and the first transistor.

[0010] According to an embodiment, the controller may be connected between the first transistor and the second node.

[0011] According to an embodiment, the controller may include a second transistor.

[0012] According to an embodiment, a gate electrode of the second transistor may be connected to the first node.

[0013] According to an embodiment, the second transistor may include a gate electrode connected to a control input terminal, and the control input terminal may receive a control signal.

[0014] According to an embodiment, the driving period of one frame may include a display scanning period for receiving a data signal and a self-scanning period for emitting light while maintaining the data signal, and the control signal may be set to a voltage level for turning on the second transistor during the display scanning period, and the control signal may be set to a voltage level for turning off the second transistor during the self-scanning period.

[0015] According to an embodiment, the second transistor may further include a second gate electrode, and the second gate electrode may be electrically connected to the gate electrode of the second transistor.

[0016] According to an embodiment, the second transistor may further include a second gate electrode, and the second gate electrode may receive a direct current (DC) voltage.

[0017] According to an embodiment, the second transistor may further include a second gate electrode, and the second gate electrode may receive an alternating current (AC) voltage.

[0018] According to an embodiment, the first transistor and the second transistor may be different types of transistors.

[0019] According to an embodiment, the first transistor may be a P-type transistor, and the second transistor may be an N-type transistor.

[0020] According to an embodiment, the first transistor may be an N-type transistor, and the second transistor may be a P-type transistor.

[0021] According to an embodiment, the first transistor and the second transistor may be P-type transistors.

[0022] According to an embodiment, the first transistor and the second transistor may be N-type transistors.

[0023] According to an embodiment, the stage circuit may further include a driver for controlling a voltage of the first node, and the controller may be connected between the driver and the first transistor.

[0024] According to an embodiment, the stage circuit may further include a driver for controlling the voltage of the first node, and the controller may be connected between the input unit and the driver.

[0025] According to an embodiment of the present disclosure, a display device includes: pixels connected to scan lines, emission control lines and data lines; a scan driver that supplies scan signals to the scan lines; and an emission driver that supplies emission control signals to the emission control lines, wherein a stage circuit is included in at least one selected from the scan driver and the emission driver, and the stage circuit includes: an output unit that supplies a scan signal or an emission control signal to an output terminal in response to a voltage of a first node and a voltage of a second node; an input unit that outputs a carry signal or a start signal input to the first input terminal in response to a clock signal; a first transistor that is connected between the input unit and the second node and is set to a conductive state during a driving period; and a controller that is connected between the input unit and the first transistor or between the first transistor and the second node, wherein the controller controls the electrical connection between the input unit and the second node.

[0026] According to an embodiment, the controller may include a second transistor.

[0027] According to an embodiment, a gate electrode of the second transistor may be connected to the first node.

[0028] According to an embodiment of the present disclosure, an electronic device includes: a processor that provides input image data; and a display device that displays an image based on the input image data; wherein the display device includes pixels connected to scan lines, emission control lines and data lines, a scan driver that supplies scan signals to the scan lines, and an emission driver that supplies emission control signals to the emission control lines, wherein a stage circuit is included in at least one selected from the scan driver and the emission driver, and the stage circuit includes: an output unit that supplies a scan signal or an emission control signal to an output terminal in response to a voltage of a first node and a voltage of a second node; an input unit that outputs a carry signal or a start signal input to the first input terminal in response to a clock signal; a first transistor that is connected between the input unit and the second node and is set to a conductive state during a driving period; and a controller that is connected between the input unit and the first transistor or between the first transistor and the second node, wherein the controller controls the electrical connection between the input unit and the second node.

[0029] According to the stage circuit and the display device including the stage circuit according to the embodiments of the present disclosure, leakage current can be minimized by a controller (or a second transistor), which remains in an on state during a first cycle (for example, a display scan cycle, or a cycle in which a scan signal is output enabled) and remains in a off state during a second cycle (for example, a self-scan cycle, or a cycle in which a scan signal is output disabled).

[0030] In an embodiment of the present disclosure, a voltage of a second node included in an output unit of a stage circuit may be boosted, thereby minimizing power consumption.

[0031] However, the effects of the present disclosure are not limited to the above-described effects, and various extensions can be made within a range that does not depart from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other features of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which:

[0033] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure;

[0034] Figure 2 It is an icon Figure 1 FIGURES of an embodiment of a scan driver and an emission driver shown in FIGURES;

[0035] Figure 3 is an equivalent circuit diagram illustrating a pixel according to an embodiment of the present disclosure;

[0036] Figure 4 The diagram shows the drive during the display scan cycle. Figure 3 The method for driving the pixel Figure 3 a waveform diagram of an embodiment of a signal of a pixel of FIG. 1 ;

[0037] Figure 5 The diagram shows the driving during the self-scan period. Figure 3 The method for driving the pixel Figure 3 a waveform diagram of an embodiment of a signal of a pixel of FIG. 1 ;

[0038] Figure 6 and Figure 7 is a diagram illustrating an embodiment of signals supplied in an active period and a blanking period;

[0039] Figure 8 It is an icon Figure 1 FIGURE 1 shows an embodiment of a scan driver shown in FIGURE 2;

[0040] Figure 9A and Figure 9B It is an icon Figure 8 FIGURE 1 shows an embodiment of a stage circuit as shown in FIGURE 2;

[0041] Figure 10 It is a graphic and Figure 9A and Figure 9B The driving method (or the method for driving the embodiment of the stage circuit shown in Figure 9A and Figure 9B ) corresponding waveform diagrams of the signals of the embodiment of the stage circuit shown in FIG;

[0042] Figure 11is a diagram illustrating a voltage of a second node when a controller is not included in a stage circuit;

[0043] Figure 12A and Figure 12B is a diagram illustrating an embodiment of a voltage of a control signal;

[0044] Figure 13 It is an icon Figure 1 FIG. 1 is a diagram of an embodiment of a scan driver;

[0045] Figure 14 It is an icon Figure 8 FIGURE 1 shows an embodiment of a stage circuit as shown in FIGURE 2;

[0046] Figure 15 is a graph illustrating a voltage of a second node included in a stage circuit;

[0047] 16A to 16C is a diagram illustrating an embodiment of a transistor included in a controller;

[0048] 17A to 17C is a diagram illustrating an embodiment of a transistor included in a controller;

[0049] Figure 18A and Figure 18B is a diagram illustrating a stage circuit according to an embodiment of the present disclosure;

[0050] Figure 19 is a diagram illustrating a stage circuit according to an embodiment of the present disclosure;

[0051] Figure 20 is a diagram illustrating a stage circuit according to an embodiment of the present disclosure;

[0052] Figure 21 and Figure 22 is a diagram illustrating a stage circuit according to an embodiment of the present disclosure;

[0053] Figure 23 is a schematic block diagram illustrating an electronic device including a display device according to an embodiment;

[0054] Figure 24 It is an icon Figure 23 A schematic diagram of an example in which the electronic device is a smartphone; and

[0055] Figure 25 It is an icon Figure 23 Schematic diagram of an example in which the electronic device is a tablet computer. DETAILED DESCRIPTION

[0056] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0057] In order to clearly describe the present disclosure, parts not related to the description are omitted, and the same or similar elements are represented by the same reference numerals throughout the specification. Therefore, the above reference numerals can be used in other drawings.

[0058] In addition, since the size and thickness of each configuration shown in the drawings are arbitrarily shown for the sake of convenience of description, the present disclosure is not necessarily limited to the size and thickness of each configuration shown in the drawings. In order to clearly show multiple layers and regions in the drawings, the thickness may be exaggerated.

[0059] In addition, the expression "is the same" in the description may mean "is substantially the same." That is, the expression "is the same" may be sufficient for a person of ordinary skill in the art to understand that they are the same. Other expressions may also be expressions that omit "substantially."

[0060] Some embodiments are described in the accompanying drawings about function blocks, units and / or modules. Those skilled in the art will understand that such function blocks, units and / or modules are physically implemented by logic circuits, single components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing technology or other manufacturing technology. Function blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, and the function blocks, units and / or modules can optionally be driven by firmware and / or software. In addition, each function block, unit and / or module can be implemented by a combination of dedicated hardware, or dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs functions different from the functions of the dedicated hardware. In addition, in some embodiments, without departing from the scope of the present invention, the function blocks, units and / or modules can be physically divided into two or more interacting separate function blocks, units and / or modules. In addition, in some embodiments, without departing from the scope of the present invention, the function blocks, units and / or modules can be physically combined into more complex function blocks, units and / or modules.

[0061] The term "connection" between two configurations may be used to include both electrical and physical connections, but is not limited thereto. For example, "connection" used based on a circuit diagram may mean electrical connection, and "connection" used based on a cross-sectional view or a plan view may mean physical connection.

[0062] It will be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings herein, the "first element," "first component," "first region," "first layer," or "first part" discussed below may be referred to as the "second element," "second component," "second region," "second layer," or "second part."

[0063] The terms used herein are only used to describe the purpose of specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, "one", "one (kind / person)", "described (should)" and "at least one (kind / person)" do not represent a restriction on quantity and are intended to include both the singular and the plural. Therefore, in the claims, a reference to "one" element follows a reference to "described (should)" element including one element and a plurality of described elements. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one (kind / person)" is not interpreted as limiting "one" or "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that when used in this specification, the terms “comprises” and / or “includes” or “contains” and / or “has” specify the presence of stated features, regions, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof.

[0064] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as illustrated in the accompanying drawings. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device in a drawing is turned over, an element described as being "below" the other elements will subsequently be oriented as being "above" the other elements. Thus, depending on the particular orientation of the drawing, the term "lower" can encompass both the "lower" and "upper" orientations. Similarly, if the device in a drawing is turned over, an element described as being "below" or "beneath" the other elements will subsequently be oriented as being "above" the other elements. Thus, the terms "below" or "beneath" can encompass both the "above" and "below" orientations.

[0065] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0066] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0067] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure. Figure 2 It is an icon Figure 1 An embodiment of a scan driver and an emission driver is shown in FIG.

[0068] refer to Figure 1 and Figure 2 , also refer to Figure 3 , the display device 100 according to an embodiment of the present disclosure may include a pixel unit 110 (or a display panel), a timing controller 120 , a scan driver 130 , a data driver 140 , an emission driver 150 , and a power supply 160 .

[0069] The display device 100 can display images at various image refresh rates (driving frequencies or screen reproduction rates) determined based on driving conditions. The image refresh rate refers to the frequency at which data signals are written to the drive transistors of the pixels PX. For example, the image refresh rate can be referred to as the screen scan rate or screen reproduction rate and can indicate the frequency at which a display image is reproduced per second.

[0070] In an embodiment, the output frequency of the data driver 140 for one horizontal line (for example, pixels PX connected to the same scan line may be classified into one horizontal line (or pixel row)) and / or the output frequency of the first scan driver 132 outputting the first scan signal (or write scan signal) may be determined corresponding to the image refresh rate. For example, the image refresh rate for driving a moving image may be a frequency of approximately 60 hertz (Hz) or higher (for example, 120 Hz or 240 Hz, etc.).

[0071] For example, the display device 100 may display images corresponding to various image refresh rates of 1 Hz to 240 Hz. However, this is an example, and the display device 100 may display images at an image refresh rate of 240 Hz or higher (eg, 480 Hz).

[0072] The pixel unit 110 may include pixels PX, which are connected to first scan lines SL11, SL12, ... and SL1n, second scan lines SL21, SL22, ... and SL2n, third scan lines SL31, SL32, ... and SL3n, fourth scan lines SL41, SL42, ... and SL4n, data lines DL1, DL2, ... and DLm, emission control lines EL1, EL2, ... and ELo, and power lines PL1, PL2, PL3, PL4 and PL5 (here, n, m, o are each a natural number equal to or greater than 2).

[0073] For example, the pixel PXij (referenced to Figure 3 ) can be connected to the i-th first scan line SL1i (also referred to as the first scan line SL1i), the i-th second scan line SL2i (also referred to as the second scan line SL2i), the i-th third scan line SL3i (also referred to as the third scan line SL3i), the i-th fourth scan line SL4i (also referred to as the fourth scan line SL4i), the k-th emission control line ELk (also referred to as the emission control line ELk) and the j-th data line DLj (also referred to as the data line DLj) (here, i is a natural number greater than or equal to 1 and equal to or less than n, j is a natural number greater than or equal to 1 and equal to or less than m, and k is a natural number greater than or equal to 1 and equal to or less than o). Here, k can be a natural number equal to or less than i. In an embodiment, for example, in the case where each of the emission control lines EL1 to ELo is connected to the pixels PX positioned in one horizontal line, k can be the same natural number as i. In an embodiment, for example, in the case where each of the emission control lines EL1 to ELo is connected to the pixels PX positioned in two or more horizontal lines, k can be a natural number less than i.

[0074] When an enabled first scan signal is supplied to the first scan lines SL11 to SL1n, a pixel PX may be selected (or activated) in units of horizontal lines (or on a horizontal line-by-horizontal line basis), and the pixel PX selected by the enabled first scan signal may receive a data signal from a data line (one of the data lines DL1 to DLm) connected to the pixel PX. The pixel PX receiving the data signal may generate light of a predetermined brightness in response to a voltage of the data signal.

[0075] The scan driver 130 may receive a scan driving signal SCS from the timing controller 120. The scan driving signal SCS may include at least one scan start signal and a clock signal for driving the scan driver 130. The scan driver 130 may generate an enabled first scan signal, an enabled second scan signal, an enabled third scan signal, and an enabled fourth scan signal while shifting the scan start signal in response to the clock signal.

[0076] In an embodiment, Figure 2 As shown in FIG, the scan driver 130 may include a first scan driver 132, a second scan driver 134, a third scan driver 136, and a fourth scan driver 138. In such an embodiment, if desired, at least two selected from the scan drivers 132, 134, 136, and 138 may be integrated into one driver circuit or module, etc.

[0077] The first scan driver 132 may receive the first scan start signal FLM1 and generate an enabled first scan signal by shifting the first scan start signal FLM1 in response to a clock signal. The first scan driver 132 may sequentially supply the enabled first scan signal to the first scan lines SL11 to SL1n. In an embodiment, the first scan driver 132 may supply the enabled first scan signal during a display scan period of one frame (one frame period).

[0078] The second scan driver 134 may receive the second scan start signal FLM2 and generate an enabled second scan signal by shifting the second scan start signal FLM2 in response to a clock signal. The second scan driver 134 may sequentially supply the enabled second scan signal to the second scan lines SL21 to SL2n. In an embodiment, the second scan driver 134 may supply the enabled second scan signal during a display scan period of one frame.

[0079] The third scan driver 136 may receive the third scan start signal FLM3 and generate an enabled third scan signal by shifting the third scan start signal FLM3 in response to a clock signal. The third scan driver 136 may sequentially supply the enabled third scan signal to the third scan lines SL31 to SL3n. In an embodiment, the third scan driver 136 may supply the enabled third scan signal during a display scan period of one frame.

[0080] The fourth scan driver 138 receives the fourth scan start signal FLM4 and generates an enabled fourth scan signal by shifting the fourth scan start signal FLM4 in response to the clock signal. The fourth scan driver 138 sequentially supplies the enabled fourth scan signal to the fourth scan lines SL41 to SL4n.

[0081] In an embodiment, the fourth scan driver 138 may supply an enabled fourth scan signal during a display scan period and a self-scan period of one frame. In an embodiment, for example, the fourth scan driver 138 may perform one scan (i.e., supply at least one enabled fourth scan signal) during the display scan period, and perform at least one scan during the self-scan period according to the image refresh rate. When the image refresh rate decreases (i.e., the frame length increases), the number of repetitions of the operation of supplying the enabled fourth scan signal to each of the fourth scan lines SL41 to SL4n by the fourth scan driver 138 during the frame period may increase.

[0082] The enabled first scan signal, the enabled second scan signal, the enabled third scan signal, and the enabled fourth scan signal may be set to a gate-on voltage so that a transistor included in the pixel PX may be turned on.

[0083] In an embodiment, for example, Figure 3 As shown in , the enabled first scan signal GW and the enabled fourth scan signal GB supplied to the P-type transistor may be set to a low level voltage, and the enabled second scan signal GC and the enabled third scan signal GI supplied to the N-type transistor may be set to a high level voltage.

[0084] exist Figure 2 , the first scan driver 132, the second scan driver 134, the third scan driver 136, and the fourth scan driver 138 are shown as being connected to the corresponding first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4, but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, at least two selected from the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4 (at least two of the scan lines SL1, SL2, SL3, and SL4) may be driven by one scan driver.

[0085] In an embodiment, for example, the second scan line SL2 and the third scan line SL3 may be driven by one scan driver. In such an embodiment, the second scan line SL2 and the third scan line SL3 may be omitted. Figure 2 One of the second scan driver 134 and the third scan driver 136 shown in FIG.

[0086] Return Reference Figure 1 , the data driver 140 may receive the output data Dout and the data drive signal DCS from the timing controller 120. The data drive signal DCS may include a sampling signal and / or a timing signal for driving the data driver 140. The data driver 140 may generate a data signal based on the data drive signal DCS and the output data Dout. For example, the data driver 140 may generate an analog data signal based on the grayscale of the output data Dout. The data driver 140 may supply the data signal in units of one horizontal period (or every horizontal period).

[0087] The emission driver 150 may receive an emission driving signal ECS from the timing controller 120. The emission driving signal ECS may include an emission start signal and a clock signal for driving the emission driver 150. The emission driver 150 may generate a disabled emission control signal EM while shifting the emission start signal in response to the clock signal.

[0088] In an embodiment, Figure 2 As shown in , the emission driver 150 may receive the emission start signal EFLM and generate a disabled emission control signal EM while shifting the emission start signal EFLM in response to a clock signal. The emission driver 150 may sequentially supply the disabled emission control signal EM to the emission control lines EL1 to ELo. The disabled emission control signal EM may be set to a gate-off voltage so that the transistor included in the pixel PX may be turned off. In an embodiment, for example, as Figure 3 As shown in , the disabled emission control signal EM supplied to the P-type transistor may be set to a high level voltage.

[0089] In an embodiment, the emission driver 150 may supply a disabled emission control signal during the display scan period and the self-scan period of one frame. In an embodiment, for example, the emission driver 150 may perform one scan during the display scan period of one frame, and may perform at least one scan during the self-scan period of one frame according to the image refresh rate. When the image refresh rate decreases (i.e., the frame length increases), the number of repetitions of the operation of supplying the disabled emission control signal EM to each of the emission control lines EL1 to ELo by the emission driver 150 during the frame period may increase.

[0090] The timing controller 120 may receive input data Din and a timing control signal TCS from the host system through an interface. In an embodiment, for example, the timing controller 120 may receive input data Din and a timing control signal TCS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP) included in the host system. The timing control signal TCS may include various signals including a clock signal.

[0091] The timing controller 120 may generate a scan driving signal SCS, a data driving signal DCS, and an emission driving signal ECS based on the timing control signal TCS. The scan driving signal SCS, the data driving signal DCS, and the emission driving signal ECS may be supplied to the scan driver 130, the data driver 140, and the emission driver 150, respectively.

[0092] The timing controller 120 may rearrange the input data Din to fit the specifications of the display device 100. In addition, the timing controller 120 may correct the input data Din to generate output data Dout and supply the output data Dout to the data driver 140. In an embodiment, the timing controller 120 may correct the input data Din in response to an optical measurement result measured in a process.

[0093] The power supply 160 may generate various powers for driving the display device 100. In an embodiment, for example, the power supply 160 may generate a first driving power (or voltage) VDD, a second driving power VSS, a first initialization power Vint1, a second initialization power Vint2, and a bias power Vbias.

[0094] The first driving power VDD may be power that supplies a driving current to the pixel PX. The second driving power VSS may be power that receives a driving current from the pixel PX. During a period in which the pixel PX is set to an emission state, the first driving power VDD may be set to a voltage higher than the voltage of the second driving power VSS.

[0095] The first initialization power Vint1 may be power for initializing the gate electrode of the driving transistor included in each of the pixels PX. The first initialization power Vint1 may be set to a voltage lower than the voltage of the data signal. The second initialization power Vint2 may be power for initializing the first electrode (or anode electrode) of the light-emitting element LD included in each of the pixels PX. The second initialization power Vint2 may be set to a voltage that turns off the light-emitting element LD. The bias power Vbias may be power for applying a turn-on bias voltage to the driving transistor included in each of the pixels PX.

[0096] The first driving power VDD generated by the power supply 160 may be supplied to the first power line PL1, the second driving power VSS may be supplied to the second power line PL2, the first initialization power Vint1 may be supplied to the third power line PL3, the second initialization power Vint2 may be supplied to the fourth power line PL4, and the bias power Vbias may be supplied to the fifth power line PL5. In an embodiment, for example, the first power line PL1, the second power line PL2, the third power line PL3, the fourth power line PL4, and the fifth power line PL5 are commonly connected to the pixel PX, but the embodiments of the present disclosure are not limited thereto.

[0097] In an embodiment, the first power line PL1 may include or be configured from a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. In an embodiment, the second power line PL2 may include or be configured from a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. In an embodiment, the third power line PL3 may include or be configured from a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. In an embodiment, the fourth power line PL4 may include or be configured from a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. In an embodiment, the fifth power line PL5 may include or be configured from a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. That is, in such an embodiment of the present disclosure, each pixel PX may be connected to a corresponding one of the first power line PL1, a corresponding one of the second power line PL2, a corresponding one of the third power line PL3, a corresponding one of the fourth power line PL4, and a corresponding one of the fifth power line PL5.

[0098] In an embodiment of the present disclosure, the display device 100 may be a flat display device, a curved display device in which a portion of the pixel unit 110 is bent, a flexible display device in which a portion of the pixel unit 110 can be folded or bent, and a stretchable display device in which a portion of the pixel unit 110 can be expanded or contracted.

[0099] In an embodiment of the present disclosure, the display device 100 may be a device that displays moving images or still images, and may include a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra-mobile PC (UMPC). In an embodiment of the present disclosure, the display device 100 may include an electronic device such as a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device.

[0100] Figure 3 is an equivalent circuit diagram illustrating a pixel according to an embodiment of the present disclosure. Figure 3 Pixels positioned in the i-th horizontal line and the j-th vertical line are shown.

[0101] refer to Figure 3 , according to an embodiment of the present disclosure, a pixel PXij can be connected to corresponding signal lines (scan lines SL1i, SL2i, SL3i, and SL4i, emission control line ELk, and data line DLj). For example, pixel PXij can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th fourth scan line SL4i, the k-th emission control line ELk, and the j-th data line DLj. In an embodiment, pixel PXij can be further connected to a first power line PL1, a second power line PL2, a third power line PL3, a fourth power line PL4, and a fifth power line PL5.

[0102] The pixel PXij according to an embodiment of the present disclosure may include a light emitting element LD and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0103] The light-emitting element LD may be connected between the first power line PL1 and the second power line PL2. In an embodiment, for example, the first electrode (or anode electrode) of the light-emitting element LD may be electrically connected to the first power line PL1 via the seventh pixel transistor M7, the third node N3, the first pixel transistor M1, the second node N2, and the sixth pixel transistor M6, and the second electrode (or cathode electrode) of the light-emitting element LD may be electrically connected to the second power line PL2. The light-emitting element LD may generate light of a predetermined brightness in response to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0104] In an embodiment, the light emitting element LD may include an organic light emitting diode. In another embodiment, the light emitting element LD may include an inorganic light emitting diode such as a micro light emitting diode (LED) or a quantum dot light emitting diode. In another embodiment, the light emitting element LD may be an element configured of a composite of an organic material and an inorganic material. In an embodiment, as Figure 3 As shown in , the pixel PXij may include a single light emitting element LD. However, in another embodiment, the pixel PXij may include a plurality of light emitting elements LD, and the plurality of light emitting elements LD may be connected to each other in series, in parallel, or in series and parallel.

[0105] In an embodiment, Figure 3As shown in , the pixel circuit may include a first pixel transistor M1, a second pixel transistor M2, a third pixel transistor M3, a fourth pixel transistor M4, a fifth pixel transistor M5, a sixth pixel transistor M6, a seventh pixel transistor M7, an eighth pixel transistor M8 and a storage capacitor Cst.

[0106] A first electrode of the first pixel transistor M1 (or driving transistor) may be connected to a second node N2, and a second electrode of the first pixel transistor M1 may be connected to a third node N3. Furthermore, a gate electrode of the first pixel transistor M1 may be connected to the first node N1. The first pixel transistor M1 may control the amount of current supplied from the first power line PL1 to which the first driving power VDD is applied via the light emitting element LD to the second power line PL2 to which the second driving power VSS is applied, in response to a voltage at the first node N1.

[0107] The second pixel transistor M2 may be connected between the data line DLj and the second node N2. Furthermore, a gate electrode of the second pixel transistor M2 may be electrically connected to the first scan line SL1i. The second pixel transistor M2 may be turned on when an enabled first scan signal GW is supplied to the first scan line SL1i to electrically connect the data line DLj and the second node N2.

[0108] A first electrode of the third pixel transistor M3 may be coupled to the first node N1, and a second electrode of the third pixel transistor M3 may be electrically coupled to the third power line PL3. Furthermore, a gate electrode of the third pixel transistor M3 may be electrically coupled to the third scan line SL3i. The third pixel transistor M3 may be turned on when an enabled third scan signal GI is supplied to the third scan line SL3i to supply a voltage of the first initialization power Vint1 to the first node N1.

[0109] The fourth pixel transistor M4 may be connected between the first node N1 and the third node N3. Furthermore, a gate electrode of the fourth pixel transistor M4 may be electrically connected to the second scan line SL2i. The fourth pixel transistor M4 may be turned on when an enabled second scan signal GC is supplied to the second scan line SL2i to electrically connect the first node N1 and the third node N3. That is, when the fourth pixel transistor M4 is turned on, the first pixel transistor M1 may be diode-connected.

[0110] A first electrode of the fifth pixel transistor M5 can be connected to the first electrode of the light emitting element LD, and a second electrode of the fifth pixel transistor M5 can be electrically connected to the fourth power line PL4. In addition, a gate electrode of the fifth pixel transistor M5 can be electrically connected to the fourth scan line SL4i. The fifth pixel transistor M5 can be turned on when an enabled fourth scan signal GB is supplied to the fourth scan line SL4i to supply a voltage of the second initialization power Vint2 to the first electrode of the light emitting element LD.

[0111] When the voltage of the second initialization power Vint2 is supplied to the first electrode of the light-emitting element LD, the parasitic capacitor of the light-emitting element LD can be discharged. Since the residual voltage charged in the parasitic capacitor of the light-emitting element LD is discharged (or removed), undesirable micro-emissions can be effectively prevented. Therefore, the black rendering capability of the pixel PXij can be improved.

[0112] A first electrode of the sixth pixel transistor M6 may be electrically connected to the first power line PL1, and a second electrode of the sixth pixel transistor M6 may be connected to the second node N2. In addition, a gate electrode of the sixth pixel transistor M6 may be electrically connected to the emission control line ELk. The sixth pixel transistor M6 may be turned off when a disabled emission control signal EM is supplied to the emission control line ELk, and may be turned on when an enabled emission control signal EM is supplied to the emission control line ELk.

[0113] The seventh pixel transistor M7 may be connected between the third node N3 and the first electrode of the light emitting element LD. In addition, the gate electrode of the seventh pixel transistor M7 may be electrically connected to the emission control line ELk. The seventh pixel transistor M7 may be turned off when a disabled emission control signal EM is supplied to the emission control line ELk, and may be turned on when an enabled emission control signal EM is supplied to the emission control line ELk.

[0114] A first electrode of the eighth pixel transistor M8 can be electrically connected to the fifth power line PL5, and a second electrode of the eighth pixel transistor M8 can be connected to the second node N2. In addition, a gate electrode of the eighth pixel transistor M8 can be electrically connected to the fourth scan line SL4i. The eighth pixel transistor M8 can be turned on when an enabled fourth scan signal GB is supplied to the fourth scan line SL4i to electrically connect the fifth power line PL5 to the second node N2.

[0115] The storage capacitor Cst may be connected between the first power line PL1 and the first node N1. The storage capacitor Cst may store a voltage applied to the first node N1.

[0116] In an embodiment, the first pixel transistor M1, the second pixel transistor M2, the fifth pixel transistor M5, the sixth pixel transistor M6, the seventh pixel transistor M7, and the eighth pixel transistor M8 may be formed of polysilicon semiconductor transistors. In an embodiment, for example, the first pixel transistor M1, the second pixel transistor M2, the fifth pixel transistor M5, the sixth pixel transistor M6, the seventh pixel transistor M7, and the eighth pixel transistor M8 may include a polysilicon semiconductor layer formed by a low-temperature polysilicon (LTPS) process as an active layer (channel). In addition, the first pixel transistor M1, the second pixel transistor M2, the fifth pixel transistor M5, the sixth pixel transistor M6, the seventh pixel transistor M7, and the eighth pixel transistor M8 may be P-type transistors (e.g., P-channel metal oxide semiconductor (PMOS) transistors). Therefore, the gate-on voltage that turns on the first pixel transistor M1, the second pixel transistor M2, the fifth pixel transistor M5, the sixth pixel transistor M6, the seventh pixel transistor M7, and the eighth pixel transistor M8 may be a voltage having a logic low level. Since the polycrystalline silicon semiconductor transistor has a desirable characteristic of fast response speed, the polycrystalline silicon semiconductor transistor can be applied to a switching element that is desired to have a fast switching characteristic.

[0117] In an embodiment, the third pixel transistor M3 and the fourth pixel transistor M4 may be formed of oxide semiconductor transistors. For example, the third pixel transistor M3 and the fourth pixel transistor M4 may be N-type oxide semiconductor transistors (e.g., N-channel metal oxide semiconductor (NMOS) transistors) and may include an oxide semiconductor layer as an active layer. Therefore, the gate-on voltage that turns on the third pixel transistor M3 and the fourth pixel transistor M4 may be a voltage having a logic high level.

[0118] Oxide semiconductor transistors can be processed at low temperatures and have a charge mobility lower than that of polysilicon semiconductor transistors. That is, oxide semiconductor transistors have high off-current characteristics. Therefore, in an embodiment in which the third pixel transistor M3 and the fourth pixel transistor M4 are formed of oxide semiconductor transistors, leakage current from the first node N1 caused by low-frequency driving can be minimized, thereby improving display quality.

[0119] Figure 4 The diagram shows the drive during the display scan cycle. Figure 3 The method for driving the pixel Figure 3 The display scanning period DSP may be included in the effective period of the frame.

[0120] refer to Figure 3 and Figure 4The display scanning period DSP may include a first period P1, a second period P2, a third period P3, and a fourth period P4. The first to third periods P1 to P3 may be set as non-emission periods, and the fourth period P4 may be set as an emission period.

[0121] The disabled emission control signal EM may be supplied to the emission control line ELk during the first to third periods P1 to P3. When the disabled emission control signal EM is supplied to the emission control line ELk, the sixth pixel transistor M6 and the seventh pixel transistor M7 are turned off. When the sixth pixel transistor M6 and the seventh pixel transistor M7 are turned off, the electrical connection between the first power line PL1 and the light emitting element LD is cut off, and thus the light emitting element LD is set to a non-emission state.

[0122] During the first period P1, the enabled third scan signal GI is supplied to the third scan line SL3i. When the enabled third scan signal GI is supplied to the third scan line SL3i, the third pixel transistor M3 is turned on. When the third pixel transistor M3 is turned on, the voltage of the first initialization power Vint1 applied to the third power line PL3 can be supplied to the first node N1.

[0123] During the second period P2, the enabled second scan signal GC is supplied to the second scan line SL2i, and thus the fourth pixel transistor M4 is turned on. When the fourth pixel transistor M4 is turned on, the first pixel transistor M1 may be diode-connected.

[0124] The enabled first scan signal GW is supplied to the first scan line SL1i during the write period P_W that overlaps with the second period P2 (the write period P_W included in the second period P2). When the enabled first scan signal GW is supplied to the first scan line SL1i, the second pixel transistor M2 is turned on. When the second pixel transistor M2 is turned on, a data signal can be supplied from the data line DLj to the second node N2. Since the first pixel transistor M1 maintains a diode connection through the turned-on fourth pixel transistor M4, the first node N1 can have a voltage that compensates for the threshold voltage of the first pixel transistor M1 in the data signal.

[0125] During the third period P3, the fourth scan signal GB is enabled and supplied to the fourth scan line SL4i. When the fourth scan signal GB is enabled and supplied to the fourth scan line SL4i, the fifth pixel transistor M5 and the eighth pixel transistor M8 are turned on. When the fifth pixel transistor M5 is turned on, the voltage of the second initialization power Vint2 can be supplied to the first electrode of the light-emitting element LD, and thus the light-emitting element LD can be initialized. When the eighth pixel transistor M8 is turned on, the voltage of the bias power Vbias is supplied to the second node N2. When the voltage of the bias power Vbias is supplied to the second node N2, the first pixel transistor M1 can be set to a conductive bias state.

[0126] In the fourth period P4, the emission control signal EM (or the emission control signal of the low level) is supplied to the emission control line ELk, and thus the sixth pixel transistor M6 and the seventh pixel transistor M7 are turned on. When the sixth pixel transistor M6 and the seventh pixel transistor M7 are turned on, a current flow path is formed from the first power line PL1 to the second power line PL2 via the sixth pixel transistor M6, the first pixel transistor M1, the seventh pixel transistor M7, and the light-emitting element LD. At this time, according to the operation of the first pixel transistor M1, a driving current corresponding to the voltage of the first node N1 can flow through the light-emitting element LD, and the light-emitting element LD can emit light with a brightness corresponding to the driving current.

[0127] Figure 5 The diagram shows the driving during the self-scan period. Figure 3 The method for driving the pixel Figure 3 The waveform diagram of the embodiment of the pixel signal). Figure 5 , also refer to Figure 1 、 Figure 3 and Figure 4 The self-scan period SSP is a period in which light is emitted while maintaining the voltage of the previously supplied data signal and an image is displayed again without switching to the next frame. In an embodiment, one frame may include one display scan period DSP and one or more self-scan periods SSP. The one or more self-scan periods SSP may be consecutively arranged or defined after the display scan period DSP. The self-scan period SSP may be included in the blanking period of the frame.

[0128] During the self-scanning period SSP, compared to the display scanning period DSP, the threshold voltage compensation operation and the data writing operation can be omitted, and the operation of applying a bias voltage to the first pixel transistor M1 (and the operation of initializing the light-emitting element LD) and the light-emitting operation can be performed. In an embodiment, the self-scanning period SSP can be set to a length that is the same as or similar to the length of the display scanning period DSP. In such an embodiment, the self-scanning period SSP can include a first period P1', a second period P2', a third period P3', and a fourth period P4'.

[0129] refer to Figure 3 and Figure 5 , the disabled emission control signal EM is supplied to the emission control line ELk in the first period P1' to the third period P3'. When the disabled emission control signal EM is supplied to the emission control line ELk, the sixth pixel transistor M6 and the seventh pixel transistor M7 are turned off, and thus the light emitting element LD is set to a non-emission state.

[0130] The enabled first scan signal GW, the enabled second scan signal GC, and the enabled third scan signal GI are not supplied during the first to third periods P1' to P3' (alternatively, the disabled scan signals GW, GC, and GI are supplied). Therefore, during the first to third periods P1' to P3', the second, third, and fourth pixel transistors M2, M3, and M4 are set to an off state.

[0131] The enabled fourth scan signal GB may be supplied to the fourth scan line SL4i in the third period P3 ′ When the enabled fourth scan signal GB is supplied to the fourth scan line SL4i, the fifth pixel transistor M5 and the eighth pixel transistor M8 may be turned on.

[0132] When the fifth pixel transistor M5 is turned on, the voltage of the second initialization power Vint2 can be supplied to the first electrode of the light emitting element LD, and thus the light emitting element LD can be initialized. When the eighth pixel transistor M8 is turned on, the voltage of the bias power Vbias is supplied to the second node N2. When the voltage of the bias power Vbias is supplied to the second node N2, the first pixel transistor M1 can be set to a conductive bias state.

[0133] Since one frame includes the display scanning period DSP and the self-scanning period SSP, the display device 100 according to the embodiment of the present disclosure described above may be driven at various driving frequencies (various frame frequencies).

[0134] Figure 6 and Figure 7 is a diagram illustrating an example of signals supplied in an active period and a blanking period. Figure 6 and Figure 7The scan signals GW, GC, GI, and GB shown in represent supply or non-supply in the display scan period DSP and the self-scan period SSP. The second scan signal GC and the third scan signal GI may be supplied from one scan driver and are thus shown as one signal.

[0135] refer to Figure 6 , also refer to Figure 1 During one frame (1Frame), one display scanning period (DSP) and one self-scanning period (SSP) may be included. In the display scanning period (DSP), an emission control signal (EM), an enabled first scanning signal (GW), an enabled second scanning signal (GC), an enabled third scanning signal (GI), and an enabled fourth scanning signal (GB) may be supplied.

[0136] In the self-scan period SSP, the emission control signal EM and the enabled fourth scan signal GB may be supplied. That is, the emission control signal EM and the enabled fourth scan signal GB may be supplied in both the display scan period DSP and the self-scan period SSP, and the remaining enabled scan signals GW, GC, and GI may be supplied only in the display scan period DSP.

[0137] In an embodiment, as the driving frequency of the display device 100 decreases (eg, low-frequency driving), the number of self-scan periods SSP included in one frame period 1Frame may be as follows: Figure 7 , and thus the number of times the emission control signal EM and the enabled fourth scan signal GB are supplied in one frame period may increase.

[0138] In such an embodiment, it may be desirable that the first scan signal GW, the second scan signal GC, and the third scan signal GI maintain a disabled state during the self-scan period SSP to allow the display device 100 to be stably driven.

[0139] Figure 8 It is an icon Figure 1 An embodiment of a scan driver is shown in FIG. Figure 8 Can be Figure 2 One of the first to fourth scan drivers 132 to 138 shown in FIG. Figure 8 , also refer to Figure 1 , in an embodiment, Figure 8 The stage circuits ST1 , ST2 , ST3 , . . . , and STn shown in may be included in the emission driver 150 .

[0140] refer to Figure 8The scan driver 130 according to an embodiment of the present disclosure may include stage circuits ST1, ST2, ST3, ..., and STn. Each of the stage circuits ST1 to STn may be connected to a corresponding one of the scan lines S1, S2, S3, ..., and Sn.

[0141] Stage circuits ST1 to STn may receive clock signals CLK1 and CLK2 from the timing controller 120. In an embodiment, for example, odd-numbered stage circuits ST1, ST3, ... may receive the second clock signal CLK2, and even-numbered stage circuits ST2, ..., and STn may receive the first clock signal CLK1.

[0142] The first-stage circuit ST1 receives a start signal FLM. The first-stage circuit ST1 can output a scan signal to the first scan line S1 in response to the second clock signal CLK2. Furthermore, the first-stage circuit ST1 can supply a carry signal CR1 to the next-stage circuit ST2 in response to the second clock signal CLK2. Here, the carry signal CR1 can be replaced by a scan signal supplied to the first scan line S1.

[0143] The second stage circuit ST2 may receive the carry signal CR1 and, in response to the first clock signal CLK1, output the carry signal CR2 to the next stage circuit ST3 while outputting the scan signal to the second scan line S2. The stage circuits ST1 to STn may sequentially output the carry signals CR1, CR2, CR3, ..., and CRn-1 while repeating the above-described operation, and sequentially output scan signals to the scan lines S1, S2, S3, ..., and Sn in response to the carry signals CR1, CR2, CR3, ..., and CRn-1.

[0144] In an embodiment, Figure 8 As shown in FIG, two clock signals CLK1 and CLK2 are supplied to the scan driver 130, but the embodiments of the present disclosure are not limited thereto. For example, the signals supplied to the scan driver 130 (e.g., clock signals or reset signals, etc.) may be set differently depending on the circuit configuration of the stage circuits ST1 to STn.

[0145] Figure 9A and Figure 9B It is an icon Figure 8 An embodiment of the stage circuit is shown in FIG. Figure 9A and Figure 9B Also refer to Figure 1 、 Figure 2 and Figure 3 , for convenience of description, an embodiment of a stage circuit included in the second scan driver 134 (and / or the third scan driver 136) outputting the second scan signal GC (and / or the third scan signal GI) is shown.

[0146] refer to Figure 9A , the stage circuit ST according to an embodiment of the present disclosure may include an input unit 200 , a driver 202 , a controller 204 , a first transistor M11 , and an output unit 206 .

[0147] The output unit 206 may control the voltage of the output terminal 214 in response to the voltage of the first node N1 and the voltage of the second node N2. Here, the voltage of the output terminal 214 may be supplied to the second scan line SL2 as the second scan signal GC. For example, when the high-level first voltage VGH is supplied to the output terminal 214, the enabled second scan signal GC may be supplied, and when the low-level second voltage VGL is supplied, the disabled second scan signal GC may be supplied.

[0148] The output unit 206 may include a third transistor M13, a fourth transistor M14, and a first capacitor C1. The third transistor M13 may be connected between the first power input terminal 215 and the output terminal 214. The gate electrode of the third transistor M13 may be connected to the first node N1. The third transistor M13 may control the electrical connection between the first power input terminal 215 and the output terminal 214, and may be turned on or off in response to the voltage of the first node N1. The first power input terminal 215 may receive a first voltage VGH. The first voltage VGH may be set to a high-level voltage.

[0149] The fourth transistor M14 may be connected between the output terminal 214 and the second power input terminal 216. The gate electrode of the fourth transistor M14 may be connected to the second node N2. The fourth transistor M14 may control the electrical connection between the second power input terminal 216 and the output terminal 214, and may be turned on or off in response to the voltage of the second node N2. The second power input terminal 216 may receive a second voltage VGL. The second voltage VGL may be set to a low-level voltage lower than the first voltage VGH.

[0150] The first capacitor C1 may be connected between the output terminal 214 and the second node N2. The first capacitor C1 may control the voltage of the second node N2 in response to the voltage of the output terminal 214. That is, the first capacitor C1 may be driven as a coupling capacitor.

[0151] The first transistor M11 may be connected between the second node N2 and the third node N3 (or the controller 204). The gate electrode of the first transistor M1 may be connected to the second power input terminal 216. The first transistor M1 may be set as a P-type transistor and thus may be set to an on state during a period (or driving period) in which the display device 100 is driven.

[0152] The first transistor M11 can be set to a conductive state and can electrically connect the second node N2 and the third node N3 to each other. When the first transistor M11 is set to a conductive state, the voltage of the third node N3 can have a voltage equal to or higher than the second voltage VGL, regardless of the voltage drop of the second node N2. In other words, the first transistor M11 can effectively prevent the voltage of the third node N3 from being reduced to a voltage equal to or lower than the second voltage VGL.

[0153] The controller 204 may be connected between the third node N3 (or the first transistor M11) and the input unit 200. The controller 204 may control the electrical connection between the input unit 200 and the second node N2. In an embodiment, the controller 204 may include a second transistor M12 (or a control transistor). The second transistor M12 may be positioned between the input unit 200 and the third node N3, and the gate electrode of the second transistor M12 may be connected to the control input terminal 213. The second transistor M12 may be turned on or off in response to a control signal CS supplied to the control input terminal 213.

[0154] The second transistor M12 may further include a second gate electrode. The second gate electrode may be connected to the control input terminal 213 (e.g., a source sink transistor). In such an embodiment where the second gate electrode is connected to the control input terminal 213, the on-state current of the second transistor M12 may be increased.

[0155] The input unit 200 may be connected between the first input terminal 211 and the controller 204. The input unit 200 may control electrical connection between the first input terminal 211 and the controller 204. In an embodiment, the input unit 200 may include a fifth transistor M15.

[0156] The fifth transistor M15 can be connected between the first input terminal 211 and the controller 204, and the gate electrode of the fifth transistor M15 can be connected to the second input terminal 212. The first input terminal 211 can receive a carry signal CR or a start signal FLM of the previous stage circuit. The second input terminal 212 can receive a clock signal CLK. The fifth transistor M15 can supply the carry signal CR or the start signal FLM to the controller 204 and the driver 202 in response to the clock signal CLK input to the second input terminal 212.

[0157] The driver 202 may control the voltage of the first node N1 in response to the carry signal CR or the start signal FLM of the input unit 200. The driver 202 may be positioned between the input unit 200 and the first node N1. Figure 9BAs shown in FIG, the driver 202 may also be positioned or connected between the controller 204 and the input unit 200. In an embodiment, the driver 202 may include an inverter, but the present disclosure is not limited thereto.

[0158] The stage circuit ST according to an embodiment of the present disclosure may include a first transistor M11 and a controller 204, and may further include various currently known circuits or be configured by various currently known circuits. In an embodiment, for example, the stage circuit ST may include a first transistor M11, a controller 204, an input unit 200, a driver 202, and an output unit 206, and may further include various currently known circuits or be configured by various currently known circuits.

[0159] Figure 10 It is a graphic and Figure 9A and Figure 9B The driving method (or the method for driving the embodiment of the stage circuit shown in Figure 9A and Figure 9B ) is a diagram of a waveform diagram corresponding to the signals of the embodiment of the stage circuit shown in FIG. Figure 11 is a diagram illustrating the voltage of the second node when the controller is not included in the stage circuit.

[0160] Figure 10 The scan signals GW, GC, GI, and GB shown in represent supply or non-supply in the display scan period DSP and the self-scan period SSP. The second scan signal GC and the third scan signal GI may be supplied from one scan driver and are thus shown as one signal.

[0161] refer to Figures 9A to 10 , the control signal CS may be set to a high level voltage during the display scanning period DSP (or effective period), and may be set to a low level voltage during the self scanning period SSP (or blanking period).

[0162] During the display scanning period DSP in which the high-level control signal CS is supplied, the second transistor M12 may be set to a conductive state, and thus the input unit 200 and the third node N3 may be electrically connected to each other. In this case, during the display scanning period DSP, the stage circuit ST may be normally driven.

[0163] During the self-scan period SSP in which the low-level control signal CS is supplied, the second transistor M12 can be set to a cut-off state, and thus the input unit 200 and the third node N3 can be electrically isolated or disconnected from each other. In this case, the current leaking from the second node N2 to the input unit 200 can be minimized, and thus the driving stability can be ensured.

[0164] As described above, the stage circuit ST may be included in the second scan driver 134 (and / or the third scan driver 136) that outputs the second scan signal GC (and / or the third scan signal GI). The second scan driver 134 sequentially outputs the enabled scan signal GC during the display scan period DSP, and supplies the disabled second scan signal GC (i.e., a low voltage) to the output terminal 214 while maintaining the voltage of the second node N2 during the self-scan period SSP.

[0165] When the high-level control signal CS is supplied during the display scan period DSP, the second transistor M12 may be set to a turn-on state, and the second scan driver 134 may normally output the enabled second scan signal GC.

[0166] When the low-level control signal CS is supplied during the self-scan period SSP, the second transistor M12 may be set to an off state and leakage current of the second node N2 may be minimized. In this case, the second scan driver 134 may stably output the disabled second scan signal GC.

[0167] In such an embodiment, when the supply of the enabled second scan signal GC is stopped, the voltage of the second node N2 may be set to approximately the second voltage VGL. At this time, when the fourth transistor M14 is turned on, the second voltage VGL may be output to the output terminal 214. Here, the second voltage VGL may be supplied to the second scan line SL2 as the disabled second scan signal GC.

[0168] In such an embodiment, when the second voltage VGL is supplied to the output terminal 214, the voltage of the second node N2 may be reduced to about the fourth voltage 2VGL due to the coupling of the first capacitor C1. Figure 11 As shown in . The fourth voltage 2VGL may be set to a voltage as low as about twice the second voltage VGL. When the second node N2 is set to the fourth voltage 2VGL, the fourth transistor M14 may stably maintain a turned-on state.

[0169] For example, when the controller 204 is not included in the stage circuit ST, the voltage of the second node N2 may increase to the second voltage VGL over time due to leakage current. When the voltage of the second node N2 increases to the second voltage VGL, the fourth transistor M14 may be turned off, and thus driving reliability may be reduced.

[0170] In an embodiment of the present disclosure, the controller 204 is included in the stage circuit ST so that leakage current flowing from the second node N2 to the input unit 200 can be effectively blocked, and thus the voltage of the second node N2 can be maintained at the fourth voltage 2VGL during the self-scan period SSP.

[0171] Figure 12A and Figure 12B is a diagram illustrating an example of a voltage of a control signal.

[0172] refer to Figure 12A , also refer to Figure 9A , a high-level voltage of the control signal CS may be set to the first voltage VGH, and a low-level voltage of the control signal CS may be set to the third voltage VGL2. The third voltage VGL2 may be set to a voltage lower than the second voltage VGL.

[0173] When the low level voltage of the control signal CS is set to the third voltage VGL2, the second transistor M12 can be stably turned off regardless of the threshold voltage deviation of the second transistor M12. In addition, the low level voltage of the control signal CS can be set to the second voltage VGL.

[0174] Figure 13 It is an icon Figure 1 FIG. 1 is a diagram of an embodiment of a scan driver. Figure 13 In the description of the above reference, the Figure 8 Any repeated detailed description of elements that are the same or similar to those described.

[0175] refer to Figure 13 , also refer to Figure 1 and Figure 6 , the control signal CS may be supplied to the stage circuits ST1 to STn via the control line CSL. The control line CSL may be commonly connected to the stage circuits ST1 to STn. The control line CSL may supply the control signal CS input from the timing controller 120 to the stage circuits ST1 to STn.

[0176] In such an embodiment, as described above, the control signal CS may be set to a high level voltage during the display scanning period DSP and may be set to a low level voltage during the self scanning period SSP.

[0177] Figure 14 It is an icon Figure 8 An embodiment of the stage circuit is shown in FIG. Figure 14 In the description of the above reference, the Figure 9A Any repeated detailed description of elements that are the same or similar to those described.

[0178] Please refer to Figure 14 , also refer to Figure 2 and Figure 8 In an embodiment of the present disclosure, the control input terminal 213 (or the gate electrode of the second transistor M12 ) included in the stage circuit ST may be connected to the first node N1 .

[0179] During a period in which an enabled scan signal (e.g., the second scan signal GC) is supplied, the voltage of the first node N1 may be set to a low level. When the voltage of the first node N1 is set to a low level voltage, the first voltage VGH may be supplied to the output terminal 214, and thus the enabled scan signal may be supplied to the output terminal 214.

[0180] In such an embodiment, the voltage of the first node N1 can be maintained at a low voltage until a low-level voltage is supplied to the second node N2, and the voltage of the first node N1 can be set to a high-level voltage during another period. In this case, the second transistor M12 can be turned off after the low-level voltage is supplied to the second node N2.

[0181] That is, in such an embodiment in which the gate electrode of the second transistor M12 is connected to the first node N1, the second transistor M12 may be turned on during a period in which an enabled scan signal is supplied to the output terminal 214, and may be turned off during a period in which a disabled scan signal is supplied to the output terminal 214. In this case, the leakage current of the second node N2 may be stably blocked without supplying a separate control signal CS.

[0182] In such an embodiment, when the gate electrode of the second transistor M12 is connected to the first node N1, the second transistor M12 included in each of the stage circuits ST1 to STn can be sequentially turned on and off. In this case, the stage circuit ST can be applied to each of the first scan driver 132, the second scan driver 134, the third scan driver 136, and the fourth scan driver 138.

[0183] Figure 15 is a diagram illustrating a voltage of a second node included in a stage circuit. Figure 15 The voltage of the second node N2 may be illustrated in a case where the first transistor M11 and the second transistor M12 are set as different types of transistors (eg, a case where the first transistor M11 is a P-type transistor and the second transistor M12 is an N-type transistor).

[0184] refer to Figure 9A and Figure 15 , after the fourth transistor M14 is turned off, the first voltage VGH may be supplied to the output terminal 214. That is, after the first voltage VGH is supplied to the second node N2, the first voltage VGH may be supplied to the output terminal 214. When the first voltage VGH is supplied to the output terminal 214, due to coupling of the first capacitor C1, the second node N2 may be boosted to a fifth voltage 2VGH, which is approximately twice the first voltage VGH.

[0185] Here, in the case where the second transistor M12 is not included in the stage circuit ST, the fifth voltage 2VGH may gradually decrease to the first voltage VGH. In an embodiment of the present disclosure, the second transistor M12 is included in the stage circuit ST so that the voltage of the second node N2 can maintain the fifth voltage 2VGH.

[0186] In such an embodiment, the second node N2 is set to the fifth voltage 2VGH, so that the fourth transistor M14 can be stably set to the off state regardless of the threshold voltage of the fourth transistor M14, and thus the driving reliability can be ensured. In addition, since the voltage of the second node N2 is boosted by the first capacitor C1, the voltage of the carry signal CR or the start signal FLM input to the first input terminal 211 can be reduced, and thus power consumption can be reduced.

[0187] In such an embodiment, the second voltage VGL is supplied to the output terminal 214, so that the voltage of the second node N2 can be reduced to about the fourth voltage 2VGL due to the coupling of the first capacitor C1. The fourth voltage 2VGL can be set to a voltage as low as about twice the second voltage VGL. In such an embodiment in which the second node N2 is set to the fourth voltage 2VGL, the fourth transistor M14 can stably maintain an on state.

[0188] 16A to 16C is a diagram illustrating an embodiment of transistors included in a controller.

[0189] refer to 16A to 16C , also refer to Figure 9A 、 Figure 12A 、 Figure 12B and Figure 14 In other embodiments, unlike the first transistor M11 configured as a P-type transistor, the second transistor M12a, M12b, or M12c included in the controller 204 may be configured as an N-type transistor. Figure 16A As shown in , the second transistor M12a can be set as a normal three-terminal transistor.

[0190] In an embodiment, Figure 16B and Figure 16C As shown in FIG, the second transistor M12b or M12c may include a second gate electrode. The second gate electrode may receive a direct current (DC) voltage or an alternating current (AC) voltage.

[0191] In an embodiment in which a DC voltage is supplied to the second gate electrode of the second transistor M12b, while controlling the threshold voltage of the second transistor M12b, the on-state current can be increased compared to a three-terminal transistor. Here, the DC voltage is set to one of the voltages supplied to the stage circuit ST. For example, the DC voltage can be set to one of the first voltage VGH, the second voltage VGL, and the third voltage VGL2.

[0192] In an embodiment in which an AC voltage is supplied to the second gate electrode of the second transistor M12c, while controlling the threshold voltage of the second transistor M12c, an on-current may be increased compared to a case in which a DC voltage is supplied.

[0193] 17A to 17C is a diagram illustrating an embodiment of transistors included in a controller.

[0194] refer to 17A to 17C In other embodiments, the second transistor M12d, M12e, or M12f included in the controller 204 may be set to a P-type transistor that is the same as the first transistor M11.

[0195] In an embodiment, the second transistor M12d may be formed as follows Figure 17A In an embodiment, the second transistor M12e may include a three-terminal transistor as shown in FIG. Figure 17B , and the second gate electrode of the second transistor M12e may be connected to the control input terminal 213. In an embodiment, the second transistor M12f may include a Figure 17C , and the second gate electrode of the second transistor M12f may receive a DC voltage or an AC voltage.

[0196] In addition, although not separately shown, the second transistor M12 d , M12 e , or M12 f included in the controller 204 may be set as an N-type transistor in full conformity with the first transistor M11 .

[0197] Figure 18A and Figure 18B is a diagram illustrating a stage circuit according to an embodiment of the present disclosure. Figure 18A and Figure 18B In the description of Figure 9A and Figure 9B The elements are the same as those of the embodiment, and any repeated detailed description thereof will be omitted.

[0198] refer to Figure 18A and Figure 18BIn an embodiment, the first transistor M11a may be set as an N-type transistor. In this case, the gate electrode of the first transistor M11a may be connected to the first power input terminal 215, and the first transistor M11a may be kept in an on state by the first voltage VGH during the driving period. In such an embodiment, the second transistor M12a included in the controller 204 may be set as a P-type transistor, and the second gate electrode of the second transistor M12a may be connected to the control input terminal 213. However, the present disclosure is not limited thereto, and as described in reference 16A to 17C As described, various types of transistors may be included in controller 204 .

[0199] Figure 19 is a diagram illustrating a stage circuit according to an embodiment of the present disclosure. Figure 19 In the description of Figure 9B The elements are the same as those of the embodiment, and any repeated detailed description thereof will be omitted.

[0200] refer to Figure 19 , the controller 204a of the stage circuit ST according to an embodiment of the present disclosure can be positioned or connected between the driver 202 and the input unit 200. The driver 202 may include various types of currently known circuits. In an embodiment, for example, the driver 202 may include an inverter. Even if the controller 204a is positioned between the driver 202 and the input unit 200, the controller 204a may be turned off during the self-scan period SSP in response to the control signal CS, and thus leakage current from the second node N2 (or the third node N3) may be prevented.

[0201] In such an embodiment, the control input terminal 213 can be connected to the first node N1, and thus can effectively prevent leakage current from the second node N2. 16A to 17C As described, various types of transistors may be included in the controller 204a.

[0202] Figure 20 is a diagram illustrating a stage circuit according to an embodiment of the present disclosure. Figure 20 In the description of Figure 9A The elements are the same as those of the embodiment, and any repeated detailed description thereof will be omitted.

[0203] refer to Figure 20 , the controller 204b of the stage circuit ST according to an embodiment of the present disclosure may be positioned or connected between the first transistor M11 (eg, the third node N3) and the second node N2. In this case, the controller 204b may be positioned or connected between the first transistor M11 (eg, the third node N3) and the second node N2. Figure 9A The controller 204 has the same function as referenced. 16A to 17CAs described, various types of transistors may be included in the controller 204b.

[0204] Figure 21 and Figure 22 is a diagram illustrating a stage circuit according to an embodiment of the present disclosure. In the present disclosure, the stage circuit ST may include various types of currently known circuits to include the first transistor M11 or M11a and the controller 204, 204a, or 204b as described above. Figure 21 and Figure 22 An embodiment of a stage circuit ST including a first transistor M11 and a controller 204 is illustrated.

[0205] refer to Figure 21 , the driver 202 a of the stage circuit ST according to an embodiment of the present disclosure may include a sixth transistor M16 , a seventh transistor M17 , and an eighth transistor M18 .

[0206] The sixth transistor M16 may be connected between the first power input terminal 215 and the first node N1. In addition, a gate electrode of the sixth transistor M16 may be connected to the third node N3.

[0207] The seventh transistor M17 may be connected between the first node N1 and the second power input terminal 216. In addition, a gate electrode of the seventh transistor M17 may be connected to the second node N2.

[0208] The eighth transistor M18 may be connected between the output terminal 214 and the second power input terminal 216. Furthermore, the gate electrode of the eighth transistor M18 may be connected to the first node N1. Each of the seventh transistor M17 and the eighth transistor M18 may further include a second gate electrode, and the second gate electrode of each of the seventh transistor M17 and the eighth transistor M18 may be connected to the third power input terminal 217 supplied with the third voltage VGL2. Furthermore, the sixth transistor M16 may be configured as a P-type transistor, and the seventh transistor M17 and the eighth transistor M18 may be configured as N-type transistors.

[0209] The second transistor M12 may be set to a turned-on state in response to a high-level control signal CS during the display scanning period DSP. The first transistor M11 may maintain a turned-on state during a driving period including the display scanning period DSP and the self-scanning period SSP.

[0210] During operation, the carry signal CR or the start signal FLM may be input to the first input terminal 211, and the clock signal CLK may be input to the second input terminal 212. In this case, the fifth transistor M15 may be turned on and thus may supply a high-level voltage (i.e., the carry signal CR or the start signal FLM) to the third node N3 and the second node N2.

[0211] When a high-level voltage is supplied to the third node N3, the sixth transistor M16 is turned off. When a high-level voltage is supplied to the second node N2, the fourth transistor M14 is turned off and the seventh transistor M17 is turned on. When the seventh transistor M17 is turned on, the second voltage VGL can be supplied to the first node N1, and thus the third transistor M13 can be turned on. In this case, the first voltage VGH (or the enabled scan signal) can be supplied to the output terminal 214.

[0212] After the first voltage VGH is supplied to the output terminal 214, the carry signal CR or the start signal FLM is stopped from being supplied to the first input terminal 211. In this case, the first input terminal 211 is set to a low level voltage. When the clock signal CLK is input to the second input terminal 212, a low level voltage may be supplied to the third node N3 and the second node N2.

[0213] When a low-level voltage is supplied to the third node N3, the sixth transistor M16 is turned on, and thus the first voltage VGH is supplied to the first node N1. When the first voltage VGH is supplied to the first node N1, the third transistor M13 is turned off, and the eighth transistor M18 is turned on. When the eighth transistor M18 is turned on, the second voltage VGL is supplied to the output terminal 214. When a low-level voltage is supplied to the second node N2, the fourth transistor M14 is turned on, and the seventh transistor M17 is turned off. When the fourth transistor M14 is turned on, the second voltage VGL is supplied to the output terminal 214.

[0214] refer to Figure 22 , also refer to Figure 6 Another embodiment of the stage circuit ST may include an input unit 200 a , a driver 202 b , a controller 204 , an output unit (or a first output unit) 206 , and a second output unit 208 .

[0215] The input unit 200a can be configured as a transmission gate. In an embodiment, for example, the input unit 200a may include a first fifth transistor M15a and a second fifth transistor M15b connected in parallel to each other between the first input terminal 211 and the controller 204 (or the fourth node N4). The first fifth transistor M15a may be set to a P-type, and the second fifth transistor M15b may be set to an N-type.

[0216] The first fifth transistor M15a can be turned on or off in response to the first clock signal CLK1 input from the first second input terminal 212a. The second fifth transistor M15b can be turned on or off in response to the second clock signal CLK2 input from the second second input terminal 212b. The first fifth transistor M15a and the second fifth transistor M15b can be turned on or off simultaneously.

[0217] The second output unit 208 may include a 21st transistor M21 and a 22nd transistor M22 connected in series between the first power input terminal 215 and the second power input terminal 216. The 21st transistor M21 may be configured as a P-type transistor, and a gate electrode of the 21st transistor M21 may be connected to the first node N1. The 22nd transistor M22 may be configured as an N-type transistor, and a gate electrode of the 22nd transistor M22 may be connected to the first node N1. A common terminal of the 21st transistor M21 and the 22nd transistor M22 may be connected to the second output terminal 218. The second output terminal 218 may output a carry signal.

[0218] The driver 202b may include a third transistor M13, a twenty-fourth transistor M24, a twenty-fifth transistor M25, a twenty-sixth transistor M26, a twenty-seventh transistor M27, and a second capacitor C2b. Here, the third transistor M13 may be included in the output unit 206 and may be a transistor that supplies the first voltage VGH to the output terminal 214. That is, the third transistor M13 may be shared by the output unit 206 and the driver 202b.

[0219] The third transistor M13 and the twenty-fourth transistor M24 may be connected in series between the first power input terminal 215 and the second power input terminal 216. Furthermore, the gate electrodes of the third transistor M13 and the twenty-fourth transistor M24 may be connected to the first node N1. The third transistor M13 may be configured as a P-type transistor, and the twenty-fourth transistor M24 may be configured as an N-type transistor. In this case, the third transistor M13 and the twenty-fourth transistor M24 may operate or be driven as inverters.

[0220] The 25th transistor M25 and the 26th transistor M26 may be connected in series with each other between the first power input terminal 215 and the second power input terminal 216. Furthermore, the gate electrode of the 25th transistor M25 and the gate electrode of the 26th transistor M26 may be connected to the fourth node N4. The 25th transistor M25 may be configured as a P-type transistor, and the 26th transistor M26 may be configured as an N-type transistor. In this case, the 25th transistor M25 and the 26th transistor M26 may be operated or driven as inverters.

[0221] The twenty-seventh transistor M27 can be connected between the first power input terminal 215 and the fourth node N4. In addition, the gate electrode of the twenty-seventh transistor M27 can be connected to the third input terminal 219. A cutoff control signal or the like can be input to the third input terminal 219, and can be used to maintain the voltage of the output terminal 214 and the voltage of the second output terminal 218 at the first voltage VGH. Each of the twenty-fourth transistor M24 and the twenty-sixth transistor M26 can also include a second gate electrode, and the second gate electrode of each of the twenty-fourth transistor M24 and the second sixteenth transistor M26 can be connected to the third power input terminal 217 to which the third voltage VGL2 is supplied.

[0222] The second capacitor C2b may be connected between the first power input terminal 215 and the fourth node N4. The second capacitor C2b may store a voltage of the fourth node N4.

[0223] The second transistor M12 may be set to a turned-on state in response to a high-level control signal CS during the display scanning period DSP. The first transistor M11 may maintain a turned-on state during a driving period including the display scanning period DSP and the self-scanning period SSP.

[0224] During operation, the carry signal CR or the start signal FLM is input to the first input terminal 211, and the clock signals CLK1 and CLK2 can be input to the second input terminals 212a and 212b, respectively. Then, the fifth transistors M15a and M15b can be set to a conductive state, and thus a high-level voltage (i.e., the carry signal CR or the start signal FLM) can be supplied to the fourth node N4.

[0225] When the high-level voltage is supplied to the fourth node N4, the twenty-sixth transistor M26 is turned on, and thus the second voltage VGL is supplied to the first node N1. When the second voltage VGL is supplied to the first node N1, the third transistor M13 and the twenty-first transistor M21 are turned on. When the third transistor M13 is turned on, the first voltage VGH (or the enabled scan signal) is supplied to the output terminal 214. When the twenty-first transistor M21 is turned on, the first voltage VGH (or the carry signal) is supplied to the second output terminal 218.

[0226] After the first voltage VGH is supplied to the output terminal 214, the carry signal CR or the start signal FLM is stopped from being supplied to the first input terminal 211, and in this case, the first input terminal 211 is set to a low level voltage. When the clock signals CLK1 and CLK2 are input to the second input terminals 212a and 212b, respectively, a low level voltage may be supplied to the fourth node N4.

[0227] When the low-level voltage is supplied to the fourth node N4, the twenty-fifth transistor M25 is turned on, and thus the first voltage VGH is supplied to the first node N1. When the first voltage VGH is supplied to the first node N1, the twenty-fourth transistor M24 and the twenty-second transistor M22 are turned on. When the twenty-fourth transistor M24 is turned on, the second voltage VGL is supplied to the output terminal 214. When the twenty-second transistor M22 is turned on, the second voltage VGL is supplied to the second output terminal 218.

[0228] In addition, when the low-level voltage is supplied to the fourth node N4 , the fourth transistor M14 may be turned on, and thus the second voltage VGL may be supplied to the output terminal 214 .

[0229] Figure 23 is a schematic block diagram illustrating an electronic device including a display device according to an embodiment.

[0230] Figure 24 It is an icon Figure 23 A schematic diagram of an example in which the electronic device is a smart phone. Figure 25 It is an icon Figure 23 Schematic diagram of an example in which the electronic device is a tablet computer.

[0231] refer to Figures 23 to 25 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be Figure 1 The electronic device 1000 may also include various ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, or other systems. Figure 24 As shown in FIG, the electronic device 1000 may be a smart phone. Figure 25 As shown in FIG, the electronic device 1000 may be a tablet computer. However, the foregoing examples are illustrative, and the electronic device 1000 is not necessarily limited to the foregoing examples. For example, the electronic device 1000 may be a cellular phone, a video phone, a smart tablet, a smartwatch, a navigation device for a vehicle, a computer monitor, a laptop computer, or a head-mounted display device.

[0232] The processor 1010 may perform specific calculations or tasks. In embodiments, the processor 1010 may include at least one of a central processing unit, an application processor, a graphics processing unit, a communication processor, an image signal processor, and a controller. The processor 1010 may be connected to other components via an address bus, a control bus, and a data bus. In embodiments, the processor 1010 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. In embodiments, the processor 1010 may provide input image data to the display device 1060. Thus, the display device 1060 may display an image based on the input image data provided from the processor 1010.

[0233] The memory device 1020 may store data required to perform operations of the electronic device 1000. The memory device 1020 may be used as a working memory and / or a buffer memory for the processor 1010. For example, the memory device 1020 may include one or more volatile memory devices such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device.

[0234] The storage device 1030 may store data in response to a control signal or data from the processor 1010. The storage device 1030 may include one or more non-volatile memory devices to retain data even when the electronic device 1000 is powered off. In some embodiments, the storage device 1030 may include a solid-state drive (SSD), a hard disk drive (HDD), a CD-ROM, or the like.

[0235] The I / O device 1040 may include input devices such as a keyboard, a keypad, a touchpad, a touch screen, and a mouse, and output devices such as a speaker and a printer. In an embodiment, the display device 1060 may be integrated with the I / O device 1040.

[0236] The power supply 1050 may supply power required to perform operations of the electronic device 1000. For example, the power supply 1050 may include a power management integrated circuit (PMIC). In an embodiment, the power supply 1050 may supply power to the display device 1060.

[0237] The display device 1060 may display images in response to image data signals and / or control signals from the processor 1010. The display device 1060 may be connected to other components through a bus or other communication link.

[0238] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0239] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A stage circuit, wherein: The stage circuit comprises: an output unit that supplies a scan signal to an output terminal in response to a voltage of the first node and a voltage of the second node; an input unit that outputs a carry signal or a start signal input to the first input terminal in response to a clock signal; a first transistor connected between the input unit and the second node and set to an on state during a driving period; and A controller is connected between the input unit and the first transistor or between the first transistor and the second node, wherein the controller controls the electrical connection between the input unit and the second node.

2. The stage circuit according to claim 1, wherein: The controller is connected between the input unit and the first transistor; or The controller is connected between the first transistor and the second node.

3. The stage circuit according to claim 1, wherein: The controller includes a second transistor; and The second transistor includes a gate electrode connected to a control input terminal, and the control input terminal receives a control signal.

4. The stage circuit according to claim 3, wherein: The driving period of one frame includes a display scanning period for receiving a data signal and a self-scanning period for emitting light while maintaining the data signal, and The control signal is set to a voltage level that turns on the second transistor during the display scanning period, and is set to a voltage level that turns off the second transistor during the self scanning period.

5. The stage circuit according to claim 3, wherein: The second transistor further includes a second gate electrode, and the second gate electrode is electrically connected to the gate electrode of the second transistor.

6. The stage circuit according to claim 3, wherein: The second transistor further includes a second gate electrode, and the second gate electrode receives a DC voltage.

7. The stage circuit according to claim 3, wherein: The second transistor further includes a second gate electrode, and the second gate electrode receives an AC voltage.

8. The stage circuit according to claim 3, wherein: The first transistor and the second transistor are different types of transistors.

9. The stage circuit according to claim 1, wherein: The stage circuit further includes: a driver, controlling the voltage of the first node, The controller is connected between the driver and the first transistor.

10. The stage circuit according to claim 1, wherein: The stage circuit further includes: a driver, controlling the voltage of the first node, Wherein, the controller is connected between the input unit and the driver.

Images