Display circuit driven by PWM and PAM in hybrid mode
By introducing PAM components into PWM driven pixels and connecting the row power line to VDD, and using GOA controlled transistors to scan row by row, the problems of inaccurate grayscale and high-frequency noise in LED driving are solved, and efficient grayscale display is achieved.
Patent Information
- Application Number
- CN202510827222.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-19
- Publication Date
- 2025-09-26
AI Technical Summary
In existing LED driving technologies, analog dimming has problems such as low efficiency, severe color deviation, and narrow dimming range. Although digital dimming is highly efficient, it has inaccurate grayscale and may generate high-frequency noise.
The PAM component is introduced into the PWM driven pixel, and VDD is connected through the row power line. The transistor controlled by GOA is used to scroll scan row by row to achieve different VDD values in different subframes. The time and amplitude adjustment are combined to fit the gamma2.2 curve.
Accurate grayscale display is achieved with a smaller number of bits, which reduces the operating frequency and the amount of memory and reduces the loss of luminous time.
Smart Images
Figure CN120708532A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a display pixel circuit, in particular to a driving circuit for OLED and LED, belonging to the field of display technology. Technical Background
[0002] Among LED driver technologies, phase-adjusted dimming (PAM) is one approach, controlling brightness by adjusting the DC current. However, this method suffers from low efficiency, severe color shift, and a narrow dimming range.
[0003] Digital dimming (PWM) drive is one of the solutions. Although it has advantages such as high dimming accuracy and high efficiency, it also has some obvious disadvantages.
[0004] If the bit count is too low, the gamma2.2 curve for grayscales 0 to 255 in a PWM drive is not smooth, resulting in some grayscale inaccuracies. To overcome this shortcoming, a 15-bit or even 20-bit gamma curve is required to approximate the 2.2 curve. This results in fast switching operations in the PWM drive, generating high-frequency noise in the circuit that may interfere with surrounding components. Summary of the Invention
[0005] The present invention adds a PAM component to PWM-driven pixels, achieving a gamma 2.2 curve covering grayscales from 0 to 255 using a relatively small number of bits. Furthermore, by routing the VDD in the pixels row by row, the VDDs between rows are not directly connected. Instead, the row power lines are connected to a peripheral power supply via transistors controlled by GOAs. The GOAs are turned on for row-by-row rolling scanning, and the row power lines are connected to the peripheral power supply row by row. The varying values of the peripheral power supply allow the coexistence of multiple VDD values in the AA region, meaning that some AA rows emit light in the a subframe, while others in the b subframe. This allows for adjustable light amplitude without sacrificing light duration.
[0006] like Figure 1 Pixel block diagram. 0 / 1 is written to memory via the data line under the control of the row scan line. The memory can be either static or dynamic. The memory output is connected to the gate of the R transistor to control its on / off. The R transistor can be a P transistor, an N transistor, or a transmission gate. Typically, a bit of 1 indicates active light emission, while a bit of 0 indicates inactive light emission. Therefore, when the R transistor is a P transistor, there is a reverse direction.
[0007] like Figure 2Em controls the E-tube's on / off state, determining its duration. The duration weights vary in each subframe. For example, using three memories, Em1's duration in the first subframe is t, Em2's duration in the first subframe is 2t, and Em3's duration in the first subframe is 4t. In the second subframe, Em1's duration is 8t, Em2's duration in the second subframe is 16t, and Em3's duration in the second subframe is 32t. Similarly, the duration of Em3 in the nth subframe is 2^k*t. h is the amplitude. The E-tube can be a P-type transistor, an N-type transistor, or a transmission gate.
[0008] The number of bits is k, the number of memories in a pixel is m, and the number of subframes is n, k=m*n.
[0009] like Figure 3 、 Figure 4 、 Figure 5 The VDD power line has different values in different subframes. For example, the VDD value of the first subframe is VDD1, the VDD value of the second subframe is VDD2, and the VDD value of the nth subframe is VDDn.
[0010] like Figure 6 Grayscale brightness is controlled by a combination of time and amplitude, with the amplitude adjusted by VDD (h1, h2, hn). Even with a small number of bits (k), amplitude adjustment can still be used to match the gamma 2.2 curve.
[0011] like Figure 7 、 Figure 8 、 Figure 9 The VDD values of different branches in a pixel within the same subframe can also be set differently. Take the three reservoirs in the pixel as an example. For example, in the first subframe, the VDD value of the first branch is VDD1a, the VDD value of the second branch is VDD1b, and the VDD value of the third branch is VDD1c; in the second subframe, the VDD value of the first branch is VDD2d, the VDD value of the second branch is VDD2e, and the VDD value of the third branch is VDD2f; in the nth subframe, the VDD value of the first branch is VDDnx, the VDD value of the second branch is VDDny, and the VDD value of the third branch is VDDnz.
[0012] like Figure 10 Grayscale brightness is controlled by a combination of time and amplitude. The amplitude is adjusted by the VDD level (h1a, h1b, hnz), and the VDD levels of different branches within the same frame can be adjusted. Even with a small number of bits, k, the amplitude can be adjusted to match the gamma 2.2 curve.
[0013] like Figure 11The luminous time of two consecutive subframes overlaps, that is, the VDD power supply of the consecutive subframes overlaps. When VDD is set to different values between different subframes, VDD is wired according to the plane (there is a direct connection between rows), which will cause erroneous display.
[0014] like Figure 12 To overcome this problem, some subframes can be set to global display. For example, the second subframe can be set to global display. This can avoid the VDD time overlap between the first and second subframes. Similarly, the VDD time overlap between the second and third subframes can be avoided. Of course, all subframes can be set to global display.
[0015] like Figure 13 , VDD uses row power supply routing. Row VDD is not directly connected between rows. Instead, row VDD is connected to the peripheral power supply via transistors around the AA: the first subframe is connected to VDD1, the second subframe is connected to VDD2, and the Nth subframe is connected to VDDn. Under the control of the GOA, the transistors are turned on row by row to connect the VDD of the display area to VDD1, VDD2, and VDDn row by row. This allows different VDD values between different subframes to coexist without affecting each other within the AA area. The VDD values of pixels in different subframes and rows can be different. If the GOA controls the switching of multiple rows at once, multiple rows can be connected at once.
[0016] like Figure 14 Taking the first and second subframes as examples, this achieves that the VDD of some rows in the AA area is VDD1, emitting light with the characteristics of the first subframe; while the VDD of some rows is VDD2, emitting light with the characteristics of the second subframe. In other words, there is no loss of light-emitting time.
[0017] like Figure 15 Each register-controlled light-emitting branch uses independent row power supply routing for its VDD. The row VDD is connected to an external power supply via transistors around the AA region: in the first subframe, the row VDD of branch 1 connects to VDD1a, the row VDD of branch 2 connects to VDD1b, the row VDD of branch 3 connects to VDD1c, and so on. In the second subframe, the row VDD of branch 1 connects to VDD2d, the row VDD of branch 2 connects to VDD2e, the row VDD of branch 3 connects to VDD2f, and so on. Under the control of the GOA, the transistors are turned on row by row, ensuring that within the AA region, the VDD is connected to VDD1a, VDD1b, VDD1c, VDD2d, VDD2e, VDD2f, and so on. The VDD values of pixels in different subframes, rows, and branches can vary. If the GOA controls the switching of multiple rows at once, multiple rows can be connected at once.
[0018] like Figure 16Taking the first and second subframes as examples, and the three memory-controlled light-emitting branches in a pixel, this achieves that the VDDs of some rows in the AA area are VDD1a, VDD1b, and VDD1c, emitting light according to the first subframe characteristics; while the VDDs of some rows are VDD2d, VDD2e, and VDD2f, emitting light according to the second subframe characteristics. This means that there is no loss of light-emitting time.
[0019] Of course, the VDDs of several branches in a pixel may also share a row VDD to reduce the number of peripheral power supplies and achieve a balance between the number of row power supplies and the number of peripheral power supplies.
[0020] The abbreviations of the present invention are described as follows: PAM drive: analog amplitude adjustment PWM drive: digitally adjustable time AA area: the area where the light is displayed Vdd: the power supply for luminous energy in pixels, Vss: cathode power supply of the light-emitting device, Vdata: data voltage, Vgs: gate-source voltage of the transistor, Vds: source-drain voltage of the transistor, Vgs-Vth: overdrive voltage of transistor, Vth is the transistor threshold voltage, U\Cox\W\L: Transistor mobility, gate oxide capacitance, width, length, N-1\N: row scan signal, GOA1, GOA2,,, (gate driver on array) output, GOA is well known in the industry Gnx: GOA (gate driver on array) output, representing the xth row of the nth subframe Em: Row light switch signal, output by EGOA (gate driver on array), GOA is well known in the industry S: row scan signal, output by SGOA (gate driver on array), GOA is well known in the industry BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 . Pixel structure Figure 2 . The weight of the luminous time of each branch in each subframe is different Figure 3 . The VDD power supply of the first subframe is VDD1 Figure 4 . The VDD power supply of the second subframe is VDD2 Figure 5. The VDD power supply of the nth subframe is VDDn Figure 6 . Take 3 memories as an example to explain the display brightness adjustment Figure 7 The VDD power supply of the first subframe is VDD1a, VDD1b, VDD1c, etc. Figure 8 The second subframe VDD power supply is VDD2d, VDD2e, VDD2f, etc. Figure 9 The VDD power supply of the nth subframe is VDDnx, VDDny, VDDnz,,, Figure 10 . Take 3 memories as an example to explain the adjustment of display brightness Figure 11 . The luminous time of the connected subframes overlaps Figure 12 . Some subframes use global display Figure 13 . GOA controls different power supplies connected to the display area Figure 14 Taking the first and second subframes as examples, different power supplies are connected to the display area. Figure 15 . GOA controls different power supplies connected to the display area (using 3 memories as an example) Figure 16 Taking the first and second subframes as examples, different power supplies are connected to the display area (using 3 memories as an example) DETAILED DESCRIPTION Example 1
[0022] The VDD is different between different subframes, that is, each row of pixels has a row power supply.
[0023] like Figure 13 VDD uses row power supply routing. Row VDD is not directly connected between rows. Instead, it is connected to an external power supply via transistors around AA: the first subframe is connected to VDD1, the second subframe is connected to VDD2, and the Nth subframe is connected to VDDn. Under GOA control, the transistors are turned on row by row to connect the VDD of the display area to VDD1, VDD2, and VDDn row by row. The VDD values of pixels in different subframes and rows can be different.
[0024] like Figure 3 、 Figure 4 、 Figure 5 The VDD power line has different values in different subframes. For example, the VDD value of the first subframe is VDD1, the VDD value of the second subframe is VDD2, and the VDD value of the nth subframe is VDDn.
[0025] like Figure 14 Taking the first subframe and the second subframe as an example, it is achieved that the VDD of some rows in the AA area is VDD1, and they emit light with the characteristics of the first subframe; the VDD of some rows is VDD2, and they emit light with the characteristics of the second subframe.
[0026] like Figure 6 Grayscale brightness is controlled by a combination of time and amplitude, with the amplitude adjusted by VDD (h1, h2, hn). Even with a small number of bits (k), amplitude adjustment can still be used to match the gamma 2.2 curve.
[0027] Therefore, when the number of bits is small, accurate display can be achieved by adjusting the amplitude, which reduces the operating frequency, the number of subframes, and the number of memories. Example 2
[0028] The VDD between different subframes is different, and the VDD of different branches of pixels in a subframe is also different, that is, each row of pixels has multiple row power supplies.
[0029] like Figure 15 Each register-controlled light-emitting branch uses independent row power supply routing for its VDD. The row VDD is connected to an external power supply via transistors around the AA region: in the first subframe, the row VDD of branch 1 connects to VDD1a, the row VDD of branch 2 connects to VDD1b, the row VDD of branch 3 connects to VDD1c, and so on. In the second subframe, the row VDD of branch 1 connects to VDD2d, the row VDD of branch 2 connects to VDD2e, the row VDD of branch 3 connects to VDD2f, and so on. Under the control of GOA, the transistors are turned on row by row, ensuring that within the AA region, the VDD is connected to VDD1a, VDD1b, VDD1c, VDD2d, VDD2e, VDD2f, and so on. The VDD values of pixels can vary across different subframes, rows, and branches.
[0030] like Figure 7 、 Figure 8 、 Figure 9 The VDD values of different branches in a pixel within the same subframe can also be set differently. Take the three reservoirs in the pixel as an example. For example, in the first subframe, the VDD value of the first branch is VDD1a, the VDD value of the second branch is VDD1b, and the VDD value of the third branch is VDD1c; in the second subframe, the VDD value of the first branch is VDD2d, the VDD value of the second branch is VDD2e, and the VDD value of the third branch is VDD2f; in the nth subframe, the VDD value of the first branch is VDDnx, the VDD value of the second branch is VDDny, and the VDD value of the third branch is VDDnz.
[0031] like Figure 16 Taking the first and second subframes as examples, and the three memory-controlled light-emitting branches in the pixel as an example, it is achieved that the VDD of some rows in the AA area is VDD1a, VDD1b, and VDD1c, and they emit light with the first subframe characteristics; while the VDD of some rows is VDD2d, VDD2e, and VDD2f, and they emit light with the second subframe characteristics.
[0032] like Figure 10 Grayscale brightness is controlled by a combination of time and amplitude. The amplitude is adjusted by VDD, and the VDD levels of different branches within the same frame are adjustable (h1a, h1b, hnz). Even with a small number of bits, k, the amplitude can be adjusted to match the gamma2.2 curve.
[0033] Therefore, when the number of bits is small, accurate display can be achieved by adjusting the amplitude, which reduces the operating frequency, the number of subframes, and the number of memories.
[0034] Industry professionals should understand that the VDDs of several branches in a pixel can also share a row VDD to reduce the number of power supplies, that is, to achieve a balance between the number of row power supplies and the number of peripheral power supplies.
[0035] The spirit and principle of this invention lies in the use of row VDD wiring for pixel VDD. Row VDDs are not directly connected, but rather connected to a peripheral power supply via transistors controlled by GOAs. The GOAs are activated for rolling scanning row by row, and the row power lines are connected to the peripheral power supply row by row. This allows the AA region to coexist with multiple VDDs of varying values, meaning that some AA rows emit light in the a subframe, while others in the b subframe. This allows for adjustable luminous amplitude without sacrificing luminous duration. Any modifications based on the spirit and principles of this invention are considered within its scope.
Claims
1. A PWM and PAM hybrid drive display circuit, characterized in that The pixel light-emitting power supply (VDD) is wired by row, and different rows are not directly connected to each other.
2. The row power lines are connected to the peripheral power supply through transistors. The transistors are turned on row by row under the control of the row drive circuit (GOA), and the row power lines are connected to the peripheral power supply row by row. The number of peripheral power supplies is greater than or equal to 2, and the numerical values have at least 2 different values.
3. Based on claim 2, each row of pixels has a row power supply, and the peripheral power supply value is different in different subframes.
4. Based on claim 2, each row of pixels has multiple row power supplies, and the peripheral power supply values are different in different subframes.
5. Based on claim 4, the light emitting power supply of each branch in the pixel adopts a separate row power supply wiring, and the peripheral power supply value is different in different subframes.