Retraining method, retraining device, electronic device and storage medium

Abstract

At least one embodiment of the invention provides a retraining method and a retraining device for a data signal of a memory module, an electronic device and a storage medium. The retraining method comprises the following steps: in response to a received initialization training request, performing initialization training operation on a target signal line by using first excitation to obtain delay values of first left and right boundaries of the target signal line; based on the delay values of the first left and right boundaries, performing retraining initialization operation on the target signal line by using second excitation to obtain delay values of second left and right boundaries of the target signal line; taking the delay value of the second left and right boundaries as a reference, and performing retraining operation on the target signal line by using second excitation to obtain a delay value of third left and right boundaries of the target signal line; and calculating a final delay value of the target signal line based on the delay values of the third left and right boundaries. According to the retraining method, the problem of relatively large deviation of a retraining result caused by different excitation complexity can be avoided.

Description

Technical Field

[0001] The present disclosure relates to a retraining method, a retraining device, an electronic device, and a storage medium. Background Art

[0002] A memory module generally refers to a data storage module used in computers, servers, and other electronic devices. For example, dynamic random access memory (DRAM) is a key data storage module in system-on-a-chip (SoC). To meet market demand for memory speed, bandwidth, and capacity, DRAM has evolved through several generations, from DDR1, DDR2, DDR3, and finally DDR4. The currently mainstream DDR4 has been available for nearly seven years. With the increasing complexity of SoC systems, the demand for big data in the mobile internet era, AI deep learning, and the widespread application of 5G, DDR4's speed and bandwidth are no longer sufficient to meet market demands. To meet market demand, JEDEC officially released the DDR5 protocol standard in July 2020, significantly improving transmission speed, bandwidth, and capacity. This, in turn, increases the design complexity of the memory controller (MC) and the corresponding physical layer (PHY). As the voltage and temperature of the chip's operating environment fluctuate, memory signal routing delays drift, requiring the DDR PHY to periodically compensate for this drift. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a retraining method for a data signal of a memory module, comprising: in response to receiving an initialization training request, performing an initialization training operation on a target signal line using a first stimulus to obtain a delay value of a first left boundary and a delay value of a first right boundary of the target signal line; based on the delay value of the first left boundary and the delay value of the first right boundary, performing a retraining initialization operation on the target signal line using a second stimulus to obtain a delay value of a second left boundary and a delay value of a second right boundary of the target signal line; based on the delay value of the second left boundary and the delay value of the second right boundary, performing a retraining operation on the target signal line using the second stimulus to obtain a delay value of a third left boundary and a delay value of a third right boundary of the target signal line, wherein the number of changes between the high level and the low level of a bit of the first stimulus is greater than the number of changes between the high level and the low level of a bit of the second stimulus; and calculating a final delay value of the target signal line based on the delay value of the third left boundary and the delay value of the third right boundary.

[0004] For example, the storage subsystem provided by at least one embodiment of the present disclosure uses a second stimulus to perform a retraining initialization operation on the target signal line based on the delay value of the first left boundary and the delay value of the first right boundary to obtain the delay value of the second left boundary and the delay value of the second right boundary of the target signal line, including: based on the delay value of the first left boundary and the delay value of the first right boundary, using the second stimulus to perform a retraining initialization operation on the target signal line through an upper computer operation to obtain the delay value of the second left boundary and the delay value of the second right boundary of the target signal line.

[0005] For example, the retraining method provided by at least one embodiment of the present disclosure uses a second stimulus to perform a retraining initialization operation on the target signal line based on the delay value of the first left boundary and the delay value of the first right boundary to obtain the delay value of the second left boundary and the delay value of the second right boundary of the target signal line, including: triggering a retraining hardware acceleration module based on the delay value of the first left boundary and the delay value of the first right boundary, and using the second stimulus to perform a retraining initialization operation on the target signal line to obtain the delay value of the second left boundary and the delay value of the second right boundary of the target signal line.

[0006] For example, the retraining method provided by at least one embodiment of the present disclosure also includes: triggering the retraining hardware acceleration module based on the delay value of the second left boundary and the delay value of the second right boundary of the target signal line, and using the second stimulus to perform a retraining initialization operation on the target signal line to obtain a new delay value of the second left boundary and a new delay value of the second right boundary of the target signal line and use them as the delay value of the second left boundary and the delay value of the second right boundary.

[0007] For example, in the retraining method provided by at least one embodiment of the present disclosure, the bits of the first stimulus and the bits of the second stimulus are binary bits, wherein the first stimulus is a pseudo-random number sequence, and the number of changes between the high level and the low level of the binary bit of the second stimulus is equal to 2.

[0008] For example, the retraining method provided by at least one embodiment of the present disclosure uses a second excitation to perform a retraining operation on the target signal line to obtain the delay value of the third left boundary and the delay value of the third right boundary of the target signal line, including: adjusting the size of the delay value of the second left boundary and the delay value of the second right boundary of the target signal line so that the sampling result of the target signal line is located at the signal jump of the target signal line loaded with the second excitation to obtain the delay value of the third left boundary and the delay value of the third right boundary of the target signal line.

[0009] For example, in the retraining method provided by at least one embodiment of the present disclosure, the sampling result is obtained by sampling the target signal line loaded with the second stimulus in response to the sampling identification signal line being valid and the sampling moment being at the rising edge of the clock signal line.

[0010] For example, the retraining method provided by at least one embodiment of the present disclosure calculates the final delay value of the target signal line based on the delay value of the third left boundary and the delay value of the third right boundary, including: taking half of the total delay value of the target signal line as the final delay value of the target signal line, wherein the total delay value is equal to the sum of the delay value of the third left boundary and the delay value of the third right boundary of the target signal line.

[0011] For example, the retraining method provided by at least one embodiment of the present disclosure, in response to there being multiple target signal lines, in response to receiving an initialization training request, uses a first stimulus to perform an initialization training operation on the target signal line to obtain a delay value of a first left boundary and a delay value of a first right boundary of the target signal line, including: performing an initialization training operation on multiple target signal lines to obtain a delay value of a first left boundary and a delay value of a first right boundary of multiple target signal lines and selecting a first target signal line and a second target signal line therefrom, wherein the first target signal line is a target signal line having the largest delay value of the first left boundary and the delay value of the first right boundary, and the second target signal line is a target signal line having the smallest delay value of the first left boundary and the delay value of the first right boundary; based on the delay value of the second left boundary and the delay value of the second right boundary, uses a second stimulus A retraining operation is performed on the target signal line to obtain the delay value of the third left boundary and the delay value of the third right boundary of the target signal line, including: respectively calculating the left offset and right offset of the delay value of the third left boundary and the delay value of the third right boundary of the first target signal line and the second target signal line relative to the delay value of the second left boundary and the delay value of the second right boundary; taking half of the sum of the left offset of the first target signal line and the left offset of the second target signal line as the total left offset of multiple target signal lines; taking half of the sum of the right offset of the first target signal line and the right offset of the second target signal line as the total right offset of multiple target signal lines; and applying the total left offset and the total right offset to multiple target signal lines at the same time to obtain the delay value of the third left boundary and the delay value of the third right boundary of multiple target signal lines.

[0012] For example, in at least one embodiment of the present disclosure, the retraining method provided by the memory module includes a register clock driver, and the target signal line includes at least one of the following: a chip select signal line, a command and address signal line, a data signal line, and a data strobe signal line.

[0013] For example, in the retraining method provided by at least one embodiment of the present disclosure, the target signal lines include a chip select signal line and the command and address signal lines, and the retraining method further includes: configuring the register clock driver to enter an accelerated command and address signal line training mode, wherein the accelerated command and address signal line training mode supports retraining operations of both the chip select signal line and the command and address signal lines.

[0014] At least one embodiment of the present disclosure also provides a retraining device for a data signal of a memory module, comprising: an initialization training module, configured to, in response to receiving an initialization training request, perform an initialization training operation on a target signal line using a first stimulus to obtain a delay value of a first left boundary and a delay value of a first right boundary of the target signal line; a retraining initialization module, configured to, based on the delay value of the first left boundary and the delay value of the first right boundary, perform a retraining initialization operation on the target signal line using a second stimulus to obtain a delay value of a second left boundary and a delay value of a second right boundary of the target signal line; a retraining module, configured to, based on the delay value of the second left boundary and the delay value of the second right boundary, perform a retraining operation on the target signal line using the second stimulus to obtain a delay value of a third left boundary and a delay value of a third right boundary of the target signal line, wherein the number of changes between the high level and the low level of a bit of the first stimulus is greater than the number of changes between the high level and the low level of a bit of the second stimulus; and a calculation module, configured to calculate a final delay value of the target signal line based on the delay value of the third left boundary and the delay value of the third right boundary.

[0015] For example, in the retraining device provided by at least one embodiment of the present disclosure, the retraining initialization module includes a retraining hardware acceleration module, and the retraining initialization module is further configured to: trigger the retraining hardware acceleration module based on the delay value of the first left boundary and the delay value of the first right boundary, and use the second stimulus to perform a retraining initialization operation on the target signal line to obtain the delay value of the second left boundary and the delay value of the second right boundary of the target signal line.

[0016] For example, in at least one embodiment of the present disclosure, a retraining device is provided, in response to the number of target signal lines, wherein the initialization training module is configured to: perform an initialization training operation on the multiple target signal lines to obtain the delay values ​​of the first left boundary and the delay values ​​of the first right boundary of the multiple target signal lines and select the first target signal line and the second target signal line therefrom, wherein the first target signal line is the target signal line with the largest delay value of the first left boundary and the delay value of the first right boundary, and the second target signal line is the target signal line with the smallest delay value of the first left boundary and the delay value of the first right boundary; the retraining module is configured to: calculate the delay values ​​of the first target signal line and the second target signal line respectively. The left offset and right offset of the delay value of the third left boundary and the delay value of the third right boundary of the second target signal line relative to the delay value of the second left boundary and the delay value of the second right boundary; taking half of the sum of the left offset of the first target signal line and the left offset of the second target signal line as the total left offset of multiple target signal lines; taking half of the sum of the right offset of the first target signal line and the right offset of the second target signal line as the total right offset of multiple target signal lines; and applying the total left offset and the total right offset to multiple target signal lines at the same time to obtain the delay value of the third left boundary and the delay value of the third right boundary of multiple target signal lines.

[0017] At least one embodiment of the present disclosure further provides an electronic device, comprising at least one processor; and at least one memory storing instructions, wherein when the instructions are executed by the at least one processor, the at least one processor executes the retraining method of any embodiment.

[0018] At least one embodiment of the present disclosure further provides a computer-readable storage medium having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by a processor, the processor is caused to perform the retraining method of any embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0020] Figure 1A A schematic flow chart of a method for retraining a data signal of a memory module according to at least one embodiment of the present disclosure is shown;

[0021] Figure 1B A schematic diagram showing a strategy of a retraining method according to at least one embodiment of the present disclosure is shown;

[0022] Figure 2 A schematic diagram illustrating the architecture of a retraining method according to at least one embodiment of the present disclosure is shown;

[0023] Figure 3 Shows examples of left and right boundary waveforms of a chip select signal line before and after offset according to at least one embodiment of the present disclosure;

[0024] Figure 4 Shows examples of left and right boundaries before and after offset of command and address signal lines according to at least one embodiment of the present disclosure;

[0025] Figure 5 A schematic diagram of a weight training device according to at least one embodiment of the present disclosure is shown;

[0026] Figure 6 A schematic diagram illustrating an electronic device according to at least one embodiment of the present disclosure is shown;

[0027] Figure 7 A schematic diagram illustrating a computer-readable storage medium according to at least one embodiment of the present disclosure; and

[0028] Figure 8 A schematic diagram illustrating another electronic device according to at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0029] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0030] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure pertains. The terms "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are merely used to distinguish between different components. Similarly, terms such as "include" or "comprise" and the like mean that the elements or objects preceding the term encompass the elements or objects listed following the term and their equivalents, without excluding other elements or objects. Terms such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper", "lower", "left", and "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0031] As mentioned above, as the voltage and temperature of the chip's operating environment change, the signal routing delay in the memory module will drift, requiring the DDR PHY to periodically compensate for the drift.

[0032] For example, in the case of multi-rank buffered dual-inline memory modules (MRDIMMs), the MRDIMM includes a multiplexed rank registering clock driver (MRCD). The chip select signal (DCS) and command / address bus inputs (DCA) serve as the two input signals for the MRCD. These signals are sampled by the differential master clock input pair (DCK) of the PLL before being used by the MRCD's internal circuitry. However, with temperature and voltage fluctuations, both the DCK sampling clock and the DCS / DCA signal lines drift, necessitating periodic DCS / DCA delay compensation. An exemplary method for compensating for temperature and voltage drift is to retrain the DCS / DCA link signal lines to find a new optimal eye diagram.

[0033] For example, initialization training is an essential step during DDR power-on initialization. Initialization training helps determine the delays on the command and data links so that commands and data meet timing requirements when they reach the DRAM. Furthermore, the DDR PHY receiver can obtain a good eye diagram to ensure correct data reception.

[0034] During the initialization training phase, in order to better reflect the impact of signal integrity issues such as inter-symbol interference on the channel, more complex excitations are used during initialization training, such as pseudo-random excitation generated by linear shift feedback, and the training time is longer.

[0035] Specifically, DDR initialization training may mainly include the following steps:

[0036] (1) Power on and reset: After the power supply is stable, the DDR memory is first reset to ensure that the memory enters a known state.

[0037] (2) Precharge: All banks are precharged to the closed state in preparation for the next operation.

[0038] (3) Read and write training: This is the core part of initialization training, including steps such as writing training mode (WriteLeveling), reading Deskew, and writing Deskew. The purpose is to find the best sampling point so that read and write operations can be performed in the most stable state.

[0039] ① Write Leveling: Used to adjust the phase of DQS relative to DCK (Clock), for example, to ensure that the written data can be accurately captured.

[0040] ②Read Deskew: Optimizes the latency of the read path to ensure that data read from the DDR memory can be received correctly.

[0041] ③ Write Deskew: For example, optimize the delay of the write path to ensure that the data written to the DDR memory can be accurately received.

[0042] (4) Verification and Adjustment: After completing the above steps, some verification tests are required, such as executing a memory test program to check whether everything is working properly, and further fine-tuning of relevant parameters may be required based on the test results.

[0043] Unlike initialization training, retraining is typically triggered periodically during task mode. For example, the phase relationship between the DQS and clock signals used in initialization training must be reassessed and adjusted to ensure accurate data reading and writing. Furthermore, during retraining, the system's access to DRAM must be suspended and resumed after retraining is complete, negatively impacting the system's memory access bandwidth. To minimize the impact on system bandwidth, retraining is performed over a short period of time, using simpler stimuli, such as a binary sequence with only two signal transitions.

[0044] The inventors of the present disclosure have discovered through research that the benchmark currently used when retraining a signal is the delay value obtained through initialization training (i.e., the result obtained through initialization training using complex excitation). Since simple excitation is used during retraining, the difference in excitation complexity will lead to significant differences in the feedback of signal integrity issues, resulting in a certain deviation in the drift obtained by training the two (i.e., complex excitation and simple excitation). Therefore, when retraining based on the results of initialization training, it is necessary to resolve this deviation caused by inconsistent excitation complexity to avoid deviation in the retraining results.

[0045] At least one embodiment of the present disclosure provides a retraining method for a data signal of a memory module, comprising: in response to receiving an initialization training request, performing an initialization training operation on a target signal line using a first stimulus to obtain a delay value of a first left boundary and a delay value of a first right boundary of the target signal line; based on the delay value of the first left boundary and the delay value of the first right boundary, performing a retraining initialization operation on the target signal line using a second stimulus to obtain a delay value of a second left boundary and a delay value of a second right boundary of the target signal line; based on the delay value of the second left boundary and the delay value of the second right boundary, performing a retraining operation on the target signal line using the second stimulus to obtain a delay value of a third left boundary and a delay value of a third right boundary of the target signal line, wherein the number of changes between the high level and the low level of a bit of the first stimulus is greater than the number of changes between the high level and the low level of a bit of the second stimulus; and calculating a final delay value of the target signal line based on the delay value of the third left boundary and the delay value of the third right boundary.

[0046] Based on the same inventive concept, at least one embodiment of the present disclosure further provides a retraining device, an electronic device, and a storage medium for a data signal of a memory module.

[0047] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0048] Figure 1A A flow chart of a method for retraining a data signal of a memory module according to at least one embodiment of the present disclosure is shown, comprising steps S100 , S110 , S120 , and S130 . Figure 1B A strategy diagram of a retraining method according to at least one embodiment of the present disclosure is shown, including initialization training step 1, retraining initialization training step 2, retraining initialization training step 3, and retraining step 4.

[0049] Step S100 : in response to receiving an initialization training request, performing an initialization training operation on a target signal line using a first stimulus to obtain a first left boundary delay value and a first right boundary delay value of the target signal line.

[0050] Step S110 : Based on the delay value of the first left boundary and the delay value of the first right boundary, use the second stimulus to perform a retraining initialization operation on the target signal line to obtain the delay value of the second left boundary and the delay value of the second right boundary of the target signal line.

[0051] Step S120: Based on the delay value of the second left boundary and the delay value of the second right boundary, the target signal line is retrained using the second stimulus to obtain the delay value of the third left boundary and the delay value of the third right boundary of the target signal line, wherein the number of changes between the high level and the low level of the bit of the first stimulus is greater than the number of changes between the high level and the low level of the bit of the second stimulus.

[0052] Step S130 : Calculating a final delay value of the target signal line based on the delay value of the third left boundary and the delay value of the third right boundary.

[0053] The stimulus (including the first stimulus and the second stimulus) herein can be any input signal applied to the target signal line. For example, the stimulus can be embodied as a data sequence including one or more high-level (1) and low-level (0) signals or a pseudo-random number sequence.

[0054] The retraining initialization operation is to load the retraining stimulus into the signal line based on the results of the initialization training to pre-retrain and obtain the result of the retraining initialization operation. Since the signal transition point of the transmitted signal line can only be aligned with the rising edge or falling edge of the clock signal line (i.e., the sampling time) in theory, there is a certain delay in the signal line relative to the clock signal line itself. For example, the delay value of the left boundary of the above-mentioned signal line can be understood as the delay value corresponding to the rising edge transition point of the stimulus in the signal line after the stimulus is loaded (e.g., the "0 to 1 transition point"), and since the stimulus signal has a length and thus has a right boundary, the delay value of the right boundary can be understood as the delay value corresponding to the falling edge transition point of the stimulus in the signal line after the stimulus is loaded (e.g., the "1 to 0 transition point").

[0055] Accordingly, step S100 corresponds to Figure 1B In the initialization training step 1, step S110 may correspond only to Figure 1B The retraining initialization training (software) step 2 in the above example may correspond only to the retraining initialization training (hardware) step 3, or may correspond to the retraining initialization training (software) step 2 and the retraining initialization training (hardware) step 3, and steps S120 and S130 may correspond to Figure 1BRetraining training step 4 in. It should be noted that, the retraining initialization training (software) step 2 and the retraining initialization training (hardware) step 3 are actually based on the delay value obtained in the previous sequence and use the second stimulus to retrain to obtain a new delay value, wherein the retraining initialization training (software) step 2 is implemented by software, and the retraining initialization training (hardware) step 3 is implemented by hardware. In actual operation, when the system is running normally, the difference between the delay values ​​obtained by software and hardware is almost negligible (that is, whether to use software or hardware to perform retraining initialization training depends on the actual situation, and retraining initialization training (software) step 2 and retraining initialization training (hardware) step 3 do not need to be executed at the same time), and because the operability of retraining initialization training implemented by software is higher, the retraining method provided by at least one embodiment of the present disclosure gives priority to step 2 for retraining initialization training. However, it can be understood that the embodiments of the present disclosure can also directly use hardware (i.e. step 3) for retraining initialization training based on actual design conditions (such as Figure 1B As shown, step 3 is directly executed after step 1 is executed), and this disclosure does not limit this.

[0056] However, if a system anomaly causes a large error in the delay value obtained only by software (i.e., retraining initialization training (software) step 2), then before retraining initialization training (software) step 2 and retraining step 4, it is necessary to recalculate the delay value by hardware (i.e., retraining initialization training (hardware) step 3) to quickly identify the problem with the system.

[0057] It should also be noted that if Figure 1B As shown, in the case of an abnormality in the above system (i.e., retraining initialization training is first performed by software and then by hardware), the output result of initialization training step 1 in the retraining method provided by at least one embodiment of the present disclosure is the input data of retraining initialization training step 2, the output result of retraining initialization training step 2 is the input data of retraining initialization training step 3, and the output result of retraining initialization training step 3 is the input data of the retraining operation, that is, step 2 is based on the delay value obtained in step 1, step 3 is based on the delay value obtained in step 2, and step 4 is based on the delay value obtained in step 3. It can be understood that when the above system operates normally, Figure 1B Retraining in Initialize Training (Hardware) Step 3 is optional (i.e. Figure 1B In the figure, step 3 is indicated as an optional state by a "dashed box"). The output result of the retraining initialization training (software) step 2 is the input data of the retraining step 4. That is, step 4 is based on the delay value obtained in step 2.

[0058] As described above, the retraining method for the data signal of the memory module provided by at least one embodiment of the present disclosure applies the excitation used for retraining to the initialization training process in advance, completes the retraining initialization operation, and uses the same excitation to perform the retraining operation based on the delay result obtained from the retraining initialization operation. This can effectively avoid the problem of large deviation in the retraining results caused by different excitation complexities, improve the effect of retraining, and thus ensure that memory reading and writing are not affected when temperature and voltage drift.

[0059] Unless otherwise specified, the following description will use at least one embodiment of the present disclosure to adopt the strategy of steps 1, 2, and 4.

[0060] Exemplarily, the following description is made using an example in which the memory module is an MRDIMM and the corresponding target signal line is a DCS and / or DCA signal line, wherein the MRDIMM may include an MRCD, which may receive a DCS or DCA signal and perform the initialization training operation, retraining initialization operation, and retraining operation described above and below on it. However, it should be understood that the embodiments of the present disclosure are not limited to this, and the initialization training operation, retraining initialization operation, and retraining operation described above and below may be performed on other memory modules. For example, additionally or alternatively, the memory module may also include other types of DIMMs such as RDIMM and UDIMM. For example, additionally or alternatively, the corresponding target signal line may also include a data signal line (Data Queue, DQ) or a data strobe signal line (Data Strobe, DQS) and other data lines, or the RCD in the RDIMM may receive a DCS or DCA signal.

[0061] Regarding step S100 : in response to receiving an initialization training request, performing an initialization training operation on a target signal line using a first stimulus to obtain a delay value of a first left boundary and a delay value of a first right boundary of the target signal line.

[0062] Since the transmission delay value of the target signal line in the system is unknown after the device is powered on, it is necessary to first initialize and train the target signal line to obtain the initial delay value of the target signal line in the system. The data on the target signal line meets its timing requirements when reaching the DRAM, and the receiving end of the DDR PHY can obtain a good eye diagram.

[0063] For step S110: based on the delay value of the first left boundary and the delay value of the first right boundary, a retraining initialization operation is performed on the target signal line using the second stimulus to obtain the delay value of the second left boundary and the delay value of the second right boundary of the target signal line.

[0064] For example, the retraining initialization operation corresponding to step S110 can be implemented by software.

[0065] For example, in one possible implementation, step S110 specifically includes: based on the delay value of the first left boundary and the delay value of the first right boundary, performing a retraining initialization operation on the target signal line using a second stimulus through an upper computer operation to obtain the delay value of the second left boundary and the delay value of the second right boundary of the target signal line.

[0066] For example, relevant retraining parameters can be flexibly configured through a host computer (such as a computer or other device) to implement a retraining initialization operation.

[0067] For example, the retraining initialization operation corresponding to step S110 may also be implemented through hardware methods.

[0068] For example, in one possible implementation, step S110 specifically includes: based on the delay value of the first left boundary and the delay value of the first right boundary, triggering the retraining hardware acceleration module, and using the second stimulus to perform a retraining initialization operation on the target signal line to obtain the delay value of the second left boundary and the delay value of the second right boundary of the target signal line.

[0069] For example, the retraining initialization operation can be achieved by executing the built-in embedded algorithm through the retraining hardware acceleration module. It should be noted that the delay value of the second left boundary and the delay value of the second right boundary of the target signal line obtained by the hardware method and the software method are theoretically equal (there is a small error in practice, which can be ignored). The hardware method can be understood as a further verification of the delay value of the second left boundary and the delay value of the second right boundary of the target signal line obtained by the software method. If the difference between the results obtained by the hardware method and the software method is too large, it means that there is a problem. In the actual application process, it is necessary to determine whether to use the software method or the hardware method to obtain the left and right boundary delay values ​​as the benchmark value for subsequent retraining operations based on actual conditions. The delay value of the target signal line after retraining initialization training obtained by the hardware method can verify the accuracy of the software method and improve the accuracy of subsequent retraining.

[0070] For example, in one possible embodiment, the retraining method further includes: triggering the retraining hardware acceleration module based on the delay value of the second left boundary and the delay value of the second right boundary of the target signal line, and performing a retraining initialization operation on the target signal line using a second stimulus to obtain a new delay value of the second left boundary and a new delay value of the second right boundary of the target signal line and use them as the delay value of the second left boundary and the delay value of the second right boundary.

[0071] For example, see Figure 1B, the above steps can correspond to the retraining initialization training (hardware) step 3, that is, Figure 1B The delay values ​​of the left and right boundaries output by the described retraining initialization training (software) step 2 serve as input to the retraining initialization training (hardware) step 3.

[0072] For example, when a large error occurs in the delay value of a target signal line obtained through a retraining operation, the retraining initialization operation can be performed again through a hardware method for debugging after the retraining initialization operation is performed through a software method, which helps to identify the cause of the relevant error.

[0073] For step S120: based on the delay value of the second left boundary and the delay value of the second right boundary, the target signal line is retrained using the second stimulus to obtain the delay value of the third left boundary and the delay value of the third right boundary of the target signal line, wherein the number of changes between the high level and the low level of the bit of the first stimulus is greater than the number of changes between the high level and the low level of the bit of the second stimulus.

[0074] For example, the first stimulus may be referred to herein as a complex stimulus, and the second stimulus may be referred to herein as a simple stimulus.

[0075] For example, the bits of the first excitation and the bits of the second excitation are binary bits, and the first excitation can be a pseudo-random number sequence. The pseudo-random number sequence has a certain complexity so that the delay value of the first left boundary and the delay value of the first right boundary of the target signal line are relatively accurate. Therefore, after the pseudo-random number sequence is represented by a binary number sequence, the rate of change between the high and low levels is relatively high. It should be noted that the first excitation can also be other types of excitations, and the present disclosure does not limit this. For example, the number of changes between the high level and the low level of the binary bit of the second excitation is equal to 2. Specifically, the second excitation can be "...00001000..." or "...111101111...". The second excitation used for the retraining initialization operation and the retraining operation is simpler than the first excitation used for the initialization training operation to increase the speed of retraining and reduce the occupancy of the system data transmission bandwidth. It should be noted that the second excitation can also be a binary number sequence of other arrangements, and the present disclosure does not limit this.

[0076] At least one embodiment of the present disclosure applies the excitation used for the retraining operation to the initialization training operation (i.e., the retraining initialization operation) in advance, which can effectively avoid the problem of large deviation in retraining results caused by different excitation complexities, improve the effect of retraining, and thus ensure that memory reading and writing are not affected when temperature and voltage drift occur.

[0077] For example, in one possible embodiment, a retraining operation is performed on the target signal line using a second excitation to obtain a delay value of the third left boundary and a delay value of the third right boundary of the target signal line, including: adjusting the size of the delay value of the second left boundary and the delay value of the second right boundary of the target signal line so that the sampling result of the target signal line is located at the signal jump of the target signal line loaded with the second excitation to obtain the delay value of the third left boundary and the delay value of the third right boundary of the target signal line.

[0078] For example, the target signal line is a chip select signal line input into the MRCD, and the chip select signal line includes a target chip select signal line.

[0079] For example, the target chip select signal line obtains a delay value of 1ns at the left boundary through the retraining initialization training operation, and a delay value of 1.5ns at the right boundary. The target chip select signal drifts with the increase of temperature and voltage. At this time, it is necessary to first adjust the delay value of the left boundary by 1ns (for example, the delay value can be adjusted in a positive or negative direction, for example, the delay value is increased in a positive direction to 1.1ns, 1.2ns, ..., and the delay value is decreased in a negative direction to 0.9ns, 0.8ns, ...) until the sampled signal in the target chip select signal line is located at the signal jump of the loaded second stimulus (for example, the rising Edge jump point), record the delay value of the left boundary at this time as the delay value of the third left boundary of the target chip select signal line; thereafter adjust the delay value of the right boundary by 1.5ns (for example, the delay value can be adjusted forward or reverse, for example, the positive increase delay value is 1.6ns, 1.7ns, ..., and the reverse decrease delay value is 1.4ns, 1.3ns, ...) until the sampled signal in the target chip select signal line is at the signal jump point of the loaded second stimulus (for example, the falling edge jump point), and record the delay value of the right boundary at this time as the delay value of the third right boundary of the target chip select signal line.

[0080] For example, in a possible implementation, the sampling result is obtained by sampling the target signal line loaded with the second stimulus in response to the sampling identification signal line being valid and the sampling moment being at the rising edge of the clock signal line.

[0081] For example, in addition to the target chip select signal line, the above-mentioned chip select signal line also includes an additional chip select signal line. The additional chip select signal line is a signal line that has been retrained and is then used as a sampling identification signal line. For the sampling identification signal line, when its sampling identification is located in the middle of the clock cycle and the sampling moment is exactly at the rising edge of the clock signal line (of course it can also be the falling edge, and the present disclosure does not limit this), this moment is used as the optimal sampling moment, and the best eye diagram can be obtained at this sampling moment. For example, the second stimulus is "...00001000...", and the delay value of the second left boundary of the target chip select signal line after the retraining initialization training operation (for example, 1ns) is exactly located at the rising edge transition of the signal from "0 to 1" in the second stimulus. While keeping the sampling moments of the clock signal line and the sampling identification signal line unchanged, the delay value of the left boundary of the target chip select signal line after drift has changed. At this time, it is necessary to adjust the delay value of the second left boundary by 1ns (for example, the delay value can be adjusted forward or reverse, such as increasing the delay value by 1.1ns in the forward direction and decreasing the delay value by 0.9ns in the reverse direction) until the delay value of the left boundary is re-aligned with the above-mentioned sampling moment, that is, the rising edge transition of the signal from "0 to 1" of the target chip select signal is re-aligned with the above-mentioned sampling moment, and the delay value of the left boundary at this time is recorded as the third left boundary of the target chip select signal line. For example, the delay value of the second right boundary of the target chip select signal line after the retraining initialization training operation (for example, 1.5ns) is exactly located at the falling edge transition of the "1 to 0" signal in the second stimulus. While keeping the sampling moments of the clock signal line and the sampling identifier chip select signal line unchanged, the delay value of the right boundary of the target chip select signal line after the drift has changed. At this time, it is necessary to adjust the delay value of the second right boundary by 1.5ns (for example, the delay value can be adjusted positively or negatively, for example, the delay value is increased by 1.6ns in the positive direction and decreased by 1.4ns in the negative direction) until the delay value of the right boundary is re-aligned with the above sampling moment, that is, the falling edge transition of the "1 to 0" signal of the target chip select signal is re-aligned with the above sampling moment, and the delay value of the right boundary at this time is recorded as the delay value of the third right boundary of the target chip select signal line.

[0082] For example, in one possible embodiment, the final delay value of the target signal line is calculated based on the delay value of the third left boundary and the delay value of the third right boundary, including: taking half of the total delay value of the target signal line as the final delay value of the target signal line, wherein the total delay value is equal to the sum of the delay value of the third left boundary and the delay value of the third right boundary of the target signal line.

[0083] For example, for the target chip select signal line, the delay value of the left boundary after the retraining operation is 1.1ns, and the delay value of the right boundary is 1.6ns. Then the final delay value of the target chip select signal line needs to be updated to 1.35ns.

[0084] The final delay value obtained by the chip select signal line retraining method provided by at least one embodiment of the present disclosure is highly accurate, avoiding the problem of large deviation in retraining results caused by different excitation complexities, and improving the retraining effect.

[0085] Through further research, the inventors of the present disclosure realized that, in the current situation where there are multiple signal lines for retraining, all signal lines need to be retrained, which will result in longer time consumption and lower retraining efficiency, and further lead to longer time when DRAM reading and writing are closed, thereby limiting the bandwidth of data transmission.

[0086] For example, in one possible embodiment, in response to there being multiple target signal lines, wherein, in response to receiving an initialization training request, an initialization training operation is performed on the target signal line using a first stimulus to obtain a delay value of a first left boundary and a delay value of a first right boundary of the target signal line, including: performing an initialization training operation on multiple target signal lines to obtain a delay value of a first left boundary and a delay value of a first right boundary of multiple target signal lines and selecting a first target signal line and a second target signal line therefrom, wherein the first target signal line is a target signal line having the largest delay value of the first left boundary and the delay value of the first right boundary, and the second target signal line is a target signal line having the smallest delay value of the first left boundary and the delay value of the first right boundary; based on the delay value of the second left boundary and the delay value of the second right boundary, a second stimulus is used. A retraining operation is performed on the target signal line to obtain the delay value of the third left boundary and the delay value of the third right boundary of the target signal line, including: respectively calculating the left offset and right offset of the delay value of the third left boundary and the delay value of the third right boundary of the first target signal line and the second target signal line relative to the delay value of the second left boundary and the delay value of the second right boundary; taking half of the sum of the left offset of the first target signal line and the left offset of the second target signal line as the total left offset of multiple target signal lines; taking half of the sum of the right offset of the first target signal line and the right offset of the second target signal line as the total right offset of multiple target signal lines; and applying the total left offset and the total right offset to multiple target signal lines at the same time to obtain the delay value of the third left boundary and the delay value of the third right boundary of multiple target signal lines.

[0087] For example, the target signal line is a DCA signal line in an MRDIMM, where there are seven DCA signal lines. To shorten the retraining time (i.e., avoid retraining every DCA signal line), at least one embodiment of the present disclosure retrains only the two DCA signal lines with the largest and smallest left and right boundary delay values ​​obtained after the retraining initialization operation. Specifically, the following describes the DCA signal line with the largest left and right boundary delay value obtained after the retraining initialization operation (referred to as the "DCA_max signal line") as an example.

[0088] First, the delay values ​​of the second left and right boundaries of the DCA_max signal line after the retraining initialization operation are recorded. Then, a second stimulus (e.g., "...000010000...") is added to the DCA_max signal line to obtain the delay values ​​of the third left and right boundaries through the retraining operation. Finally, the offset of the delay values ​​of the third left and right boundaries of the DCA_max signal line relative to the delay values ​​of the second left and right boundaries is calculated. For example, after the retraining initialization operation, the delay values ​​of the second left and right boundaries are 1.1ns and 1.5ns, respectively, and the delay values ​​of the third left and right boundaries are 1.5ns and 1.9ns, respectively, indicating left and right offsets of 0.4ns in the positive and negative directions. The specific operation method for the DCA signal line with the smallest left and right boundary delay values ​​obtained after the retraining initialization operation is similar and will not be repeated here. For example, if the DCA signal line with the smallest left and right boundary delay values ​​(referred to as the "DCA_min signal line") obtained after the retraining initialization operation has left and right offsets of 0.2ns and 0.2ns, the calculated total left offset is 0.3ns and the calculated total right offset is 0.3ns. This total left offset of 0.3ns and the calculated total right offset of 0.3ns are then applied to the seven DCA signal lines to determine the final left and right boundary delay values ​​for each DCA signal line. For example, for one of the seven DCA signal lines (denoted as DCA_3), the second left and right boundary delay values ​​obtained after the retraining initialization operation for this DCA_3 signal line are 0.9s and 1.2ns, respectively. Therefore, the third left and right boundary delay values ​​for this DCA_3 signal line are 1.2ns and 1.5ns, respectively. The calculation method for the remaining six DCA signal lines is similar and will not be further described here.

[0089] For example, after obtaining the delay values ​​of the third left and right boundaries of the seven DCA signal lines, half of the sum of the delay values ​​of the third left and right boundaries of the seven DCA signal lines is used as the final delay value of the seven DCA signal lines. For example, the final delay value of the DCA_3 signal line is 1.35 ns. The calculation method for the remaining DCA signal lines is similar and is not further described here.

[0090] At least one embodiment of the present disclosure provides a DCA signal line retraining method that only requires retraining the two DCA signal lines with the smallest and largest delays obtained after retraining initialization. Finally, the average value is taken and applied to all DCA signal lines, greatly reducing the time consumed in retraining all DCA signal lines.

[0091] While the above embodiment performs initialization training on all seven DCA signal lines to obtain the first and second target signal lines, the embodiments of the present disclosure are not limited thereto. For example, initialization training can be performed on a subset of all target signal lines to obtain the first and second target signal lines. This approach can further reduce the time required to retrain all DCA signal lines. For example, this method is applicable when the wiring lengths of all target signal lines are substantially the same.

[0092] For example, in one possible embodiment, the target signal lines include chip select signal lines and command and address signal lines, and the retraining method further includes: configuring the register clock driver to enter an accelerated command and address signal line training mode, wherein the accelerated command and address signal line training mode supports retraining operations of both the chip select signal lines and the command and address signal lines.

[0093] For example, in the Enhanced DCA training mode, the chip select and command and address lines can be retrained without switching modes. For example, the chip select line can be retrained first, followed by the command and address lines without switching training modes, improving the efficiency of retraining between different signal lines.

[0094] Figure 2 A schematic diagram of the architecture of a retraining method according to at least one embodiment of the present disclosure is shown. This schematic diagram is intended to describe an exemplary application scenario (e.g., an application scenario for retraining the chip select signal (DCS) and command and address signal (DCA) of an MRCD in an MRDIMM) to implement one or more aspects of the data signal retraining method for a memory module according to at least one embodiment of the present disclosure. However, the present disclosure is not limited thereto.

[0095] like Figure 2As shown, this retraining method can be applied to two sets of input signals to the MRCD in an MRDIMM: the chip select signal (DCS) and the command and address signal (DCA). Chip select signal / command and address signal initialization training can correspond to step S100 described above; chip select signal / command and address signal retraining initialization 1 and chip select signal / command and address signal retraining initialization 2 can correspond to step S110 described above. Chip select signal / command and address signal retraining initialization 1 can be implemented via software, while chip select signal / command and address signal retraining initialization 2 can be implemented via hardware. Chip select signal / command and address signal retraining can correspond to steps S120 and S130 described above. Initialization training uses a first stimulus (e.g., a complex stimulus), while retraining initialization and retraining both use a second stimulus (e.g., a simple stimulus, such as "...00001000..."). The trained chip select signal lines or command and address signal lines are sent to the memory multiplexer clock driver via the chip select signal generator or command and address signal generator via the physical layer interface. The specific operation method is described above and will not be repeated here.

[0096] For example, taking the initialization training operation as an example, after the DDR is powered on, the chip select signal / command address signal line is initialized and trained using a first stimulus (e.g., complex stimulus) to obtain an initial delay value. This initial delay value is then compensated to the chip select signal / command address signal line generator. The chip select signal / command address signal line generator aligns the generated chip select signal (CS), command and address signal (CA) with the system clock signal (CK) before sending it to the physical layer interface. The physical layer interface configures the received chip select signal (CS), command and address signal (CA) and system clock signal (CK) into an input chip select signal (DCS), input command and address signal (DCA), and input clock signal (DCK), which are then forwarded to the memory multiplexer clock register driver for allocation to the various DRAMs in the MRDIMM for use. The data transmission process in the remaining three retraining schemes is similar to that in initialization training and will not be further described here.

[0097] Figure 3 The figure shows examples of left and right boundary waveforms of a chip select signal line before and after offset according to at least one embodiment of the present disclosure.

[0098] like Figure 3 As shown, for Figure 3In the upper half of the diagram, DCK is the clock signal line, DCS1 is the sampling identification signal line (i.e., DCS1 has completed the retraining operation), and DCS0 is the target signal line to be retrained (specifically, including DCS0 before and after the offset). The initial left boundary is the second left boundary mentioned above, and the delay value of the initial left boundary is the delay value of the second left boundary mentioned above, that is, the delay value of the left boundary obtained after the retraining initialization operation. The rising edge of DCK is the sampling moment, and this sampling moment falls within the low-level range of DCS1. That is, at the moment of the DCK clock rising edge, the sampling identification signal of DCS1 is low, allowing other signals (e.g., DCS0) to be correctly sampled. It should be noted that when the sampling moment is exactly in the middle of the low-level range of DCS1, this corresponds to the optimal sampling moment. The stimulus applied to DCS0 (i.e., the second stimulus mentioned above) is a simple binary number sequence "...00001000...". For DCS0 before the shift (i.e., DCS0 initialized after retraining), its initial left boundary is located at the rising edge transition from "0 to 1". For example, the delay value of the initial left boundary is 1ns. As the temperature and voltage increase, the left boundary of DCS0 shifts (e.g., Figure 3 offset to the right as shown), and thus Figure 3 The new left boundary shown is no longer aligned with the optimal sampling moment (the signal collected at the optimal sampling moment is 0), and the offset DCS0 needs to be retrained. Specifically, taking the initial left boundary delay value of 1ns as a benchmark, the delay value of the left boundary is gradually reduced in the reverse direction at a certain unit time length (for example, 0.1ns) so that the offset DCS0 moves to the left so that the data collected at the optimal sampling moment is a rising jump from "0 to 1". The delay value recorded at this time is the delay value of the new left boundary after retraining. For example, when the delay value of the left boundary is adjusted to 0.8ns, the collected data is a jump from "0 to 1". At this time, the delay value of the new left boundary is 0.8ns, that is, the delay value of the third left boundary is 0.8ns.

[0099] For Figure 3 The lower half of the initial right boundary is the second right boundary mentioned above, and the delay value of the initial right boundary is the delay value of the second right boundary mentioned above, that is, the delay value of the right boundary obtained after the retraining initialization operation. Similar to the left boundary mentioned above, for DCS0 before the shift (that is, DCS0 after retraining initialization), its initial right boundary is located at the falling edge transition from "1 to 0". For example, the delay value of the initial right boundary is 1.5ns. As the temperature and voltage increase, the right boundary of DCS0 shifts (for example Figure 3 offset to the right as shown), and thus Figure 3The new right boundary shown is no longer aligned with the optimal sampling moment (the signal collected at the optimal sampling moment is 1), and the offset DCS0 needs to be retrained. Specifically, based on the initial right boundary delay value of 1.5ns, the delay value of the left boundary is gradually reduced in the opposite direction at a certain unit time length (for example, 0.1ns) so that the offset DCS0 moves to the left so that the data collected at the optimal sampling moment is a falling jump from "1 to 0". The delay value recorded at this time is the delay value of the new right boundary after retraining. For example, when the delay value of the right boundary is adjusted to 1.3ns, the data collected is a jump from "1 to 0". At this time, the delay value of the new right boundary is 1.3ns, that is, the delay value of the third right boundary is 1.3ns.

[0100] After obtaining the new delay values ​​for the left and right boundaries (i.e., the delay values ​​for the third left and right boundaries), half of the sum of these new delay values ​​(e.g., 0.8 ns and 1.3 ns) is used as the final delay value for DCS0 after the shift, which is 1.05 ns. The updated DCS0 delay value of 1.05 ns is then applied to DCS0 to eliminate the effect of the shift.

[0101] The DCS signal line retraining method provided by at least one embodiment of the present disclosure can effectively avoid the problem of large deviation in retraining results caused by different excitation complexities, improve the effect of retraining, and thus ensure that memory reading and writing are not affected when temperature and voltage drift occur.

[0102] Figure 4 Examples of left and right boundaries before and after the shift of command and address signal lines according to at least one embodiment of the present disclosure are shown.

[0103] like Figure 4 As shown, DCK is the clock signal line, DCS0 is the sampling identification signal line (i.e., DCS0 has completed the retraining operation), and the DCA signal line with the largest delay after retraining initialization (denoted as the "DCA_max signal line") is the target signal line to be retrained. The initial left boundary is the second left boundary mentioned above, and the delay value of the initial left boundary is the delay value of the second left boundary mentioned above, that is, the delay value of the left boundary obtained after the retraining initialization operation. The DCA_max signal line is also loaded with a simple binary number sequence "...00001000..." (i.e., the second stimulus). The method for obtaining the new delay values ​​of the left and right boundaries of the DCA_max signal line is the same as Figure 3 The DCS0 is similar and will not be described here.

[0104] It should be noted that for the DCA_max signal line, it is also necessary to further obtain the left offset and right offset of the delay values ​​of the new left and right boundaries relative to the delay values ​​of the initial left and right boundaries (i.e., drift_left_max and drift_right_max in the figure). Figure 4 In the upper half of the left boundary, the initial delay value is 1.6ns, and the new delay value is 1.62ns, that is, drift_left_max is 0.02ns in the positive direction. Figure 4 In the lower half of the image, the initial right boundary delay value is 2.6ns, and the new right boundary delay value is 2.625ns, that is, drift_right_max is 0.025ns in the positive direction (the new left and right boundary delay values ​​are the delay values ​​of the third left and right boundaries).

[0105] Using the same method, we can obtain the left and right offsets (drift_left_min and drift_right_min) of the new left and right boundary delays of the DCA signal line with the minimum delay after retraining and initialization (denoted as the "DCA_min signal line") relative to the initial left and right boundary delays. For example, if the initial left boundary delay is 1.58ns, the new left boundary delay is 1.59ns, meaning that drift_left_min is 0.01ns in the positive direction. If the initial right boundary delay is 2.58ns, the new right boundary delay is 2.595ns, meaning that drift_right_min is 0.015ns in the positive direction.

[0106] Use half the sum of drift_left_max and drift_left_min (0.015ns in the positive direction) as the total left skew for all DCA lines. Use half the sum of drift_right_max and drift_right_min (0.02ns in the positive direction) as the total right skew for all DCA lines. For example, the final delay values ​​for the third left and right edges of the DCA_max line should be 1.615ns and 2.62ns, respectively; the final delay values ​​for the third left and right edges of the DCA_min line should be 1.595ns and 2.6ns, respectively. Consequently, the final delay values ​​for the DCA_max line are 2.1175ns, and the final delay values ​​for the DCA_min line are 2.0975ns. Since there are seven DCA lines in total, the calculation methods for the remaining five are similar and are not detailed here.

[0107] At least one embodiment of the present disclosure provides a retraining method for DCA signal lines. Because temperature and voltage drift are directly proportional to line delay, particularly clock tree length, retraining is performed only on the DCA signal lines with the maximum and minimum delays obtained after retraining initialization. The average value is then taken and applied to all DCA signal lines, significantly reducing the time required to retrain all DCA signal lines.

[0108] The embodiment of the present disclosure further provides a retraining device for a clock register driver of a storage system. Figure 5 A schematic diagram of a weight training device according to at least one embodiment of the present disclosure is shown.

[0109] like Figure 5 As shown, the retraining device 500 includes an initialization training module 510, a retraining initialization module 520, a retraining module 530, and a computing module 540. For example, these units can be implemented by hardware (e.g., circuit) modules or software modules, etc. The following embodiments are the same and will not be repeated here. For example, these units can be implemented by a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a field programmable gate array (FPGA), or other forms of processing units with data processing capabilities and / or instruction execution capabilities, and corresponding computer instructions.

[0110] Initialization training module 510 is configured to, in response to receiving an initialization training request, perform an initialization training operation on the target signal line using a first stimulus to obtain a delay value of a first left boundary and a delay value of a first right boundary of the target signal line. For example, initialization training module 510 may implement step S100 described above. The specific implementation method thereof may be referred to the description of step S100 and will not be further described here.

[0111] The retraining initialization module 520 is configured to perform a retraining initialization operation on the target signal line using the second stimulus based on the delay value of the first left boundary and the delay value of the first right boundary to obtain the delay value of the second left boundary and the delay value of the second right boundary of the target signal line. For example, the retraining initialization module 520 can implement the above-mentioned step S110. The specific implementation method thereof can be referred to the relevant description of step S110 and will not be repeated here.

[0112] The retraining module 530 is configured to retrain the target signal line using a second stimulus, based on the delay value of the second left boundary and the delay value of the second right boundary, to obtain a delay value of a third left boundary and a delay value of a third right boundary of the target signal line, wherein the number of changes between the high level and the low level of the bit of the first stimulus is greater than the number of changes between the high level and the low level of the bit of the second stimulus. For example, the retraining module 530 can implement the above-mentioned step S120. The specific implementation method thereof can be referred to the relevant description of step S120 and is not repeated here.

[0113] The calculation module 540 is configured to calculate the final delay value of the target signal line based on the delay value of the third left boundary and the delay value of the third right boundary. For example, the calculation module 540 can implement the above-mentioned step S130. The specific implementation method can be referred to the relevant description of step S130 and will not be repeated here.

[0114] It should be noted that for the sake of clarity and brevity, the embodiments of this disclosure do not illustrate all components of the weight training device 500. To achieve the necessary functions of the weight training device 500, those skilled in the art may provide or configure other components not shown as needed, and the embodiments of this disclosure are not limited thereto.

[0115] For example, in one possible embodiment, the retraining initialization module 520 is configured to perform a retraining initialization operation on the target signal line using a second stimulus through upper computer operation based on the delay value of the first left boundary and the delay value of the first right boundary to obtain the delay value of the second left boundary and the delay value of the second right boundary of the target signal line.

[0116] For example, in one possible embodiment, the retraining initialization module 520 is configured to trigger the retraining hardware acceleration module based on the delay value of the first left boundary and the delay value of the first right boundary, and use the second stimulus to perform a retraining initialization operation on the target signal line to obtain the delay value of the second left boundary and the delay value of the second right boundary of the target signal line.

[0117] For example, in one possible embodiment, the retraining device 500 also includes a second retraining initialization module, which is configured to trigger the retraining hardware acceleration module based on the delay value of the second left boundary and the delay value of the second right boundary of the target signal line, and use the second stimulus to perform a retraining initialization operation on the target signal line to obtain a new delay value of the second left boundary and a new delay value of the second right boundary of the target signal line and use them as the delay value of the second left boundary and the delay value of the second right boundary.

[0118] For example, in one possible implementation, the bits of the first stimulus and the bits of the second stimulus are binary bits, wherein the first stimulus is a pseudo-random number sequence, and the number of changes between the high level and the low level of the binary bit of the second stimulus is equal to 2.

[0119] For example, in one possible embodiment, the retraining module 530 is configured to adjust the size of the delay value of the second left boundary and the delay value of the second right boundary of the target signal line so that the sampling result of the target signal line is located at the signal jump of the target signal line loaded with the second stimulus to obtain the delay value of the third left boundary and the delay value of the third right boundary of the target signal line.

[0120] For example, in a possible implementation, the sampling result is obtained by sampling the target signal line loaded with the second stimulus in response to the sampling identification signal line being valid and the sampling moment being at the rising edge of the clock signal line.

[0121] For example, in one possible embodiment, the calculation module 540 is configured to take half of the total delay value of the target signal line as the final delay value of the target signal line, where the total delay value is equal to the sum of the delay value of the third left boundary and the delay value of the third right boundary of the target signal line.

[0122] For example, in one possible embodiment, in response to the number of target signal lines, the initialization training module 510 is configured to perform an initialization training operation on the multiple target signal lines to obtain the delay values ​​of the first left boundary and the delay values ​​of the first right boundary of the multiple target signal lines and select the first target signal line and the second target signal line therefrom, wherein the first target signal line is the target signal line with the delay value of the first left boundary and the delay value of the first right boundary, and the second target signal line is the target signal line with the smallest delay value of the first left boundary and the delay value of the first right boundary; the retraining module 530 is configured to calculate the delay values ​​of the first target signal line and the second target signal line, respectively. The left offset and right offset of the delay value of the third left boundary and the delay value of the third right boundary of the signal line relative to the delay value of the second left boundary and the delay value of the second right boundary; taking half of the sum of the left offset of the first target signal line and the left offset of the second target signal line as the total left offset of multiple target signal lines; taking half of the sum of the right offset of the first target signal line and the right offset of the second target signal line as the total right offset of multiple target signal lines; and applying the total left offset and the total right offset to multiple target signal lines at the same time to obtain the delay value of the third left boundary and the delay value of the third right boundary of multiple target signal lines.

[0123] For example, in one possible implementation, the memory module includes a registered clock driver, and the target signal line includes at least one of the following: a chip select signal line, a command and address signal line, a data signal line, and a data strobe signal line.

[0124] For example, in one possible embodiment, the retraining device 500 further includes a mode configuration module configured to configure the register clock driver to enter an accelerated command and address signal line training mode, wherein the accelerated command and address signal line training mode supports retraining operations on both the chip select signal line and the command and address signal lines.

[0125] In addition, it should be noted that, unless otherwise specified, the above modules or units can be implemented by software, hardware, firmware, or a combination thereof.

[0126] At least one embodiment of the present disclosure further provides an electronic device. Figure 6 A schematic diagram of an electronic device according to at least one embodiment of the present disclosure is shown.

[0127] For example, Figure 6 As shown, the electronic device 600 includes a processor 610 and a memory 620. The memory 620 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 610 is used to execute the computer program instructions. When the computer program instructions are executed by the processor 610, the retraining method provided by any embodiment of the present disclosure is executed. The memory 620 and the processor 610 can be interconnected via a bus system and / or other form of connection mechanism (not shown).

[0128] The processor 610 may be a device with data processing and / or program execution capabilities, such as a central processing unit (CPU), a tensor processing unit (TPU), a network processor (NP), or a graphics processing unit (GPU). It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. For example, the central processing unit (CPU) may be an X86 or ARM architecture. The processor 610 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 600 to perform desired functions.

[0129] For example, the memory 620 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, and the like. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 610 may execute one or more computer program modules to implement various functions of the electronic device 900. The computer-readable storage medium may also store various applications and various data, as well as various data used and / or generated by the applications.

[0130] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the electronic device 600 can be referred to the above description of the retraining method, which will not be repeated here.

[0131] At least one embodiment of the present disclosure further provides a non-transitory storage medium. Figure 7 A schematic diagram of a computer-readable storage medium provided for at least one embodiment of the present disclosure. Figure 7 As shown, the storage medium 700 non-transitorily stores computer-executable instructions 710 . When the non-transitory computer-executable instructions 710 are executed by a computer (including a processor), the retraining method of any embodiment of the present disclosure can be executed.

[0132] For example, one or more computer instructions may be stored on the storage medium 700. Some of the computer instructions stored on the storage medium 700 may be, for example, instructions for implementing one or more steps in the above-mentioned retraining method.

[0133] For example, the storage medium may include a tablet computer storage component, a personal computer hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), compact disc read-only memory (CD-ROM), flash memory, or any combination thereof, or other suitable storage media. For example, the storage medium 700 may include the memory 620 in the aforementioned electronic device 600.

[0134] The technical effects of the storage medium provided by the embodiments of the present disclosure can be referred to the corresponding description of the retraining method in the above embodiments, which will not be repeated here.

[0135] Figure 8 A schematic diagram illustrating an electronic device according to at least another embodiment of the present disclosure is shown. Figure 8 The electronic device 800 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0136] like Figure 8 As shown, in some examples, electronic device 800 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 801, which can include a processor core of any of the above-described embodiments. It can perform various appropriate actions and processes based on programs stored in a read-only memory (ROM) 802 or programs loaded from a storage device 808 into a random access memory (RAM) 803. RAM 803 also stores various programs and data required for the operation of the computer system. Processing device 801, ROM 802, and RAM 803 are connected to each other via a bus 1104. An input / output (I / O) interface 805 is also connected to bus 1104.

[0137] For example, the following components may be connected to the I / O interface 805: an input device 806 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; an output device 807 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; a storage device 808 including, for example, a magnetic tape, hard disk, etc.; and a communication device 809, which may also include, for example, a network interface card such as a LAN card or modem. The communication device 809 may allow the electronic device 800 to communicate with other devices wirelessly or wired to exchange data, performing communication processing via a network such as the Internet. A drive 810 is also connected to the I / O interface 805 as needed. Removable media 811, such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed in the drive 810 as needed, so that computer programs read from the removable media can be installed into the storage device 808 as needed.

[0138] Although Figure 8 The electronic device 800 is shown as including various devices, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0139] For example, the electronic device 800 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 809 may communicate with a network and other devices via wireless communication, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communications may use any of a variety of communication standards, protocols, and technologies, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0140] For example, the electronic device 800 may include any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or may be a combination of any data processing device and hardware, and the embodiments of the present disclosure do not limit this.

[0141] Regarding this disclosure, the following points need to be explained:

[0142] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design.

[0143] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0144] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for retraining a data signal of a memory module, comprising: In response to receiving the initialization training request, performing an initialization training operation on the target signal line using a first stimulus to obtain a delay value of a first left boundary and a delay value of a first right boundary of the target signal line; Based on the delay value of the first left boundary and the delay value of the first right boundary, using a second stimulus to perform a retraining initialization operation on the target signal line to obtain a delay value of a second left boundary and a delay value of a second right boundary of the target signal line; performing a retraining operation on the target signal line using the second stimulus based on the delay value of the second left boundary and the delay value of the second right boundary to obtain a delay value of a third left boundary and a delay value of a third right boundary of the target signal line, wherein the number of changes between the high level and the low level of the bit of the first stimulus is greater than the number of changes between the high level and the low level of the bit of the second stimulus; and A final delay value of the target signal line is calculated based on the delay value of the third left boundary and the delay value of the third right boundary.

2. The retraining method according to claim 1, wherein: The retraining initialization operation is performed on the target signal line using a second stimulus based on the delay value of the first left boundary and the delay value of the first right boundary to obtain a delay value of a second left boundary and a delay value of a second right boundary of the target signal line, comprising: Based on the delay value of the first left boundary and the delay value of the first right boundary, the host computer operates the second stimulus to perform the retraining initialization operation on the target signal line to obtain the delay value of the second left boundary and the delay value of the second right boundary of the target signal line.

3. The retraining method according to claim 1, wherein: The retraining initialization operation is performed on the target signal line using a second stimulus based on the delay value of the first left boundary and the delay value of the first right boundary to obtain a delay value of a second left boundary and a delay value of a second right boundary of the target signal line, comprising: Based on the delay value of the first left boundary and the delay value of the first right boundary, the retraining hardware acceleration module is triggered, and the retraining initialization operation is performed on the target signal line using the second stimulus to obtain the delay value of the second left boundary and the delay value of the second right boundary of the target signal line.

4. The retraining method according to claim 2, further comprising: Based on the delay value of the second left boundary and the delay value of the second right boundary of the target signal line, the retraining hardware acceleration module is triggered, and the retraining initialization operation is performed on the target signal line using the second stimulus to obtain a new delay value of the second left boundary and a new delay value of the second right boundary of the target signal line and use them as the delay value of the second left boundary and the delay value of the second right boundary.

5. The retraining method according to claim 1, wherein: The bits of the first stimulus and the bits of the second stimulus are binary bits, wherein, The first excitation is a pseudo-random number sequence, and the number of changes between a high level and a low level of a binary bit of the second excitation is equal to 2.

6. The retraining method according to claim 1, wherein: The retraining operation on the target signal line using the second stimulus to obtain a delay value of a third left boundary and a delay value of a third right boundary of the target signal line includes: Adjust the delay value of the second left boundary and the delay value of the second right boundary of the target signal line so that the sampling result of the target signal line is located at the signal jump of the target signal line loaded with the second excitation to obtain the delay value of the third left boundary and the delay value of the third right boundary of the target signal line.

7. The retraining method according to claim 6, wherein: The sampling result is obtained by sampling the target signal line loaded with the second stimulus in response to the sampling identification signal line being valid and the sampling moment being at the rising edge of the clock signal line.

8. The retraining method according to claim 1, wherein: The calculating, based on the delay value of the third left boundary and the delay value of the third right boundary, to obtain a final delay value of the target signal line includes: Half of the total delay value of the target signal line is used as the final delay value of the target signal line, wherein the total delay value is equal to the sum of the delay values ​​of the third left boundary and the third right boundary of the target signal line.

9. The retraining method according to claim 1, wherein: In response to the number of target signal lines being multiple, In response to receiving the initialization training request, performing an initialization training operation on the target signal line using a first stimulus to obtain a delay value of a first left boundary and a delay value of a first right boundary of the target signal line, comprising: performing the initialization training operation on the plurality of target signal lines to obtain delay values ​​of first left boundaries and first right boundaries of the plurality of target signal lines and selecting a first target signal line and a second target signal line therefrom, wherein the first target signal line is a target signal line having the largest delay value of the first left boundary and the first right boundary, and the second target signal line is a target signal line having the smallest delay value of the first left boundary and the first right boundary; The retraining operation on the target signal line using the second stimulus based on the delay value of the second left boundary and the delay value of the second right boundary to obtain the delay value of the third left boundary and the delay value of the third right boundary of the target signal line includes: respectively calculating left offsets and right offsets of the delay values ​​of the third left boundary and the third right boundary of the first target signal line and the second target signal line relative to the delay values ​​of the second left boundary and the second right boundary; taking half of the sum of the left offset of the first target signal line and the left offset of the second target signal line as the total left offset of the plurality of target signal lines; taking half of the sum of the right offset of the first target signal line and the right offset of the second target signal line as the total right offset of the plurality of target signal lines; and The total left offset and the total right offset are simultaneously applied to the plurality of target signal lines to obtain delay values ​​of the third left boundary and the third right boundary of the plurality of target signal lines.

10. The retraining method according to any one of claims 1 to 9, wherein: The memory module includes a register clock driver, and the target signal line includes at least one of the following: a chip select signal line, a command and address signal line, a data signal line, and a data strobe signal line.

11. The retraining method according to claim 10, wherein: The target signal lines include the chip select signal lines and the command and address signal lines, and the retraining method further includes: The registered clock driver is configured to enter an accelerated command and address signal line training mode, wherein the accelerated command and address signal line training mode supports the retraining operation of both the chip select signal line and the command and address signal lines.

12. A retraining device for a clock register driver of a memory module, comprising: an initialization training module configured to, in response to receiving an initialization training request, perform an initialization training operation on a target signal line using a first stimulus to obtain a delay value of a first left boundary and a delay value of a first right boundary of the target signal line; a retraining initialization module, configured to perform a retraining initialization operation on the target signal line using a second stimulus based on the delay value of the first left boundary and the delay value of the first right boundary to obtain a delay value of a second left boundary and a delay value of a second right boundary of the target signal line; a retraining module configured to perform a retraining operation on the target signal line using the second stimulus based on the delay value of the second left boundary and the delay value of the second right boundary to obtain a delay value of a third left boundary and a delay value of a third right boundary of the target signal line, wherein the number of changes between the high level and the low level of the bit of the first stimulus is greater than the number of changes between the high level and the low level of the bit of the second stimulus; as well as The calculation module is configured to calculate a final delay value of the target signal line based on the delay value of the third left boundary and the delay value of the third right boundary.

13. The weight training device of claim 12, wherein: The retraining initialization module includes a retraining hardware acceleration module, and the retraining initialization module is further configured to: Based on the delay value of the first left boundary and the delay value of the first right boundary, the retraining hardware acceleration module is triggered, and the retraining initialization operation is performed on the target signal line using the second stimulus to obtain the delay value of the second left boundary and the delay value of the second right boundary of the target signal line.

14. The weight training device of claim 12, wherein: In response to the number of target signal lines being multiple, The initialization training module is configured as follows: performing the initialization training operation on the plurality of target signal lines to obtain delay values ​​of first left boundaries and first right boundaries of the plurality of target signal lines and selecting a first target signal line and a second target signal line therefrom, wherein the first target signal line is a target signal line having the largest delay value of the first left boundary and the first right boundary, and the second target signal line is a target signal line having the smallest delay value of the first left boundary and the first right boundary; The retraining module is configured to: respectively calculating left offsets and right offsets of the delay values ​​of the third left boundary and the third right boundary of the first target signal line and the second target signal line relative to the delay values ​​of the second left boundary and the second right boundary; taking half of the sum of the left offset of the first target signal line and the left offset of the second target signal line as the total left offset of the plurality of target signal lines; taking half of the sum of the right offset of the first target signal line and the right offset of the second target signal line as the total right offset of the plurality of target signal lines; and The total left offset and the total right offset are simultaneously applied to the plurality of target signal lines to obtain delay values ​​of the third left boundary and the third right boundary of the plurality of target signal lines.

15. An electronic device comprising: at least one processor; At least one memory storing instructions, When the instruction is executed by the at least one processor, the at least one processor executes the retraining method according to any one of claims 1 to 11.

16. A computer-readable storage medium having computer-readable instructions stored thereon, in, When the computer-readable instructions are executed by a processor, the processor is caused to perform the retraining method according to any one of claims 1 to 11.

Images