16Bit off-chip one-time programmable circuit

Abstract

A 16Bit off-chip one-time programmable circuit belongs to the technical field of programming circuits and comprises a basic storage unit, a clock module, a pulse generator module, a counter module, a latch module, a codec module, a turn-off delay module and a switch module which are electrically connected. Under the combined action of related modules, the electromigration resistive random access memory comprises a resistance device, and the resistor is a common device in a circuit, so that the electromigration resistive random access memory is easy to implement, the manufacturing cost of a mask plate is reduced, the current generated by the resistor for generating electromigration is smaller than the current generated by fusing a FUSE resistor, and the performance of the electromigration resistive random access memory is improved. Metal splashing is not generated to influence the safety of surrounding circuits, and the area required by the electromigration resistive random access memory is small, so that the tape-out cost can be reduced; in addition, the comparator can detect small changes of the resistance value, the error-tolerant rate of data writing is increased to a certain extent, data can be written after being integrally packaged into a chip, and parameter calibration of the chip in the actual use environment is facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of storage circuits, in particular to a 16-bit off-chip one-time programmable circuit. Background Art

[0002] One-time programmable memory devices, classified as non-volatile memory (NVM), have irreversible programming. Because they are less expensive than multi-time programmable devices, they are suitable for low-cost electronic products with fixed programs, such as power management chips. Specifically, power management chips primarily utilize analog circuits, subject to process and manufacturing errors. Parameter calibration is often required for chips after tape-out (the transition from virtual chips to actual physical chips). This is accomplished by adding memory modules and register modules to the chip. After debugging, the determined values ​​are burned into the chip (non-volatile memory). When the chip is powered on, the values ​​in the memory modules are loaded into the registers, completing the calibration of the analog circuit parameters. A characteristic of non-volatile memory is that stored data persists even when the power is turned off. Traditional one-time programmable memory devices include fuses (which store information by blowing), Schottky diodes (which store information by thermal breakdown), and floating-gate transistors (which store information by injecting charge into the floating gate).

[0003] Existing memory devices based on Schottky diodes or crystal floating gates (one-time programmable memory devices) require special semiconductor process support. In addition, new layout levels will be introduced, and subsequent wafer fabs will require more layers of masks, increasing the chip tape-out production cost. In addition, memories based on FUSE resistors require applying voltage through a probe on the wafer to fuse the FUSE resistor (bare die, meaning an independent chip unit cut from the wafer and not packaged in semiconductor manufacturing) before chip packaging. This process will cause the FUSE metal to splash, affecting the safety of the circuits around the FUSE. In addition, incomplete blowing of the FUSE resistor may affect the accuracy of the written data. Summary of the Invention

[0004] In order to overcome the drawbacks of existing traditional one-time programmable memory devices due to technical limitations as described in the background technology, the present invention provides a finished product prepared by the joint action of relevant modules, which includes a resistor device. The electromigration resistive memory is easy to implement and reduces the mask production cost in the chip preparation process. The current required for the resistor to generate electromigration is small, and no metal splashing will be generated to affect the safety of surrounding circuits, which can reduce the wafer production cost. A comparator is used to judge the resistance change of the resistive memory to increase the data writing tolerance to a certain extent. Data can be written after the chip is packaged, which facilitates parameter calibration of the chip in the actual use environment. A 16-bit off-chip one-time programmable circuit.

[0005] The technical solution adopted by the present invention to solve its technical problem is: A 16-bit off-chip one-time programmable circuit, comprising an electrically connected basic storage unit, a clock module, a pulse generator module, a counter module, a latch module, a codec module, a shutdown delay module, and a switch module; the switch module and the counter module each have multiple channels, one end of the first switch module is connected to the first signal interaction end of the first counter module, the other end of the first switch module is connected to the first signal interaction end of the codec, the second signal interaction end of the first counter module is connected to the first signal interaction end of the shutdown delay module; the second signal of the codec module is connected to the first signal interaction end of the shutdown delay module; The signal interaction end is connected to the signal interaction end of the clock module and one end of the second switch module, the other end of the second switch module is connected to the first signal interaction end of the pulse generator module, the second signal interaction end of the pulse generator module is connected to the first signal interaction end of the second counter module and the first signal interaction end of the latch module; the second signal interaction end of the latch module is connected to the first signal interaction end and the second signal interaction end of the basic storage unit and the second signal interaction end of the encoder-decoder module, and the third signal interaction end of the encoder-decoder module is connected to the third signal interaction end of the basic storage unit.

[0006] Furthermore, the basic storage unit is composed of a PMOS tube and a resistor, a comparator chip, and a switch that are electrically connected. The PMOS tube, the resistor, and the comparator COMP together constitute a basic storage unit, namely, an OTP circuit.

[0007] Furthermore, in the basic storage unit, the PMOS tube generates two currents of equal size, namely a PMOS current mirror, which converts the resistance values ​​of the two resistors into voltages for comparison by the comparator chip; the first resistor serves as a reference resistor and has a resistance greater than that of the second resistor, and the second resistor serves as the object of electromigration current application; when the second resistor does not undergo electromigration, the resistance value of the first resistor is greater than that of the second resistor, and the comparator outputs a low level, that is, the memory stores "0"; when the second resistor undergoes electromigration and its resistance value is greater than that of the first resistor, the comparator outputs a high level, that is, the memory stores "1".

[0008] Furthermore, in the basic storage unit, the first switch is controlled by the comparator chip pin Din, and when the first switch is closed, "1" is written, and when the second switch is open, "0" is written; the second switch is controlled by the external write clock of the comparator chip, and when the second switch is closed, the storage unit enters the write mode; the third switch is controlled by the internal read clock of the comparator chip, and when the third switch is closed, the storage unit enters the read mode; the comparator chip reserves the pin Din to control the electromigration current, thereby obtaining a one-time programmable 1-bit storage unit that can be written off-chip; specifically, to realize the writing and reading of multiple data, the storage unit requires a set of serial write and read circuit modules, resulting in a 16-bit one-time programmable circuit based on pre-electromigration resistive memory.

[0009] Furthermore, the signal interaction end of the first counter module and the shutdown delay module is the EN enable pin. After the shutdown delay, the ENB signal is obtained to enable other circuits of the chip. The EN signal guides the OTP circuit into the write mode through the pulse counter.

[0010] Furthermore, when the encoder module is working, in write mode, the encoder module input is switched to the external write clock signal, and the encoder module sequentially outputs a 16-bit writable signal to enable the corresponding storage unit to enter write mode. The external data write pin of the storage unit can control the MOS gate voltage of the corresponding switch tube, thereby controlling the access of the electromigration current, and ultimately controlling whether the corresponding resistor produces an electromigration effect.

[0011] Furthermore, when the codec module is working, in the read mode, the codec module input is switched to its own internal write clock, and the codec module outputs 16-bit readable signals in sequence. The comparator judges the 16 resistors in sequence. If the resistor undergoes electromigration, the resistance value increases and the comparator outputs a high level. If the resistance value does not change, the comparator outputs a low level. At the same time, the rising edge of the read clock passes through the pulse generator module to obtain a narrow pulse Latch signal with a pulse width of 1us. The 1us time when Latch is at a high level is used for the comparator module to read, and the falling edge of the narrow pulse is used for latching by the latch module. The latch will latch the output result of the comparator, and the output signal Dout of the latch is the 16-bit output signal of the OTP memory.

[0012] Furthermore, when the second counter module is working, in the read mode, the second counter module counts the latch signal Latch of the latch module. After 16 read cycles, the output of the second counter module Sleep mode becomes high, shutting down all modules in the OTP circuit, reducing the static current of the OTP circuit, and the OTP circuit enters sleep mode to reduce circuit power consumption.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: under the joint action of the relevant modules, the finished product prepared by the present invention contains a resistor device in the semiconductor process. In addition, since the resistor is a commonly used device in the circuit, the electromigration resistive memory is easy to implement, and no new layout level will be introduced when the overall circuit is prepared into a chip, which reduces the mask production cost. The current that causes the resistor to generate electromigration is smaller than the current of the fuse resistor, and no metal splash will be generated to affect the safety of the surrounding circuits. There is no need to leave a large safety space for it on the layout. The electromigration resistive memory requires a small area, which can reduce the wafer cost. In addition, the comparator can detect slight changes in the resistance value, which increases the fault tolerance of data writing to a certain extent. The data can be written after the whole is packaged into a chip, which is convenient for calibrating the parameters of the chip in the actual use environment. In summary, the present invention has good application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0015] Figure 1 This is a schematic diagram of the structure of the basic storage unit (electromigration resistive memory) of the present invention.

[0016] Figure 2 It is a block diagram of the OTP circuit structure and a schematic diagram of its working principle of the present invention.

[0017] Figure 3 It is a timing diagram of the OTP circuit of the present invention.

[0018] Figure 4 This is a diagram of the resistance electromigration effect. DETAILED DESCRIPTION

[0019] Figure 1 、 2As shown in , 3, a 16-bit off-chip one-time programmable circuit includes a basic storage unit, a clock module, a pulse generator module, a counter module, a latch module, a codec module, a shutdown delay module, and a switch module connected by wires; the switch module and the counter module have multiple channels, one end of the first switch module is connected to the first signal interaction end of the first counter module, the other end of the first switch module is connected to the first signal interaction end of the codec, and the second signal interaction end of the first counter module is connected to the first signal interaction end of the shutdown delay module; the codec module The second signal interaction end of the block is connected to the signal interaction end of the clock module and one end of the second switch module, the other end of the second switch module is connected to the first signal interaction end of the pulse generator module, the second signal interaction end of the pulse generator module is connected to the first signal interaction end of the second counter module and the first signal interaction end of the latch module; the second signal interaction end of the latch module is connected to the first signal interaction end and the second signal interaction end of the basic storage unit and the second signal interaction end of the encoder-decoder module, and the third signal interaction end of the encoder-decoder module is connected to the third signal interaction end of the basic storage unit.

[0020] Figure 1 As shown in the figure, in the present invention, the basic storage unit is composed of PMOS tubes M0, M1, M2, resistors R1, R2, comparator chips COMP, switches S1, S2, S3, etc., which are electrically connected via wires. The PMOS tubes M1, M2, resistors R1, R2, and comparator COMP together constitute a basic storage unit, namely, an OTP circuit (single OTP circuit). The 16-bit OTP circuit introduced later is composed of 16 basic storage units. It is an expansion circuit of the basic storage unit and mainly solves problems such as serial writing, parallel output, and circuit operation timing. Specifically, PMOS transistors M1 and M2 generate two currents of equal magnitude (PMOS current mirrors), converting the resistance values ​​of resistors R1 and R2 into voltages for comparison by the comparator. Resistor R1 serves as a reference resistor with a resistance slightly greater than that of resistor R2. Resistor R2 is the target of the electromigration current I_EM. When electromigration does not occur in resistor R2, resistor R1 is slightly greater than resistor R2, and the comparator COMP outputs a low level, meaning the memory stores "0." When electromigration occurs in resistor R2 and its resistance value is greater than that of resistor R1, the comparator COMP outputs a high level, meaning the memory stores "1." Switch S1 is controlled by the comparator COMP pin Din. When switch S1 is closed, "1" is written, and when S2 is open, "0" is written. Switch S2 is controlled by the external write clock of the comparator COMP. When switch S2 is closed, the memory enters write mode. Switch S3 is controlled by the internal read clock of the chip. When switch S3 is closed, the memory enters read mode. The specific principle of the present invention is to use the electromigration effect of resistors to make a memory. Figure 1It is a basic storage unit. A large current I_EM causes the resistor R2 to produce an electromigration effect. After electromigration, the resistance of R2 increases. M1 and M2 are current sources of equal size. The resistance information is converted into voltage information, which is used by the comparator COMP to judge the resistance value. The comparator is used to judge the size of the resistance R2 and the reference resistance R1 to obtain information on whether electromigration occurs. If electromigration occurs, it is recorded as "1", and if no electromigration occurs, it is recorded as "0". The chip can reserve the pin Din to control the electromigration current, thereby obtaining a one-time programmable 1-bit storage unit that can be written off-chip.

[0021] Figure 1 、 2 As shown, the one-time programmable 1-bit storage unit of the present invention requires a set of serial writing and reading circuits to realize the writing and reading of multiple data. The following introduces a 16-bit one-time programmable circuit designed based on the electromigration resistive memory described above, hereinafter referred to as the OTP circuit. Figure 2 In the chip, the EN signal (peripheral circuit output) is the enable pin of the chip's counter module and shutdown delay module (peripheral circuit output). When the input is high, the ENB signal output by the shutdown delay module immediately becomes high, and the chip ( Figure 2The overall circuit structure begins operation. When the EN input is low, after a shutdown delay, ENB goes low, and the chip stops operating. When the EN input receives a continuous pulse signal, and the low-level duration of the pulse signal does not exceed the shutdown delay, a counter counts the pulses. When the counter counts seven pulses, the counter outputs the Wmode signal high, and the OTP circuit enters write mode. After the shutdown delay, the ENB signal is generated to enable other chip circuits. The EN signal, passing through the pulse counter, directs the OTP circuit into write mode. In write mode, the codec module input switches to the write clock CK_W signal (output by the peripheral circuit). The codec module sequentially outputs 16-bit write enable signals W<0:15>, placing the corresponding memory cells in write mode. Din is the external data write pin of the chip (basic memory cell). It controls the gate voltage of the switch MOSFET, thereby controlling the flow of the electromigration current I_EM, and ultimately controlling whether the corresponding resistor RES_EM generates an electromigration effect. In read mode, the encoder module input switches to the internal write clock, and the encoder module sequentially outputs 16-bit readable signals R<0:15>; the comparator sequentially judges the 16 resistors RES_EM. If the resistor undergoes electromigration, the resistance value increases, and the comparator module outputs a high level; if the resistance value does not change, the comparator outputs a low level; at the same time, the rising edge of the read clock passes through the pulse generator module to obtain a narrow pulse Latch signal with a pulse width of 1us. The 1us time when Latch is high is used for the comparator module to read, and the falling edge of the narrow pulse is used for latching in the latch module. The latch module latches the output result of the comparator, and the output Dout<0:15> of the latch module is the 16-bit ( Figure 2 The output signal of the overall circuit structure is shown in Figure 1. In read mode, the counter module counts the latch signal Latch. After 16 read cycles, the counter module outputs Sleep mode, which becomes high. This shuts down all modules in the OTP circuit, reducing the quiescent current of the OTP circuit. The OTP circuit enters sleep mode to reduce circuit power consumption.

[0022] Figure 3 The timing and mode of operation of the OTP circuit: Figure 3 is the OTP circuit ( Figure 2 Overall circuit configuration) using the timing diagram, OTP circuit ( Figure 2 The overall circuit structure) has three operating modes: write mode (the external pins of the OTP circuit are only EN, CK_W, Din, and the internal connections are detailed in the updated circuit block diagram Figure 3, where the lines with the same name are physically connected together, R<0:15> means there are 16 lines (R <0> 、R <1> ...R <15> ) For example, R <0> and the control signal R on the switch <0> Seven consecutive pulses on the EN pin put the circuit into write mode. At this point, writes can be made to the D0 memory module via the Din pin. A high level on Din writes a high level, and a low level writes a low level. Each rising edge of the write clock CK_W switches the circuit to write mode for the next memory bit, and writes to each bit in sequence until all 16 bits of memory are written.

[0023] When reading in read mode, after the circuit is enabled, when EN is continuously high, the circuit automatically enters read mode. With each rising edge of the read clock CK_R, the OTP circuit reads and latches one bit until all 16 bits are read. The internal latch is performed 1us after the rising edge of CK_R, so the pulse width of CK_R must be more than 2us to maintain a stable latch signal. In sleep mode, after 16 read clock cycles, the circuit automatically enters sleep mode to reduce power consumption (the external pins of the OTP circuit are EN, CK_W, and Din. When using, the user needs to follow Figure 3 The timing diagram of Figure 2 Input signals to the corresponding pins shown. In write mode, the chip's enable pin is connected to the internal counter and delay shutdown module, CK_W is connected to the internal codec, and the Din pin is connected to the control switch of the electromigration current source.

[0024] Figure 4 In the background technology, electromigration is the metal migration phenomenon caused by the action of current and temperature on metal wires. The moving electrons and the main metal lattice exchange momentum with each other. When metal atoms migrate along the direction of electron flow, voids are formed at their original positions. At the same time, the migration and accumulation of metal atoms form hillocks, which will increase the resistance of the metal wire or even cause it to break (forming an open circuit). Figure 1 、 2As shown in , 3, through the above technical solution, the present invention, under the joint action of relevant modules, the finished semiconductor process prepared includes a resistor device. In addition, since the resistor is a commonly used device in the circuit, the electromigration resistive memory is easy to realize, and no new layout level will be introduced when the overall circuit is prepared into the chip, which reduces the mask production cost. The current that causes the resistor to generate electromigration is smaller than the current of the fuse resistor, and no metal splash will be generated to affect the safety of the surrounding circuits. There is no need to leave a large safety space for it on the layout. The electromigration resistive memory requires a small area, which can reduce the wafer cost. In addition, the comparator can detect slight changes in the resistance value, which increases the fault tolerance of data writing to a certain extent. The data can be written after the whole is packaged into a chip, which is convenient for calibrating the parameters of the chip in the actual use environment.

[0025] The basic principles and main features of the present invention and the advantages of the present invention are shown and described above. It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive. The scope of the present invention is defined by the appended claims rather than the foregoing description, and all changes that come within the meaning and range of equivalents of the claims are intended to be included therein.

[0026] In addition, it should be understood that although this specification is described in terms of implementation methods, the implementation methods do not only include an independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A 16-bit off-chip one-time programmable circuit, characterized in that: It includes an electrically connected basic storage unit, a clock module, a pulse generator module, a counter module, a latch module, a codec module, a shutdown delay module, and a switch module; the switch module and the counter module have multiple channels respectively, one end of the first switch module is connected to the first signal interaction end of the first counter module, the other end of the first switch module is connected to the first signal interaction end of the codec, and the second signal interaction end of the first counter module is connected to the first signal interaction end of the shutdown delay module; the second signal interaction end of the codec module is connected to the signal interaction end of the clock module and one end of the second switch module, the other end of the second switch module is connected to the first signal interaction end of the pulse generator module, the second signal interaction end of the pulse generator module is connected to the first signal interaction end of the second counter module and the first signal interaction end of the latch module; the second signal interaction end of the latch module is connected to the first signal interaction end and the second signal interaction end of the basic storage unit and the second signal interaction end of the codec module, and the third signal interaction end of the codec module is connected to the third signal interaction end of the basic storage unit.

2. A 16-bit off-chip one-time programmable circuit according to claim 1, characterized in that: The basic storage unit is composed of an electrically connected PMOS tube, a resistor, a comparator chip, and a switch. The PMOS tube, the resistor, and the comparator COMP together constitute a basic storage unit, namely, an OTP circuit.

3. A 16-bit off-chip one-time programmable circuit according to claim 1, characterized in that: In the basic memory cell, a PMOS transistor generates two currents of equal magnitude, known as a PMOS current mirror, which converts the resistances of the two resistors into voltages for comparison in a comparator chip. The first resistor acts as a reference resistor, with a greater resistance than the second resistor, to which the electromigration current is applied. When electromigration does not occur in the second resistor, the first resistor's resistance is greater than that of the second resistor, and the comparator outputs a low level, meaning "0" is stored in the memory. When electromigration occurs in the second resistor, its resistance is greater than that of the first resistor, and the comparator outputs a high level, meaning "1" is stored in the memory.

4. A 16-bit off-chip one-time programmable circuit according to claim 1, characterized in that: In a basic memory cell, the first switch is controlled by the comparator chip's pin Din. When the first switch is closed, a "1" is written, and when the second switch is open, a "0" is written. The second switch is controlled by the comparator chip's external write clock. When the second switch is closed, the memory cell enters write mode. The third switch is controlled by the comparator chip's internal read clock. When the third switch is closed, the memory cell enters read mode. The comparator chip reserves the pin Din to control the electromigration current, thereby creating a one-time programmable 1-bit memory cell that can be written off-chip. Specifically, to achieve the writing and reading of multiple data, the memory cell requires a set of serial write and read circuit modules, resulting in a 16-bit one-time programmable circuit based on pre-electromigration resistive random access memory.

5. The 16-bit off-chip one-time programmable circuit according to claim 1, characterized in that: The signal interaction end of the first counter module and the shutdown delay module is the EN enable pin. After the shutdown delay, the ENB signal is obtained to enable other circuits of the chip. The EN signal guides the OTP circuit into write mode through the pulse counter.

6. A 16-bit off-chip one-time programmable circuit according to claim 1, characterized in that: When the codec module is working, in write mode, the codec module input is switched to the external write clock signal, and the codec module outputs 16-bit writable signals in sequence to make the corresponding storage unit enter write mode. The external data write pin of the storage unit can control the MOS gate voltage of the corresponding switch tube, and then control the access of the electromigration current, and finally control whether the corresponding resistor produces an electromigration effect.

7. The 16-bit off-chip one-time programmable circuit according to claim 1, characterized in that: When the codec module is working, in the read mode, the codec module input is switched to its own internal write clock, and the codec module outputs 16-bit readable signals in sequence. The comparator judges the 16 resistors in sequence. If the resistor undergoes electromigration, the resistance value increases and the comparator outputs a high level. If the resistance value does not change, the comparator outputs a low level. At the same time, the rising edge of the read clock passes through the pulse generator module to obtain a narrow pulse Latch signal with a pulse width of 1us. The 1us time when Latch is high is used for the comparator module to read, and the falling edge of the narrow pulse is used for latching in the latch module. The latch will latch the output result of the comparator. The output signal Dout of the latch is the 16-bit output signal of the OTP memory.

8. The 16-bit off-chip one-time programmable circuit according to claim 1, characterized in that: When the second counter module is working, in read mode, the second counter module counts the latch signal Latch of the latch module. After 16 read cycles, the second counter module outputs Sleep mode and becomes high, turning off all modules in the OTP circuit, reducing the static current of the OTP circuit, and the OTP circuit enters sleep mode to reduce circuit power consumption.

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