Test circuit and memory

Abstract

The embodiment of the invention provides a test circuit and a memory, and the test circuit comprises a serial interface circuit which is connected with a test machine and is used for receiving an initial starting signal sent by the test machine and decoding the initial starting signal to obtain a first target signal; the testing module is also used for transmitting the testing result of the target address to the testing machine, and the testing machine determines whether the target address is invalid based on the testing result; the command decoding circuit is used for receiving the first target signal or the second target signal and decoding the first target signal to obtain a test starting signal for starting the built-in self-test module; or decoding the second target signal to obtain a decoding result which is used for testing the target address in the storage area; and the built-in self-test module is used for starting the test according to the test starting signal and sending a second target signal to the command decoding circuit after the test is started.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a test circuit and a memory. Background Art

[0002] With the continuous advancement of semiconductor technology, the demand for data transmission speeds in the manufacture and use of devices such as computers is increasing. Taking dynamic random access memory (DRAM) as an example, to ensure the correctness of its storage function, memory testing is required, such as performing built-in self-test (BIST). BIST is a testability technology that embeds test logic during the design phase, enabling chips to independently complete functional verification. Summary of the Invention

[0003] Embodiments of the present disclosure provide a test circuit and a memory.

[0004] In a first aspect, an embodiment of the present disclosure provides a test circuit, comprising:

[0005] a serial interface circuit connected to the test machine, configured to receive an initial startup signal sent by the test machine, decode the initial startup signal, and obtain a first target signal; and further configured to transmit a test result of the target address to the test machine, wherein the test machine determines whether the target address is invalid based on the test result;

[0006] a command decoding circuit, configured to receive the first target signal or the second target signal, decode the first target signal to obtain a test enable signal for enabling a built-in self-test module; or decode the second target signal to obtain a decoding result, wherein the decoding result is used to implement a test of the target address in the storage area;

[0007] The built-in self-test module is configured to start a test according to the test start signal, and send the second target signal to the command decoding circuit after starting the test.

[0008] In some embodiments, the transmission port between the serial interface circuit and the test machine includes: a first data port, a clock port, and a second data port;

[0009] The first data port is used for the test machine to send a data signal to the serial interface circuit;

[0010] The clock port is used for the test machine to send a clock signal to the serial interface circuit;

[0011] The second data port is used by the serial interface circuit to send a data signal to the test machine.

[0012] In some embodiments, the second target signal comprises a command address signal;

[0013] The command decoding circuit is used to decode the command address signal to obtain a command signal and an address signal; wherein the address signal is used to represent the target address in the storage area, and the command signal represents the operation performed on the target address; the target address corresponds to multiple storage units.

[0014] In some embodiments, the test circuit further comprises:

[0015] a data writing circuit, configured to write data to the plurality of storage cells corresponding to the target address based on the write command signal and the address signal when the command signal is a write command signal;

[0016] The data reading circuit is configured to read data from the plurality of storage units corresponding to the target address based on the read command signal and the address signal when the command signal is a read command signal.

[0017] In some embodiments, the test circuit further comprises:

[0018] a compression read circuit, configured to compress the data read from the plurality of storage cells corresponding to the target address, obtain the test result and send it to the serial interface circuit, wherein the test result is single-bit data;

[0019] Among them, the multiple storage cells corresponding to the target address are divided into multiple storage cell columns, and the same data is written into the multiple storage cell columns. If the data read from the multiple storage cell columns are all the same, the test result obtained after the compression processing is a first value; if there is at least one difference in the data read from the multiple storage cell columns, the test result obtained after the compression processing is a second value.

[0020] In some embodiments, when the test result is the first value, the test machine determines that the target address is not failed; when the test result is the second value, the test machine determines that the target address is failed.

[0021] In some embodiments, the built-in self-test module is configured to sequentially send a plurality of the second target signals to the command decoding circuit in a preset order;

[0022] The testing machine is used to determine the target address corresponding to the current test result according to the preset sequence.

[0023] In some embodiments, the test circuit further includes an input buffer circuit and an input circuit;

[0024] The serial interface circuit is further configured to receive a test entry signal sent by the test machine, generate a port closing signal according to the test entry signal, and use the port closing signal to close the input buffer circuit;

[0025] The input circuit is respectively connected to the serial interface circuit, the input buffer circuit and the built-in self-test module, and is used to send the first target signal or the second target signal or the third target signal output by the input buffer circuit to the command decoding circuit.

[0026] In some embodiments, the test circuit further includes a frequency multiplication circuit; the test machine sends a first clock signal to the serial interface circuit and the frequency multiplication circuit;

[0027] The frequency multiplication circuit is used to adjust the frequency of the first clock signal to obtain a second clock signal and send it to the built-in self-test module, so that the built-in self-test module operates under the second clock signal; the frequency of the second clock signal is higher than that of the first clock signal.

[0028] In some embodiments, the serial interface circuit includes a synchronous output circuit;

[0029] The synchronous output circuit is used to receive the test result, reduce the speed of the test result based on the first clock signal, and then send it to the test machine.

[0030] In some embodiments, the frequency multiplication circuit includes a delay circuit and an XOR gate;

[0031] The delay circuit is configured to receive a delay control signal and the first clock signal, and delay the first clock signal based on the delay control signal to obtain a delayed clock signal;

[0032] The first input end of the XOR gate is connected to the output end of the delay circuit for receiving the delayed clock signal; the second input end of the XOR gate is used to receive the first clock signal; and the output end of the XOR gate is used to output the second clock signal.

[0033] In a second aspect, an embodiment of the present disclosure provides a memory, comprising a storage area and a test circuit as described in any one of the first aspects;

[0034] The test circuit is connected to the test machine and is used to receive an initial start signal sent by the test machine through the serial interface circuit, and start the built-in self-test module based on the initial start signal to test the storage area.

[0035] An embodiment of the present disclosure provides a test circuit and a memory, wherein the test circuit includes: a serial interface circuit, connected to a test machine, for receiving an initial start signal sent by the test machine, decoding the initial start signal, and obtaining a first target signal; and also for transmitting a test result of a target address to the test machine, wherein the test machine determines whether the target address is invalid based on the test result; a command decoding circuit, for receiving a first target signal or a second target signal, decoding the first target signal, and obtaining a test start signal for starting a built-in self-test module; or decoding the second target signal to obtain a decoding result, wherein the decoding result is used to implement a test of a target address in a storage area; and a built-in self-test module, for starting a test according to the test start signal, and sending a second target signal to the command decoding circuit after starting the test.

[0036] In this way, on the one hand, the embodiment of the present disclosure uses a serial interface circuit to realize the connection between the test machine and the memory. When starting the test, the test machine sends an initial startup signal to the serial interface circuit. During the test, the serial interface circuit sends the test results to the test machine. Since the serial interface circuit transmits data in a serial manner, the initial startup signal and the test results are both transmitted in a serial manner, so only a small number of data ports are needed to realize data transmission. There is no need to set a large number of data ports for the test board connecting the memory and the test machine, which effectively saves the number of ports for transmitting data and thus saves hardware resources.

[0037] On the other hand, when starting the test, the serial interface circuit sends the first target signal obtained by decoding the initial start signal to the command decoding circuit, and the command decoding circuit decodes the first target signal to obtain a test start signal for starting the built-in self-test module; during the test process, the built-in self-test module sends the second target signal required for the test to the command decoding circuit, and the command decoding circuit decodes the second target signal to obtain a decoding result for implementing the test; in this way, the embodiment of the present disclosure reuses the command decoding circuit during the startup test and the test process, and there is no need to set up an additional circuit for starting the test, which saves memory area and hardware resources.

[0038] On the other hand, the command decoding circuit is a circuit that decodes command signals during the normal operation of the memory. During the startup test and the test process, the embodiment of the present disclosure reuses the command decoding circuit and other related circuits (such as data writing circuit and data reading circuit) of the memory during normal operation. Compared with the test scheme that uses two different paths for testing and normal operation respectively, the embodiment of the present disclosure does not need to configure related circuits for testing, thereby further saving the area and resources of the memory.

[0039] In addition, in some embodiments, the embodiments of the present disclosure also use a compression read circuit to generate a single-bit test result, which not only has a fast transmission speed but also saves the limited capacity of the test machine and prevents a large amount of data or addresses from occupying too much space on the test machine. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of a test system provided in an embodiment of the present disclosure Figure 1 ;

[0041] Figure 2 A schematic diagram of a test system provided in an embodiment of the present disclosure Figure 2 ;

[0042] Figure 3 A signal timing diagram provided in an embodiment of the present disclosure;

[0043] Figure 4 A schematic diagram of a test system provided in an embodiment of the present disclosure Figure 3 ;

[0044] Figure 5 A schematic diagram of data compression provided by an embodiment of the present disclosure;

[0045] Figure 6 A schematic diagram of a test system provided in an embodiment of the present disclosure Figure 4 ;

[0046] Figure 7 A schematic diagram of the structure of a frequency multiplication circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to illustrate the relevant disclosure and are not intended to limit the disclosure. It should also be noted that for ease of description, only the portions relevant to the relevant disclosure are shown in the drawings.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0049] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0050] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0051] Before further explaining the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are explained first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0052] Built-in self-test (BIST);

[0053] Dynamic Random Access Memory (DRAM);

[0054] Double Data Rate DRAM (DDR DRAM);

[0055] Low Power Double Data Rate DRAM (LPDDR DRAM);

[0056] Pad (PAD);

[0057] Automatic Test Equipment (ATE);

[0058] Serial Peripheral Interface (SPI);

[0059] Command / Address (CA);

[0060] Chip Select (CS);

[0061] JEDEC (Joint Electron Device Engineering Council);

[0062] bit;

[0063] Input Buffer (IB);

[0064] Bank Group (BG);

[0065] Storage block (Bank, BK);

[0066] Read Latency (RL).

[0067] BIST is a testability technology that embeds test logic during the design phase, enabling chips to autonomously complete functional verification. Current BIST requires a large number of PADs to receive and transmit data, consuming significant hardware resources. Furthermore, memories like DRAM contain a large amount of address information. During BIST, failed addresses are sent to the ATE machine, which has limited memory capacity.

[0068] Based on this, an embodiment of the present disclosure provides a test circuit that uses a serial interface circuit to achieve a connection between a memory and a test circuit. When starting the test, the test machine sends a start signal to the serial interface circuit. Since the serial interface circuit transmits data in a serial manner, the number of ports for transmitting data can be saved, thereby saving hardware resources. During the test process, the command decoding circuit and other related circuits of the memory are reused when it is working normally. Compared with the test solution that uses two different paths for testing and normal operation, the embodiment of the present disclosure does not need to configure related circuits for testing, further saving the area and resources of the memory. In addition, the embodiment of the present disclosure also uses a compressed read circuit to generate a single-bit test result, which not only has a fast transmission speed, but also saves the limited capacity of the test machine, and avoids a large amount of data or addresses taking up too much space on the test machine.

[0069] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0070] In one embodiment of the present disclosure, see Figure 1 , which shows a schematic diagram of the composition structure of a test system 50 provided by an embodiment of the present disclosure. Figure 1 As shown, the test system 50 may include a memory 40 (or memory chip, Chip) and a test machine 30. The memory 40 includes a test circuit 10 and a storage area 20 (or memory array, Array).

[0071] The test machine 30 can be, but is not limited to, an ATE machine; the memory 40 can be, but is not limited to, DRAM; for example, it can also be SRAM or FLASH. The storage area 20 is the component of the memory 40 used to store data. The test circuit 10 is connected to the test machine 30 and is used to test the storage area 20 to determine whether addresses in the storage area 20 are invalid, such as read or write errors. Specifically, the serial interface circuit 101 receives an initial startup signal from the test machine 30 and activates the built-in self-test module 103 based on the initial startup signal to test the storage area 20.

[0072] like Figure 1 As shown, the test circuit 10 may include a serial interface circuit 101, a command decoding circuit 102, and a built-in self-test module 103. The serial interface circuit 101 is an interface circuit for serially receiving data. The serial interface circuit 101 operates according to its corresponding serial interface protocol, for example, decoding and transmitting received signals.

[0073] Here, the serial interface circuit 101 can be an SPI circuit, but is not limited thereto. SPI generally includes two modes: master and slave. In SPI communication, the master is responsible for controlling the initiation and termination of communication and timing, while the slave passively responds to the master's instructions to transmit data. In the embodiment of the present disclosure, the test machine 30 can serve as the master, and the memory 40 can serve as the slave responding to the test machine 30. In the subsequent description, the serial interface circuit 101 is taken as an SPI interface circuit as an example.

[0074] like Figure 1 As shown, in the embodiment of the present disclosure, the test machine 30 and the memory 40 communicate with each other through the serial interface circuit 101. The transmission ports between the serial interface circuit 101 and the test machine 30 include: a first data port Tdq0, a clock port clk, and a second data port Tdq1;

[0075] The first data port Tdq0 is used for the test equipment 30 to serially send data signals to the serial interface circuit 101. For example, the test equipment 30 serially sends an initial start signal for starting a built-in self-test or configuration information of the serial interface circuit 101 to the serial interface circuit 101 through the first data port Tdq0.

[0076] The clock port clk is used for the test machine 30 to send a clock signal to the serial interface circuit 101; the clock signal sent by the test machine 30 to the serial interface circuit 101 is recorded as the first clock signal;

[0077] The second data port Tdq1 is used for the serial interface circuit 101 to send data signals to the test machine 30; for example, the serial interface circuit 101 can send the test results of the built-in self-test to the test machine 30 via the second data port Tdq1, or the serial interface circuit 101 can respond to other requirements of the test machine 30 and reply with other required data signals.

[0078] In this way, only three data ports (corresponding to three PADs, ie, three pins) are needed between the test machine 30 and the memory 40 to implement signal transmission during the test process, smoothly start the built-in self-test, and transmit the test results.

[0079] In addition, if Figure 1 As shown, a reset port RESET_n may also be included. Reset port RESET_n is used by the test machine 30 to send a reset signal to the memory 40. The test machine 30 can also send a reset signal to the serial interface circuit 101 through reset port RESET_n to implement the corresponding reset function. In this way, only four PADs are required to implement the connection test. Taking LPDDR5 as an example, it requires 11 PADs, while this solution only requires four PADs, saving the number of PADs and hardware resources.

[0080] like Figure 1 As shown, in the test circuit 10, the serial interface circuit 101 is connected to the test machine 30 and is used to receive the initial start signal sent by the test machine 30, decode the initial start signal, and obtain the first target signal; it is also used to transmit the test result of the target address to the test machine 30, and the test machine 30 determines whether the target address is invalid based on the test result;

[0081] The command decoding circuit 102 is configured to receive a first target signal or a second target signal, decode the first target signal to obtain a test enable signal for enabling the built-in self-test module 103, or decode the second target signal to obtain a decoding result for implementing a test on a target address in the storage area 20.

[0082] The built-in self-test module 103 is configured to start a test according to a test start signal, and send a second target signal to the command decoding circuit 102 after starting the test.

[0083] It should be noted that the working process of the test circuit 10 can be divided into a test startup phase and a test phase, which are described below respectively. In the test startup phase:

[0084] The test machine 30 sends an initial startup signal serially to the serial interface circuit 101. The initial startup signal can be a data frame. The test machine 30 can send the data frame to the serial interface circuit 101 in accordance with the frame format specified by the SPI protocol. The data frame carries at least information for starting the test, and can also include other information such as a frame header and a frame footer. The serial interface circuit 101 decodes the information for starting the test in the initial startup signal to obtain a first target signal, and sends it to the command decoding circuit 102. The data format of the first target signal is a data format supported by the memory 40, such as a format specified by the standard formulated by JEDEC. Here, "information for starting the test" can be a piece of information in the initial startup signal, which can be the same as the first target signal, or needs to be further processed to be converted into the first target signal. The specific information is related to the interface protocol and the setting method, and is not specifically limited to this.

[0085] It should be noted that the aforementioned method of transmitting the initial start signal using a data frame is only an example. In practice, it is related to different chip manufacturers, circuit configurations, protocol regulations, etc.

[0086] The command decoding circuit 102 receives the first target signal sent by the serial interface circuit 101, decodes the first target signal, obtains a test start signal, and sends it to the built-in self-test module 103 to start the built-in self-test.

[0087] It should be noted that the command decoding circuit 102 can be an original circuit inside the memory 40. The embodiment of the present disclosure multiplexes the command decoding circuit 102, which can not only decode the first target signal for starting the built-in self-test, but also decode the second target signal during the test process to implement related test operations on the storage area 20.

[0088] Since command decoding circuit 102 is an existing circuit within memory 40, its decoding function is pre-designed and is typically used to decode the CA signal. Therefore, the first target signal may include the CA signal. For example, assuming the CA signal is 7 bits, the 7-bit CA signal obtained by the SPI interface circuit decoding the initial start signal can be recorded as: SPI CA<0:6>. Furthermore, the first target signal may also include a chip select signal. The chip select signal obtained by the SPI interface circuit decoding the initial start signal can be recorded as: SPI CS.

[0089] It should also be noted that the first target signal is used to activate the built-in self-test (BIST). Therefore, there are no specific requirements for the command and address corresponding to the first target signal. It is sufficient to ensure that the command decoding circuit 102 can successfully decode it, thereby generating a test activation signal to activate the built-in self-test module 103. For example, the tester 30 can use a fixed initial activation signal, which can then be decoded by the serial interface circuit 101 and the command decoding circuit 102 to generate a fixed test activation signal.

[0090] The built-in self-test module 103 receives the test start signal sent by the command decoding circuit 102 and starts the test (i.e., built-in self-test) based on the test start signal. The test circuit 10 enters the test phase:

[0091] After the test is started, the built-in self-test module 103 generates a second target signal and sends it to the command decoding circuit 102. The command decoding circuit 102 decodes the second target signal to obtain a decoding result, which is used to implement the test of the storage area 20, specifically the test of the target address indicated by the decoding result; the serial interface circuit 101 receives the test result of the target address and sends it to the test machine 30, so that the test machine 30 can determine whether the target address is invalid based on the test result.

[0092] In this way, on the one hand, the embodiment of the present disclosure uses the serial interface circuit 101 to realize the connection between the test machine 30 and the memory 40. When starting the test, the test machine 30 sends an initial startup signal to the serial interface circuit 101. During the test, the serial interface circuit 101 sends the test results to the test machine 30. Since the serial interface circuit 101 transmits data in a serial manner, the initial startup signal and the test results are both transmitted in a serial manner, so only a small number of data ports are needed to realize data transmission. There is no need to set a large number of data ports for the test board connecting the memory 40 and the test machine 30, which effectively saves the number of ports for transmitting data and thus saves hardware resources.

[0093] On the other hand, when starting the test, the serial interface circuit 101 sends the first target signal obtained by decoding the initial start signal to the command decoding circuit 102, and the command decoding circuit 102 decodes the first target signal to obtain a test start signal for starting the built-in self-test module 103; during the test process, the built-in self-test module 103 sends the second target signal required for the test to the command decoding circuit 102, and the command decoding circuit 102 decodes the second target signal to obtain a decoding result for implementing the test; in this way, the embodiment of the present disclosure reuses the command decoding circuit 102 during the startup test and the test process, and there is no need to set up an additional circuit for starting the test, which saves the area of ​​the memory 40 and saves hardware resources.

[0094] On the other hand, the command decoding circuit 102 is a circuit that decodes command signals during the normal operation of the memory 40. During the startup test and the test process, the embodiment of the present disclosure reuses the command decoding circuit 102 and other related circuits (such as data writing circuit and data reading circuit) of the memory 40 during normal operation. Compared with the test scheme that uses two different paths for testing and normal operation respectively, the embodiment of the present disclosure does not need to configure related circuits for testing, thereby further saving the area and resources of the memory 40.

[0095] It should be noted that the built-in self-test module 103 (i.e., the BIST circuit) is a test module built into the memory 40 (e.g., DRAM). It specifies a known command and data flow. At each known clock node, the operation within the built-in self-test module 103 can be determined. Therefore, after the built-in self-test module 103 is enabled, it sends the second target signal to the command decoding circuit 102 according to its internal specifications.

[0096] like Figure 1 As shown, the signal at the input end of the command decoding circuit 102 is recorded as the input target signal. In the test startup phase, the command decoding circuit 102 is controlled by the serial interface circuit 101, the input target signal is the first target signal, and the command decoding circuit 102 is used to decode the first target signal. At this time, the built-in self-test module 103 is not started and will not send the second target signal. In the test phase, the BIST is started, the serial interface circuit 101 is controlled by the built-in self-test module 103, the input target signal is the second target signal, and the command decoding circuit 102 is used to decode the second target signal. At this time, the serial interface circuit 101 will not send the first target signal.

[0097] It should be noted that the second target signal includes a CA signal, for example, a 7-bit CA signal. The 7-bit CA signal sent by the built-in self-test module 103 can be recorded as: BIST CA<0:6>; at the same time, the second target signal can also include a chip select signal. The chip select signal sent by the built-in self-test module 103 can be recorded as: BIST CS.

[0098] Accordingly, the decoding result obtained by the command decoding circuit 102 from decoding the second target signal may include a command signal and an address signal; wherein the address signal is used to represent the target address in the storage area 20, and the command signal indicates the operation to be performed on the target address; the target address corresponds to multiple storage cells. The memory 40 may include multiple chips, and the chip select signal is used to select the corresponding chip. When the chip select signal is enabled, the command decoding circuit 102 decodes the command address signal; otherwise, it does not decode the command address signal.

[0099] It should be noted that the second target signal is a signal used for addressing and performing related operations during the test process. The address signal can be used to locate the target address in the storage area 20. The multiple storage cells corresponding to the target address can be referred to as a storage cell group. For example, the storage area 20 includes multiple BGs, each BG includes multiple BKs, each BK includes multiple storage cell groups, each storage cell group includes multiple storage cells, and each storage cell is used to store 1 bit of data.

[0100] In the disclosed embodiments, the decoded address signal can be used to locate the corresponding storage cell group. The command signal indicates the operation to be performed on the target address, such as whether to write data, read data, or refresh the storage cell. By writing data to and reading data from the storage cell group, the target address is tested for failure.

[0101] It should also be noted that if all the data read from the storage unit is sent as test results to the test machine 30 for judgment, and the failure address is also sent to the test machine 30, it will not only take up a lot of time, but also occupy a lot of resources. The capacity of the test machine 30 is limited, which may affect the performance of the test machine 30. Therefore, the embodiment of the present disclosure adopts a compressed read method to obtain the test results and send them to the test machine 30. Figure 1 As shown, the test circuit 10 may further include:

[0102] The compression read circuit 104 is used to compress the data read from the multiple storage units corresponding to the target address, obtain a test result and send it to the serial interface circuit 101. The test result is single-bit data;

[0103] Among them, the multiple storage cells corresponding to the target address are divided into multiple storage cell columns, and the same data is written into the multiple storage cell columns. If the data read from the multiple storage cell columns are all the same, the test result obtained after compression processing is a first value. If there is at least one difference in the data read from the multiple storage cell columns, the test result obtained after compression processing is a second value.

[0104] Correspondingly, when the test result is the first value, the test machine 30 determines that the target address is not failed; when the test result is the second value, the test machine 30 determines that the target address is failed.

[0105] It should be noted that, taking a memory cell group comprising 256 memory cells as an example, the 256 memory cells can be divided into 32 memory cell columns (CPs), denoted as CP1, CP2, ..., CP32, each of which includes 8 memory cells. Here, a memory cell column can represent 8 memory cells connected by a bit line. During testing, the same data is written to the 32 CPs corresponding to the target address. The 8 bits of data written to each CP can be denoted as: CP1<0:7>, CP2<0:7>, ..., CP32<0:7>, where CP1<0:7> = CP2<0:7> = ... = CP32<0:7>. Data is read from each CP. The 8-bit data read from each CP can be recorded as CP1*<0:7>, CP2*<0:7>, ..., CP32*<0:7>. If CP1*<0:7>=CP2*<0:7>=...=CP32*<0:7>, the compression read circuit 104 compresses the read 256-bit data into a first value as a test result and sends it to the serial interface circuit 101. If any of the values ​​are not equal, the compression read circuit 104 compresses the read 256-bit data into a second value as a test result and sends it to the serial interface circuit 101. The first value and the second value are both 1-bit data (single-bit data). The serial interface circuit 101 only needs to send the 1-bit test result to the tester 30 via the second data port Tdq0. The tester 30 determines the test result based on whether the test result is the first value or the second value, saving data transmission time and space.

[0106] It should also be noted that the specific compression process can be implemented using XOR logic, XNOR logic, OR logic, NOR logic, etc., alone or in combination. For example: first, the data of the corresponding bits of the 8-bit data read from the 32 CPs are subjected to XOR logic processing, that is, CP1* <0> 、CP2* <0> 、……、CP32* <0> Perform XOR processing, CP1* <1> 、CP2* <1> 、……、CP32* <1> Perform XOR processing, ..., CP1* <7> 、CP2* <7> 、……、CP32* <7> Perform XOR processing, and each bit gets an XOR result, and finally gets an 8-bit XOR result. Since the corresponding bits are written with the same data, if the data read out of the corresponding bits are also the same, the XOR result of the bit is "0". If there is any difference, the XOR result is "1", that is, in the absence of a failed storage unit, the 8-bit XOR results should all be 0, otherwise, there will be an XOR result of "1". The 8-bit XOR result is further compressed. Assuming that the first value is "1" (the corresponding target address is not failed) and the second value is "0" (the corresponding target address is failed), the 8-bit XOR result can be compressed using NOR logic; assuming that the first value is "0" (the corresponding target address is not failed) and the second value is "1" (the corresponding target address is failed), the 8-bit XOR result can be compressed using OR logic.

[0107] It should be noted that the above-mentioned compressed read method is merely an example. Alternatively, the corresponding bits of the 8-bit data read from the 32 CPs may be subjected to XOR logic processing to obtain an 8-bit XOR result. Then, in combination with the specific settings for the first and second values, the 8-bit XOR result may be compressed into a single-bit test result using OR logic or NOR logic. Alternatively, the same data may be written to all 256 memory cells. In this case, there is no need to compare the corresponding bits of the memory cell columns. The 256 read data may be directly subjected to XOR logic or XOR logic processing to obtain a single-bit XOR logic result or a single-bit XOR logic result. Then, in combination with the specific settings for the first and second values, the OR logic result or the single-bit XOR logic result may be directly used as the test result, or the single-bit OR logic result or the single-bit XOR logic result may be inverted to obtain the final test result.

[0108] In this way, the embodiment of the present disclosure uses the compression read circuit 104 to compress the read 256-bit read data into single-bit data, and then the serial interface circuit 101 sends the single-bit test result to the test machine 30, which greatly reduces the amount of data sent and saves test costs.

[0109] It should also be noted that if Figure 1As shown, the built-in self-test module 103 is a test circuit inside the DRAM. The internal fixed test program will automatically traverse the address and call the compression read circuit 104 when the test is started. Figure 1 As shown, the built-in self-test module 103 sends a compression enable signal to the compression read circuit 104. When the compression enable signal is in an enabled state, the compression read circuit 104 performs a compression read function.

[0110] In this way, the compression read circuit 104 will perform the compression read function only after the test is started, thereby preventing data that may be generated during the test start-up phase from being transmitted to the test machine 30 and causing erroneous test results.

[0111] It should also be noted that, in order to ensure that the test machine 30 can accurately determine which target address is failed or not failed, the built-in self-test module 103 is used to send multiple second target signals to the command decoding circuit 102 in a preset order;

[0112] The testing machine 30 is used to determine the target address corresponding to the current test result according to a preset sequence.

[0113] It should be noted that the built-in self-test module 103 is a test module built into the memory 40. It specifies a known command and data flow, allowing the operation within the built-in self-test module 103 to be determined at each known clock node. Specifically, the tester 30 sends second command signals corresponding to different target addresses to the command decoding circuit 102 in a preset sequence, thereby traversing the target addresses in the storage area 20. After receiving the corresponding test result, the tester 30, because the preset sequence is known and the target address to which the test result corresponds is known, can determine the target address corresponding to the test result and parse the target address. This eliminates the need for the test circuit 10 to send address signals to the tester 30, simplifying the data transmission process and preventing excessive address information from occupying the limited storage space of the tester 30.

[0114] In some embodiments, as Figure 1 As shown, the test circuit 10 further includes:

[0115] The input circuit 105 is connected to the serial interface circuit 101 and the built-in self-test module 103 respectively, and is used to select the first target signal or the second target signal as the input target signal to be sent to the command decoding circuit 102 .

[0116] It should be noted that the serial interface circuit 101 and the built-in self-test module 103 do not simultaneously transmit the first target signal and the second target signal. The input circuit 105 may include a first OR logic circuit OR1, whose first input terminal receives the first target signal, whose second input terminal receives the second target signal, and whose output terminal is connected to the input terminal of the command decoding circuit 102. The first OR logic circuit OR1 operates in an OR logic mode to output the first target signal as the input target signal during the test startup phase and output the second target signal as the input target signal during the test phase.

[0117] Furthermore, if Figure 2 As shown, in some embodiments, the test circuit 10 may further include an input buffer circuit 106;

[0118] The serial interface circuit 101 is further configured to receive a test entry signal sent by the test machine 30 through the first data port Tdq0, generate a port close signal according to the test entry signal, and use the port close signal to close the input buffer circuit 106;

[0119] The input circuit 105 is connected to the serial interface circuit 101 , the input buffer circuit 106 and the built-in self-test module 103 respectively, and is used to send the first target signal or the second target signal or the third target signal output by the input buffer circuit 106 to the command decoding circuit 102 .

[0120] It should be noted that input buffer circuit 106 is a signal input module originally included in memory 40, and is used to receive the third target signal and transmit it to command decode circuit 102. The third target signal may also include a CA signal and a chip select signal. Assuming a 7-bit CA signal and a 1-bit chip select signal, eight pins are required to transmit data. In the disclosed embodiment, serial interface circuit 101 is used to initiate the built-in test and transmit data, eliminating the need for input buffer circuit 106. Therefore, the input terminal of input buffer circuit 106 is in a floating state.

[0121] Correspondingly, the input circuit 105 may further include a second OR logic circuit OR2, a first input end of which is connected to the output end of the input buffer circuit 106 to receive the third target signal, a second input end of which is connected to the serial interface circuit 101 to receive the first target signal, an output end of which is connected to the first input end of the first OR logic circuit OR1, a second input end of the first OR logic circuit OR1 receives the second target signal, and an output end of the first OR logic circuit OR1 is connected to the command decoding circuit 102.

[0122] It should also be noted that the input circuit 105 can also be a three-input OR logic circuit. The first target signal, the second target signal and the third target signal will not be sent to the input circuit 105 at the same time. The input circuit 105 operates according to the OR logic and outputs the received signal as the input target signal.

[0123] To ensure that the input buffer circuit 106 does not affect the test, before the test startup phase, the test machine 30 will first send a test entry signal (which can be recorded as SPI Entry) to the serial interface circuit 101. Based on the test entry signal, the serial interface circuit 101 generates a port close signal (which can be recorded as SPI Entry to closeIB) and sends it to the input buffer circuit 106 to close the input buffer circuit 106.

[0124] It should also be noted that, see Figure 3 , where RESET_n represents the signal transmitted by the reset port, poweron4 represents the power-on signal of the memory 40, and Tdq0 represents the signal transmitted by the first data port Tdq0. The timing for the serial interface circuit 101 to shut down the input buffer circuit 106 may be as follows: during the power-on reset period, if the serial interface circuit 101 detects three falling edges (or four, five, etc.) of the signal transmitted by the first data port Tdq0 (or after decoding the signal), confirming that a test entry signal has been detected, a port shutdown signal is generated to shut down the input buffer circuit 106.

[0125] The disclosed embodiment utilizes serial interface circuit 101 to initiate a built-in self-test (BIST). Compared to solutions that utilize input buffer circuit 106 to receive a third target signal to initiate the BIST, this solution addresses the issue of requiring too many PADs for testing. Input buffer circuit 106 requires PADs for all command address signals and chip select signals. This solution utilizes a serial interface, requiring only four PADs, thus reducing hardware costs. For example, test equipment 30 can be connected to memory 40 via a test board for testing. If input buffer circuit 106 were used, for example, for a 7-bit CA signal and a 1-bit chip select signal, eight pins would be required just to transmit the third target signal. However, using serial interface circuit 101, only four pins would be required.

[0126] Furthermore, the embodiment of the present disclosure can reuse the original data writing circuit and data reading circuit in the memory 40 to write data to the target address or read data from the target address during the test process. Figure 2 On the basis of Figure 4 As shown, the test circuit 10 further includes:

[0127] The data writing circuit 107 is configured to write data to a plurality of storage cells corresponding to a target address based on the write command signal and the address signal when the command signal is a write command signal;

[0128] The data reading circuit 108 is configured to read data from a plurality of storage cells corresponding to a target address based on the read command signal and the address signal when the command signal is a read command signal.

[0129] It should be noted that if Figure 1 or Figure 2 As shown, the specific write data can be transmitted from the built-in self-test module 103 to the storage area 20 via the data line. Among them, the data reading circuit 108 can be connected to the compression reading circuit 104 to send the read data to the compression reading circuit 104 for compression to obtain the test result.

[0130] It should also be noted that the embodiment of the present disclosure can also test multiple target addresses at the same time. Figure 5 As shown, the same target address of BK0 in BG0-BG3 is tested, and 256 bits of data are read out respectively. The 256 bits of data are then compressed into 1 bit of data (the compression process is recorded as 256:1). The four test results are recorded as: test result 0, test result 1, test result 2, and test result 3. Since serial data is transmitted between the serial interface circuit 101 and the test machine 30, the serial interface circuit 101 may further include a parallel-to-serial circuit to perform parallel-to-serial processing on test results 0-3 to obtain serial test results <3:0>, and send them to the test machine 30 through the second data port Tdq1. Here, the parallel-to-serial conversion rules are known, so the test machine 30 can determine which BG has a failed target address based on the serial test results.

[0131] Furthermore, the operating frequency that the memory 40 can achieve may be higher than the clock frequency issued by the test machine 30. In this case, if it still operates according to the clock frequency issued by the test machine 30, it will cause waste. Figure 6 As shown, the test circuit 10 may further include a frequency multiplication circuit 109; the test machine 30 sends a first clock signal to the serial interface circuit 101 and the frequency multiplication circuit 109;

[0132] The frequency multiplier circuit 109 is used to adjust the frequency of the first clock signal to obtain a second clock signal and send it to the built-in self-test module 103 so that the built-in self-test module 103 operates under the second clock signal; the frequency of the second clock signal is higher than the first clock signal.

[0133] It should be noted that Figure 6Part of the structure of the test circuit 10 is omitted, and the details can be referred to the aforementioned drawings and related descriptions. The frequency multiplication circuit 109 specifically increases the frequency of the first clock signal, and adjusts the relatively low-frequency first clock signal to a relatively high-frequency second clock signal. Among them, the frequency of the first clock signal needs to meet the frequency range supported by the memory 40. In this way, in the memory 40, the built-in self-test module 103 operates under a high-frequency clock, so that the entire test process is in a high-speed state (relatively higher than the first clock signal). Specifically, in the memory 40, the built-in self-test module 103, the command decoding circuit 102 of the test phase, the storage area 20, the compression read circuit 104, and Figure 6 The data writing circuit 107 and the data reading circuit 108 not shown in the figure all operate in the high-frequency clock domain of the second clock signal, and the test machine 30, the serial interface circuit 101, the frequency multiplication circuit 109, and the command decoding circuit 102 in the test startup phase operate in the low-frequency clock domain of the first clock signal.

[0134] Correspondingly, such as Figure 6 As shown, the serial interface circuit 101 includes a synchronous output circuit 1011;

[0135] The synchronous output circuit 1011 is used to receive the test result, reduce the speed of the test result based on the first clock signal, and then send it to the test machine 30.

[0136] It should be noted that the synchronous output circuit 1011 within the serial interface circuit 101 is responsible for widening the test results under the clock domain of the second clock signal to the clock domain of the first clock signal, and then synchronizing the widened signal with the first clock signal of the test machine 30. After a read delay (for example, delaying the period of the first clock signal), the test results are output to the test machine 30 through the first clock signal.

[0137] In this way, the synchronous output circuit 1011 converts the test results under the clock domain of the second clock signal into the clock domain of the first clock signal, and then sends it to the test machine 30 to ensure that the test machine 30 can smoothly receive the test results, avoiding the low-frequency test machine 30 being unable to receive and process high-frequency test results.

[0138] It should also be noted that the synchronous output circuit 1011 can send the test results in a double-edge data transmission manner, that is, send data on both the rising edge and the falling edge of the clock signal, so as to further improve the processing speed.

[0139] For example, see Figure 7 , which shows a schematic diagram of the structure of a frequency multiplication circuit 109 provided by an embodiment of the present disclosure. Figure 7 As shown, the frequency multiplication circuit 109 includes a delay circuit 1091 and an XOR gate 1092;

[0140] Delay circuit 1091, used to receive the delay control signal trim <n:0>and the first clock signal clk2T, based on the delay control signal trim <n:0>Delaying the first clock signal clk2T to obtain a delayed clock signal clk1;

[0141] The first input of the XOR gate 1092 is connected to the output of the delay circuit 1091 for receiving the delayed clock signal clk1; the second input of the XOR gate 1092 is used to receive the first clock signal clk2T; the output of the XOR gate 1092 is used to output the second clock signal clk1T.

[0142] It should be noted that the delay control signal trim <n:0>It is used to control the delay circuit 1091 to delay the first clock signal clk2T. For example, the period of the first clock signal clk2T is 2T. In order to obtain the second clock signal clk1T with a period of 1T, the delay control signal trim <n:0>The delay circuit 1091 may be controlled to delay the first clock signal clk2T by half of T.

[0143] For example, the delay control signal trim <n:0>The configuration information sent by the test machine 30 to the serial interface circuit 101 can be decoded and obtained. The serial interface circuit 101 decodes the delay control signal trim <n:0>Stored in its own register, and sent to the delay circuit 1091 when necessary.

[0144] In this way, the test machine 30 can adjust the frequency multiplication circuit 109 through the serial interface circuit 101 to achieve, for example, a double frequency with a 50% duty cycle. The test machine 30 then initiates the BIST through the serial interface circuit 101. During the test phase, most circuits will operate under the frequency multiplication clock (i.e., the second clock signal). The BIST data output is synchronized with the external clock (i.e., the first clock signal) through the serial interface circuit 101. The test machine 30 can sample the failure address information at the clock edge specified within the BIST through the serial interface circuit 101. After the test is completed, the data (test results) obtained by the test machine 30 are analyzed according to the execution program within the BIST to restore all failure address conditions.

[0145] In summary, the disclosed embodiments provide a low-cost parsing solution for BIST failure addresses, which relates to the relevant fields of DRAM and other memory testing, can reduce the hardware cost of BIST testing, increase the BIST test speed, and obtain failure address information. In this solution, the test machine starts BIST via a serial interface command; wherein, the serial interface circuit provides a test method with a small number of interfaces, which is suitable for starting BIST without sending a large number of commands. After the BIST is started, the DRAM will automatically perform relevant tests. By compressing the read data into a single-bit test result through a compression read circuit, the problem of a large amount of memory address information and the limited memory capacity of the test machine is solved. It can not only compress the data to the maximum extent without losing information, but also does not increase the test time cost.

[0146] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[0147] It should be noted that, in this disclosure, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0148] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0149] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0150] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0151] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0152] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A test circuit, characterized in that: include: a serial interface circuit connected to the test machine, configured to receive an initial start signal sent by the test machine, decode the initial start signal, and obtain a first target signal; further configured to transmit a test result of the target address to the test machine, and the test machine determines whether the target address is invalid based on the test result; a command decoding circuit, configured to receive the first target signal or the second target signal, decode the first target signal to obtain a test enable signal for enabling a built-in self-test module; or decode the second target signal to obtain a decoding result, wherein the decoding result is used to implement a test of the target address in the storage area; The built-in self-test module is configured to start a test according to the test start signal, and send the second target signal to the command decoding circuit after starting the test.

2. The test circuit according to claim 1, wherein: The transmission port between the serial interface circuit and the test machine includes: a first data port, a clock port and a second data port; The first data port is used for the test machine to send a data signal to the serial interface circuit; The clock port is used for the test machine to send a clock signal to the serial interface circuit; The second data port is used by the serial interface circuit to send a data signal to the test machine.

3. The test circuit according to claim 1, wherein: The second target signal includes a command address signal; The command decoding circuit is used to decode the command address signal to obtain a command signal and an address signal; wherein the address signal is used to represent the target address in the storage area, and the command signal represents the operation performed on the target address; the target address corresponds to multiple storage units.

4. The test circuit according to claim 3, characterized in that: The test circuit further includes: a data writing circuit, configured to write data to the plurality of storage cells corresponding to the target address based on the write command signal and the address signal when the command signal is a write command signal; The data reading circuit is configured to read data from the plurality of storage units corresponding to the target address based on the read command signal and the address signal when the command signal is a read command signal.

5. The test circuit according to claim 3, characterized in that: The test circuit further includes: a compression read circuit, configured to compress the data read from the plurality of storage cells corresponding to the target address, obtain the test result and send it to the serial interface circuit, wherein the test result is single-bit data; Among them, the multiple storage cells corresponding to the target address are divided into multiple storage cell columns, and the same data is written into the multiple storage cell columns. If the data read from the multiple storage cell columns are all the same, the test result obtained after the compression processing is a first value; if there is at least one difference in the data read from the multiple storage cell columns, the test result obtained after the compression processing is a second value.

6. The test circuit according to claim 5, characterized in that: When the test result is the first value, the test machine determines that the target address is not failed; when the test result is the second value, the test machine determines that the target address is failed.

7. The test circuit according to claim 1, wherein: The built-in self-test module is configured to sequentially send a plurality of second target signals to the command decoding circuit in a preset order; The testing machine is used to determine the target address corresponding to the current test result according to the preset sequence.

8. The test circuit according to claim 1, wherein: The test circuit further includes an input buffer circuit and an input circuit; The serial interface circuit is further configured to receive a test entry signal sent by the test machine, generate a port closing signal according to the test entry signal, and use the port closing signal to close the input buffer circuit; The input circuit is respectively connected to the serial interface circuit, the input buffer circuit and the built-in self-test module, and is used to send the first target signal or the second target signal or the third target signal output by the input buffer circuit to the command decoding circuit.

9. The test circuit according to any one of claims 1 to 8, characterized in that: The test circuit further includes a frequency multiplication circuit; the test machine sends a first clock signal to the serial interface circuit and the frequency multiplication circuit; The frequency multiplication circuit is used to adjust the frequency of the first clock signal to obtain a second clock signal and send it to the built-in self-test module, so that the built-in self-test module operates under the second clock signal; the frequency of the second clock signal is higher than that of the first clock signal.

10. The test circuit according to claim 9, characterized in that: The serial interface circuit includes a synchronous output circuit; The synchronous output circuit is used to receive the test result, reduce the speed of the test result based on the first clock signal, and then send it to the test machine.

11. The test circuit according to claim 9, wherein: The frequency multiplication circuit includes a delay circuit and an XOR gate; The delay circuit is configured to receive a delay control signal and the first clock signal, and delay the first clock signal based on the delay control signal to obtain a delayed clock signal; The first input end of the XOR gate is connected to the output end of the delay circuit for receiving the delayed clock signal; the second input end of the XOR gate is used to receive the first clock signal; and the output end of the XOR gate is used to output the second clock signal.

12. A memory, characterized in that: comprising a storage area and a test circuit according to any one of claims 1 to 11; The test circuit is connected to the test machine and is used to receive an initial start signal sent by the test machine through the serial interface circuit, and start the built-in self-test module based on the initial start signal to test the storage area.

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