Low-stress low-interface-thermal-resistance silicon nitride dielectric layer bonding and annealing method
By using low-temperature plasma etching and silicon nitride dielectric layer bonding technology in SiC and diamond bonding, the problems of poor interface quality and high thermal resistance are solved, high-strength bonding is achieved, and heat dissipation performance and device stability are improved.
Patent Information
- Application Number
- CN202510835347.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-20
- Publication Date
- 2025-09-26
AI Technical Summary
The existing technology has problems with SiC and diamond bonding, such as poor interface quality, high thermal resistance, and low bonding strength. In particular, heat dissipation is difficult under high-power operating conditions, affecting the stability and life of the device.
Low-temperature plasma etching is used to surface-activate diamond and semiconductor wafers, and nano-sized crystalline and amorphous silicon nitride dielectric layers are deposited. Silicon nitride dielectric layer bonding with low interface thermal resistance is formed through bonding and annealing processes. Crystalline and amorphous silicon nitride gradient layers are used to relieve thermal mismatch stress and improve bonding strength.
It achieves SiC and diamond bonding with low interface thermal resistance and high bonding strength, simplifies the process flow, reduces costs, is suitable for heat dissipation applications in the field of semiconductor material integration, and improves the reliability and service life of the device.
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Figure CN120709154A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of diamond and silicon carbide bonding, in particular to a silicon nitride dielectric layer bonding with low interface thermal resistance and an annealing method thereof. Background Art
[0002] Semiconductor devices based on silicon carbide (SiC) or gallium nitride (GaN) have become the main development direction of power devices. These materials have attracted widespread attention and have been widely used in life because of their ability to achieve higher operating frequencies, high operating voltages, and high power density outputs. In particular, SiC materials are often used as substrates for GaN devices due to their high temperature resistance, low loss rate, excellent thermal conductivity, and small lattice mismatch with GaN, and have performed well in large-scale applications in various fields. However, as the Joule heat generated by power devices under high-power operating conditions increases, the heat dissipation problem becomes particularly prominent. Due to the thermal conductivity limitations of the device itself, the heat source cannot be dissipated quickly, resulting in heat accumulation, which not only affects the operating stability of the device, but may also shorten its service life.
[0003] To address this issue, diamond, with its extremely high thermal conductivity, has attracted widespread attention. Diamond's thermal conductivity is much higher than that of SiC and GaN, and can significantly improve the heat dissipation effect of the device. Therefore, in order to achieve high-power operation of the device, researchers have explored combining SiC devices and SiC-based GaN devices with grown diamond. This combination not only fully utilizes the excellent electrical properties of SiC and GaN, but also effectively solves the heat dissipation problem through the high thermal conductivity of diamond, thereby improving the reliability and service life of the device. Therefore, the combination of SiC and diamond is of great significance in the development of power devices, providing key technical support for the performance improvement of future high-power electronic devices.
[0004] There are two ways to form diamond-based SiC structures: growing diamond structures on a SiC surface using chemical vapor deposition (CVD) and bonding SiC to diamond. However, CVD is a time-consuming process, resulting in high manufacturing costs. The specific gas environment can also damage the SiC surface or alter its chemical properties. Nucleation on a foreign substrate is also a challenge. Poor interface quality between the diamond layer and SiC can affect the device's electrical performance, such as increasing leakage current or reducing breakdown voltage. Bonding is generally simpler than CVD diamond growth, eliminating the need for complex gas environments and high-temperature conditions, reducing process complexity and equipment costs. Complex pretreatment of the SiC surface (such as nucleation layer deposition) is unnecessary, simplifying the manufacturing process. Bonding technology allows for flexible selection of diamond thickness and size to meet the needs of different devices. Bonding can achieve close contact between SiC and diamond through surface planarization and cleaning, reducing interface defects and thermal resistance. The use of an intermediate layer can optimize interface bonding quality and further enhance thermal conductivity. More importantly, the bonding technology is relatively mature and has been widely used in other material systems (such as direct bonding of silicon to silicon), so the commercial application of SiC-diamond composite structures can be realized more quickly.
[0005] Regarding the bonding of SiC and diamond, Minoura Y et al. in the paper "Surface activated bonding of SiC / diamond for thermal management of high-output po Wer GaN HEMTs" bonded the carbon polar surface of the prepared semi-insulating SiC wafer to a single crystal diamond material with a (100) orientation through surface activated bonding (SAB) to bond the two wafers together. However, the argon ion beam will form a low-density damage layer on the diamond surface, resulting in slightly low bonding strength and requiring expensive ultra-high vacuum (UHV) equipment. Therefore, a bonding method with simple process, low stress, low interface thermal resistance and high bonding strength is needed.
[0006] The thermal expansion coefficient of silicon nitride (SiN) is 2.5-3.0×10 -6 K -1 ) between SiC(3.0-4.5×10 -6 K -1 ) and diamond (1-1.5×10 -6 K -1 ), and the thermal expansion of SiN is isotropic, while that of SiC is anisotropic. Among them, amorphous SiN (2.5×10 -6 K -1 ) than crystalline SiN (3.0×10 -6 K -1) has a lower thermal expansion coefficient. Combining crystalline Si3N4 and amorphous SiN as a dielectric layer with a reduced thermal expansion coefficient gradient between SiC and diamond can alleviate thermal mismatch stress. Furthermore, silicon-rich SiN is more susceptible to Si and N decomposition and bond recombination at lower temperatures than nitrogen-rich SiN, making it more suitable for bonding and exhibiting higher bond strength. Summary of the Invention
[0007] The technical problem to be solved by this invention is to provide a low-interface thermal resistance diamond-based wafer bonding and annealing method, which can achieve high bond strength and low interfacial thermal resistance, while requiring a low vacuum bonding environment. This invention is particularly suitable for the heat dissipation application requirements of certain devices in the field of semiconductor material integration.
[0008] A method for bonding a silicon nitride dielectric layer with low interface thermal resistance and annealing the same, characterized by comprising the following steps:
[0009] S1, performing surface activation on diamond and semiconductor wafers by plasma etching respectively;
[0010] S2, depositing a nano-sized crystalline silicon nitride dielectric layer on one side of the semiconductor wafer;
[0011] S3, depositing nano-sized amorphous silicon-rich silicon nitride dielectric layers on the crystalline silicon nitride surface and diamond obtained in step S2 respectively
[0012] S4, performing surface activation on the silicon nitride surface obtained in step S3 by plasma etching;
[0013] S5, inverting one of the wafers obtained in step S4 so that the dielectric layers on the two wafers are in contact with each other;
[0014] S6, bonding under bond and conditions;
[0015] S7. Annealing is performed under annealing conditions.
[0016] Wherein, the diamond substrate in step S1 is a polished single crystal diamond or polycrystalline diamond, and the semiconductor wafer may or may not include a substrate, that is, it may be a semiconductor wafer or a silicon-based semiconductor wafer.
[0017] Preferably, the diamond has a thickness of 400-600 μm, and the semiconductor wafer has a thickness of 300-500 μm.
[0018] Among them, preferably, the semiconductor wafer can be selected from one or more semiconductor materials of SiC, Si, GaN, and AlN.
[0019] Wherein, preferably, the diamond and semiconductor wafer in step S1 both meet the surface flatness <3 μm and roughness Rq ≤ 2 nm, which is beneficial to improving the flatness and roughness of the deposited silicon nitride dielectric layer, thereby facilitating improving the bonding strength.
[0020] The plasma etching treatment in steps S1 and S3 may be ICP, RIE, or other low-temperature plasma treatment methods. Preferably, the plasma etching treatment in step S1 is specifically performed by bombarding the surface of the bonded wafer with ICP Ar, N2, or H2 plasma. Preferably, the plasma etching treatment in step S4 is specifically performed by bombarding the surface of the silicon nitride dielectric layer with ICP Ar, N2, or H2 plasma.
[0021] Among them, preferably, the diamond and semiconductor wafers described in step S1 need to be cleaned before etching, and the cleaning steps include: first ultrasonic cleaning with acetone for 15 minutes, taking out and rinsing with deionized water, and then ultrasonic cleaning with anhydrous ethanol for 15 minutes, taking out and rinsing with deionized water, and finally ultrasonic cleaning with deionized water for 15 minutes. After cleaning, take out and blow dry with nitrogen for standby use.
[0022] Wherein, preferably, the surface activation conditions in step S1 and step S4 include: -3 Pa below, the ICP power is 160-240W, the RF power is 40-60W, the treatment atmosphere is an oxygen-free protective atmosphere, and the treatment time is 40-80s. This preferred solution is more conducive to removing adsorbed gases and the native oxide layer, while not significantly changing the surface roughness of the bonding surface, cleaning the wafer surface and increasing the activation energy. At the same time, it also makes the wafer surface have suitable flatness and roughness, which is beneficial for bonding the silicon nitride dielectric layer, increasing the bond strength and bonding efficiency. However, the plasma treatment time should not be too long, and the energy should not be too high, otherwise the surface roughness will increase.
[0023] The silicon nitride dielectric layer deposition in steps S2 and S3 may be physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
[0024] Wherein, preferably, the deposition adopts physical vapor deposition method, and the silicon nitride dielectric layer is prepared by direct target magnetron sputtering of a silicon target.
[0025] The deposition process should be carried out under low temperature, low power and short time conditions to ensure that the deposited gradient layer has a suitable nanometer size.
[0026] At a vacuum of 4×10 -4 Below Pa, pre-sputtering is first performed with a sputtering power of 180-220 W, an argon flow rate of 80-100 sccm, and a pre-sputtering time of 5-10 min;
[0027] The crystalline silicon nitride dielectric layer is deposited by setting the argon flow rate to 5-15 sccm, the nitrogen flow rate to 5-15 sccm, the ratio of argon to nitrogen to 1:1, the sputtering power to 180-220 W, the temperature to 350-400°C, the chamber pressure to 0.75-1.5 Pa, and the deposition time to 90-110 s to complete the deposition of the crystalline silicon nitride dielectric layer.
[0028] Preferably, the temperature in step S2 should be raised to a vacuum degree of 4×10 -4 Pa below 50-60 minutes, reduce the temperature to the vacuum degree of 4 × 10 -4 Cooling below Pa for 3-4 hours is beneficial to relieve wafer stress, avoid surface oxidation of the plated silicon nitride dielectric layer, and help improve bonding strength and bonding efficiency.
[0029] Wherein, preferably, the deposition process in step S3 includes:
[0030] At a vacuum of 4×10 -4 Below Pa, pre-sputtering is first performed with a sputtering power of 180-220 W, an argon flow rate of 80-100 sccm, and a pre-sputtering time of 5-10 min;
[0031] The silicon nitride dielectric layer is deposited with an argon flow rate of 10-30 sccm, a nitrogen flow rate of 5-15 sccm, an argon to nitrogen ratio of 2:1, a sputtering power of 180-220 W, a temperature of 180-220° C., a chamber pressure of 0.75-1.5 Pa, and a deposition time of 40-60 s to complete the deposition of the amorphous silicon-rich silicon nitride dielectric layer.
[0032] Preferably, the temperature in step S3 should be raised to a vacuum degree of 4×10 -4 Pa below 30-40 minutes, reduce the temperature to the vacuum degree of 4 × 10 -4 Cooling below Pa for 3-4 hours is beneficial to relieve wafer stress, avoid surface oxidation of the plated silicon nitride dielectric layer, and help improve bonding strength and bonding efficiency.
[0033] Under this preferred solution, it is beneficial to uniformly deposit the silicon nitride dielectric layer on the entire wafer surface, and to obtain a deposited layer of suitable size, which is beneficial for subsequent bonding.
[0034] In the above deposition method, the thickness of the deposited silicon nitride dielectric layer should be between 5-15 nm.
[0035] Among them, step S5 is used to perform lamination, and the specific operation is: the sides of the wafers coated with the silicon nitride dielectric layer are bonded together face to face, placed in a corresponding wafer size mold fixed on the bonding equipment, and the upper and lower wafers are aligned using the mold.
[0036] Wherein, preferably, the bonding conditions described in step S6 include: vacuum degree of 1×10 -3 Pa, gradually apply pressure to both sides of the wafers to reach 0.1-0.5MPa within 30s; then heat the upper and lower wafers simultaneously, the heating temperature is 400-450℃, and maintain for 50-60 minutes.
[0037] After the bonding is completed according to the present invention, a denitrification reaction occurs in the dielectric layer, and nitrogen elements overflow.
[0038] Preferably, after the bonding is completed in step S6, the vacuum degree should be maintained at 1×10 -3 Samples below Pa are cooled naturally with the equipment to avoid oxidation and help relieve stress.
[0039] The annealing in step S7 should meet the conditions of vacuum, high temperature, slow heating and slow cooling to ensure that the silicon nitride dielectric layer can be fully denitrified and the wafer can fully relieve stress. Preferably, a tube furnace is selected as the annealing device.
[0040] Wherein, preferably, the annealing process in step S7 includes:
[0041] The sample was placed in a tube furnace at a vacuum of 1×10 -3 Pa, set the temperature to 800-900℃, set the heating process to 60-120 minutes, set the heat preservation time to 180-240 minutes, and set the cooling process to 240-320 minutes.
[0042] The method of the present invention can be extended to the bonding of various semiconductor materials, such as SiC / SiC bonding, SiC / Si bonding, Si / diamond bonding, GaN / diamond bonding, etc., and the conditions can be optimized according to the specific materials.
[0043] The bonding strength of the diamond-based wafer of the present invention can reach the maximum strength of bulk silicon.
[0044] The beneficial effects of the present invention are:
[0045] The above-mentioned silicon nitride dielectric layer serves as an intermediate layer with good thermal conductivity, and can act as a heat-conducting layer. Carbon diffusion occurs between silicon nitride and diamond or SiC at high temperatures to form a SiC phase transition layer. The thermal conductivity of SiC and SiN is very high, and they can be applied to SiC / diamond, GaN / SiC / diamond and other integrated processes of the heat dissipation system.
[0046] It avoids the introduction of elements such as metals, reduces the introduction of multiple interfaces, prevents interface scattering during phonon / electron coupling transmission, and significantly improves interface thermal conductivity.
[0047] The crystalline silicon nitride and amorphous silicon nitride gradient dielectric layers between SiC and diamond form a gradient decrease in thermal expansion coefficient from SiC to diamond, which helps to gradually relieve thermal mismatch stress.
[0048] According to the different thermal expansion coefficients of different materials bonded to diamond, multiple layers of silicon nitride crystalline and amorphous gradient dielectric layers with different processes can be constructed to control the thermal expansion coefficient gradient, which has a wide range of applications.
[0049] The silicon-rich silicon nitride dielectric layer is more likely to overflow with a large amount of nitrogen during high-temperature annealing, transforming it into a transition phase between SiC and Si. Ideally, it can reach the strength of bulk silicon. High-temperature annealing can significantly improve the bonding strength.
[0050] The process is simple, the conditions are easy to obtain, an ultra-high vacuum environment is not required, and the requirements for wafer surface roughness are low. Compared with methods such as SAB, the cost is lower and the interface thermal conductivity is higher. BRIEF DESCRIPTION OF THE DRAWINGS
[0051] Figure 1 It is a schematic diagram of the manufacturing process of bonding and annealing the silicon nitride dielectric layer provided by the present invention;
[0052] Figure 2 It is a schematic diagram of the manufacturing method of bonding and annealing the silicon nitride dielectric layer provided by the present invention;
[0053] Explanation of the accompanying symbols: 1. Diamond substrate; 2. SiC substrate; 3. Plasma etching; 4. Crystalline silicon nitride dielectric layer; 5. Amorphous silicon-rich silicon nitride dielectric layer; 6. Pressure; 7. Lower temperature; 8. Higher temperature. DETAILED DESCRIPTION
[0054] The present invention is further described below with reference to specific embodiments and accompanying drawings.
[0055] Example 1
[0056] 4H-SiC and single-crystal diamond were used as the original substrate wafers. The original substrate size was 5×5mm, the diamond thickness was 500μm, the surface flatness was less than 3μm, and the surface roughness Rq was 0.4nm. The 4H-SiC had a (0001) surface preferred orientation, a thickness of 500μm, and a C-plane surface roughness Ra less than 0.5nm. The wafer surface was first cleaned with acetone ultrasonic cleaning for 15 minutes, then transferred to anhydrous ethanol and ultrasonically cleaned for 15 minutes, and finally transferred to deionized water and ultrasonically cleaned for 15 minutes, and then blown dry with nitrogen for later use.
[0057] ICP argon plasma treatment. -3 Pa, the ICP power was 200 W, the RF power was 50 W, the processing atmosphere was argon, and the processing time was 60 s.
[0058] A 15 nm thick crystalline SiN film was deposited on the 4H-SiC surface by magnetron sputtering. Two wafers were placed in the equipment for sputtering; at a vacuum of 4×10 -4 Pa, pre-sputtering is first performed with a sputtering power of 200 W, an argon flow rate of 100 sccm, and a pre-sputtering time of 5 min; then the crystalline SiN dielectric layer is deposited, the argon flow rate is set to 10 sccm, the nitrogen flow rate is set to 10 sccm, the sputtering power is set to 200 W, the temperature is set to 400 ° C, the heating time is set to 60 minutes, the cooling time is set to 5 hours, the chamber pressure is set to 1 Pa, the deposition time is 150 s, and the crystalline SiN dielectric layer deposition is completed.
[0059] Magnetron sputtering was used to deposit 5 nm amorphous silicon-rich SiN films on the surface of diamond and 4H-SiC on which crystalline SiN had been deposited. The two wafers were placed in the equipment for sputtering; at a vacuum of 4×10 -4 Pa, pre-sputtering is first performed with a sputtering power of 200 W, an argon flow rate of 100 sccm, and a pre-sputtering time of 5 min; then an amorphous silicon-rich SiN dielectric layer is deposited, the argon flow rate is set to 10 sccm, the nitrogen flow rate is set to 5 sccm, the sputtering power is set to 200 W, the temperature is set to 200 ° C, the heating time is set to 30 minutes, the cooling time is set to 4 hours, the chamber pressure is set to 1 Pa, and the deposition time is 50 s to complete the deposition of the amorphous silicon-rich SiN dielectric layer.
[0060] ICP argon plasma treatment. -3 Pa, the ICP power was 200 W, the RF power was 50 W, the processing atmosphere was argon, and the processing time was 60 s.
[0061] Lamination. The wafers are placed face-to-face with their silicon nitride dielectric layers on one side. These wafers are then placed into a mold of the corresponding wafer size, which is fixed to the bonding equipment. The mold is then used to align the upper and lower wafers.
[0062] Bonding. Vacuum degree is 1×10 -3 Pa, gradually apply pressure to both sides of the wafers until it reaches 0.1MPa within 30s; then heat the upper and lower wafers simultaneously at 400℃ and maintain the above pressure and temperature for 50 minutes. After bonding is completed, the vacuum degree should be maintained at 1×10 -3 Samples below Pa are cooled naturally with the equipment and taken out at a temperature below 40°C.
[0063] Annealing. Place the sample in a tube furnace at a vacuum of 1×10 -3 Pa, set the temperature to 800 ° C, set the heating process to 100 minutes, set the heat preservation time to 180 minutes, and set the cooling process to 300 minutes. Obtain the sample.
[0064] Example 2
[0065] Two single-crystal diamond wafers were used as the original substrates. The original substrates were 5×5 mm in size, with a diamond thickness of 500 μm, a surface flatness of less than 3 μm, and a surface roughness Rq of 0.4 nm. The wafer surfaces were first cleaned using acetone ultrasonic cleaning for 15 minutes, then transferred to anhydrous ethanol and ultrasonically cleaned for 15 minutes, and finally transferred to deionized water and ultrasonically cleaned for 15 minutes. The wafers were then dried with nitrogen and set aside.
[0066] ICP argon plasma treatment. -3 Pa, the ICP power was 200 W, the RF power was 50 W, the processing atmosphere was argon, and the processing time was 60 s.
[0067] Magnetron sputtering was used to deposit 10nm amorphous silicon-rich SiN films on the surfaces of two single-crystal diamond wafers. The two wafers were placed in the equipment for sputtering; at a vacuum of 4×10 -4 Pa, pre-sputtering is first performed with a sputtering power of 200 W, an argon flow rate of 100 sccm, and a pre-sputtering time of 5 minutes; then the silicon nitride dielectric layer is deposited, the argon flow rate is set to 10 sccm, the nitrogen flow rate is set to 5 sccm, the sputtering power is set to 200 W, the temperature is set to 200°C, the heating time is set to 30 minutes, the cooling time is set to 4 hours, the chamber pressure is set to 1 Pa, and the deposition time is 100 seconds to complete the deposition of the amorphous silicon-rich SiN dielectric layer.
[0068] ICP argon plasma treatment. -3 Pa, the ICP power was 200 W, the RF power was 50 W, the processing atmosphere was argon, and the processing time was 60 s.
[0069] Lamination. The wafers are placed face-to-face with their silicon nitride dielectric layers on one side. These wafers are then placed into a mold of the corresponding wafer size, which is fixed to the bonding equipment. The mold is then used to align the upper and lower wafers.
[0070] Bonding. Vacuum degree is 1×10 -3 Pa, gradually apply pressure to both sides of the wafers until it reaches 0.4MPa within 30s; then heat the upper and lower wafers simultaneously at 400℃ and maintain the above pressure and temperature for 60 minutes. After bonding is completed, the vacuum degree should be maintained at 1×10 -3Samples below Pa are cooled naturally with the equipment and taken out at a temperature below 40°C.
[0071] Annealing. Place the sample in a tube furnace at a vacuum of 1×10 -3 Pa, set the temperature to 800℃, set the heating process to 60 minutes, set the heat preservation time to 240 minutes, and set the cooling process to 240 minutes.
[0072] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.
Claims
1. A low interfacial thermal resistance silicon nitride dielectric layer bonding and annealing method thereof, characterized in that: The following steps are involved: S1, performing surface activation on diamond and semiconductor wafers by plasma etching respectively; S2, depositing a nano-sized crystalline silicon nitride dielectric layer on one side of the semiconductor wafer; The vacuum degree is 4×10 -4 Below Pa, pre-sputtering is first performed with a sputtering power of 180-220 W, an argon flow rate of 80-100 sccm, and a pre-sputtering time of 5-10 min; Deposit a crystalline silicon nitride dielectric layer, set the argon flow rate to 5-15 sccm, the nitrogen flow rate to 5-15 sccm, the ratio of argon to nitrogen to 1:1, set the sputtering power to 180-220 W, the temperature to 350-400 ° C, the chamber pressure to 0.75-1.5 Pa, and the deposition time to 90-110 s to complete the deposition of the crystalline silicon nitride dielectric layer; S3, depositing nanometer-sized amorphous silicon-rich silicon nitride dielectric layers; The vacuum degree is 4×10 -4 Below Pa, pre-sputtering is first performed with a sputtering power of 180-220 W, an argon flow rate of 80-100 sccm, and a pre-sputtering time of 5-10 min; Deposit a silicon nitride dielectric layer with an argon flow rate of 10-30 sccm, a nitrogen flow rate of 5-15 sccm, an argon to nitrogen ratio of 2:1, a sputtering power of 180-220 W, a temperature of 180-220°C, a chamber pressure of 0.75-1.5 Pa, and a deposition time of 40-60 s to complete the deposition of an amorphous silicon-rich silicon nitride dielectric layer. S4, performing surface activation on the silicon nitride surface obtained in step S2 by plasma etching; S5, inverting one of the wafers obtained in step S3 so that the dielectric layers on the two wafers are in contact with each other; S6, bonding under bond and conditions; The vacuum degree is 1×10 -3 Pa, gradually apply pressure to both sides of the wafers to reach 0.1-0.5MPa within 30s; then heat the upper and lower wafers simultaneously at 400-450℃ and maintain for 50-60 minutes; S7, then annealing under annealing conditions; The sample was placed in a tube furnace with a vacuum degree of 1×10 -3 Pa, set the temperature to 800-900℃, set the heating process to 60-120 minutes, set the heat preservation time to 180-240 minutes, and set the cooling process to 240-320 minutes.
2. The bonding and annealing method according to claim 1, characterized in that: Steps S1 and S4 activation treatment were performed at a vacuum degree of 3×10 -3 Pa below, ICP power is 160-240W, RF power is 40-60W, treatment atmosphere is oxygen-free protective atmosphere, treatment time is 40-80s; Ultrasonic cleaning is required before etching. First, ultrasonic cleaning is performed with acetone for 15 minutes. Then, it is taken out and rinsed with deionized water, and then ultrasonic cleaning is performed with anhydrous ethanol for 15 minutes. Then, it is taken out and rinsed with deionized water, and finally ultrasonic cleaning is performed with deionized water for 15 minutes. After cleaning, it is taken out and blown dry with nitrogen for later use.
3. The bonding and annealing method according to claim 1, characterized in that: The plasma etching treatment in steps S1 and S4 is specifically to bombard the surface of the bonded wafer using ICP Ar, N2, H2 plasma.
4. The bonding and annealing method according to claim 1, characterized in that: The semiconductor wafer in step S1 is selected from one or more semiconductor materials of SiC, Si, GaN, and AlN.
5. The bonding and annealing method according to claim 1, characterized in that: The thickness of the deposited crystalline silicon nitride dielectric layer on one side shown in step S2 is not less than 10 nm and not more than 15 nm.
6. The bonding and annealing method according to claim 1, characterized in that: The thickness of the deposited amorphous silicon-rich silicon nitride dielectric layer on one side shown in step S3 is not less than 5 nm and not more than 10 nm.
7. The bonding and annealing method according to claim 1, characterized in that: The methods for depositing silicon nitride in steps S2 and S3 include physical vapor deposition, chemical vapor deposition, and atomic layer deposition.
8. The bonding and annealing method according to claim 1, characterized in that: The silicon nitride deposited in steps S2 and S3 is a gradient dielectric layer of crystalline silicon nitride and amorphous silicon nitride, which can be adjusted according to different materials bonded to diamond.
9. The bonding and annealing method according to claim 1, characterized in that: In step S5, the sample is stacked and placed into a mold of the corresponding wafer size fixed on the bonding equipment, and aligned up and down.
10. The bonding and annealing method according to claim 1, characterized in that: The annealing in step S7 should meet the conditions of vacuum, high temperature, slow heating and slow cooling to ensure that the silicon nitride dielectric layer can be fully denitrified and the wafer can fully relieve stress.