Substrate bump processing method, packaging substrate and packaging structure

Abstract

The invention discloses a substrate salient point processing method, a packaging substrate and a packaging structure, and relates to the technical field of semiconductors, and the substrate salient point processing method comprises the steps: carrying out the resistance welding windowing of a resistance welding layer coated on the substrate based on the warping degree information of the substrate, and obtaining at least two types of resistance welding openings with different opening sizes; a solder ball is correspondingly implanted into each solder resisting opening, the implanted solder balls are connected with the bonding pad through reflow soldering, and convex points correspondingly formed by the solder balls are flattened; under the condition that the surface of the substrate where the solder mask layer is located is in a concave warping shape, the first opening size of the solder mask opening in the central area is smaller than the second opening size of the solder mask opening in the first peripheral area; or under the condition that the surface, where the solder mask layer is located, of the substrate is in convex surface warping, the size of the first opening is larger than that of the second opening. According to the invention, the coplanarity among the salient points on the large-size substrate can be optimized.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a substrate bump processing method, a packaging substrate, and a packaging structure. Background Art

[0002] With the rapid development of the electronics industry, the requirements for chip integration and performance are increasing. To meet these demands, the design and manufacturing technology of packaging substrates, as key components connecting electronic chips to external circuits, are constantly evolving. A packaging substrate is a printed circuit board specifically used for electronic packaging, primarily used to mount various types of electronic chips, such as flip chip packages (Flip chip packages), chip scale packages (CSPs), and ball grid arrays (BGAs). In these applications, factors such as the spacing, precision, reliability, and cost of the electronic contacts between the packaging substrate and the electronic chip mounted on its surface are important factors in determining the overall packaging performance.

[0003] To improve the quality and reliability of the electrical connection between the package substrate and the chip, the traditional package substrate manufacturing process typically involves solder on pad (SOP) and coining the electronic contacts on the substrate after completing the solder mask and surface treatment. The SOP process involves planting tin balls (solder balls are commonly used solder balls) on the pads and then reflowing them to melt and fix them onto the pads, forming bumps. Subsequently, the tops of these bumps are flattened using an indenter to ensure consistent bump height and coplanarity (for example, the bumps are generally required to protrude 5-30 microns above the solder mask surface, with coplanarity controlled within 25 microns). This ensures assembly quality during the subsequent chip packaging process.

[0004] However, with the rise of cutting-edge technologies such as 5G communications, artificial intelligence, and high-performance computing, multiple chips are being integrated onto a single interposer. This has led to a significant increase in chip size after integration and a sharp increase in the number of electronic contacts connecting the chip to the substrate (for example, from 60,000 to 160,000 or even more). This not only requires a larger substrate to accommodate more electronic contacts, but also presents new challenges: as the substrate size increases, its warpage also increases, resulting in poor coplanarity between the individual bumps on large substrates. These issues directly impact the quality and reliability of the solder joints between the chip and substrate in the final packaged product, becoming one of the major bottlenecks facing current high-density integrated packaging technology. Therefore, effectively addressing these issues has become a pressing technical challenge for those skilled in the art. Summary of the Invention

[0005] The main purpose of this application is to provide a substrate bump processing method, a packaging substrate and a packaging structure, aiming to solve the technical problem that the coplanarity between the bumps on a large-size substrate is poor, resulting in low quality and reliability of the solder joints between the chip and the substrate in the packaged product.

[0006] To achieve the above objectives, the present application provides a substrate bump processing method, comprising: Based on the warpage information of the substrate, performing solder mask opening on the solder mask layer coated on the substrate to obtain solder mask openings with at least two different opening sizes; Implanting solder balls into each solder resist opening respectively, connecting the implanted solder balls to the pads by reflow soldering, and flattening the bumps formed corresponding to the solder balls; In the case where the surface of the substrate where the solder resist layer is located is concavely warped, a first opening size of the solder resist opening in the central area is smaller than a second opening size of the solder resist opening in the first peripheral area; or, in the case where the surface of the substrate where the solder resist layer is located is convexly warped, the first opening size is larger than the second opening size; wherein the central area is an area constructed around the position with the largest warpage in the concave surface of the substrate or the convex surface of the substrate, and the first peripheral area is different from the central area and forms a cover for the central area.

[0007] In addition, to achieve the above-mentioned purpose, the present application also provides a packaging substrate, which is a substrate manufactured using the substrate bump processing method as described above.

[0008] In addition, to achieve the above-mentioned purpose, the present application also provides a packaging structure, including a packaging substrate as described above, and a chip soldered to the substrate surface of the packaging substrate, wherein the bumps at the bottom of the chip are connected one-to-one with the bumps of the packaging substrate.

[0009] The embodiment of the present application provides a substrate bump processing method, a packaging substrate and a packaging structure. The technical solution of the embodiment of the present application is to perform solder mask opening on the solder mask layer coated on the substrate based on the warpage information of the substrate to obtain at least two solder mask openings with different opening sizes, and then implant a solder ball into each solder mask opening respectively, and connect the implanted solder ball to the pad through reflow soldering, and flatten the bumps formed corresponding to each solder ball. When the substrate surface where the solder mask layer is located is concavely warped, the first opening size of the solder mask opening in the central area is smaller than the second opening size of the solder mask opening in the first peripheral area; or, when the substrate surface where the solder mask layer is located is convexly warped, the first opening size is larger than the second opening size, wherein, The central area is an area constructed around the position with the largest warpage in the concave surface or convex surface of the substrate. The first peripheral area is different from the central area and forms a cover for the central area, so that the embodiment of the present application refines the solder mask openings, and in the solder mask processing before ball planting and surface treatment, based on the warpage performance of the first board of the substrate (convex or concave surface), the solder mask openings are refined, so that after ball planting and before flattening, the bump height in the area where the solder mask opening is enlarged is reduced, and the bump height in the area where the solder mask opening is reduced is increased, so as to compensate and optimize the problem of poor bump coplanarity caused by substrate warping, optimize the bump leveling height and coplanarity, improve the quality and reliability of the solder joints between the chip and the substrate in the packaged product, and thereby improve the stability of the electrical connection between the package substrate and the chip.

[0010] It is worth mentioning that in the case of substrates with a high number of interconnected electronic contacts or large sizes, the embodiments of the present application achieve optimization of the height and coplanarity of the bumps on the substrate through an innovative process of refining the solder mask openings. This optimization can accurately control the height and coplanarity of the substrate bumps, ensuring that the height and coplanarity of the bumps formed on the large-size substrate fully meet high-standard requirements. The optimized bump height and coplanarity meet strict requirements, greatly improving the quality of the solder joints between the large-size chip and the substrate after packaging. The bumps with consistent height and good coplanarity ensure a stable electrical connection between the chip and the substrate, reduce the probability of problems such as cold solder joints and short circuits, and effectively improve stability and reliability during long-term use. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0012] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0013] Figure 1 A schematic flow chart of the first embodiment of the substrate bump processing method provided in the present application; Figure 2 This is a schematic diagram of a scenario in which bumps of a chip and a substrate are interconnected in a specific embodiment of the present application; Figure 3 This is a warpage distribution diagram corresponding to concave warping in a specific embodiment of the present application; Figure 4 A schematic diagram of refined solder mask openings and partitions corresponding to concave warping in a specific embodiment of the present application; Figure 5 This is a schematic diagram of the process corresponding to concave warping in a specific embodiment of the present application; Figure 6 This is a warpage distribution diagram corresponding to convex warping in a specific embodiment of the present application; Figure 7 Schematic diagram of refined solder mask openings and partitions corresponding to convex surface warping in a specific embodiment of the present application; Figure 8 This is a schematic diagram of the process corresponding to convex surface warping in a specific embodiment of the present application; Figure 9 This is a comparison diagram of the effects of substrate bump processing in a specific implementation of this application.

[0014] The purpose, features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0015] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0016] It should be understood that the specific embodiments described herein are merely used to explain the technical solutions of the present application and are not intended to limit the present application.

[0017] Currently, in the bumping process for semiconductor packaging substrates, the solder mask windowing process assumes the substrate is ideally flat and employs a uniform opening design strategy, setting solder mask openings of the same size in different areas of the substrate surface. This strategy assumes the substrate is perfectly flat and free of warpage. It controls solder ball placement through fixed opening dimensions and relies on a subsequent flattening process to forcefully correct for bump height variations, achieving uniform bump height. However, this approach ignores the impact of substrate warpage on bump height.

[0018] In actual production scenarios, large-scale substrates magnify differences in thickness tolerances and residual stress across different regions, leading to more severe warpage (concave or convex deformation). This results in significant vertical height differences in pads across different regions: when concave warpage exists on the substrate surface, the actual pad height in the center is lower than in the peripheral areas; conversely, when convex warpage exists, the actual pad height in the center is higher than in the peripheral areas. Traditional uniformized opening design strategies cannot compensate for the bump height differences caused by substrate warpage, resulting in poor coplanarity and, consequently, lower solder joint quality and reliability between the chip and substrate in the packaged product. This systematic deviation is geometrically amplified on large-scale substrates, causing localized cold solder joints or short circuits during the chip-to-substrate soldering process, severely impacting the quality of the final product.

[0019] In this regard, the main solution of the embodiment of the present application is a substrate bump processing method, which includes: based on the warpage information of the substrate, performing solder mask windowing on the solder mask layer coated on the substrate to obtain at least two solder mask openings with different opening sizes; respectively implanting a solder ball into each solder mask opening, and connecting the implanted solder ball to the pad through reflow soldering, and flattening the bumps formed corresponding to each solder ball; when the surface of the substrate where the solder mask layer is located is concavely warped, the first opening size of the solder mask opening in the central area is smaller than the second opening size of the solder mask opening in the first peripheral area; or, when the surface of the substrate where the solder mask layer is located is convexly warped, the first opening size is larger than the second opening size; wherein the central area is an area constructed around the position with the largest warpage in the concave surface or the convex surface of the substrate, and the first peripheral area is different from the central area and forms a cover for the central area.

[0020] The embodiment of the present application refines the solder mask openings and, during the solder mask processing before ball planting and surface treatment, performs refined solder mask window processing based on the warpage performance of the first substrate (convex or concave), so that the bump height is reduced in the area where the solder mask window is enlarged and before flattening after ball planting, and the bump height is increased in the area where the solder mask window is reduced, so as to compensate for and optimize the problem of poor bump coplanarity caused by substrate warping, optimize the bump leveling height and coplanarity, improve the quality and reliability of the solder joints between the chip and the substrate in the packaged product, and thereby improve the stability of the electrical connection between the package substrate and the chip.

[0021] It is worth mentioning that in the case of substrates with a high number of interconnected electronic contacts or large sizes, the embodiments of the present application achieve optimization of the height and coplanarity of the bumps on the substrate through an innovative process of refining the solder mask openings. This optimization can accurately control the height and coplanarity of the substrate bumps, ensuring that the height and coplanarity of the bumps formed on the large-size substrate fully meet high-standard requirements. The optimized bump height and coplanarity meet strict requirements, greatly improving the quality of the solder joints between the large-size chip and the substrate after packaging. The bumps with consistent height and good coplanarity ensure a stable electrical connection between the chip and the substrate, reduce the probability of problems such as cold solder joints and short circuits, and effectively improve stability and reliability during long-term use.

[0022] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0023] This application proposes a substrate bump processing method according to a first embodiment.

[0024] Please refer to Figure 1 , Figure 1 A schematic flow chart of the first embodiment of the substrate bump processing method provided in the present application.

[0025] In this embodiment, the substrate bump processing method includes steps S100 to S200: Step S100 : performing solder resist windowing on the solder resist layer coated on the substrate based on the warpage information of the substrate to obtain solder resist openings of at least two different opening sizes.

[0026] It should be noted that warpage information reflects the warpage of the substrate surface and may include information such as the warpage at various locations on the substrate surface and the warpage pattern (concave or convex). This warpage information can be obtained using a laser interferometer or optical profilometer, and is not specifically limited in this embodiment. The opening size quantifies the size of the solder mask opening.

[0027] It should be noted that in this embodiment, when the warping mode is concave warping, the warping degree indicates the degree of depression, and the greater the warping degree, the deeper the depression; and when the warping mode is convex warping, the warping degree indicates the degree of convexity, and the greater the warping degree, the higher the convexity.

[0028] Those skilled in the art will recognize that solder mask is an insulating, protective layer covering the surface of a substrate, used to limit the exposure of the pad area and prevent unnecessary soldering during the soldering process. A solder mask opening is an opening of a specific shape and size (also known as a solder mask opening) formed at a specific location in the solder mask through photolithography or laser etching. This exposes the pad area, facilitating accurate solder ball placement and connection.

[0029] In step S200 , solder balls are implanted into corresponding solder resist openings, and the implanted solder balls are connected to pads by reflow soldering, and bumps formed corresponding to the solder balls are flattened.

[0030] When the surface of the substrate where the solder resist layer is located is concavely warped, the first opening size of the solder resist opening in the central area is smaller than the second opening size of the solder resist opening in the first peripheral area; or, when the surface of the substrate where the solder resist layer is located is convexly warped, the first opening size is larger than the second opening size; wherein the central area is an area constructed around the position with the largest warpage in the concave surface of the substrate or the convex surface of the substrate, and the first peripheral area is different from the central area and forms a cover for the central area.

[0031] Those skilled in the art will recognize that a solder ball is a preformed spherical solder body, typically made of a tin-based alloy or an indium-based alloy, used to establish electrical and mechanical connections between the package substrate and the chip. Solder ball implantation (also known as ball placement) involves the precise placement of a solder ball onto a pad within a solder mask opening using ball placement equipment. Reflow soldering involves heating the solder ball to melt and form a secure bond with the pad. Flattening involves using a mechanical press to level the bumps formed within the solder mask opening after reflow soldering, ensuring that all bumps are of uniform height and have good coplanarity.

[0032] This embodiment divides the solder mask layer into a central region and a peripheral region (including a first peripheral region) based on the warpage of the substrate surface on which the solder mask layer is located. The central region is the area surrounding the location with the greatest warpage on the concave or convex surface of the substrate, while the peripheral region is the area outside the central region. The first peripheral region is the area within the peripheral region that encloses the central region. Obviously, the central region has a higher warpage than the first peripheral region.

[0033] It should be noted that the opening size refers to the area of ​​the solder mask opening. The first opening size refers to the opening size of a single solder mask opening with a solder mask window in the central area of ​​the solder mask layer coated thereon, and the second opening size refers to the opening size of a single solder mask opening with a solder mask window in the first peripheral area of ​​the solder mask layer coated thereon.

[0034] It is not difficult to understand that, when the surface of the substrate where the solder mask layer is located is concavely warped, the central area is an area constructed around the position of the largest warping in the concave surface of the substrate (i.e., the concave surface of the substrate), and when the surface of the substrate where the solder mask layer is located is convexly warped, the central area is an area constructed around the position of the largest warping in the convex surface of the substrate (i.e., the convex surface of the substrate).

[0035] In this embodiment, when the surface of the substrate where the solder resist layer is located is concavely warped, the first opening size of a single solder resist opening with a solder resist window in the central area of ​​the solder resist layer coated on the first peripheral area is smaller than the second opening size of a single solder resist opening with a solder resist window in the first peripheral area of ​​the solder resist layer coated on the first peripheral area. When the surface of the substrate where the solder resist layer is located is convexly warped, the first opening size is larger than the second opening size.

[0036] It is worth mentioning that, in this embodiment, each solder resist opening corresponds to implanting a solder ball, wherein the volume of each implanted solder ball is consistent, or the volume difference between each implanted solder ball is less than a third preset threshold.

[0037] It should be noted that the third preset threshold is a pre-set volume difference threshold, which is used to determine whether the volumes of the solder balls are almost the same. When the volume difference between the solder balls is less than the third preset threshold, it means that the volumes of the solder balls are almost the same. When the opening sizes of the solder mask openings are the same, the heights of the bumps formed by the solder balls after solidification after reflow soldering are basically the same, and the impact on coplanarity can be ignored. When the volume difference between the solder balls is greater than or equal to the third preset threshold, it means that the volume difference between the solder balls, when the opening sizes of the solder mask openings are the same, will cause the heights of the bumps formed by the solder balls after solidification after reflow soldering to be inconsistent, and will have an impact on coplanarity that cannot be ignored.

[0038] It's easy to understand that the larger the opening size, the wider the area of ​​wetting and spreading of the solder ball after melting during reflow. If the implanted solder balls have a uniform or nearly uniform volume and the substrate is not warped, the wider the area of ​​wetting and spreading of the solder ball after melting, the lower the bump height formed in the solder mask opening during solidification.

[0039] This embodiment pre-determines the warpage condition (including warpage and warpage pattern) of the substrate surface where the solder mask layer is located based on the warpage information of the substrate, thereby dividing the area requiring solder mask openings into a central area and a first peripheral area, so as to accurately match the warpage gradient distribution of the substrate surface where the solder mask layer is located (i.e., the central area is constructed around the position with the largest warpage on the concave surface or the convex surface of the substrate, the first peripheral area is different from the central area and forms a cover for the central area, and the warpage degree of the central area is generally higher than that of the peripheral area). When solder mask windows are opened on the solder mask layer coated on the substrate, the opening sizes of the solder mask openings in each area are differentially regulated, and the difference in bump height caused by the substrate warpage is converted into a controllable difference in the opening size of the solder mask opening. In addition, the influence of the substrate warpage on the bump height is pre-compensated before ball planting, laying the foundation for subsequent bump coplanarity optimization, realizing active optimization of bump height and coplanarity, and ensuring the consistency of bump height and uniformity of coplanarity after flattening.

[0040] Specifically, when the surface of the substrate where the solder resist layer is located is concavely warped, this embodiment reduces the opening size of the solder resist opening when performing solder resist windowing on the solder resist layer coated on the central area, and increases the opening size of the solder resist opening when performing solder resist windowing on the solder resist layer coated on the first peripheral area, so that the first opening size is smaller than the second opening size, thereby making the solder balls implanted in the solder resist openings in the central area require a smaller range of wetting and spreading after melting during reflow soldering, and the height of the bumps formed during solidification is higher, compensating for the base surface height difference caused by the actual height of the pads in the central area being lower than that of the first peripheral area under the concave warping, and thereby correcting the bump coplanarity offset caused by the depression of the base surface.

[0041] Accordingly, in the case where the surface of the substrate where the solder resist layer is located is convexly warped, this embodiment increases the opening size of the solder resist opening when performing solder resist windowing on the solder resist layer coated on the central area, and reduces the opening size of the solder resist opening when performing solder resist windowing on the solder resist layer coated on the first peripheral area, so that the first opening size is larger than the second opening size, thereby making the solder balls implanted in the solder resist openings in the central area need to wet and spread over a larger area after melting during reflow soldering, and the height of the bumps formed during solidification is lower, thereby balancing the actual height of the pads in the central area under the convex warping to be higher than the base surface height difference caused by the first peripheral area, thereby correcting the bump coplanarity deviation caused by the bulge of the base surface.

[0042] For example, in a feasible implementation, the substrate bump processing method may further include steps A10 to A20: In step A10 , when it is determined based on the warpage information that the maximum warpage of the substrate surface is the first warpage, the absolute value of the size difference between the first opening size and the second opening size is set as a first value.

[0043] In step A20, when it is determined based on the warpage information that the maximum warpage of the substrate surface is the second warpage, the absolute value of the size difference between the first opening size and the second opening size is set to the second value, wherein the first warpage is greater than the second warpage, and the first value is greater than the second value.

[0044] It should be noted that in this embodiment, the maximum warpage of the substrate surface can reflect whether the warpage of the substrate surface is severe. When the maximum warpage is a first warpage, it indicates that the warpage is severe, while when the maximum warpage is a second warpage, it indicates that the warpage is mild. In this embodiment, a preset threshold value can be used as the boundary to distinguish the first warpage from the second warpage.

[0045] Specifically, when the maximum warpage of the substrate surface is greater than the preset threshold, the maximum warpage of the substrate surface can be determined to be the first warpage. At this time, the warpage of the substrate surface is relatively serious, and the base surface height difference between the central area and the peripheral area is large. It is necessary to achieve a stronger compensation effect through a larger size difference to ensure that when the base surface height difference is large, the bumps formed after the solder balls in each area melt have the same or nearly the same height, thereby avoiding coplanarity problems caused by severe warpage of the substrate. Therefore, this embodiment can pre-calibrate the absolute value of the size difference between the first opening size and the second opening size that needs to be set when the coplanarity collapse or bulge caused by severe warpage is effectively suppressed under the first warpage, and record it as the first value. In actual application, the absolute value of the size difference between the first opening size and the second opening size is directly set to the pre-calibrated first value, simplifying the parameter adjustment steps in the production process and improving production efficiency and consistency.

[0046] When the warpage of the substrate surface is less than or equal to the threshold, the maximum warpage of the substrate surface can be determined to be the first warpage. At this time, the warpage of the substrate surface is relatively slight, and a smaller size difference can meet the coplanarity requirement, ensuring the consistency of the bump height and good coplanarity. Therefore, this embodiment can pre-calibrate the absolute value of the size difference between the first opening size and the second opening size that needs to be set when the coplanarity requirement is met without reverse deviation due to overcompensation under the second warpage, and record it as the second value. In actual application, the absolute value of the size difference between the first opening size and the second opening size is directly set to the pre-calibrated second value, further simplifying the parameter adjustment steps in the production process and improving production efficiency and consistency.

[0047] This embodiment dynamically adjusts the solder mask opening size difference through the warpage, and directly converts the quantitative data of the warpage into process parameters, so that the compensation strength and the degree of warpage accurately correspond to each other. This effectively suppresses the coplanarity collapse or bulge caused by severe warpage, while avoiding the reverse deviation caused by excessive compensation, thereby significantly improving the universality and stability of the substrate bump processing technology.

[0048] This embodiment refines the solder mask openings and performs refined solder mask window processing based on the warpage performance of the first substrate (convex or concave) during the solder mask processing before ball planting and surface treatment. This allows the bump height to be reduced in the area where the solder mask window is enlarged and increased in the area where the solder mask window is reduced after ball planting and before flattening, so as to compensate for and optimize the problem of poor bump coplanarity caused by substrate warping, optimize the bump leveling height and coplanarity, improve the quality and reliability of the solder joints between the chip and the substrate in the packaged product, and further improve the stability of the electrical connection between the package substrate and the chip.

[0049] It is worth mentioning that in the case of substrates with a high number of interconnected electronic contacts or large sizes, this embodiment achieves optimization of the bump leveling height and coplanarity on the substrate through an innovative process of refining the solder mask openings. This optimization can accurately control the height and coplanarity of the substrate bumps, ensuring that the bump height and coplanarity formed on large-scale substrates fully meet high standards. The optimized bump height and coplanarity meet strict requirements, greatly improving the quality of the solder joints between large-scale chips and the substrate after packaging. The highly consistent and well-coplanar bumps ensure a stable electrical connection between the chip and the substrate, reducing the probability of problems such as cold solder joints and short circuits, and effectively improving stability and reliability during long-term use.

[0050] It is worth mentioning that in a feasible embodiment, when the surface of the substrate where the solder mask layer is located is concavely warped, the third opening size of the solder mask opening at the second peripheral area is larger than the second opening size; or, when the surface of the substrate where the solder mask layer is located is convexly warped, the third opening size is smaller than the second opening size; wherein the second peripheral area is different from the first peripheral area and forms a cover for the first peripheral area.

[0051] It should be noted that the second peripheral area refers to an area in the peripheral area that is outer than the first peripheral area and covers the first peripheral area. The third opening size refers to the opening size of a single solder mask opening of the solder mask layer coated in the second peripheral area.

[0052] It is not difficult to understand that in this embodiment, when the surface of the substrate where the solder resist layer is located is concavely warped, the third opening size of the single solder resist opening of the solder resist layer coated in the second peripheral area is larger than the second opening size, and when the surface of the substrate where the solder resist layer is located is convexly warped, the third opening size is larger than the second opening size.

[0053] In this embodiment, the peripheral area is subdivided into a first peripheral area and a second peripheral area, wherein the first peripheral area forms a cover on the central area and has a lower warping degree than the central area, and the second peripheral area forms a cover on the first peripheral area and has a lower warping degree than the first peripheral area.

[0054] This embodiment divides the peripheral area into a first peripheral area and a second peripheral area according to the degree of warping, and performs more refined multi-level differentiated control on the opening size of the solder mask opening, accurately matching the warping gradient distribution of the substrate surface where the solder mask layer is located, and realizing more fine-grained active optimization of the bump height and coplanarity, further ensuring the consistency of the bump height and the uniformity of the coplanarity after flattening treatment.

[0055] In a feasible implementation, before the step of implanting solder balls into each solder resist opening in step S200, the substrate bump processing method may further include step B10: Step B10, performing surface treatment on the pad, and after the surface treatment is completed, applying flux on the pad; Those skilled in the art will understand that surface treatment refers to a series of physical or chemical processes performed on solder pads, such as cleaning and oxide layer removal, to ensure a clean and activated surface, thereby enhancing wettability and joint strength during subsequent soldering. Flux is a chemical used to remove oxides from metal surfaces during soldering and prevent the formation of new oxide layers. It improves the fluidity of molten solder and enhances soldering quality.

[0056] In this embodiment, proper surface treatment of the pads before solder ball implantation effectively removes contaminants and oxide layers from the pad surfaces, increasing wettability between the solder and the pads, thereby improving soldering quality. Applying flux to the treated pads further promotes solder fluidity and wettability during reflow, reducing the likelihood of soldering defects such as cold solder joints and short circuits, ultimately improving the reliability and stability of the solder joints.

[0057] Before the step of flattening the bumps formed corresponding to the solder balls in step S200, the substrate bump processing method may further include step C10: Step C10: After the reflow process is completed, a de-fluxing process is performed on the solder pad.

[0058] Those skilled in the art will recognize that defluxing is the process of removing flux residue remaining around solder joints after soldering using specific solvents or cleaning processes. Flux residue can affect the long-term stability and electrical performance of a circuit and must therefore be thoroughly removed.

[0059] After reflow, residual flux, if not promptly cleaned, can cause corrosion, reduce insulation resistance, and affect appearance. This is particularly critical in high-density and fine-line substrate designs. This embodiment effectively removes flux residue left over from the soldering process by performing a defluxing process on the solder pads, ensuring the cleanliness of the area surrounding the solder joints, avoiding potential issues caused by flux residue, and guaranteeing high product quality standards. Furthermore, this provides better working conditions for the subsequent flattening process, helping to achieve a more uniform and smooth bump height distribution, further improving the overall performance and reliability of the packaged product.

[0060] Based on the above-mentioned first embodiment, a substrate bump processing method according to a second embodiment of the present application is proposed.

[0061] In the second embodiment of the present application, for the same or similar contents as those in the above embodiments, please refer to the above introduction and will not be repeated hereafter.

[0062] In this embodiment, the step of flattening the bumps formed corresponding to the solder balls in step S200 may include step S210: Step S210 , performing a zone-by-zone flattening process on the bumps formed corresponding to the solder balls.

[0063] The partition flattening process refers to dividing the area covered by each convex point into a plurality of convex point areas, and performing flattening process on the convex points in each convex point area in turn.

[0064] It should be noted that partitioned flattening means that during the flattening process, not all convex points are flattened at once, but they are divided into several smaller areas (i.e., convex point areas) according to certain rules, and then the convex points in each area are flattened independently in turn.

[0065] Those skilled in the art will recognize that conventional one-shot flattening requires a machine capable of providing sufficient total pressure to simultaneously flatten all bumps. However, with larger substrates resulting in a significantly increased number of bumps, the pressure required for a single flattening operation rapidly increases with the number of bumps. Most conventional flattening machines are unable to meet this high pressure requirement, necessitating urgent upgrades and improvements to these machines.

[0066] In this regard, this embodiment proposes a method for zonal flattening processing. By logically dividing the area covered by the bumps on the substrate surface into multiple smaller bump areas and performing independent flattening operations on each bump area in sequence, the total pressure required for a single flattening operation is significantly reduced, avoiding excessive requirements for the machine equipment. In addition, zonal flattening processing not only alleviates the pressure limitation of the machine equipment but also improves the accuracy and uniformity in the flattening process because this method can better adapt to local warping of the substrate or uneven bump distribution, ensuring that each bump can be properly flattened. This method enables high-quality bump coplanarity control to be achieved through existing or moderately upgraded machines even when the number of bumps increases significantly due to large-sized substrates, thereby ensuring stable electrical connection between the chip and the substrate and reducing the occurrence probability of potential problems such as virtual soldering and short circuits, improving the reliability and stability of the final product.

[0067] In this embodiment, the bump areas can be flexibly divided according to the actual warping condition of the substrate, bump distribution density, or other factors, ensuring that the bumps in each area can be evenly and precisely flattened.

[0068] Exemplarily, in a feasible implementation manner, the method of dividing the area covered by each bump into multiple bump areas includes: dividing the area covered by each bump into four equal parts to obtain four bump areas; or dividing the area where each bump is located into a first bump area and a second bump area, where the first bump area is a bump area constructed around the position with the maximum warping degree on the concave surface or convex surface of the substrate, and the second bump area is a bump area different from the first bump area.

[0069] This embodiment provides two zonal division methods. The first is the zonal division method based on quartering, and the second is the zonal division method based on the geometric center (the second is similar to a "square within a square" zonal division method).

[0070] In the first zonal division method based on quartering, the area covered by the bumps on the substrate surface is evenly divided into four equal bump areas. Each bump area is independently flattened, which can significantly reduce the total pressure required for a single operation, enabling the existing machine to work effectively within its capacity, ensuring that the bumps in each area can obtain a relatively uniform pressure distribution, and avoiding the situation of excessive or insufficient local pressure.

[0071] It can be understood that, in addition to quartering, it can also be divided into eight equal parts or sixteen equal parts according to the actual situation, and this embodiment does not make specific restrictions on this.

[0072] It is not difficult to understand that in the zonal division method based on equal division (such as quartering, eight equal division), flattening the bumps covered by each bump area in sequence includes: Using the same or similar size of the indenter, and the same or similar pressure parameter conditions, the convex points covered by each convex point area are flattened in turn.

[0073] It should be noted that pressure parameters refer to a series of key process parameters set when performing the flattening operation with the indenter. These parameters directly affect the flattening effect of the bump and the final quality consistency. Specifically, pressure parameters may include pressure level (i.e., the amount of force applied by the indenter on the bump area), action time (i.e., the length of time the indenter exerts pressure on the bump area), and flattening speed (i.e., the speed at which the indenter approaches and applies pressure to the bump area).

[0074] It can be understood that pressure heads of similar sizes indicate that the size difference between the pressure heads is less than the preset value, and similar pressure parameter conditions indicate that the pressure difference between the pressure parameter conditions is less than the preset pressure difference threshold, the action time difference is less than the preset time difference threshold, the flattening speed difference is less than the preset speed difference threshold, etc.

[0075] In the equally divided zoning method, when flattening the bumps in each bump zone, the same or similar sized indenters and the same or similar pressure parameters are used. This means that all bump zones use the same or similar process parameters throughout the flattening process. This not only ensures the height consistency and coplanarity uniformity of the bumps within each bump zone, but also simplifies the process flow, reduces the errors that may be introduced by frequent adjustments to machine parameters, and improves overall production efficiency and product quality stability.

[0076] It is worth mentioning that in the partitioning method based on equal division, the number of convex points covered by each convex point area is equal; or, the difference in the number of convex points covered by each convex point area is less than a first preset threshold; or, the area of ​​each convex point area is equal; or, the area difference between each convex point area is less than a second preset threshold.

[0077] It should be noted that the first preset threshold is a preset number threshold used to determine whether the number of bumps covered by different bump regions is approximately equal. When the difference in the number of bumps covered by different bump regions is less than the first preset threshold, it indicates that the number of bumps covered by each bump region is approximately equal. The second preset threshold is a preset area threshold used to determine whether the areas of different bump regions are approximately equal. When the difference in the areas of different bump regions is less than the second preset threshold, it indicates that the areas of each bump region are approximately equal.

[0078] By controlling the difference in the number of bumps or the difference in area between each bump area, this embodiment can ensure that the bump density in each bump area is relatively consistent, avoiding excessive pressure or insufficient pressure on certain bump areas due to uneven bump distribution, ensuring a more balanced pressure distribution during the flattening operation, thereby achieving a more uniform pressure effect during the flattening process and further optimizing the bump coplanarity.

[0079] In the second partitioning method based on the geometric center, the area covered by the bumps on the substrate surface is divided into the first bump area and the second bump area according to the degree of warping. Therefore, for the number of bumps in each bump area, corresponding process parameter settings can be used (including the size of the pressure head and the pressure parameter conditions. When the number of bumps is the same or similar, the same process parameter settings are used. Generally, the more bumps there are in the bump area, the larger the value of the process parameter setting) to achieve a higher quality flattening effect. This differentiated process parameter setting can not only effectively cope with the challenges brought by substrate warping, but also optimize resource utilization and improve production efficiency while ensuring quality. In addition, by adopting targeted flattening parameters for different areas, the stability and reliability of the final product are further enhanced, and the probability of problems such as cold solder joints and short circuits caused by poor coplanarity is reduced, thereby meeting the strict requirements in high-density packaging scenarios.

[0080] It is not difficult to understand that when the surface of the substrate where the solder mask layer is located is concavely warped, the first bump area is a bump area constructed around the position of the largest warping in the concave surface of the substrate, and when the surface of the substrate where the solder mask layer is located is convexly warped, the first bump area is a bump area constructed around the position of the largest warping in the convex surface of the substrate.

[0081] It is worth mentioning that the second bump region covers the first bump region.

[0082] Although the present embodiment adds a partitioning step, the pressure requirement for each operation is greatly reduced, so the flattening task can be completed more efficiently during the actual production process, reducing the burden on equipment and the risk of potential failure.

[0083] In order to facilitate understanding of the technical concept or technical principle of the above-mentioned embodiment of the substrate bump processing method of the present application, a specific embodiment is listed below: like Figure 2As shown in the figure, in a package structure, the chip and substrate are connected via interconnecting bumps. As chip integration increases, the number of electronic contacts (i.e., bumps) connecting the chip and substrate increases dramatically, and the required substrate size also increases. This increase in substrate size leads to increased substrate warpage, making it more difficult to level large areas of bumps on the substrate to ensure that the required bump height and coplanarity (the difference between the maximum and minimum bump heights) are met. This ultimately affects the quality and reliability of the solder joints between the chip and substrate after packaging.

[0084] In addition, as the number of electronic contacts interconnecting the chip and the substrate increases dramatically, the demand for bumps on the substrate side increases accordingly. When flattening them, the required flattening pressure (flattening pressure = pressure of a single bump * number of bumps) will exceed the configuration of existing manufacturers' machines, requiring machine upgrades.

[0085] To address the above issues, this specific implementation proposes a technical solution of refined solder mask opening + step-by-step flattening, which can optimize the bump leveling height and coplanarity, and better ensure that the height and coplanarity meet the requirements, thereby improving the quality and reliability of the electrical connection between the packaging substrate and the chip.

[0086] Specifically, this specific embodiment first performs a warping analysis on the substrate to obtain the warping information of the substrate, and uses different colors to represent the warping conditions of different areas on the substrate through a warping distribution map, thereby intuitively displaying the warping information of the substrate, allowing engineers to quickly understand the warping conditions of the substrate through the changes in color on the warping distribution map.

[0087] Next, in this specific embodiment, during solder mask windowing before solder ball implantation and surface treatment, the solder mask layer is divided into different regions based on the warpage information displayed in the warpage distribution map, thereby fine-tuning the solder mask openings in the solder mask layer and achieving differentiated control of the opening sizes of the solder mask openings in different regions. In other words, based on the warpage information of the substrate, solder mask windows are opened in the solder mask layer applied to the substrate, resulting in at least two solder mask openings of different opening sizes.

[0088] Exemplarily, the solder resist layer is divided into a central region and a peripheral region, so that when the substrate surface where the solder resist layer is located is concavely warped, the opening size of a single solder resist opening in the central region is reduced by 2 μm or more, and the opening size of a single solder resist opening in the peripheral region is increased by 2 μm or more; when the substrate surface where the solder resist layer is located is convexly warped, the opening size of a single solder resist opening in the central region is increased by 2 μm or more, and the opening size of a single solder resist opening in the peripheral region is reduced by 2 μm or more. That is, when the substrate surface where the solder resist layer is located is concavely warped, the first opening size of the solder resist opening in the central region is smaller than the second opening size of the solder resist opening in the first peripheral region; or, when the substrate surface where the solder resist layer is located is convexly warped, the first opening size is larger than the second opening size; wherein the central region is a region constructed around the position with the largest warpage on the concave or convex surface of the substrate, and the first peripheral region is distinct from the central region and forms a covering around the central region.

[0089] In addition, based on processing feasibility considerations, this specific embodiment requires that when each solder mask opening is respectively implanted with a solder ball, the volume of the solder ball to be implanted in each solder mask opening should be consistent or nearly consistent, to ensure that before flattening after ball implantation, the larger the opening size of the solder mask opening, the lower the height formed after the solder ball is implanted and wetted and spread out. This ensures that the height of the bump after reflow soldering can be actively adjusted by adjusting the opening size of the solder mask opening in each area to compensate for the impact of the base surface height difference caused by substrate warping on the bump height.

[0090] It should be noted that the size of the solder mask opening is determined according to the warpage information. This specific embodiment can divide the warpage of the substrate surface into multiple gradients from low to high, and different gradients correspond to solder mask openings of different sizes. In the case of concave warping, the higher the warpage gradient, the smaller the corresponding solder mask opening, and in the case of convex warping, the higher the warpage gradient, the larger the corresponding solder mask opening. That is, when the maximum warpage of the substrate surface is determined to be the first warpage based on the warpage information, the absolute value of the size difference between the first opening size and the second opening size is set to the first value; when the maximum warpage of the substrate surface is determined to be the second warpage based on the warpage information, the absolute value of the size difference between the first opening size and the second opening size is set to the second value, wherein the first warpage is greater than the second warpage, and the first value is greater than the second value.

[0091] Finally, in this embodiment, the implanted solder balls are connected to the pads by reflow soldering, and the bumps formed by each solder ball are flattened in different areas. That is, a solder ball is implanted in each solder resist opening, and the implanted solder balls are connected to the pads by reflow soldering, and the bumps formed by each solder ball are flattened in different areas.

[0092] Specifically, this specific embodiment first divides the area covered by the convex points on the basic surface into multiple small convex point areas based on the principle of similar number of convex points in each divided area (that is, the number of convex points covered by each convex point area is equal; or the difference in the number of convex points covered by each convex point area is less than a first preset threshold; or the area of ​​each convex point area is equal; or the area difference between each convex point area is less than a second preset threshold). Then, using an indenter of the same or similar size and the same or similar pressure parameter conditions, the convex points covered by each convex point area are flattened in sequence.

[0093] It is not difficult to understand that after the area covered by the bump is divided into multiple small bump areas, the number of bumps required to be flattened in a single flattening is greatly reduced, and the required flattening pressure is correspondingly greatly reduced. There is no need to significantly update and upgrade the existing machine, which effectively reduces the equipment cost. In addition, different bump areas can use the same or similar size of indenters and set the same or similar pressure parameter conditions to ensure that the flattening effect of each bump area after the partition flattening process is almost the same, thereby providing consistency in bump height and uniformity in coplanarity.

[0094] In this specific embodiment, there are two warping modes on the substrate surface of the large-size substrate, the first being concave warping and the second being convex warping.

[0095] In one example, in the warpage distribution graph, the closer the color of the area is to dark red, the lower the actual height of the welding plate is, and the closer the color of the area is to blue-purple, the higher the actual height of the welding plate is.

[0096] like Figure 3 ,When the warpage distribution diagram obtained by the warpage analysis, the color of the area closer to the center position is closer to dark red, ,indicating that the substrate surface is concavely warped.

[0097] like Figure 4When the substrate surface is concavely warped, this specific embodiment can divide the solder mask layer into a central area and a peripheral area. The central area is constructed around the location of the largest warpage in the concave surface of the substrate, corresponding to the area covered by the blue dots in the figure. The peripheral area is the area outside the central area, and can be specifically subdivided into a first peripheral area, a second peripheral area, and four corner areas. Among them, the first peripheral area covers the central area, corresponding to the area covered by the cyan dots in the figure, the second peripheral area covers the second peripheral area, corresponding to the area covered by the yellow dots in the figure, and the four corner areas correspond to the areas covered by the red dots in the figure.

[0098] After dividing the center area, the first peripheral area, the second peripheral area, and the four corner areas, the solder mask openings can be refined by area. Different areas are processed to obtain solder mask openings of different opening sizes. The opening size of the solder mask openings in the four corner areas (i.e., the red dots) is larger than the opening size of the solder mask openings in the second peripheral area (i.e., the yellow dots), larger than the opening size of the solder mask openings in the first peripheral area (i.e., the cyan dots), and larger than the opening size of the solder mask openings in the center area (i.e., the blue dots). This ensures that the bumps formed by solidification after reflow soldering can compensate for the effect of the solder plate being lower in the middle and higher around the edges due to substrate concavity on the coplanarity of the bumps. In other words, if the substrate surface where the solder mask layer is located is concave and warped, the first opening size of the solder mask opening in the center area is smaller than the second opening size of the solder mask opening in the first peripheral area, and the third opening size of the solder mask opening in the second peripheral area is larger than the second opening size.

[0099] Finally, based on the four-equal division method, the area covered by each bump is divided into four bump areas with the same or almost the same area or number of bumps. Using the same or similar size indenter and the same or similar pressure parameter conditions, the bumps covered by each bump area are flattened in turn.

[0100] In addition, if Figure 5 As shown in the figure, when the substrate surface is concavely warped, the solder mask layer can be divided into a central area and a peripheral area. The central area is constructed around the location of the substrate's concave surface with the largest warpage (corresponding to the area covered by the red dots in the figure). The peripheral area is the area outside the central area and covers the central area. It can be specifically subdivided into a corner area including at least four corners (corresponding to the area covered by the yellow dots in the figure) and other areas (corresponding to the area covered by the brown dots in the figure).

[0101] After dividing the central area and the peripheral area, the solder mask opening can be refined according to the area. Different areas are processed to obtain solder mask openings of different opening sizes. The opening of the solder mask opening in the central area (i.e., the red dot) is reduced, and the opening of the solder mask opening in other areas of the peripheral area (i.e., the brown dot) remains unchanged. The opening of the solder mask opening in at least four corner areas in the peripheral area (i.e., the yellow dot) is enlarged to ensure that the bumps formed by solidification after reflow soldering can compensate for the impact of the lower middle and higher surrounding areas of the solder plate caused by the depression of the substrate on the coplanarity of the bumps.

[0102] Finally, based on the four-equal division method, the area covered by each bump is divided into four bump areas with the same or almost the same area or number of bumps. After surface treatment, solder ball implantation, reflow soldering and deflux, the bumps covered by the four bump areas are flattened in turn using small indenters of the same or similar size and the same or similar pressure parameter conditions.

[0103] like Figure 6 ,When the warpage distribution diagram obtained by the warpage analysis, the color of the area closer to the center position is closer to blue-purple, ,it indicates that the substrate surface is convexly warped.

[0104] like Figure 7 When the substrate surface is convex and warped, this specific embodiment can divide the solder mask layer into a central area and a peripheral area. The central area is constructed around the location of the maximum warpage on the convex surface of the substrate, corresponding to the area covered by the red dots in the figure. The peripheral area is the area outside the central area and can be specifically divided into a first peripheral area and a corner area. The first peripheral area covers the central area and corresponds to the area covered by the yellow dots in the figure, and the corner area corresponds to the area covered by the blue dots in the figure.

[0105] After dividing the central area, the first peripheral area and the corner area, the solder mask openings can be refined according to the area. Different areas are processed to obtain solder mask openings of different opening sizes. The opening size of the solder mask openings in the corner area (i.e., the blue dots) is larger than the opening size of the solder mask openings in the first peripheral area (i.e., the yellow dots), and larger than the opening size of the solder mask openings in the central area (i.e., the red dots). This ensures that the bumps formed by solidification after reflow soldering can compensate for the impact of the substrate protrusion causing the solder plate to be higher in the middle and lower around on the bump height.

[0106] Finally, based on the U-shaped partitioning method, the area covered by each bump is divided into a first bump area and a second bump area, wherein the first bump area is a bump area constructed at the position with the largest warping in the concave surface of the substrate (corresponding to the central area), and the second bump area is a bump area different from the first bump area (corresponding to the peripheral area), so that corresponding process parameter settings (including the size of the pressure head and pressure parameter conditions) are adopted for the number of bumps in each bump area to achieve a higher quality flattening effect.

[0107] In addition, if Figure 8 As shown, when the substrate surface is convex and warped, this specific embodiment can divide the solder mask layer into a central area and a peripheral area. The central area is constructed around the location of the maximum warpage on the convex surface of the substrate (corresponding to the area covered by the red dots in the figure). The peripheral area is the area outside the central area and can be specifically subdivided into a first peripheral area (corresponding to the area covered by the brown dots in the figure) and a second peripheral area (corresponding to the area covered by the yellow dots in the figure). The first peripheral area forms a cover around the central area, and the second peripheral area forms a cover around the first peripheral area.

[0108] After dividing the central and peripheral regions, the solder mask openings can be refined by region. Different regions are processed to obtain solder mask openings of different opening sizes. The openings of the solder mask openings in the central region (i.e., the red dots) are reduced, the openings of the solder mask openings in the first peripheral region (i.e., the brown dots) remain unchanged, and the openings of the solder mask openings in the second peripheral region (i.e., the yellow dots) are increased. This ensures that the bumps formed by solidification after reflow can compensate for the impact of the bump coplanarity caused by the substrate protrusion, which is higher in the middle and lower around the edges. In other words, if the substrate surface where the solder mask layer is located is convex and warped, the first opening size is larger than the second opening size, and the third opening size is smaller than the second opening size.

[0109] Finally, based on the U-shaped partitioning method, the area covered by each bump is divided into a first bump area and a second bump area, wherein the first bump area is a bump area constructed at the position with the largest warping in the concave surface of the substrate (corresponding to the central area and the first peripheral area), and the second bump area is a bump area different from the first bump area (corresponding to the second peripheral area). After surface treatment, solder ball implantation, reflow soldering and deflux, corresponding process parameter settings (including the size and pressure parameter conditions of the indenter, for example, a small indenter is used in the first bump area and a U-shaped indenter is used in the second bump area) can be used for the number of bumps in each bump area, thereby achieving a higher quality flattening effect.

[0110] like Figure 9As shown, the bump heights of the package substrate 1 processed using the related art are inconsistent and the coplanarity is poor, while the bump heights of the package substrate 2 processed using the substrate bump processing method provided in this specific embodiment are consistent and have good coplanarity. Compared with the related art, the substrate bump processing method provided in this specific embodiment can accurately control the height and coplanarity of the substrate bumps, ensuring that the bump height and coplanarity formed on large-scale substrates fully meet high standards, thereby forming a stable electrical connection between the chip and the substrate, reducing the probability of problems such as cold solder joints and short circuits, and effectively improving stability and reliability during long-term use.

[0111] It should be noted that the above examples are only used to assist in understanding the present application and do not constitute a limitation on the substrate bump processing method of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0112] In addition, an embodiment of the present application also provides a packaging substrate, which is a substrate manufactured using the substrate bump processing method in the above embodiment.

[0113] The packaging substrate provided in this application can address the technical issue of poor coplanarity between individual bumps on large-scale substrates, which leads to low solder joint quality and reliability between the chip and substrate in packaged products. Compared to the prior art, the packaging substrate provided in this application provides the same beneficial effects as the substrate bump processing method provided in the aforementioned embodiment, and will not be further elaborated here.

[0114] In addition, an embodiment of the present application also provides a packaging structure, which includes a packaging substrate in the above embodiment and a chip soldered to the substrate surface of the packaging substrate, and the bumps on the bottom of the chip are connected one-to-one with the bumps on the packaging substrate.

[0115] The packaging structure provided in this application can address the technical issue of poor coplanarity between bumps on large-scale substrates, which leads to low solder joint quality and reliability between the chip and substrate in packaged products. Compared to the prior art, the packaging structure provided in this application provides the same beneficial effects as the packaging substrate provided in the aforementioned embodiments, and will not be further elaborated here.

[0116] The above description is only part of the embodiments of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made by using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A substrate bump processing method comprising: Based on the warpage information of the substrate, performing solder mask opening on the solder mask layer coated on the substrate to obtain solder mask openings with at least two different opening sizes; Implanting solder balls into each solder resist opening respectively, connecting the implanted solder balls to the pads by reflow soldering, and flattening the bumps formed corresponding to the solder balls; In the case where the surface of the substrate where the solder resist layer is located is concavely warped, a first opening size of the solder resist opening in the central area is smaller than a second opening size of the solder resist opening in the first peripheral area; or, in the case where the surface of the substrate where the solder resist layer is located is convexly warped, the first opening size is larger than the second opening size; wherein the central area is an area constructed around the position with the largest warpage in the concave surface of the substrate or the convex surface of the substrate, and the first peripheral area is different from the central area and forms a cover for the central area.

2. The substrate bump processing method according to claim 1, wherein: The method further comprises: When it is determined based on the warpage information that the maximum warpage of the substrate surface is a first warpage, setting the absolute value of the size difference between the first opening size and the second opening size to a first value; When it is determined that the maximum warpage of the substrate surface is the second warpage based on the warpage information, the absolute value of the size difference between the first opening size and the second opening size is set to a second value, wherein the first warpage is greater than the second warpage, and the first value is greater than the second value.

3. The substrate bump processing method according to claim 1, wherein: Flattening the bumps formed corresponding to the solder balls, including: Performing a zone-by-zone flattening process on the bumps formed corresponding to the solder balls; The partition flattening process refers to dividing the area covered by each of the convex points into a plurality of convex point areas, and performing flattening process on the convex points in each of the convex point areas in turn.

4. The substrate bump processing method according to claim 3, wherein: The number of convex points covered by each convex point region is equal; or, The difference in the number of convex points covered by each convex point region is less than a first preset threshold; or, The area of ​​each of the convex point regions is equal; or, The area difference between each of the convex point regions is smaller than a second preset threshold.

5. The substrate bump processing method according to claim 3, wherein: The method of dividing the area covered by each of the convex points into a plurality of convex point areas includes: Divide the area covered by each of the convex points into four equal parts to obtain four convex point areas; or, The area where each of the convex points is located is divided into a first convex point area and a second convex point area, wherein the first convex point area is a convex point area constructed around the position with the largest warping in the concave surface of the substrate or the convex surface of the substrate, and the second convex point area is a convex point area different from the first convex point area.

6. The substrate bump processing method according to claim 4, wherein: The convex points covered by each convex point area are flattened in sequence, including: Using indenters of the same or similar size and the same or similar pressure parameter conditions, the convex points covered by each convex point area are flattened in turn.

7. The substrate bump processing method according to any one of claims 1 to 6, wherein: Each solder resist opening is corresponding to the implantation of a solder ball, wherein the volume of each implanted solder ball is consistent, or the volume difference between each implanted solder ball is less than a third preset threshold.

8. The substrate bump processing method according to claim 7, wherein: In a case where the substrate surface where the solder resist layer is located is concavely warped, a third opening size of the solder resist opening at the second peripheral area is larger than the second opening size; or, In a case where the substrate surface where the solder resist layer is located is convexly warped, the third opening size is smaller than the second opening size; The second peripheral area is different from the first peripheral area and covers the first peripheral area.

9. The substrate bump processing method according to any one of claims 1 to 6, wherein: Before implanting solder balls into each solder resist opening, the method further includes: Performing surface treatment on the pad, and coating the pad with soldering flux after the surface treatment is completed; Before flattening the bumps formed corresponding to the solder balls, the method further includes: After the reflow process is completed, a de-fluxing process is performed on the solder pad.

10. A packaging substrate, characterized in that: The packaging substrate is a substrate manufactured by the substrate bump processing method according to any one of claims 1 to 9.

11. A packaging structure, characterized in that: It comprises the packaging substrate as claimed in claim 10, and a chip soldered to the substrate surface of the packaging substrate, wherein the bumps on the bottom of the chip are connected to the bumps on the packaging substrate in a one-to-one correspondence.

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