Chip packaging structure and packaging method thereof

Abstract

The invention provides a chip packaging structure and a packaging method thereof. The chip packaging method comprises the following steps that a plurality of chips are provided, a plurality of bonding welding pads are formed on the surface of each chip, and a plurality of conductive welding pads are formed on the back face of each chip; forming a plurality of conductive wires on the side surface of each chip, wherein each conductive wire is electrically connected with the corresponding bonding welding pad and the corresponding conductive welding pad; a substrate is provided, the multiple chips are sequentially stacked on the surface of the substrate to form a chip stacking structure, and the bonding welding pads of the chips on the lower layer of every two adjacent chips are correspondingly and electrically connected to the conductive welding pads of the chips on the upper layer of every two adjacent chips. According to the technical scheme, the conductive welding pads are formed on the back surface of the chip, and the bonding welding pads on the surface of the chip are conductively connected with the conductive welding pads on the back surface by using the conductive wires arranged on the side surface of the chip. Vertical stacking can be carried out without using a through silicon via (TSV), the product size can be controlled, and the cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging, and in particular to a chip packaging structure and a packaging method thereof. Background Art

[0002] Currently, traditional multi-chip stacked storage products use die attach film (DAF) material to stick on the back of the chip through the die attaching process to achieve chip fixation and multi-chip stacking, and wire bonding to achieve electrical connection between each layer of chips.

[0003] This method significantly increases the size and material consumption of storage products. DAF material itself has a certain thickness. When stacking multiple chips, each layer of chips requires DAF bonding. This increases the spacing between chips, thereby increasing the vertical thickness of the entire chip stack, which is not conducive to product miniaturization.

[0004] Furthermore, since wire bonding requires that a location for a bonding pad be reserved on the chip surface, the chip stack is offset in the horizontal direction, thereby increasing the horizontal dimension of the chip stack structure.

[0005] In addition, during the multi-chip stacking process, a large amount of DAF material is required to paste each layer of chips, and a large amount of lead consumables are also consumed, which not only increases the material procurement cost, but also increases the material consumption in the entire production process.

[0006] Therefore, how to improve the size increase and increased material consumption caused by the chip bonding process is a problem that needs to be solved at present. Summary of the Invention

[0007] The technical problem to be solved by the present invention is how to improve the size increase and material consumption increase caused by the chip bonding process, and to provide a chip packaging structure and a packaging method thereof.

[0008] In order to solve the above problems, the present invention provides a chip packaging method, comprising the following steps:

[0009] Providing a plurality of chips, each of which has a plurality of bonding pads formed on a surface thereof and a plurality of conductive pads formed on a back surface thereof;

[0010] A plurality of conductive lines are formed on the side surface of each chip, each conductive line being electrically connected to the corresponding bonding pad and the conductive pad;

[0011] A substrate is provided, and a plurality of chips are sequentially stacked on the surface of the substrate to form a chip stacking structure, wherein the bonding pads of the lower chip of two adjacent chips are electrically connected to the conductive pads of the upper chip.

[0012] In some embodiments, a plurality of chips having the same size are provided, and side surfaces of the plurality of chips are flush.

[0013] In some embodiments, the method of providing a plurality of chips, wherein a plurality of bonding pads are formed on the surface of each chip, and a plurality of conductive pads are formed on the back of each chip, specifically comprises the following steps:

[0014] Providing a wafer, wherein a plurality of chips are formed on a surface of the wafer, and a plurality of bonding pads are formed at an edge of the surface of each chip;

[0015] forming a plurality of conductive pads on the back side of the wafer, wherein the conductive pads are distributed at the edge of each chip;

[0016] The wafer is cut into individual chips.

[0017] In some embodiments, before the step of forming a plurality of conductive pads on the back side of the wafer, the following steps are further included:

[0018] forming a protective film on the surface of the wafer;

[0019] The back side of the wafer is thinned.

[0020] In some embodiments, forming a plurality of conductive pads on the back side of the wafer specifically includes the following steps:

[0021] A dry film is applied to the back of the wafer and patterned to form a patterned dry film; a patterned metal layer is formed on the back of the wafer using the patterned dry film as a mask layer to serve as the conductive pad;

[0022] The protective film and the dry film are removed.

[0023] In some embodiments, forming a plurality of conductive lines on the side of the chip specifically includes the following steps:

[0024] A plurality of conductive lines are formed on the side of the chip by a wire bonding process, and each conductive line extends from the bonding pad to the corresponding conductive pad.

[0025] In some embodiments, forming a plurality of conductive lines on the side of the chip specifically includes the following steps:

[0026] A plurality of conductive lines are formed on the side of the chip by using flexible microelectronic printing technology, and each conductive line extends from the bonding pad through the chip surface, the chip side, the chip back and the corresponding conductive pad.

[0027] In some embodiments, forming a plurality of conductive lines on the side of the chip specifically includes the following steps:

[0028] A plurality of conductive lines are formed on the side of the chip by a wire bonding process, and each conductive line extends from the bonding pad to the corresponding conductive pad.

[0029] In some embodiments, before the step of forming a plurality of conductive lines on each side surface of the chip, the method further includes: forming a first dielectric layer between the side surface of the chip and the conductive lines.

[0030] In some embodiments, before the step of forming a plurality of conductive lines on each side surface of the chip, the method further includes: forming a second dielectric layer between the back surface of the chip and the conductive pad.

[0031] In some embodiments, after forming a plurality of conductive lines on the side surface of each chip, the method further includes forming solder at the conductive pad.

[0032] In some embodiments, the chip and the substrate are fixed and electrically connected via the solder; and two adjacent chips are fixed and electrically connected via the solder.

[0033] In some embodiments, after the step of sequentially stacking the plurality of chips on the surface of the substrate to form a chip stacking structure, the method further includes the following steps:

[0034] Soldering is completed using a reflow process.

[0035] In some embodiments, after the step of sequentially stacking the plurality of chips on the surface of the substrate to form a chip stacking structure, the method further includes the following steps:

[0036] A plastic package covering the chip is formed on the surface of the substrate.

[0037] In some embodiments, forming a plastic package covering the chip on the surface of the substrate specifically includes the following steps:

[0038] The plastic package is formed by injection molding of epoxy resin molding compound.

[0039] In order to solve the above problems, the present invention provides a chip packaging structure, comprising:

[0040] substrate;

[0041] A chip stacking structure includes multiple chips stacked in sequence on the surface of the substrate, multiple bonding pads formed on the surface of each chip, multiple conductive pads formed on the back of each chip, and multiple conductive lines formed on the side of each chip. Each conductive line is electrically connected to the corresponding bonding pad and the conductive pad, and the bonding pad of the lower chip of two adjacent chips is electrically connected to the conductive pad of the upper chip.

[0042] In some embodiments, a plurality of chips having the same size are provided, and side surfaces of the plurality of chips are flush.

[0043] In some embodiments, the bonding pad is located at an edge of the chip surface;

[0044] The conductive pad is located at the edge of the back side of the chip.

[0045] In some embodiments, each of the conductive wires extends from the bonding pad through the chip surface, the chip side surface, the chip back surface, and the corresponding conductive pad.

[0046] In some embodiments, each of the conductive lines extends from the bonding pad to the corresponding conductive pad through the side surface of the chip.

[0047] In some embodiments, solder is formed on the conductive pad.

[0048] In some embodiments, the bonding pads of the lower chip of two adjacent chips are electrically connected to the conductive pads of the upper chip through the solder.

[0049] In some embodiments, the conductive pad is a metal layer.

[0050] In some embodiments, a first dielectric layer is formed between the side surface of the chip and the conductive line.

[0051] In some embodiments, a second dielectric layer is formed between the back side of the chip and the conductive pad.

[0052] In some embodiments, the chip and the substrate are fixed and electrically connected via the solder; and two adjacent chips are fixed and electrically connected via the solder.

[0053] In some embodiments, a plastic package is further included, covering the substrate and the chip surface.

[0054] The above technical solution forms the conductive pads on the back of the chip and uses conductive wires arranged on the side of the chip to electrically connect the bonding pads on the chip surface to the conductive pads on the back. This allows vertical stacking without the use of through-silicon vias (TSVs), which can control product size and reduce costs.

[0055] First, traditional TSV technology requires deep hole machining and filling on the wafer, which is not only complex and costly, but also prone to stress concentration and reduced reliability. By eliminating the complex machining process required by TSV technology, there is no need to reserve deep hole space inside the chip, reducing process complexity and conserving internal chip space.

[0056] Secondly, traditional chip stacking methods typically use thick die-attachment films to secure the chips, which undoubtedly increases the overall thickness of the chip stack. However, in the present invention, the conductive pads are extremely thin, offering a significant thickness advantage over traditional die-attachment films. This improvement significantly reduces the vertical thickness of the chip stack.

[0057] Taking a common chip stacking application as an example, when using chip adhesive film, the vertical thickness of the chip stack structure can reach several millimeters or even thicker. However, using the chip packaging method described in this invention, this vertical thickness can be reduced to a fraction of the original thickness or even less. This reduction in thickness effectively reduces the vertical dimensions of the chip stack structure, making it possible to achieve thinner and lighter electronic devices.

[0058] Furthermore, the solder is further used to vertically secure and electrically connect the underlying chips, allowing chips of the same size to be stacked vertically. Traditional chip stacking methods often result in uneven horizontal arrangement of chips due to process limitations, thereby increasing the horizontal size of the entire chip stack. The chip packaging method of the present invention, by maintaining the side surfaces of the chips flush, can limit the horizontal size of the chip stack to the size of the chips, further reducing the size of the device in the horizontal direction.

[0059] Finally, traditional chip stacking methods require the use of large amounts of chip-bonding film to bond each layer of chips, as well as a significant amount of lead wire consumables. The procurement costs of these materials account for a significant portion of the entire chip manufacturing process. The chip packaging method described in the present invention eliminates the need for large amounts of chip-bonding film to bond each layer of chips, nor does it consume a significant amount of lead wire consumables, thus reducing material procurement costs.

[0060] In summary, this technical solution has achieved remarkable results in reducing the thickness of the chip stacking structure, reducing the device size, and reducing material costs by forming a conductive pad on the back of the chip and using flexible microelectronics printing technology to achieve conductive connection, providing a new feasible solution for the development of semiconductor chip manufacturing technology.

[0061] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present invention. Technologies, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered part of the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for describing the specific embodiments. Obviously, the drawings described below are only some specific embodiments of the present invention. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0063] Figure 1 A schematic diagram of a chip packaging structure formed by stacking multiple chips using a die bonding film and a die bonding process;

[0064] Figure 2 A flowchart of the steps of an embodiment of the chip packaging method of the present invention;

[0065] Figure 3 A cross-sectional process structure diagram of a wafer is provided for one embodiment of the chip packaging method of the present invention;

[0066] Figure 4 A cross-sectional structural diagram of the process for thinning the back side of the wafer according to an embodiment of the chip packaging method of the present invention;

[0067] Figure 5 A backside process structure diagram of a wafer is provided for one embodiment of the chip packaging method of the present invention;

[0068] Figure 6 This is a back-side process structure diagram of attaching a dry film to the back side of the wafer according to an embodiment of the chip packaging method of the present invention;

[0069] Figure 7 This is a backside process structure diagram of forming a conductive pad on the backside of the wafer according to an embodiment of the chip packaging method of the present invention;

[0070] Figure 8 A back-side process structure diagram of removing the protective film and the dry film according to an embodiment of the chip packaging method of the present invention;

[0071] Figure 9 A cross-sectional process structure diagram of the individual chips formed by cutting the wafer according to an embodiment of the chip packaging method of the present invention;

[0072] Figure 10 A cross-sectional process structure diagram showing a process of forming a plurality of conductive lines on the side surface of each chip according to an embodiment of the chip packaging method of the present invention;

[0073] Figure 11 A cross-sectional structural diagram of a process for forming solder at the conductive pad according to an embodiment of the chip packaging method of the present invention;

[0074] Figure 12 A cross-sectional structural diagram of a chip packaging method according to an embodiment of the present invention for packaging the chip on the surface of the substrate;

[0075] Figure 13 A cross-sectional process diagram of forming a chip stacking structure according to an embodiment of the chip packaging method of the present invention;

[0076] Figure 14 This is a cross-sectional structural diagram of the process for forming a plastic package body according to an embodiment of the chip packaging method of the present invention;

[0077] Figure 15 A schematic structural diagram of a chip packaging structure formed by another embodiment of the chip packaging method of the present invention;

[0078] Figure 16 This is a cross-sectional process structure diagram of forming multiple conductive lines on the side surface of each chip according to another embodiment of the chip packaging method of the present invention. DETAILED DESCRIPTION

[0079] The following is a clear and complete description of the technical solutions in the embodiments of the present invention, with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present invention.

[0080] Multi-chip stacked storage products use chip attaching film (DAF) material to stick on the back of the chip through the die attaching process to achieve chip fixation and multi-chip stacking, and use wire bonding to achieve electrical connection between each layer of chips.

[0081] See also Figure 1 , which is a schematic diagram of the chip packaging structure formed by using a die bonding film and die bonding process to stack multiple chips. The specific process steps are as follows:

[0082] (1) providing a wafer, and performing back grinding and thinning on the wafer;

[0083] (2) attaching a die attach film (DAF) 11 to the back side of the wafer;

[0084] (3) cutting the wafer to form individual chips 12;

[0085] (4) sucking the chip 12 with a nozzle;

[0086] (5) Encapsulating the chip 12 onto the substrate 13 through a die attaching process;

[0087] (6) stacking a plurality of the chips 12 and bonding the chips 12 with wires 14;

[0088] (7) Forming a plastic package body 15.

[0089] like Figure 1 As shown, the chip adhesive film 11 itself has a certain thickness. When multiple chips 12 are stacked, each layer of the chips 12 needs to be adhered using the chip adhesive film 11, which increases the spacing between the chips 12, thereby increasing the thickness of the entire chip stacking structure in the vertical direction, which is not conducive to the miniaturization development of the product.

[0090] Furthermore, since the bonding of the wires 14 requires that a bonding pad be reserved on the surface of the chip 12 , when the chips 12 are stacked, an offset needs to be formed in the horizontal direction, thereby increasing the horizontal dimension of the chip stacking structure.

[0091] In addition, during the stacking process of multiple chips 12, a large amount of the chip adhesive film 11 is required to stick each layer of the chip 12, and a large amount of the lead 14 consumables are also consumed, which not only increases the material procurement cost, but also increases the material consumption in the entire production process.

[0092] In order to improve the size increase and material consumption increase caused by the chip bonding process, the present invention provides a chip packaging method.

[0093] See also Figure 2 , which is a step flow chart of an embodiment of the chip packaging method of the present invention.

[0094] like Figure 2 As shown, the chip packaging method includes the following steps:

[0095] Step S21, providing a plurality of chips, wherein a plurality of bonding pads are formed on the surface of each chip, and a plurality of conductive pads are formed on the back surface of each chip;

[0096] Step S22, forming a plurality of conductive lines on the side surface of each chip, wherein each conductive line is electrically connected to the corresponding bonding pad and the conductive pad;

[0097] In step S23 , a substrate is provided, and a plurality of chips are sequentially stacked on the surface of the substrate to form a chip stacking structure, wherein the bonding pads of the lower chip of two adjacent chips are electrically connected to the conductive pads of the upper chip.

[0098] See also Figures 3 to 14 ,in, Figure 3 A cross-sectional process structure diagram of a wafer is provided for one embodiment of the chip packaging method of the present invention; Figure 4 A cross-sectional structural diagram of the process for thinning the back side of the wafer according to an embodiment of the chip packaging method of the present invention; Figure 5 A backside process structure diagram of a wafer is provided for one embodiment of the chip packaging method of the present invention; Figure 6 This is a back-side process structure diagram of attaching a dry film to the back side of the wafer according to an embodiment of the chip packaging method of the present invention; Figure 7 This is a backside process structure diagram of forming a conductive pad on the backside of the wafer according to an embodiment of the chip packaging method of the present invention; Figure 8 A back-side process structure diagram of removing the protective film and the dry film according to an embodiment of the chip packaging method of the present invention; Figure 9 A cross-sectional process structure diagram of the individual chips formed by cutting the wafer according to an embodiment of the chip packaging method of the present invention; Figure 10 A cross-sectional process structure diagram showing a process of forming a plurality of conductive lines on the side surface of each chip according to an embodiment of the chip packaging method of the present invention; Figure 11 A cross-sectional structural diagram of a process for forming solder at the conductive pad according to an embodiment of the chip packaging method of the present invention; Figure 12 A cross-sectional structural diagram of a chip packaging method according to an embodiment of the present invention for packaging the chip on the surface of the substrate; Figure 13 A cross-sectional process diagram of forming a chip stacking structure according to an embodiment of the chip packaging method of the present invention; Figure 14 This is a cross-sectional structural diagram of the process for forming a plastic package body according to an embodiment of the chip packaging method of the present invention.

[0099] See also Figures 3 to 9 In step S21 , a plurality of chips 31 are provided. A plurality of bonding pads 311 are formed on a surface S1 of each chip 31 , and a plurality of conductive pads 312 are formed on a back surface S2 of each chip 31 .

[0100] Specifically, if Figures 3 to 9As shown, in some embodiments, providing a plurality of chips 31, each of the chips 31 having a plurality of bonding pads 311 formed on a surface S1 thereof, and each of the chips 31 having a plurality of conductive pads 312 formed on a back surface S2 thereof specifically includes the following steps:

[0101] like Figures 3 to 5 As shown, a wafer 30 is provided, wherein the wafer 30 includes a plurality of chips 31, and a plurality of bonding pads 311 (shown in FIG. Figures 9 to 14 ). The surface of the wafer 30 is the surface S1 of the chip 31 (shown in FIG. Figures 9 to 14 ), the back side of the wafer 30 is the back side S2 of the chip 31 (shown in FIG. Figures 9 to 14 ).

[0102] In some embodiments, before the step of forming a plurality of conductive pads 312 on the back side of the wafer 30 , the following steps are further included:

[0103] like Figure 3 As shown, a protective film 301 is formed on the surface of the wafer 30. In some embodiments, a functional circuit layer 310 is further formed on the surface of the chip 31, and the protective film 301 is formed on the surface of the functional circuit layer 310.

[0104] like Figure 4 As shown, the back side of the wafer 30 is thinned. In some embodiments, the back side of the wafer 30 can be thinned by mechanical grinding or chemical mechanical polishing (CMP).

[0105] like Figures 6 to 8 As shown, a plurality of conductive pads 312 are formed on the back side of the wafer 30 , and the conductive pads 312 are distributed at the edge of each chip 31 .

[0106] The bonding pad 311 and the conductive pad 312 are both disposed on the edge of the chip 31 to reduce the length of the conductive line 313 to be formed subsequently, thereby reducing costs and process complexity.

[0107] Figures 6 to 8 An embodiment of forming a plurality of conductive pads 312 on the back side of the wafer 30 is provided.

[0108] In this embodiment, forming a plurality of conductive pads 312 on the back side of the wafer 30 specifically includes the following steps:

[0109] like Figure 6 As shown, a dry film 302 is attached to the back of the wafer 30 and patterned to form the patterned dry film 302. In this embodiment, the step of patterning the dry film 302 further includes exposing and developing the dry film 302.

[0110] like Figure 7 As shown, the patterned dry film 302 is used as a mask layer to form a patterned metal layer on the back side of the wafer 30 to serve as the conductive pad 312 .

[0111] In this embodiment, the metal layer is a copper plating layer. Copper can be plated on the back of the wafer 30 by using electroplating, chemical plating or other processes to form the copper plating layer.

[0112] Using the copper plating layer as the conductive pad 312 can provide an extremely low-resistance path for current transmission between the chips 31, effectively reducing signal transmission loss and power loss, and significantly improving the electrical performance and operating efficiency of the chip.

[0113] During the manufacturing process, the copper plating parameters can be flexibly adjusted according to the design requirements of the chip 31, such as increasing the plating thickness in areas that require higher conductivity, and achieving ultra-thin and uniform plating in areas where high dimensional accuracy is required, to meet diverse chip manufacturing needs and improve production efficiency and product yield.

[0114] The use of copper plating as the conductive pad 312 makes the conductive pad 312 extremely thin, which is significantly thinner than conventional chip attach films. This improvement greatly reduces the thickness of the chip stacking structure in the vertical direction.

[0115] In other embodiments, the metal layer may also be a silver-plated layer.

[0116] Taking a common chip stacking application as an example, when using chip adhesive film, the vertical thickness of the chip stack structure can reach several millimeters or even thicker. However, using the chip packaging method described in this invention, this vertical thickness can be reduced to a fraction of the original thickness or even less. This reduction in thickness effectively reduces the vertical dimensions of the chip stack structure, making it possible to achieve thinner and lighter electronic devices.

[0117] like Figure 8 As shown, remove the protective film 301 (shown in Figures 3 and 4 ) and the dry film 302 (shown in Figures 5 to 7 ).

[0118] Finish Figures 6 to 8 The process steps shown are used to form a plurality of conductive pads 312 on the back side of the wafer 30 .

[0119] like Figure 9 As shown, the wafer 30 is cut to form the independent chips 31. Each cut surface of the chip 31 is a side surface S3 of the chip 31.

[0120] In some embodiments, the wafer 30 may be cut into independent chips 31 by mechanical cutting, laser cutting, or plasma cutting.

[0121] Finish Figures 3 to 9 Through the process steps shown, a plurality of chips 31 can be obtained. A plurality of bonding pads 311 are formed on the surface S1 of each chip 31 , and a plurality of conductive pads 312 are formed on the back surface S2 of each chip 31 .

[0122] In some embodiments, a functional circuit layer 310 is further formed on the surface of the chip 31 , and the bonding pad 311 is electrically connected to the functional circuit layer 310 .

[0123] See also Figure 10 And step S22 , forming a plurality of conductive lines 313 on the side surface S3 of each chip 31 , wherein each conductive line 313 electrically connects the corresponding bonding pad 311 and the conductive pad 312 .

[0124] Specifically, in some embodiments, forming a plurality of conductive lines 313 on the side surface S3 of the chip 31 specifically includes the following steps:

[0125] A plurality of conductive lines 313 are formed on the side surface S3 of the chip 31 using flexible microelectronics printing technology. Each conductive line 313 extends from the bonding pad 311 through the surface S1 of the chip 31, the side surface S3 of the chip 31, the back surface S2 of the chip 31, and the corresponding conductive pad 312.

[0126] The flexible microelectronic printing technology can precisely control the width, spacing, and thickness of the conductive lines 313 , thereby achieving precise resistance and capacitance matching.

[0127] Flexible microelectronic printing technology can form the conductive wire 313 on complex geometric shapes, realizing the three-dimensional layout of the circuits on the surface S1, side S3 and back S2 of the chip 31; this not only increases the wiring density of the chip 31, providing the possibility of integrating more functional modules, but also optimizes the current distribution on the surface S1, side S3 and back S2 of the chip 31, reducing current congestion and local overheating.

[0128] In terms of manufacturing, the flexible microelectronics printing technology greatly simplifies the manufacturing process for the chip 31. Traditional chip wiring processes require multiple complex and expensive steps, such as photolithography, etching, and electroplating. However, flexible microelectronics printing technology can directly print the conductive wires 313 on the surface S1, side S3, and back S2 of the chip 31, reducing the process flow and manufacturing costs. Furthermore, this direct printing method is highly customizable, allowing the pattern and parameters of the conductive wires 313 to be quickly adjusted according to the design requirements of different chips, enabling personalized chip manufacturing.

[0129] In addition, by rationally planning the direction and layout of the conductive wires 313 , the heat dissipation of the chip 31 can be made more uniform, thereby improving the reliability and stability of the chip 31 and extending the service life of the chip 31 .

[0130] Figure 16 This is a cross-sectional process structure diagram of forming multiple conductive lines on the side surface of each chip according to another embodiment of the chip packaging method of the present invention. Figure 16 In the embodiment shown, forming a plurality of conductive lines 313 on the side surface S3 of the chip 31 specifically includes the following steps:

[0131] A plurality of conductive wires 313 are formed on the side surface S3 of the chip 31 by a wire bonding process. Each conductive wire 313 extends from the bonding pad 311 to the corresponding conductive pad 312 .

[0132] In some embodiments, the conductive wire 313 may be formed by using bonding methods such as thermocompression bonding, ultrasonic bonding, or thermosonic bonding.

[0133] In some embodiments, the conductive wire 313 formed by the wire bonding process is made of metal wire, such as gold wire, aluminum wire, or copper wire. The metal wire achieves physical connection, and the conductive wire 313 has a large cross-sectional area and low DC resistance.

[0134] In addition, compared with the conductive line 313 formed by flexible microelectronic printing technology, the conductive line 313 formed by the bonding wire process avoids the contact resistance problem between particles in the conductive line 313 formed by flexible microelectronic printing technology due to the continuity of the metal wire, and the signal attenuation is smaller.

[0135] In addition, the bonding wire process is more mature, with higher production efficiency and lower production costs, which reduces the overall process cost.

[0136] In some embodiments, the bonding pads 311 correspond to the conductive pads 312 on the chip 31 in a one-to-one manner, so as to reduce the length of the conductive lines 313 formed subsequently, reduce costs, and reduce process complexity.

[0137] like Figure 11 As shown, in some embodiments, after forming the plurality of conductive lines 313 on the side surface S3 of each chip 31 , the method further includes forming solder 32 on the conductive pad 312 .

[0138] In some embodiments, the solder 32 is solder paste. Solder paste primarily consists of alloy solder powder and flux. The solder paste exhibits excellent thixotropy, meaning that when stirred or squeezed by an external force, its viscosity decreases and its fluidity increases, facilitating printing or dispensing onto the conductive pads 312. Once the external force disappears, the paste's viscosity gradually recovers, maintaining its consistency on the conductive pads 312 without flowing or collapsing.

[0139] See also Figures 12 and 13 And step S23, providing a substrate 33, stacking multiple chips 31 in sequence on the surface S4 of the substrate 33 to form a chip stacking structure, and the bonding pads 311 of the upper chip 31 of two adjacent chips 31 are electrically connected to the conductive pads 312 of the lower chip 31 through the solder 32.

[0140] like Figure 12 As shown, a chip 31 is packaged on the surface S4 of the substrate 33. In some embodiments, the chip 31 and the substrate 33 are fixed and electrically connected via the solder 32.

[0141] like Figure 13 As shown, a plurality of the chips 31 are stacked in sequence to form a chip stacking structure. In some embodiments, two adjacent chips 31 are fixed by the solder 32 to form an electrical connection.

[0142] In some embodiments, after the step of sequentially stacking the plurality of chips 31 on the surface S4 of the substrate 33 to form a chip stacking structure, the following step is further included: performing welding using a reflow process.

[0143] In this embodiment, the chip stack structure is sent to a reflow oven for heating. During the reflow process, the solder 32 undergoes stages such as preheating, activation, reflow, and cooling.

[0144] During the preheating stage, the solvent of the solder 32 evaporates, and the flux begins to work, removing oxides from the bonding pad 311 and the conductive pad 312 .

[0145] During the reflow stage, the temperature rises to above the melting point of the conductive pad 312 , the conductive pad 312 melts, and under the action of surface tension, a good solder joint is automatically formed between the bonding pad 311 and the conductive pad 312 .

[0146] During the cooling stage, the solder 32 solidifies to form a strong electrical and mechanical connection. After being heated and melted, the solder 32 can spread between the bonding pad 311 and the conductive pad 312 and form a good metallurgical bond.

[0147] In some embodiments, multiple chips 31 of the same size are provided, and the side surfaces S3 of the multiple chips 31 are flush. In traditional chip stacking methods, due to process limitations, the chips are often not neatly arranged in the horizontal direction, thereby increasing the horizontal size of the entire chip stack structure. However, the chip packaging method of the present invention, by maintaining the side surfaces S3 of the chips 31 flush, can limit the horizontal size of the chip stack structure to the size of the chips 31, further reducing the size of the device in the horizontal direction.

[0148] like Figure 14 As shown, after the step of sequentially stacking the plurality of chips 31 on the surface S4 of the substrate 33 to form a chip stacking structure, the following step is further included: forming a plastic package 35 covering the chips 31 on the surface S4 of the substrate 33 .

[0149] The plastic package 35 provides a solid physical barrier for the chip 31, protecting it from external mechanical shock, vibration, and abrasion, preventing damage to the chip due to external forces and ensuring its structural integrity in various complex operating environments. The excellent insulation properties of the plastic package 35 effectively isolate the chip 31 from the external environment, preventing electrical short circuits and leakage, and ensuring the normal operation of the chip 31 circuit and the stability of signal transmission.

[0150] In some embodiments, forming the plastic package 35 covering the chip 31 on the surface S4 of the substrate 33 specifically includes the following steps:

[0151] The plastic package body 35 is formed by injection molding of epoxy molding compound (EMC). The epoxy molding compound is a composite material composed of epoxy resin, curing agent, filler, coupling agent, release agent and other components.

[0152] The above technical solution forms the conductive pad 312 on the back side S2 of the chip 31 and uses a conductive wire 313 provided on the side S3 of the chip 31 to electrically connect the bonding pad 311 on the surface S1 of the chip 31 to the conductive pad 312 on the back side S2. This allows vertical stacking without the use of through-silicon vias (TSVs), thus controlling product size and reducing costs.

[0153] First, in traditional solutions, TSV technology requires deep hole machining and filling on the wafer 30. This is not only complex and costly, but also prone to stress concentration and reduced reliability. By eliminating the complex machining process required by TSV technology, there is no need to reserve deep hole space within the chip 31, reducing process complexity and conserving internal space within the chip 31.

[0154] Secondly, the traditional chip stacking method usually uses a thicker chip adhesive film to fix the chip, which undoubtedly increases the overall thickness of the chip stacking structure. In the present invention, since the thickness of the conductive pad 312 is extremely small, its thickness advantage is significant compared to the traditional chip adhesive film. This improvement greatly reduces the thickness of the chip stacking structure in the vertical direction. Taking the common chip stacking application scenario as an example, when the chip adhesive film was originally used, the vertical thickness of the chip stacking structure may reach several millimeters or even thicker. After adopting the chip packaging method described in the present invention, the vertical thickness can be reduced to a fraction of the original or even lower. This reduction in thickness effectively reduces the size of the chip stacking structure in the vertical direction, making it possible to achieve lighter and thinner electronic devices.

[0155] In addition, the solder 32 is further used to vertically fix and electrically connect the chip 31 in the lower layer, so that the chips 31 of the same size can be stacked vertically. In traditional chip stacking methods, due to the limitations of the process itself, the chips are often not arranged neatly in the horizontal direction, thereby increasing the horizontal size of the entire chip stacking structure. The chip packaging method described in the present invention, by keeping the side S3 of the chip 31 flush, can limit the horizontal size of the chip stacking structure to the size of the chip 31, further reducing the size of the device in the horizontal direction.

[0156] Finally, traditional chip stacking methods require the use of large amounts of chip-bonding film to bond each layer of chips, as well as a significant amount of lead wire consumables. The procurement costs of these materials account for a significant portion of the entire chip manufacturing process. The chip packaging method described in the present invention eliminates the need for large amounts of chip-bonding film to bond each layer of chips, nor does it consume a significant amount of lead wire consumables, thus reducing material procurement costs.

[0157] To sum up, this technical solution has achieved remarkable results in reducing the thickness of the chip stacking structure, reducing the device size and reducing material costs by forming a conductive pad 312 on the back side S2 of the chip 31 and using flexible microelectronic printing technology to achieve conductive connection, providing a new feasible solution for the development of semiconductor chip manufacturing technology.

[0158] Figure 15 This is a schematic structural diagram of a chip packaging structure formed by another embodiment of the chip packaging method of the present invention. Figure 15 The embodiment shown is Figures 3 to 14 The embodiment shown differs in that:

[0159] In this embodiment, before the step of forming a plurality of conductive lines 313 on the side surface S3 of each chip 31 , the step further includes: forming a first dielectric layer 341 between the side surface S3 of the chip 31 and the conductive lines 313 .

[0160] In this embodiment, before forming a plurality of conductive lines 313 on the side surface S3 of each chip 31, the process further includes forming a second dielectric layer 342 between the back surface S2 of the chip 31 and the conductive pads 312. Specifically, the second dielectric layer 342 is formed before the conductive pads 312 and may cover the entire back surface of the chip 31 or only the location of the conductive pads 312.

[0161] A dielectric layer is formed between the side surface S3 of the chip 31 and the conductive wire 313 and between the back surface S2 of the chip 31 and the conductive pad 312 to ensure accurate connection between the conductive pad 312 and the bonding pad 311 and avoid short circuit problems caused by cross-connection.

[0162] At the same time, the dielectric layer has good physical stability and chemical inertness, and can provide a stable support structure for the conductive wire 313 during the chip manufacturing process, ensuring that the conductive wire 313 is accurately laid along a preset path.

[0163] In addition, the dielectric layer has a high surface flatness, which can ensure good adhesion between the conductive wire 313 and the side surface S3 and the back surface S2 of the chip 31, thereby reducing signal transmission errors caused by inaccurate connections.

[0164] Based on the same inventive concept, an embodiment of the present invention further provides a chip packaging structure.

[0165] See also Figure 14 , the chip packaging structure includes:

[0166] substrate 33;

[0167] The chip stacking structure includes multiple chips 31 stacked in sequence on the surface S4 of the substrate 33, each of the chip 31 surfaces S1 is formed with multiple bonding pads 311, each of the chip 31 back side S2 is formed with multiple conductive pads 312, each of the chip 31 side S3 is formed with multiple conductive wires 313, each of the conductive wires 313 is electrically connected to the corresponding bonding pad 311 and the conductive pad 312, solder 32 is formed at the conductive pad 312, and the bonding pad 311 of the lower chip 31 of the two adjacent chips 31 is electrically connected to the conductive pad 312 of the upper chip 31 through the solder.

[0168] In some embodiments, multiple chips 31 of the same size are provided, and the side surfaces S3 of the multiple chips 31 are flush. In traditional chip stacking methods, due to process limitations, the chips are often not neatly arranged in the horizontal direction, thereby increasing the horizontal size of the entire chip stack structure. However, the chip packaging method of the present invention, by maintaining the side surfaces S3 of the chips 31 flush, can limit the horizontal size of the chip stack structure to the size of the chips 31, further reducing the size of the device in the horizontal direction.

[0169] In some embodiments, the bonding pads 311 are located at the edge of the surface S1 of the chip 31, and the conductive pads 312 are located at the edge of the back surface S2 of the chip 31. Providing both the bonding pads 311 and the conductive pads 312 at the edge of the chip 31 reduces the length of the conductive wires 313, reduces costs, and reduces process complexity.

[0170] In some embodiments, each conductive line 313 extends from the bonding pad 311 to the corresponding conductive pad 312 through the chip side S3. The bonding pads 311 and the conductive pads 312 on the chip 31 correspond one-to-one to each other, thereby reducing the length of the conductive lines 313 formed subsequently, reducing costs, and reducing process complexity.

[0171] In some embodiments, each conductive wire 313 extends from the bonding pad 311 through the surface S1 of the chip 31, the side S3 of the chip 31, the back S2 of the chip 31, and the corresponding conductive pad 312. In this embodiment, the conductive wires 313 are formed using flexible microelectronic printing technology and are attached to the surface of the bonding pad 311, the surface S1 of the chip 31, the side S3 of the chip 31, the back S2 of the chip 31, and the surface of the corresponding conductive pad 312. By rationally planning the direction and layout of the conductive wires 313, heat dissipation from the chip 31 can be more uniform, improving the reliability and stability of the chip 31, and extending the service life of the chip 31.

[0172] In some embodiments, each of the conductive wires 313 extends from the bonding pad 311 to the corresponding conductive pad 312 through the side surface S3 of the chip 31. In this embodiment, the conductive wires are formed by a wire bonding process.

[0173] In some embodiments, the conductive wire 313 formed by the wire bonding process is made of metal wire, such as gold wire, aluminum wire, or copper wire. The metal wire achieves physical connection, and the conductive wire 313 has a large cross-sectional area and low DC resistance.

[0174] In addition, compared with the conductive line 313 formed by flexible microelectronic printing technology, the conductive line 313 formed by the bonding wire process avoids the contact resistance problem between particles in the conductive line 313 formed by flexible microelectronic printing technology due to the continuity of the metal wire, and the signal attenuation is smaller.

[0175] In addition, the bonding wire process is more mature, with higher production efficiency and lower production costs, which reduces the overall process cost.

[0176] In some embodiments, the conductive pad 312 is a metal layer. In this embodiment, the metal layer is a copper plating layer. Using the copper plating layer as the conductive pad 312 can provide an extremely low-resistance path for current transmission between the chips 31, effectively reducing signal transmission loss and power loss, and significantly improving the electrical performance and operating efficiency of the chip.

[0177] During the manufacturing process, the copper plating parameters can be flexibly adjusted according to the design requirements of the chip 31, such as increasing the plating thickness in areas that require higher conductivity, and achieving ultra-thin and uniform plating in areas where high dimensional accuracy is required, to meet diverse chip manufacturing needs and improve production efficiency and product yield.

[0178] The use of copper plating as the conductive pad 312 makes the conductive pad 312 extremely thin, which is significantly thinner than conventional chip attach films. This improvement greatly reduces the thickness of the chip stacking structure in the vertical direction.

[0179] In other embodiments, the metal layer may also be a silver-plated layer.

[0180] Taking a common chip stacking application as an example, when using chip adhesive film, the vertical thickness of the chip stack structure can reach several millimeters or even thicker. However, using the chip packaging method described in this invention, this vertical thickness can be reduced to a fraction of the original thickness or even less. This reduction in thickness effectively reduces the vertical dimensions of the chip stack structure, making it possible to achieve thinner and lighter electronic devices.

[0181] In some embodiments, solder 32 is formed on the conductive pad 312 .

[0182] In this embodiment, the solder 32 is solder paste. Solder paste primarily consists of alloy solder powder and flux. Solder paste exhibits excellent thixotropy, meaning that when stirred or squeezed by an external force, its viscosity decreases and its fluidity increases, facilitating printing or dispensing onto the conductive pads 312. Once the external force is removed, the paste's viscosity gradually recovers, maintaining its position on the conductive pads 312 without flowing or collapsing.

[0183] In some embodiments, the chip 31 and the substrate 33 are fixed and electrically connected via the solder 32 ; and two adjacent chips 31 are fixed and electrically connected via the solder 32 .

[0184] After being heated and melted, the solder 32 can spread between the bonding pad 311 and the conductive pad 312 and form a good metallurgical bond.

[0185] In some embodiments, a plastic encapsulation body 35 is further included, formed on the surface S1 of the substrate 33 and covering the chip 31. The plastic encapsulation body 35 provides a solid physical barrier for the chip 31, protecting it from external mechanical shock, vibration, and abrasion, preventing damage to the chip due to external forces and ensuring its structural integrity in various complex operating environments. The excellent insulation properties of the plastic encapsulation body 35 effectively isolate the chip 31 from the external environment, preventing electrical short circuits and leakage, and ensuring the normal operation of the chip 31 circuit and the stability of signal transmission.

[0186] In some embodiments, the plastic package 35 is formed of epoxy resin molding compound, which is a composite material composed of epoxy resin, curing agent, filler, coupling agent, release agent and other components.

[0187] The above technical solution forms the conductive pad 312 on the back side S2 of the chip 31 and uses a conductive wire 313 provided on the side S3 of the chip 31 to electrically connect the bonding pad 311 on the surface S1 of the chip 31 to the conductive pad 312 on the back side S2. This allows vertical stacking without the use of through-silicon vias (TSVs), thus controlling product size and reducing costs.

[0188] The chip packaging structure described in the present invention achieves significant results in reducing the thickness of the chip stacking structure, shrinking the device size, and lowering material costs by copper plating S2 on the back side of the chip 31 to form a conductive pad 312 and using flexible microelectronic printing technology to achieve conductive connection. It provides a new and feasible solution for the development of semiconductor chip manufacturing technology.

[0189] Figure 15 FIG. 1 is a schematic structural diagram of another embodiment of the chip packaging structure of the present invention. Figure 15 The embodiment shown is Figure 14 The embodiment shown differs in that:

[0190] In this embodiment, a first dielectric layer 341 is formed between the side surface S3 of the chip 31 and the conductive line 313 .

[0191] In this embodiment, a second dielectric layer 342 is formed between the back surface S2 of the chip 31 and the conductive pad 312. Specifically, the second dielectric layer 342 may cover the entire back surface of the chip 31 or only cover the location of the conductive pad 312.

[0192] A dielectric layer is formed between the side surface S3 of the chip 31 and the conductive wire 313 and between the back surface S2 of the chip 31 and the conductive pad 312 to ensure accurate connection between the conductive pad 312 and the bonding pad 311 and avoid short circuit problems caused by cross-connection.

[0193] At the same time, the dielectric layer has good physical stability and chemical inertness, and can provide a stable support structure for the conductive wire 313 during the chip manufacturing process, ensuring that the conductive wire 313 is accurately laid along a preset path.

[0194] In addition, the dielectric layer has a high surface flatness, which can ensure good adhesion between the conductive wire 313 and the side surface S3 and the back surface S2 of the chip 31, thereby reducing signal transmission errors caused by inaccurate connections.

[0195] It should be noted that references in the specification to "one embodiment," "an embodiment," "exemplary embodiments," "some embodiments," etc. indicate that the described embodiments may include specific features, structures, or characteristics, but every embodiment may not necessarily include the specific features, structures, or characteristics. Moreover, such phrases do not necessarily refer to the same embodiment.

[0196] In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of persons skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0197] Generally, terms can be understood, at least in part, from their usage in context. For example, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a feature, structure, or combination of features in a plural sense, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" can also be understood to express either singular or plural usage, depending, at least in part, on the context.

[0198] Additionally, the term "based on" should be understood as not necessarily intended to convey an exclusive set of factors, but may instead allow for the presence of other factors not necessarily explicitly described, again depending at least in part on the context.

[0199] It should also be noted that in this specification, “connected / coupled” refers not only to direct coupling of one component to another component, but also to indirect coupling of one component to another component via an intermediate component.

[0200] It should be noted that the terms "including," "having," and their variations, as used in this document, are intended to cover non-exclusive inclusions. Terms such as "first," "second," and the like are used to distinguish similar items and are not necessarily used to describe a specific order or precedence. Unless the context clearly indicates otherwise, it should be understood that such terms are interchangeable where appropriate. Furthermore, the embodiments and features within the embodiments of this invention may be combined with one another where no conflict exists.

[0201] In addition, in the above description, descriptions of well-known components and technologies are omitted to avoid unnecessary confusion of the concepts of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to in detail.

[0202] The above description is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A chip packaging method, characterized in that: The steps include: Providing a plurality of chips, each of which has a plurality of bonding pads formed on a surface thereof and a plurality of conductive pads formed on a back surface thereof; A plurality of conductive lines are formed on the side surface of each chip, each conductive line being electrically connected to the corresponding bonding pad and the conductive pad; A substrate is provided, and a plurality of chips are sequentially stacked on the surface of the substrate to form a chip stacking structure, wherein the bonding pads of the lower chip of two adjacent chips are electrically connected to the conductive pads of the upper chip.

2. The chip packaging method according to claim 1, wherein: A plurality of chips with the same size are provided, and side surfaces of the plurality of chips are flush.

3. The chip packaging method according to claim 1, wherein: The method of providing a plurality of chips, wherein a plurality of bonding pads are formed on the surface of each chip and a plurality of conductive pads are formed on the back of each chip, specifically comprises the following steps: Providing a wafer, wherein a plurality of chips are formed on a surface of the wafer, and a plurality of bonding pads are formed at an edge of the surface of each chip; forming a plurality of conductive pads on the back side of the wafer, wherein the conductive pads are distributed at the edge of each chip; The wafer is cut into individual chips.

4. The chip packaging method according to claim 3, wherein: Before the step of forming a plurality of conductive pads on the back side of the wafer, the following steps are also included: forming a protective film on the surface of the wafer; The back side of the wafer is thinned.

5. The chip packaging method according to claim 4, characterized in that: The forming of a plurality of conductive pads on the back side of the wafer specifically includes the following steps: affixing a dry film on the back side of the wafer and patterning the dry film to form a patterned dry film; Using the patterned dry film as a mask layer, a patterned metal layer is formed on the back side of the wafer to serve as the conductive pad; The protective film and the dry film are removed.

6. The chip packaging method according to claim 5, wherein: The step of forming a plurality of conductive lines on the side surface of each chip specifically includes the following steps: A plurality of conductive lines are formed on the side of the chip by a wire bonding process, and each conductive line extends from the bonding pad to the corresponding conductive pad.

7. The chip packaging method according to claim 5, characterized in that: The step of forming a plurality of conductive lines on the side surface of each chip specifically includes the following steps: A plurality of conductive lines are formed on the side of the chip by using flexible microelectronic printing technology, and each conductive line extends from the bonding pad through the chip surface, the chip side, the chip back and the corresponding conductive pad.

8. The chip packaging method according to any one of claims 1 to 7, characterized in that: Before the step of forming a plurality of conductive lines on each side surface of the chip, the method further includes: forming a first dielectric layer between the side surface of the chip and the conductive lines.

9. The chip packaging method according to any one of claims 1 to 7, characterized in that: Before the step of forming a plurality of conductive lines on each side surface of the chip, the method further includes: forming a second dielectric layer between the back surface of the chip and the conductive pad.

10. The chip packaging method according to claims 1 to 7, characterized in that: After forming a plurality of conductive lines on the side surface of each chip, the method further includes the following step: forming solder at the conductive pad.

11. The chip packaging method according to claim 10, wherein: The chip and the substrate are fixed and electrically connected via the solder; and two adjacent chips are fixed and electrically connected via the solder.

12. The chip packaging method according to claim 11, wherein: After the step of sequentially stacking the plurality of chips on the surface of the substrate to form a chip stacking structure, the method further includes the following steps: Soldering is completed using a reflow process.

13. The chip packaging method according to claim 12, wherein: After the step of sequentially stacking the plurality of chips on the surface of the substrate to form a chip stacking structure, the method further includes the following steps: A plastic package covering the chip is formed on the surface of the substrate.

14. The chip packaging method according to claim 13, wherein: The step of forming a plastic package covering the chip on the substrate surface specifically includes the following steps: The plastic package is formed by injection molding of epoxy resin molding compound.

15. A chip packaging structure, characterized in that: include: substrate; A chip stacking structure includes multiple chips stacked in sequence on the surface of the substrate, multiple bonding pads formed on the surface of each chip, multiple conductive pads formed on the back of each chip, and multiple conductive lines formed on the side of each chip. Each conductive line is electrically connected to the corresponding bonding pad and the conductive pad, and the bonding pad of the lower chip of two adjacent chips is electrically connected to the conductive pad of the upper chip.

16. The chip packaging structure according to claim 15, wherein: A plurality of chips with the same size are provided, and side surfaces of the plurality of chips are flush.

17. The chip packaging structure according to claim 15, wherein: The bonding pad is located at the edge of the chip surface; The conductive pad is located at the edge of the back side of the chip.

18. The chip packaging structure according to claim 17, wherein: Each of the conductive wires extends from the bonding pad to the corresponding conductive pad through the side surface of the chip.

19. The chip packaging structure according to claim 17, wherein: Each of the conductive wires extends from the bonding pad and passes through the chip surface, the chip side surface, the chip back surface and the corresponding conductive pad.

20. The chip packaging structure according to any one of claims 15 to 19, wherein: The conductive pad is a metal layer.

21. The chip packaging structure according to any one of claims 15 to 19, wherein: A first dielectric layer is formed between the side surface of the chip and the conductive line.

22. The chip packaging structure according to any one of claims 15 to 19, characterized in that: A second dielectric layer is formed between the back side of the chip and the conductive pad.

23. The chip packaging structure according to claims 15 to 19, characterized in that: Solder is formed on the conductive pad.

24. The chip packaging structure according to claim 23, wherein: The chip and the substrate are fixed and electrically connected via the solder; and two adjacent chips are fixed and electrically connected via the solder.

25. The chip packaging structure according to any one of claims 15 to 19, characterized in that: It also includes a plastic package covering the substrate and the chip surface.

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