Substrate, chip packaging structure and electronic equipment

Abstract

The invention discloses a substrate, a chip packaging structure and electronic equipment. The substrate sequentially comprises a first wiring layer, a composite core layer and a second wiring layer in the thickness direction. The side, back to the composite core layer, of the first wiring layer is connected with the chip, and the side, back to the composite core layer, of the second wiring layer is connected with the circuit board. The composite core layer comprises a glass core area and a peripheral area surrounding the glass core area, the thermal expansion coefficient of the peripheral area is larger than that of the glass core area, the thermal expansion coefficient of the glass core area is matched with that of the chip, and the thermal expansion coefficient of the peripheral area is matched with that of the circuit board. Therefore, if the substrate is connected between the chip and the circuit board, when the temperature of the environment where the substrate is located changes, the deformation stress generated by the chip and the substrate due to the temperature can be reduced, and meanwhile, the deformation stress generated by the substrate and the circuit board due to the temperature change can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit packaging, and in particular to a substrate, a chip packaging structure and an electronic device. Background Art

[0002] In the substrate, the thermal expansion coefficient of the chip and the thermal expansion coefficient of the printed circuit board are different. The substrate is provided between the chip and the circuit board. The chip and the substrate are welded, and the substrate is welded to the printed circuit board.

[0003] Currently, substrates are often made of organic or glass materials. The thermal expansion coefficients of organic substrates and chips are mismatched, which can easily cause cracking at the junction between the substrate and chip. The thermal expansion coefficients of glass substrates and printed circuit boards are also mismatched, which can easily cause cracking at the junction between the substrate and printed circuit board. Summary of the Invention

[0004] The present application provides a substrate, a chip packaging structure and an electronic device, aiming to solve the problem of thermal expansion coefficient mismatch between the substrate and the chip and the circuit board.

[0005] In a first aspect, the present application provides a substrate comprising, in order along the thickness direction, a first wiring layer, a composite core layer, and a second wiring layer. The first wiring layer is provided with circuits for transmitting electrical signals, and the second wiring layer is provided with circuits for transmitting electrical signals. The side of the first wiring layer facing away from the composite core layer is connected to a chip, and the side of the second wiring layer facing away from the composite core layer is connected to a circuit board. The composite core layer is connected between the first and second wiring layers and can support the chip. The chip is primarily composed of silicon, the thermal expansion coefficient of the circuit board is much greater than that of the chip, and the thermal expansion coefficient of the glass core region is mismatched with that of the circuit board. The composite core layer includes a glass core region and a peripheral region surrounding the glass core region. The thermal expansion coefficient of the peripheral region is greater than that of the glass core region, the thermal expansion coefficient of the glass core region matches that of the chip, and the thermal expansion coefficient of the peripheral region is relatively compatible with that of the circuit board. Thus, when the substrate is connected between the chip and the circuit board, changes in the ambient temperature of the substrate can reduce temperature-induced deformation stresses in the chip and substrate, while also reducing temperature-induced deformation stresses in the substrate and circuit board.

[0006] In combination with the first aspect, in a possible implementation, the thermal expansion coefficient of the glass core region is [3×10 -6 / ℃,8×10 -6 / ℃], and the thermal expansion coefficient of the peripheral area is [5×10 -6 / ℃, 12×10 -6 / ℃]. The thermal expansion coefficient of the chip is generally 2×10 -6 / ℃ to 4×10-6 / ℃, the thermal expansion coefficient of the glass core area is close to that of the chip. The thermal expansion coefficient of the circuit board is generally 12×10 -6 / ℃ to 18×10 -6 / ℃, the thermal expansion coefficient of the peripheral area is close to that of the circuit board. In this way, the thermal expansion coefficient mismatch problem when the substrate is connected to the chip can be solved, and the thermal expansion coefficient mismatch problem when the substrate is connected to the circuit board can also be solved.

[0007] In combination with the first aspect, in a possible implementation, the thermal expansion coefficient of the peripheral area is a, the thermal expansion coefficient of the glass core area is b, and 1×10 -6 / ℃≤ab≤15×10 -6 / °C. The difference in thermal expansion coefficient between the peripheral area and the glass core area is made equivalent to the difference between the thermal expansion coefficients of the circuit board and the chip. Thus, while the thermal expansion coefficients of the glass core area and the chip are close, the thermal expansion coefficients of the peripheral area and the circuit board are close. This resolves the thermal expansion coefficient mismatch problem when connecting the substrate to the chip, and also when connecting the substrate to the circuit board.

[0008] In conjunction with the first aspect, in one possible implementation, at least a portion of the chip's projection in the thickness direction of the substrate is located within the glass core region. The glass core region supports the chip, and its coefficient of thermal expansion matches that of the chip. Furthermore, because the chip's projection in the thickness direction is located within the glass plate's projection in the thickness direction, if the temperature changes, the glass core region and the chip deform to a similar extent. This reduces the risk of cracking at the connection between the chip and the first wiring layer in the substrate, thereby improving the stability of the connection between the chip and the substrate.

[0009] In combination with the first aspect, in a possible implementation, a plurality of the chips are provided in the first wiring layer, and a projection of at least one of the chips in the thickness direction of the substrate is completely within the glass core region.

[0010] In conjunction with the first aspect, in one possible implementation, the glass core region and the peripheral region are connected via an adhesive. Connecting the glass core region and the peripheral region with an adhesive can improve the connection strength between the glass core region and the peripheral region. The adhesive acts as a transition between the glass core region and the peripheral region, reducing the negative impact of a mismatch in the thermal expansion coefficients between the glass core region and the peripheral region. The negative impact of a mismatch in the thermal expansion coefficients between the glass core region and the peripheral region refers to an unstable connection resulting from this mismatch in the thermal expansion coefficients.

[0011] In conjunction with the first aspect, in one possible implementation, the peripheral region is made of glass. It should be noted that the thermal expansion coefficient of the glass material in the peripheral region is higher than that of the glass core region, and the thermal expansion coefficient of the glass material in the peripheral region is relatively close to that of the circuit board. Therefore, even if the ambient temperature of the substrate fluctuates significantly, the connection between the substrate and the circuit board is less likely to crack due to thermal expansion coefficient mismatch.

[0012] In conjunction with the first aspect, in one possible implementation, the peripheral region is made of an organic material. The thermal expansion coefficient of the organic material is close to that of the circuit board. Therefore, even if the ambient temperature of the substrate fluctuates significantly, the connection between the substrate and the circuit board is less likely to crack due to a mismatch in thermal expansion coefficients.

[0013] In conjunction with the first aspect, in one possible implementation, the glass core region is provided with a plurality of through-glass vias in the thickness direction, through which first conductors for transmitting communication signals or electrical energy are passed, connecting the first wiring layer and the second wiring layer; and the peripheral region is provided with a plurality of organic through-holes in the thickness direction, through which second conductors for transmitting electrical energy are passed, connecting the first wiring layer and the second wiring layer. In the substrate, the glass core region has a relatively low coefficient of thermal expansion, and smaller through-glass vias can be formed in the glass core region, which is beneficial for increasing the interconnection density between the substrate and the chip. The first conductive layer is distributed in the middle region of the substrate, and the communication signal is transmitted by the first conductor, which can shorten the communication distance between the chip and the circuit board, thereby improving the communication speed between the chip and the circuit board.

[0014] In conjunction with the first aspect, in one possible implementation, the diameter of the through-glass via is 50 μm-100 μm, and the diameter of the organic through-glass via is 100 μm-250 μm. Because the glass core region has a smaller coefficient of thermal expansion, when the ambient temperature of the substrate changes, the deformation of the glass core region is smaller. Therefore, smaller through-glass vias can be provided in the glass core region. The diameter of the through-glass via can be set to 50 μm-100 μm. More through-glass vias can be provided in the glass core region, which helps to increase the interconnection density between the substrate and the chip.

[0015] In conjunction with the first aspect, in one possible implementation, the composite core layer has a thickness of 300 μm to 1200 μm. Due to the relatively low thermal expansion coefficient of glass, the overall thickness of the composite core layer can be set thinner, which is beneficial for improving the energy density of the substrate.

[0016] In the second aspect, the present application provides a chip packaging structure, which includes a chip and the substrate described in the first aspect; the chip is connected to the side of the first wiring layer facing away from the composite core layer, and the side of the second wiring layer facing away from the composite core layer is used to connect to the circuit board.

[0017] In a third aspect, the present application provides an electronic device comprising an electronic device, a circuit board, and a chip packaging structure as described in the second aspect, wherein the electronic device is connected to the circuit board, and the chip packaging structure is connected to the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 An electronic device provided in an embodiment of the present application;

[0019] Figure 2 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0020] Figure 3 A schematic structural diagram of a substrate provided in an embodiment of the present application;

[0021] Figure 4 A schematic diagram of the structure of the chip packaging structure connected to the circuit board;

[0022] Figure 5 Schematic diagram of the evolution of substrate manufacturing methods.

[0023] Description of reference numerals:

[0024] 1000, electronic device; 100, chip packaging structure; 110, substrate; 111, first wiring layer; 112, composite core layer; 112a, glass core region; 112b, peripheral region; 112c, through-glass via; 112d, organic via; 113, second wiring layer; 114, adhesive; 120, chip; 200, circuit board; 300, electronic device. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of this application clearer, this application will be further described in detail below with reference to the accompanying drawings.

[0026] See Figure 1 , Figure 1An electronic device 1000 is provided in an embodiment of the present application, and the electronic device 1000 includes an electronic device 300, a circuit board 200 and a chip packaging structure 100. Among them, the electronic device 300 is connected to the circuit board 200, and the chip packaging structure 100 is connected to the circuit board 200. Specifically, the electronic device 300 can be some electronic components with specific functions such as resistors, capacitors, and interfaces. The electronic device 300 can be welded on the circuit board 200 to be electrically connected to the circuit board 200, and the chip packaging structure 100 can also be welded on the circuit board 200 to be electrically connected to the circuit board 200. Since the electronic device 300 and the chip packaging structure 100 are both connected to the circuit board 200, the chip packaging structure 100 is electrically connected to the electronic device 300 through the circuit board 200, and the chip packaging structure 100 can send electrical signals to control the operation of the electronic device 300.

[0027] Please attend Figure 2 , Figure 2 This is a schematic diagram of a chip package structure 100 provided in an embodiment of the present application. The chip package structure 100 includes a chip 120 and a substrate 110. The substrate 110 is connected to the chip 120. Figure 3 , Figure 3 This is a schematic diagram of the structure of a substrate 110 provided in an embodiment of the present application. Substrate 110 includes a first wiring layer 111, a composite core layer 112, and a second wiring layer 113, which are stacked sequentially along the thickness direction. Composite core layer 112 is located between first wiring layer 111 and second wiring layer 113. Chip 120 is soldered to the surface of first wiring layer 111 away from composite core layer 112 via solder balls. Composite core layer 112 includes a glass core region 112a and a peripheral region 112b. Glass core region 112a is connected between first wiring layer 111 and second wiring layer 113, while peripheral region 112b is connected between first wiring layer 111 and second wiring layer 113. Furthermore, peripheral region 112b surrounds glass core region 112a. Glass core region 112a is made of glass and has a coefficient of thermal expansion (CTE) similar to that of chip 120. The material of the peripheral region 112 b can be glass or an organic material. The thermal expansion coefficient of the peripheral region 112 b is close to the thermal expansion coefficient of the circuit board 200 .

[0028] See Figure 4 , Figure 4This is a schematic diagram of the structure of a chip package structure 100 connected to a circuit board 200. The chip 120 is primarily composed of silicon. The circuit board 200 has a much higher thermal expansion coefficient than the chip 120, and the thermal expansion coefficient of the glass core region 112a is mismatched with that of the circuit board 200. The composite core layer 112 includes a glass core region 112a and a peripheral region 112b surrounding the glass core region 112a. The thermal expansion coefficient of the peripheral region 112b is greater than that of the glass core region 112a, matching that of the chip 120. The thermal expansion coefficient of the peripheral region 112b is relatively well matched with that of the circuit board 200. Thus, if the substrate 110 is connected between the chip 120 and the circuit board 200, changes in the ambient temperature of the substrate 110 can reduce the temperature-induced deformation stress in the chip 120 and the substrate 110, and can also reduce the temperature-induced deformation stress in the substrate 110 and the circuit board 200.

[0029] In one possible implementation, the thermal expansion coefficient of the glass core region 112a is [3×10 -6 / ℃,8×10 -6 / °C], and the thermal expansion coefficient of the peripheral region 112b is [5×10 -6 / ℃, 12×10 -6 / ℃]. The thermal expansion coefficient of the chip 120 is generally 2×10 -6 / ℃ to 4×10 -6 / ℃, the thermal expansion coefficient of the glass core region 112a is close to that of the chip 120. The thermal expansion coefficient of the circuit board 200 is generally 12×10 -6 / ℃ to 18×10 -6 / °C, the thermal expansion coefficient of the peripheral area 112b is relatively close to the thermal expansion coefficient of the circuit board 200. In this way, the thermal expansion coefficient mismatch problem when the substrate 110 and the chip 120 are connected can be solved, and the thermal expansion coefficient mismatch problem when the substrate 110 and the circuit board 200 are connected can also be solved.

[0030] In a possible implementation, the thermal expansion coefficient of the glass core region 112a is close to that of the chip 120, and the thermal expansion coefficient of the peripheral region 112b is close to that of the circuit board 200. The thermal expansion coefficient of the chip 120 is generally 2×10 -6 / ℃ to 4×10 -6 / ℃, the thermal expansion coefficient of the circuit board 200 is generally 12×10 -6 / ℃ to 18×10 -6 / ℃. If the thermal expansion coefficient of the outer region 112b is a, the thermal expansion coefficient of the glass core region 112a is b, 1×10-6 / ℃≤ab≤15×10 -6 / °C, so that the difference between the thermal expansion coefficients of the peripheral region 112b and the glass core region 112a is equivalent to the difference between the thermal expansion coefficients of the circuit board 200 and the chip 120. In this way, when the thermal expansion coefficients of the glass core region 112a are close to those of the chip 120, the thermal expansion coefficients of the peripheral region 112b are close to those of the circuit board 200. This can solve the problem of thermal expansion coefficient mismatch when the substrate 110 and the chip 120 are connected, and can also solve the problem of thermal expansion coefficient mismatch when the substrate 110 and the circuit board 200 are connected.

[0031] In the embodiment provided in the present application, one chip 120 may be provided in the first wiring layer 111 , or a plurality of chips 120 may be provided.

[0032] When a chip 120 is provided on the first wiring layer 111, at least part of the projection of the chip 120 in the thickness direction of the substrate 110 is located in the glass core area 112a; in one example, the projection of the chip 120 in the thickness direction of the substrate 110 is completely located in the glass core area 112a; in another example, the projection of a part of the chip 120 in the thickness direction of the substrate 110 is located in the glass core area 112a, and the projection of another part of the chip 120 in the thickness direction of the substrate 110 is located in the peripheral area 112b.

[0033] When multiple chips 120 are provided on the first wiring layer 111, the projection of at least one chip 120 in the thickness direction of the substrate 110 is completely within the glass core region 112a. In one example, all chips 120 on the first wiring layer 111 are completely within the glass core region 112a. In another example, the projection of at least one chip 120 in the thickness direction of the substrate 110 is completely within the glass core region 112a, while the projections of some chips 120 in the thickness direction are located in the peripheral region 112b.

[0034] Chip 120 is soldered to the side of first wiring layer 111 facing away from glass core region 112a. Glass core region 112a supports chip 120. The coefficient of thermal expansion of glass core region 112a is relatively close to that of chip 120. When the ambient temperature of chip 120 and substrate 110 fluctuates significantly, the deformation of glass core region 112a and chip 120 is also relatively close. This reduces the likelihood of cracking at the connection between chip 120 and substrate 110, thereby improving the stability of the connection between chip 120 and substrate 110. It should be noted that the coefficient of thermal expansion of glass core region 112a closely matches that of chip 120, and the projection of chip 120 in the thickness direction of substrate 110 is within the projection of glass core region 112a in the thickness direction of substrate 110. If the ambient temperature of the chip 120 and substrate 110 changes, the distance between various locations on the chip 120 and the center of the glass core region 112a is short, and the stress between the chip 120 and the glass core region 112a is low. The center of the glass core region 112a is the geometric center of the projection of the glass core region 112a in the thickness direction of the substrate 110. The glass core region 112a is located within the encirclement of the peripheral region 112b, and the distance between various locations on the glass core region 112a and the center of the circuit board 200 is short. Therefore, when the ambient temperature changes, the stress between the chip 120 and the circuit board 200 is low. The geometric center of the circuit board 200 is the geometric center of the projection of the circuit board 200 in the thickness direction.

[0035] In the examples provided in this application, see Figure 3 The substrate 110 further includes an adhesive 114, through which the glass core region 112a and the peripheral region 112b are connected. Specifically, the adhesive 114 is disposed between the outer sidewall of the glass core region 112a and the inner sidewall of the peripheral region 112b, and the adhesive 114 bonds the glass core region 112a and the peripheral region 112b together. Connecting the glass core region 112a and the peripheral region 112b with the adhesive 114 helps improve the connection strength between the glass core region 112a and the peripheral region 112b. The adhesive 114 acts as a transition between the glass core region 112a and the peripheral region 112b, thereby reducing the negative impact caused by the mismatch in thermal expansion coefficients between the glass core region 112a and the peripheral region 112b. The negative impact caused by the mismatch in thermal expansion coefficients between the glass core region 112a and the peripheral region 112b refers to the unstable connection between the glass core region 112a and the peripheral region 112b due to the mismatch in thermal expansion coefficients.

[0036] In some embodiments provided herein, the projected area of ​​the peripheral region 112b along the thickness direction of the substrate 110 is greater than or equal to the projected area of ​​the glass core region 112a. It is understood that the ratio of the projected area of ​​the peripheral region 112b along the thickness direction of the substrate 110 to the projected area of ​​the substrate 110 along the thickness direction is greater than or equal to 50%. The peripheral region 112b protects the glass core region 112a, making the edges of the glass core region 112a less susceptible to breakage.

[0037] In one feasible implementation, the material of the peripheral region 112b is glass. It should be noted that the thermal expansion coefficient of the glass material of the peripheral region 112b is higher than that of the glass core region 112a, and the thermal expansion coefficient of the glass material of the peripheral region 112b is relatively close to that of the circuit board 200. Therefore, even if the ambient temperature of the substrate 110 fluctuates significantly, the connection between the substrate 110 and the circuit board 200 is unlikely to crack due to thermal expansion coefficient mismatch.

[0038] In one feasible implementation, the material of the peripheral region 112b is an organic material. The thermal expansion coefficient of the organic material is relatively close to that of the circuit board 200. Even if the ambient temperature of the substrate 110 fluctuates significantly, the connection between the substrate 110 and the circuit board 200 is less likely to crack due to the mismatch in thermal expansion coefficients.

[0039] In the substrate 110 provided in this application, continue to refer to Figure 3 The glass core region 112a is provided with a plurality of through glass vias 112c (TGVs) in the thickness direction. Since the glass core region 112a has a higher coefficient of thermal expansion, the through glass vias 112c provided in the glass core region 112a can be smaller in size, and the diameter of the through glass vias 112c can be set to 50μm-100μm. The through glass vias 112c are used to pass through first conductive wires, which connect the first wiring layer 111 and the second wiring layer 113. The first conductive wires can transmit communication signals or electrical energy. Since the size of the through glass vias 112c can be set smaller, more through glass vias 112c can be provided on the substrate 110 of the same size. More first conductive wires connecting the first wiring layer 111 and the second wiring layer 113 can be provided on the substrate 110. When the chip 120 is connected to the first wiring layer 111, the interconnection density between the chip 120 and the substrate 110 can be improved. In the embodiment provided in the present application, the first wire is distributed in the middle area of ​​the substrate 110. Using the first wire to transmit communication signals can shorten the communication distance between the chip 120 and the circuit board 200, which is beneficial to improving the communication speed between the chip 120 and the circuit board 200.

[0040] The peripheral region 112b is provided with a plurality of organic through holes 112d in the thickness direction. The size of the organic through holes 112d can be 100 μm-250 μm. The organic through holes 112d are penetrated by second wires for connecting the first wiring layer 111 and the second wiring layer 113. The second wires are used for transmitting electrical energy.

[0041] The composite core layer 112 has a thickness dimension of 300 μm to 1200 μm. Because glass has a relatively low coefficient of thermal expansion, the overall thickness of the composite core layer 112 can be set thinner, which helps increase the energy density of the substrate 110. Preferably, the composite core layer 112 has a thickness dimension of 500 μm to 1000 μm. Preferably, the composite core layer 112 has a thickness dimension of 500 μm to 800 μm.

[0042] In some examples provided in this application, see Figure 5 , Figure 5 Schematic diagram of the evolution of the method for manufacturing the substrate 110. The method for manufacturing the substrate 110 includes:

[0043] Provide organic core;

[0044] providing an organic through hole 112d in the organic core;

[0045] metallizing the organic vias 112d;

[0046] A hollow cavity is formed in the organic core to retain a peripheral region 112b;

[0047] A glass core region 112a having a glass through hole 112c is embedded in the hollow cavity;

[0048] The glass core region 112a and the peripheral region 112b are connected by an adhesive 114 to form a composite core layer 112;

[0049] The first wiring layer 111 and the second wiring layer 113 are formed on the composite core layer 112 and are disposed on opposite sides of the composite core layer 112. The thermal expansion coefficient of the peripheral region 112b is greater than that of the glass core region 112a.

[0050] The through-glass via 112 c is filled with metal material to form a first conductive line, and the organic through-glass via 112 d is metallized to form a second conductive line.

[0051] The thermal expansion coefficient of the peripheral region 112 b is close to that of the circuit board 200 , and the thermal expansion coefficient of the glass core region 112 a is close to that of the chip 120 .

[0052] In some embodiments, a method of making a substrate includes:

[0053] providing a glass core;

[0054] providing a through-glass hole in the glass core;

[0055] A hollow cavity is opened in the glass core to preserve the peripheral area;

[0056] A glass core region having a through-glass hole is embedded in the hollow cavity;

[0057] The glass core region and the peripheral region are connected by an adhesive to form a composite core layer.

[0058] The thermal expansion coefficient of the peripheral region is greater than that of the glass core region, and the diameter of the through-glass via in the peripheral region can be larger than that of the through-glass via in the glass core region. The thermal expansion coefficient of the peripheral region is close to that of the circuit board, while the thermal expansion coefficient of the glass core region is close to that of the chip.

[0059] It should be understood that expressions such as "include" and "may include" used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as "include" and / or "have" may be interpreted as indicating specific characteristics, numbers, operations, constituent elements, components, or combinations thereof, but may not be interpreted as excluding the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0060] In addition, in this application, the expression "and / or" includes any and all combinations of the associated listed words. For example, the expression "A and / or B" may include A, may include B, or may include both A and B.

[0061] In this application, expressions including ordinal numbers such as "first" and "second" may modify various elements. However, such elements are not limited by the above expressions. For example, the above expressions do not limit the order and / or importance of the elements. The above expressions are only used to distinguish one element from other elements. For example, a first user device and a second user device indicate different user devices, even though the first user device and the second user device are both user devices. Similarly, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0062] When a component is referred to as being "connected" or "accessed" to another component, it should be understood that the component is not only directly connected to or accessed to the other component, but also that another component may exist between the component and the other component. On the other hand, when a component is referred to as being "directly connected to" or "directly accessed" to another component, it should be understood that no component exists between them.

[0063] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A substrate, characterized in that The method comprises a first wiring layer, a composite core layer and a second wiring layer in sequence along the thickness direction of the substrate; The composite core layer includes a glass core area and a peripheral area surrounding the glass core area. The thermal expansion coefficient of the peripheral area is greater than the thermal expansion coefficient of the glass core area. The side of the first wiring layer facing away from the composite core layer is used to connect to the chip, and the side of the second wiring layer facing away from the composite core layer is used to connect to the circuit board.

2. The substrate according to claim 1, wherein The thermal expansion coefficient of the glass core region is [3×10 -6 / ℃,8×10 -6 / °C], and the thermal expansion coefficient of the peripheral area is [5×10 -6 / ℃, 12×10 -6 / ℃].

3. The substrate according to claim 1, wherein The thermal expansion coefficient of the peripheral area is a, the thermal expansion coefficient of the glass core area is b, 1×10 -6 / ℃≤ab≤15×10 -6 / ℃.

4. The substrate according to any one of claims 1 to 3, characterized in that At least a portion of the chip is projected in the thickness direction of the substrate within the glass core region.

5. The substrate according to any one of claims 1 to 3, characterized in that A plurality of the chips are provided on the first wiring layer, and a projection of at least one of the chips in the thickness direction of the substrate is completely within the glass core region. 6 . The substrate according to claim 1 , wherein the composite core layer further comprises an adhesive, and the glass core region and the peripheral region are connected by the adhesive.

7. The substrate according to any one of claims 1 to 6, characterized in that: The material of the outer area is glass.

8. The substrate according to any one of claims 1 to 6, characterized in that: The material of the outer area is an organic material.

9. The substrate according to claim 8, characterized in that The glass core area is provided with a plurality of glass through-holes in the thickness direction, and the glass through-holes are penetrated by a first wire connecting the first wiring layer and the second wiring layer for transmitting communication signals or transmitting electrical energy. The peripheral area is provided with a plurality of organic through-holes in the thickness direction, and the organic through-holes are penetrated by a second wire connecting the first wiring layer and the second wiring layer for transmitting electrical energy.

10. The substrate according to claim 8, wherein The diameter of the glass through-hole is 50 μm-100 μm, and the diameter of the organic through-hole is 100 μm-250 μm.

11. The substrate according to any one of claims 1 to 10, characterized in that: The size of the composite core layer in the thickness direction is 300 μm-1200 μm.

12. A chip packaging structure, characterized in that: It comprises a chip and a substrate as described in any one of claims 1-10; the chip is connected to the side of the first wiring layer facing away from the composite core layer, and the side of the second wiring layer facing away from the composite core layer is used to connect to a circuit board.

13. An electronic device, characterized in that: The invention comprises an electronic device, a circuit board and the chip packaging structure according to claim 11, wherein the electronic device is connected to the circuit board, and the chip packaging structure is connected to the circuit board.

Images